diff --git a/CPLD/LCMXO2-1200HC/.run_manager.ini b/CPLD/LCMXO2-1200HC/.run_manager.ini new file mode 100644 index 0000000..8c0aa7b --- /dev/null +++ b/CPLD/LCMXO2-1200HC/.run_manager.ini @@ -0,0 +1,9 @@ +[Runmanager] +Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) +windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) + +[impl1%3CStrategy1%3E] +isChecked=false +isHidden=false +isExpanded=false diff --git a/CPLD/LCMXO2-1200HC/.setting.ini b/CPLD/LCMXO2-1200HC/.setting.ini new file mode 100644 index 0000000..39eb32a --- /dev/null +++ b/CPLD/LCMXO2-1200HC/.setting.ini @@ -0,0 +1,4 @@ +[General] +PAR.auto_tasks=PARTrace, IOTiming +Map.auto_tasks=MapTrace, MapVerilogSimFile, MapVHDLSimFile +Export.auto_tasks=Jedecgen diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf new file mode 100644 index 0000000..c6d7112 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf new file mode 100644 index 0000000..63de512 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf @@ -0,0 +1,68 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +LOCATE COMP "CROW[0]" SITE "10" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "RCLK" SITE "62" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "MAin[0]" SITE "14" ; +LOCATE COMP "MAin[1]" SITE "12" ; +LOCATE COMP "MAin[2]" SITE "13" ; +LOCATE COMP "MAin[3]" SITE "21" ; +LOCATE COMP "MAin[4]" SITE "20" ; +LOCATE COMP "MAin[5]" SITE "19" ; +LOCATE COMP "MAin[6]" SITE "24" ; +LOCATE COMP "MAin[7]" SITE "18" ; +LOCATE COMP "MAin[8]" SITE "25" ; +LOCATE COMP "MAin[9]" SITE "32" ; +LOCATE COMP "UFMSDO" SITE "27" ; +LOCATE COMP "nFWE" SITE "28" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "RA[1]" SITE "67" ; +LOCATE COMP "RA[2]" SITE "69" ; +LOCATE COMP "RA[3]" SITE "71" ; +LOCATE COMP "RA[4]" SITE "74" ; +LOCATE COMP "RA[5]" SITE "70" ; +LOCATE COMP "RA[6]" SITE "68" ; +LOCATE COMP "RA[7]" SITE "75" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[9]" SITE "63" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "UFMCLK" SITE "29" ; +LOCATE COMP "UFMSDI" SITE "30" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "nRCS" SITE "57" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[7]" SITE "43" ; diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcl.html b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcl.html new file mode 100644 index 0000000..b85aee7 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcl.html @@ -0,0 +1,70 @@ + +Lattice TCL Log + + +
pn230815050136
+#Start recording tcl command: 8/15/2023 05:01:06
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf"
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 8/15/2023 05:01:36
+
+
+
+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+
+ + diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcr.dir/pn230815050136.tcr b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcr.dir/pn230815050136.tcr new file mode 100644 index 0000000..857aaf4 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC_tcr.dir/pn230815050136.tcr @@ -0,0 +1,5 @@ +#Start recording tcl command: 8/15/2023 05:01:06 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC +prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf" +prj_run Export -impl impl1 -forceAll +#Stop recording: 8/15/2023 05:01:36 diff --git a/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_640HC1.sty b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_640HC1.sty new file mode 100644 index 0000000..7292d5f --- /dev/null +++ b/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_640HC1.sty @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-1200HC/impl1/.build_status b/CPLD/LCMXO2-1200HC/impl1/.build_status new file mode 100644 index 0000000..94e5b25 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/.build_status @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb b/CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb new file mode 100644 index 0000000..f28b48b Binary files /dev/null and b/CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb differ diff --git a/CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_rtl.vdb b/CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_rtl.vdb new file mode 100644 index 0000000..9ab3777 Binary files /dev/null and b/CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_rtl.vdb differ diff --git a/CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_tech.vdb b/CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_tech.vdb new file mode 100644 index 0000000..24412d5 Binary files /dev/null and b/CPLD/LCMXO2-1200HC/impl1/.vdbs/RAM2GS_tech.vdb differ diff --git a/CPLD/LCMXO2-1200HC/impl1/.vdbs/dbStat.txt b/CPLD/LCMXO2-1200HC/impl1/.vdbs/dbStat.txt new file mode 100644 index 0000000..0a575a4 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/.vdbs/dbStat.txt @@ -0,0 +1 @@ +RAM2GS_rtl.vdb diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt new file mode 100644 index 0000000..9569a06 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.alt @@ -0,0 +1,75 @@ +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Tue Aug 15 05:03:45 2023 * +NOTE DESIGN NAME: RAM2GS * +NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[7] : 43 : inout * +NOTE PINS RD[6] : 42 : inout * +NOTE PINS RD[5] : 41 : inout * +NOTE PINS RD[4] : 40 : inout * +NOTE PINS RD[3] : 39 : inout * +NOTE PINS RD[2] : 38 : inout * +NOTE PINS RD[1] : 37 : inout * +NOTE PINS RD[0] : 36 : inout * +NOTE PINS Dout[7] : 82 : out * +NOTE PINS Dout[6] : 78 : out * +NOTE PINS Dout[5] : 84 : out * +NOTE PINS Dout[4] : 83 : out * +NOTE PINS Dout[3] : 85 : out * +NOTE PINS Dout[2] : 87 : out * +NOTE PINS Dout[1] : 86 : out * +NOTE PINS Dout[0] : 76 : out * +NOTE PINS LED : 34 : out * +NOTE PINS RBA[1] : 60 : out * +NOTE PINS RBA[0] : 58 : out * +NOTE PINS RA[11] : 59 : out * +NOTE PINS RA[10] : 64 : out * +NOTE PINS RA[9] : 63 : out * +NOTE PINS RA[8] : 65 : out * +NOTE PINS RA[7] : 75 : out * +NOTE PINS RA[6] : 68 : out * +NOTE PINS RA[5] : 70 : out * +NOTE PINS RA[4] : 74 : out * +NOTE PINS RA[3] : 71 : out * +NOTE PINS RA[2] : 69 : out * +NOTE PINS RA[1] : 67 : out * +NOTE PINS RA[0] : 66 : out * +NOTE PINS nRCS : 57 : out * +NOTE PINS RCKE : 53 : out * +NOTE PINS nRWE : 49 : out * +NOTE PINS nRRAS : 54 : out * +NOTE PINS nRCAS : 52 : out * +NOTE PINS RDQMH : 51 : out * +NOTE PINS RDQML : 48 : out * +NOTE PINS nUFMCS : 47 : out * +NOTE PINS UFMCLK : 29 : out * +NOTE PINS UFMSDI : 30 : out * +NOTE PINS PHI2 : 8 : in * +NOTE PINS MAin[9] : 32 : in * +NOTE PINS MAin[8] : 25 : in * +NOTE PINS MAin[7] : 18 : in * +NOTE PINS MAin[6] : 24 : in * +NOTE PINS MAin[5] : 19 : in * +NOTE PINS MAin[4] : 20 : in * +NOTE PINS MAin[3] : 21 : in * +NOTE PINS MAin[2] : 13 : in * +NOTE PINS MAin[1] : 12 : in * +NOTE PINS MAin[0] : 14 : in * +NOTE PINS CROW[1] : 16 : in * +NOTE PINS CROW[0] : 10 : in * +NOTE PINS Din[7] : 1 : in * +NOTE PINS Din[6] : 2 : in * +NOTE PINS Din[5] : 98 : in * +NOTE PINS Din[4] : 99 : in * +NOTE PINS Din[3] : 97 : in * +NOTE PINS Din[2] : 88 : in * +NOTE PINS Din[1] : 96 : in * +NOTE PINS Din[0] : 3 : in * +NOTE PINS nCCAS : 9 : in * +NOTE PINS nCRAS : 17 : in * +NOTE PINS nFWE : 28 : in * +NOTE PINS RCLK : 62 : in * +NOTE PINS UFMSDO : 27 : in * +NOTE CONFIGURATION MODE: NONE * +NOTE COMPRESSION: on * diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.arearep b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.arearep new file mode 100644 index 0000000..b2ad5bc --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.arearep @@ -0,0 +1,21 @@ +---------------------------------------------------------------------- +Report for cell RAM2GS.TECH +Register bits: 102 of 1520 (6.711%) +I/O cells: 67 + Cell usage: + cell count Res Usage(%) + BB 8 100.0 + CCU2D 10 100.0 + FD1P3AX 29 100.0 + FD1P3AY 5 100.0 + FD1P3IX 3 100.0 + FD1S3AX 47 100.0 + FD1S3IX 14 100.0 + FD1S3JX 4 100.0 + GSR 1 100.0 + IB 26 100.0 + INV 3 100.0 + LUT4 122 100.0 + OB 33 100.0 + PFUMX 1 100.0 + TOTAL 306 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn new file mode 100644 index 0000000..38d8e8b --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.bgn @@ -0,0 +1,86 @@ +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:42 2023 + + +Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf + +Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| RamCfg | Reset** | ++---------------------------------+---------------------------------+ +| MCCLK_FREQ | 2.08** | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| JTAG_PORT | ENABLE** | ++---------------------------------+---------------------------------+ +| SDM_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| SLAVE_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MASTER_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| I2C_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MUX_CONFIGURATION_PORTS | DISABLE** | ++---------------------------------+---------------------------------+ +| CONFIGURATION | CFG** | ++---------------------------------+---------------------------------+ +| COMPRESS_CONFIG | ON** | ++---------------------------------+---------------------------------+ +| MY_ASSP | OFF** | ++---------------------------------+---------------------------------+ +| ONE_TIME_PROGRAM | OFF** | ++---------------------------------+---------------------------------+ +| ENABLE_TRANSFR | DISABLE** | ++---------------------------------+---------------------------------+ +| SHAREDEBRINIT | DISABLE** | ++---------------------------------+---------------------------------+ +| BACKGROUND_RECONFIG | OFF** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... + +Bitstream Status: Final Version 1.95. + +Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed". + +=========== +UFM Summary. +=========== +UFM Size: 511 Pages (128*511 Bits). +UFM Utilization: General Purpose Flash Memory. + +Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510). +Initialized UFM Pages: 0 Page. + +Total CPU Time: 2 secs +Total REAL Time: 3 secs +Peak Memory Usage: 253 MB diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd new file mode 100644 index 0000000..c492e5d Binary files /dev/null and b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd differ diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.pad b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.pad new file mode 100644 index 0000000..dd18c97 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.pad @@ -0,0 +1,309 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO2-1200HC +Performance Grade: 4 +PACKAGE: TQFP100 +Package Status: Final Version 1.44 + +Tue Aug 15 05:03:35 2023 + +Pinout by Port Name: ++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | ++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ +| CROW[0] | 10/3 | LVCMOS25_IN | PL4B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| CROW[1] | 16/3 | LVCMOS25_IN | PL8A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[0] | 3/3 | LVCMOS25_IN | PL3A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[1] | 96/0 | LVCMOS25_IN | PT10B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[2] | 88/0 | LVCMOS25_IN | PT12A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[3] | 97/0 | LVCMOS25_IN | PT10A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[4] | 99/0 | LVCMOS25_IN | PT9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[5] | 98/0 | LVCMOS25_IN | PT9B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[6] | 2/3 | LVCMOS25_IN | PL2D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[7] | 1/3 | LVCMOS25_IN | PL2C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Dout[0] | 76/0 | LVCMOS25_OUT | PT17D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[1] | 86/0 | LVCMOS25_OUT | PT12C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[2] | 87/0 | LVCMOS25_OUT | PT12B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[3] | 85/0 | LVCMOS25_OUT | PT12D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[4] | 83/0 | LVCMOS25_OUT | PT15B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[5] | 84/0 | LVCMOS25_OUT | PT15A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[6] | 78/0 | LVCMOS25_OUT | PT16C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[7] | 82/0 | LVCMOS25_OUT | PT15C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| LED | 34/2 | LVCMOS25_OUT | PB9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| MAin[0] | 14/3 | LVCMOS25_IN | PL5C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[1] | 12/3 | LVCMOS25_IN | PL5A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[2] | 13/3 | LVCMOS25_IN | PL5B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[3] | 21/3 | LVCMOS25_IN | PL9B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[4] | 20/3 | LVCMOS25_IN | PL9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[5] | 19/3 | LVCMOS25_IN | PL8D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[6] | 24/3 | LVCMOS25_IN | PL10C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[7] | 18/3 | LVCMOS25_IN | PL8C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[8] | 25/3 | LVCMOS25_IN | PL10D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[9] | 32/2 | LVCMOS25_IN | PB6D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| PHI2 | 8/3 | LVCMOS25_IN | PL3D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| RA[0] | 66/1 | LVCMOS25_OUT | PR4D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[10] | 64/1 | LVCMOS25_OUT | PR5B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[11] | 59/1 | LVCMOS25_OUT | PR8D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[1] | 67/1 | LVCMOS25_OUT | PR4C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[2] | 69/1 | LVCMOS25_OUT | PR4A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[3] | 71/1 | LVCMOS25_OUT | PR3A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[4] | 74/1 | LVCMOS25_OUT | PR2B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[5] | 70/1 | LVCMOS25_OUT | PR3B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[6] | 68/1 | LVCMOS25_OUT | PR4B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[7] | 75/1 | LVCMOS25_OUT | PR2A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[8] | 65/1 | LVCMOS25_OUT | PR5A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[9] | 63/1 | LVCMOS25_OUT | PR5C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RBA[0] | 58/1 | LVCMOS25_OUT | PR9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RBA[1] | 60/1 | LVCMOS25_OUT | PR8C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RCKE | 53/1 | LVCMOS25_OUT | PR9D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RCLK | 62/1 | LVCMOS25_IN | PR5D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| RDQMH | 51/1 | LVCMOS25_OUT | PR10D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RDQML | 48/2 | LVCMOS25_OUT | PB20C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RD[0] | 36/2 | LVCMOS25_BIDI | PB11C | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[1] | 37/2 | LVCMOS25_BIDI | PB11D | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[2] | 38/2 | LVCMOS25_BIDI | PB11A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[3] | 39/2 | LVCMOS25_BIDI | PB11B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[4] | 40/2 | LVCMOS25_BIDI | PB15A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[5] | 41/2 | LVCMOS25_BIDI | PB15B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[6] | 42/2 | LVCMOS25_BIDI | PB18A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[7] | 43/2 | LVCMOS25_BIDI | PB18B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| UFMCLK | 29/2 | LVCMOS25_OUT | PB6A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| UFMSDI | 30/2 | LVCMOS25_OUT | PB6B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| UFMSDO | 27/2 | LVCMOS25_IN | PB4C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nCCAS | 9/3 | LVCMOS25_IN | PL4A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nCRAS | 17/3 | LVCMOS25_IN | PL8B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nFWE | 28/2 | LVCMOS25_IN | PB4D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nRCAS | 52/1 | LVCMOS25_OUT | PR10C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nRCS | 57/1 | LVCMOS25_OUT | PR9B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nRRAS | 54/1 | LVCMOS25_OUT | PR9C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nRWE | 49/2 | LVCMOS25_OUT | PB20D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nUFMCS | 47/2 | LVCMOS25_OUT | PB18D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | ++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 2.5V | +| 1 | 2.5V | +| 2 | 2.5V | +| 3 | 2.5V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| 1/3 | Din[7] | LOCATED | LVCMOS25_IN | PL2C | L_GPLLT_IN | | | +| 2/3 | Din[6] | LOCATED | LVCMOS25_IN | PL2D | L_GPLLC_IN | | | +| 3/3 | Din[0] | LOCATED | LVCMOS25_IN | PL3A | PCLKT3_2 | | | +| 4/3 | unused, PULL:DOWN | | | PL3B | PCLKC3_2 | | | +| 7/3 | unused, PULL:DOWN | | | PL3C | | | | +| 8/3 | PHI2 | LOCATED | LVCMOS25_IN | PL3D | | | | +| 9/3 | nCCAS | LOCATED | LVCMOS25_IN | PL4A | | | | +| 10/3 | CROW[0] | LOCATED | LVCMOS25_IN | PL4B | | | | +| 12/3 | MAin[1] | LOCATED | LVCMOS25_IN | PL5A | PCLKT3_1 | | | +| 13/3 | MAin[2] | LOCATED | LVCMOS25_IN | PL5B | PCLKC3_1 | | | +| 14/3 | MAin[0] | LOCATED | LVCMOS25_IN | PL5C | | | | +| 15/3 | unused, PULL:DOWN | | | PL5D | | | | +| 16/3 | CROW[1] | LOCATED | LVCMOS25_IN | PL8A | | | | +| 17/3 | nCRAS | LOCATED | LVCMOS25_IN | PL8B | | | | +| 18/3 | MAin[7] | LOCATED | LVCMOS25_IN | PL8C | | | | +| 19/3 | MAin[5] | LOCATED | LVCMOS25_IN | PL8D | | | | +| 20/3 | MAin[4] | LOCATED | LVCMOS25_IN | PL9A | PCLKT3_0 | | | +| 21/3 | MAin[3] | LOCATED | LVCMOS25_IN | PL9B | PCLKC3_0 | | | +| 24/3 | MAin[6] | LOCATED | LVCMOS25_IN | PL10C | | | | +| 25/3 | MAin[8] | LOCATED | LVCMOS25_IN | PL10D | | | | +| 27/2 | UFMSDO | LOCATED | LVCMOS25_IN | PB4C | CSSPIN | | | +| 28/2 | nFWE | LOCATED | LVCMOS25_IN | PB4D | | | | +| 29/2 | UFMCLK | LOCATED | LVCMOS25_OUT | PB6A | | | | +| 30/2 | UFMSDI | LOCATED | LVCMOS25_OUT | PB6B | | | | +| 31/2 | unused, PULL:DOWN | | | PB6C | MCLK/CCLK | | | +| 32/2 | MAin[9] | LOCATED | LVCMOS25_IN | PB6D | SO/SPISO | | | +| 34/2 | LED | LOCATED | LVCMOS25_OUT | PB9A | PCLKT2_0 | | | +| 35/2 | unused, PULL:DOWN | | | PB9B | PCLKC2_0 | | | +| 36/2 | RD[0] | LOCATED | LVCMOS25_BIDI | PB11C | | | | +| 37/2 | RD[1] | LOCATED | LVCMOS25_BIDI | PB11D | | | | +| 38/2 | RD[2] | LOCATED | LVCMOS25_BIDI | PB11A | PCLKT2_1 | | | +| 39/2 | RD[3] | LOCATED | LVCMOS25_BIDI | PB11B | PCLKC2_1 | | | +| 40/2 | RD[4] | LOCATED | LVCMOS25_BIDI | PB15A | | | | +| 41/2 | RD[5] | LOCATED | LVCMOS25_BIDI | PB15B | | | | +| 42/2 | RD[6] | LOCATED | LVCMOS25_BIDI | PB18A | | | | +| 43/2 | RD[7] | LOCATED | LVCMOS25_BIDI | PB18B | | | | +| 45/2 | unused, PULL:DOWN | | | PB18C | | | | +| 47/2 | nUFMCS | | LVCMOS25_OUT | PB18D | | | | +| 48/2 | RDQML | LOCATED | LVCMOS25_OUT | PB20C | SN | | | +| 49/2 | nRWE | LOCATED | LVCMOS25_OUT | PB20D | SI/SISPI | | | +| 51/1 | RDQMH | LOCATED | LVCMOS25_OUT | PR10D | DQ1 | | | +| 52/1 | nRCAS | LOCATED | LVCMOS25_OUT | PR10C | DQ1 | | | +| 53/1 | RCKE | LOCATED | LVCMOS25_OUT | PR9D | DQ1 | | | +| 54/1 | nRRAS | LOCATED | LVCMOS25_OUT | PR9C | DQ1 | | | +| 57/1 | nRCS | LOCATED | LVCMOS25_OUT | PR9B | DQ1 | | | +| 58/1 | RBA[0] | LOCATED | LVCMOS25_OUT | PR9A | DQ1 | | | +| 59/1 | RA[11] | LOCATED | LVCMOS25_OUT | PR8D | DQ1 | | | +| 60/1 | RBA[1] | LOCATED | LVCMOS25_OUT | PR8C | DQ1 | | | +| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | | +| 62/1 | RCLK | LOCATED | LVCMOS25_IN | PR5D | PCLKC1_0/DQ0 | | | +| 63/1 | RA[9] | LOCATED | LVCMOS25_OUT | PR5C | PCLKT1_0/DQ0 | | | +| 64/1 | RA[10] | LOCATED | LVCMOS25_OUT | PR5B | DQS0N | | | +| 65/1 | RA[8] | LOCATED | LVCMOS25_OUT | PR5A | DQS0 | | | +| 66/1 | RA[0] | LOCATED | LVCMOS25_OUT | PR4D | DQ0 | | | +| 67/1 | RA[1] | LOCATED | LVCMOS25_OUT | PR4C | DQ0 | | | +| 68/1 | RA[6] | LOCATED | LVCMOS25_OUT | PR4B | DQ0 | | | +| 69/1 | RA[2] | LOCATED | LVCMOS25_OUT | PR4A | DQ0 | | | +| 70/1 | RA[5] | LOCATED | LVCMOS25_OUT | PR3B | DQ0 | | | +| 71/1 | RA[3] | LOCATED | LVCMOS25_OUT | PR3A | DQ0 | | | +| 74/1 | RA[4] | LOCATED | LVCMOS25_OUT | PR2B | DQ0 | | | +| 75/1 | RA[7] | LOCATED | LVCMOS25_OUT | PR2A | DQ0 | | | +| 76/0 | Dout[0] | LOCATED | LVCMOS25_OUT | PT17D | DONE | | | +| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | | +| 78/0 | Dout[6] | LOCATED | LVCMOS25_OUT | PT16C | | | | +| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | | +| 82/0 | Dout[7] | LOCATED | LVCMOS25_OUT | PT15C | JTAGENB | | | +| 83/0 | Dout[4] | LOCATED | LVCMOS25_OUT | PT15B | | | | +| 84/0 | Dout[5] | LOCATED | LVCMOS25_OUT | PT15A | | | | +| 85/0 | Dout[3] | LOCATED | LVCMOS25_OUT | PT12D | SDA/PCLKC0_0 | | | +| 86/0 | Dout[1] | LOCATED | LVCMOS25_OUT | PT12C | SCL/PCLKT0_0 | | | +| 87/0 | Dout[2] | LOCATED | LVCMOS25_OUT | PT12B | PCLKC0_1 | | | +| 88/0 | Din[2] | LOCATED | LVCMOS25_IN | PT12A | PCLKT0_1 | | | +| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | | +| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | | +| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | | +| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | | +| 96/0 | Din[1] | LOCATED | LVCMOS25_IN | PT10B | | | | +| 97/0 | Din[3] | LOCATED | LVCMOS25_IN | PT10A | | | | +| 98/0 | Din[5] | LOCATED | LVCMOS25_IN | PT9B | | | | +| 99/0 | Din[4] | LOCATED | LVCMOS25_IN | PT9A | | | | +| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | | +| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | | +| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | | +| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | | +| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | | +| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | | +| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | | +| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | | +| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | | +| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | | +| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | | +| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | | +| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | | +| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | | +| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | | +| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | | +| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | | +| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | | +| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | | +| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | | +| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | | +| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | | +| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | +| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | | +| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | | +| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | | +| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | | +| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ + +sysCONFIG Pins: ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | +| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | +| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | +| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | ++----------+--------------------+--------------------+----------+-------------+-------------------+ + +Dedicated sysCONFIG Pins: + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "10"; +LOCATE COMP "CROW[1]" SITE "16"; +LOCATE COMP "Din[0]" SITE "3"; +LOCATE COMP "Din[1]" SITE "96"; +LOCATE COMP "Din[2]" SITE "88"; +LOCATE COMP "Din[3]" SITE "97"; +LOCATE COMP "Din[4]" SITE "99"; +LOCATE COMP "Din[5]" SITE "98"; +LOCATE COMP "Din[6]" SITE "2"; +LOCATE COMP "Din[7]" SITE "1"; +LOCATE COMP "Dout[0]" SITE "76"; +LOCATE COMP "Dout[1]" SITE "86"; +LOCATE COMP "Dout[2]" SITE "87"; +LOCATE COMP "Dout[3]" SITE "85"; +LOCATE COMP "Dout[4]" SITE "83"; +LOCATE COMP "Dout[5]" SITE "84"; +LOCATE COMP "Dout[6]" SITE "78"; +LOCATE COMP "Dout[7]" SITE "82"; +LOCATE COMP "LED" SITE "34"; +LOCATE COMP "MAin[0]" SITE "14"; +LOCATE COMP "MAin[1]" SITE "12"; +LOCATE COMP "MAin[2]" SITE "13"; +LOCATE COMP "MAin[3]" SITE "21"; +LOCATE COMP "MAin[4]" SITE "20"; +LOCATE COMP "MAin[5]" SITE "19"; +LOCATE COMP "MAin[6]" SITE "24"; +LOCATE COMP "MAin[7]" SITE "18"; +LOCATE COMP "MAin[8]" SITE "25"; +LOCATE COMP "MAin[9]" SITE "32"; +LOCATE COMP "PHI2" SITE "8"; +LOCATE COMP "RA[0]" SITE "66"; +LOCATE COMP "RA[10]" SITE "64"; +LOCATE COMP "RA[11]" SITE "59"; +LOCATE COMP "RA[1]" SITE "67"; +LOCATE COMP "RA[2]" SITE "69"; +LOCATE COMP "RA[3]" SITE "71"; +LOCATE COMP "RA[4]" SITE "74"; +LOCATE COMP "RA[5]" SITE "70"; +LOCATE COMP "RA[6]" SITE "68"; +LOCATE COMP "RA[7]" SITE "75"; +LOCATE COMP "RA[8]" SITE "65"; +LOCATE COMP "RA[9]" SITE "63"; +LOCATE COMP "RBA[0]" SITE "58"; +LOCATE COMP "RBA[1]" SITE "60"; +LOCATE COMP "RCKE" SITE "53"; +LOCATE COMP "RCLK" SITE "62"; +LOCATE COMP "RDQMH" SITE "51"; +LOCATE COMP "RDQML" SITE "48"; +LOCATE COMP "RD[0]" SITE "36"; +LOCATE COMP "RD[1]" SITE "37"; +LOCATE COMP "RD[2]" SITE "38"; +LOCATE COMP "RD[3]" SITE "39"; +LOCATE COMP "RD[4]" SITE "40"; +LOCATE COMP "RD[5]" SITE "41"; +LOCATE COMP "RD[6]" SITE "42"; +LOCATE COMP "RD[7]" SITE "43"; +LOCATE COMP "UFMCLK" SITE "29"; +LOCATE COMP "UFMSDI" SITE "30"; +LOCATE COMP "UFMSDO" SITE "27"; +LOCATE COMP "nCCAS" SITE "9"; +LOCATE COMP "nCRAS" SITE "17"; +LOCATE COMP "nFWE" SITE "28"; +LOCATE COMP "nRCAS" SITE "52"; +LOCATE COMP "nRCS" SITE "57"; +LOCATE COMP "nRRAS" SITE "54"; +LOCATE COMP "nRWE" SITE "49"; +LOCATE COMP "nUFMCS" SITE "47"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:38 2023 + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.par b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.par new file mode 100644 index 0000000..55962c2 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.par @@ -0,0 +1,301 @@ + +Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" +Tue Aug 15 05:03:31 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67+4(JTAG)/108 66% used + 67+4(JTAG)/80 89% bonded + + SLICE 75/640 11% used + + + +Number of Signals: 285 +Number of Connections: 674 +WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors. + +Pin Constraint Summary: + 66 out of 67 pins locked (98% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + +WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + +WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +No signal is selected as Global Set/Reset. +. +Starting Placer Phase 0. +.......... +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +................... +Placer score = 143529. +Finished Placer Phase 1. REAL time: 4 secs + +Starting Placer Phase 2. +. +Placer score = 143450 +Finished Placer Phase 2. REAL time: 4 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 0 out of 8 (0%) + General PIO: 3 out of 108 (2%) + PLL : 0 out of 1 (0%) + DCM : 0 out of 2 (0%) + DCC : 0 out of 8 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 8 (25%) + SECONDARY: 1 out of 8 (12%) + +Edge Clocks: + No edge clock selected. + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 + 4(JTAG) out of 108 (65.7%) PIO sites used. + 67 + 4(JTAG) out of 80 (88.8%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+-----------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref | ++----------+----------------+------------+-----------+ +| 0 | 13 / 19 ( 68%) | 2.5V | - | +| 1 | 20 / 21 ( 95%) | 2.5V | - | +| 2 | 17 / 20 ( 85%) | 2.5V | - | +| 3 | 17 / 20 ( 85%) | 2.5V | - | ++----------+----------------+------------+-----------+ + +Total placer CPU time: 4 secs + +Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. + +0 connections routed; 674 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. +WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=6 clock_loads=4 + +Completed router resource preassignment. Real time: 7 secs + +Start NBR router at 05:03:38 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:38 08/15/23 + +Start NBR section for initial routing at 05:03:38 08/15/23 +Level 1, iteration 1 +2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score; +Estimated worst slack/total negative slack: -5.186ns/-468.418ns; real time: 7 secs +Level 2, iteration 1 +11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-377.051ns; real time: 8 secs +Level 3, iteration 1 +20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-373.496ns; real time: 8 secs +Level 4, iteration 1 +11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-386.255ns; real time: 8 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:39 08/15/23 +Level 1, iteration 1 +7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-379.537ns; real time: 8 secs +Level 4, iteration 1 +9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-380.800ns; real time: 8 secs +Level 4, iteration 2 +6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-390.587ns; real time: 8 secs +Level 4, iteration 3 +6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs +Level 4, iteration 4 +6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs +Level 4, iteration 5 +4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs +Level 4, iteration 6 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs +Level 4, iteration 7 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs +Level 4, iteration 8 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs +Level 4, iteration 9 +2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs +Level 4, iteration 10 +3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs +Level 4, iteration 11 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs +Level 4, iteration 12 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs +Level 4, iteration 13 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs +Level 4, iteration 14 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs +Level 4, iteration 15 +2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 16 +3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 17 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs +Level 4, iteration 18 +1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs +Level 4, iteration 19 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 20 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 21 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 22 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 23 +1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs +Level 4, iteration 24 +1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs +Level 4, iteration 25 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:39 08/15/23 +Level 4, iteration 1 +1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-405.830ns; real time: 8 secs +Level 4, iteration 2 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for re-routing at 05:03:39 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for post-routing at 05:03:39 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 254 (37.69%) + Estimated worst slack : -4.650ns + Timing score : 391939 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=6 clock_loads=4 + +Total CPU time 7 secs +Total REAL time: 8 secs +Completely routed. +End of route. 674 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 391939 + +Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -4.650 +PAR_SUMMARY::Timing score> = 391.939 +PAR_SUMMARY::Worst slack> = 0.304 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 8 secs +Total REAL time to completion: 8 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1_par.asd b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1_par.asd new file mode 100644 index 0000000..38b1fbf --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/5_1_par.asd @@ -0,0 +1,38 @@ +[ActiveSupport PAR] +; Global primary clocks +GLOBAL_PRIMARY_USED = 2; +; Global primary clock #0 +GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; +GLOBAL_PRIMARY_0_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_0_LOADNUM = 40; +; Global primary clock #1 +GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; +GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_1_LOADNUM = 13; +; # of global secondary clocks +GLOBAL_SECONDARY_USED = 1; +; Global secondary clock #0 +GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c; +GLOBAL_SECONDARY_0_DRIVERTYPE = PIO; +GLOBAL_SECONDARY_0_LOADNUM = 9; +GLOBAL_SECONDARY_0_SIGTYPE = CLK; +; I/O Bank 0 Usage +BANK_0_USED = 13; +BANK_0_AVAIL = 19; +BANK_0_VCCIO = 2.5V; +BANK_0_VREF1 = NA; +; I/O Bank 1 Usage +BANK_1_USED = 20; +BANK_1_AVAIL = 21; +BANK_1_VCCIO = 2.5V; +BANK_1_VREF1 = NA; +; I/O Bank 2 Usage +BANK_2_USED = 17; +BANK_2_AVAIL = 20; +BANK_2_VCCIO = 2.5V; +BANK_2_VREF1 = NA; +; I/O Bank 3 Usage +BANK_3_USED = 17; +BANK_3_AVAIL = 20; +BANK_3_VCCIO = 2.5V; +BANK_3_VREF1 = NA; diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/RAM2GS_LCMXO2_1200HC_impl1.par b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/RAM2GS_LCMXO2_1200HC_impl1.par new file mode 100644 index 0000000..9d23cf4 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.dir/RAM2GS_LCMXO2_1200HC_impl1.par @@ -0,0 +1,28 @@ +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:31 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t +RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir +RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml + + +Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 -4.650 391939 0.304 0 08 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 8 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.drc b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.drc new file mode 100644 index 0000000..ec074a2 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.drc @@ -0,0 +1 @@ +DRC detected 0 errors and 0 warnings. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed new file mode 100644 index 0000000..8ec6c65 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed @@ -0,0 +1,2779 @@ +* +NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.* +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* +NOTE All Rights Reserved.* +NOTE DATE CREATED: Tue Aug 15 05:03:43 2023* +NOTE DESIGN NAME: RAM2GS_LCMXO2_1200HC_impl1.ncd* +NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100* +NOTE JEDEC FILE STATUS: Final Version 1.95* +NOTE PIN ASSIGNMENTS* +NOTE PINS RD[7] : 43 : inout* +NOTE PINS RD[6] : 42 : inout* +NOTE PINS RD[5] : 41 : inout* +NOTE PINS RD[4] : 40 : inout* +NOTE PINS RD[3] : 39 : inout* +NOTE PINS RD[2] : 38 : inout* +NOTE PINS RD[1] : 37 : inout* +NOTE PINS RD[0] : 36 : inout* +NOTE PINS Dout[7] : 82 : out* +NOTE PINS Dout[6] : 78 : out* +NOTE PINS Dout[5] : 84 : out* +NOTE PINS Dout[4] : 83 : out* +NOTE PINS Dout[3] : 85 : out* +NOTE PINS Dout[2] : 87 : out* +NOTE PINS Dout[1] : 86 : out* +NOTE PINS Dout[0] : 76 : out* +NOTE PINS LED : 34 : out* +NOTE PINS RBA[1] : 60 : out* +NOTE PINS RBA[0] : 58 : out* +NOTE PINS RA[11] : 59 : out* +NOTE PINS RA[10] : 64 : out* +NOTE PINS RA[9] : 63 : out* +NOTE PINS RA[8] : 65 : out* +NOTE PINS RA[7] : 75 : out* +NOTE PINS RA[6] : 68 : out* +NOTE PINS RA[5] : 70 : out* +NOTE PINS RA[4] : 74 : out* +NOTE PINS RA[3] : 71 : out* +NOTE PINS RA[2] : 69 : out* +NOTE PINS RA[1] : 67 : out* +NOTE PINS RA[0] : 66 : out* +NOTE PINS nRCS : 57 : out* +NOTE PINS RCKE : 53 : out* +NOTE PINS nRWE : 49 : out* +NOTE PINS nRRAS : 54 : out* +NOTE PINS nRCAS : 52 : out* +NOTE PINS RDQMH : 51 : out* +NOTE PINS RDQML : 48 : out* +NOTE PINS nUFMCS : 47 : out* +NOTE PINS UFMCLK : 29 : out* +NOTE PINS UFMSDI : 30 : out* +NOTE PINS PHI2 : 8 : in* +NOTE PINS MAin[9] : 32 : in* +NOTE PINS MAin[8] : 25 : in* +NOTE PINS MAin[7] : 18 : in* +NOTE PINS MAin[6] : 24 : in* +NOTE PINS MAin[5] : 19 : in* +NOTE PINS MAin[4] : 20 : in* +NOTE PINS MAin[3] : 21 : in* +NOTE PINS MAin[2] : 13 : in* +NOTE PINS MAin[1] : 12 : in* +NOTE PINS MAin[0] : 14 : in* +NOTE PINS CROW[1] : 16 : in* +NOTE PINS CROW[0] : 10 : in* +NOTE PINS Din[7] : 1 : in* +NOTE PINS Din[6] : 2 : in* +NOTE PINS Din[5] : 98 : in* +NOTE PINS Din[4] : 99 : in* +NOTE PINS Din[3] : 97 : in* +NOTE PINS Din[2] : 88 : in* +NOTE PINS Din[1] : 96 : in* +NOTE PINS Din[0] : 3 : in* +NOTE PINS nCCAS : 9 : in* +NOTE PINS nCRAS : 17 : in* +NOTE PINS nFWE : 28 : in* +NOTE PINS RCLK : 62 : in* +NOTE PINS UFMSDO : 27 : in* +QP100* +QF343936* +G0* +F0* +L000000 +11111111111111111011110110110011111111111111111100111011000000000000000000000000000000100000000000000000000000001100000000001010 +00000011001010000000010101010000010010001111111101000110000000000000000000000000101110001110000000000001010011010000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000100011000001000100100110000000000000000001000110000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010000000000000000000011 +00111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +01101001100111001000000000000000000000100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000001100010100000001001010000000100100000000000000000100011000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000010010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000010011100000010000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000 +00000000010010000000000000100110000001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000100010000000001000010000000001001100000000000010001100000100011000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000010000000000100001100111000000001001110000000000000000000100001000001000010000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000100000000000000000000000000000000 +00001000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000100010000000000000000000000000000000000000000000000000000000000000000000000010001010011100000000000000000000000000000000000 +00000000000000000000000000000100000000000000000000000000000000000000000100011000000000000000000000000000000000000000000000100110 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010100000000 +00000000000000000000000000100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000001000110000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000110000110000000001000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00100001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00001100001100000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000110000110000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100110000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100 +00110000000000010101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000100111000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000010101000000010001100001000011001110000000000000000010001100000000000000000000000000000000001000110000000000000000 +00000000000000000000000000100110000000000000000000000000000000000001001100000000000000000000000000000000000000000000000000000000 +00010010100000000000000000000000000000000000010011000000000000000000000000000000000000000000000000000000000000000000001001010000 +00000000000000000000000000000000000000000000000000000000000000000001001000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000100011100011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000100100000 +00000000000000000000000000000000000000000001001011001010000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000001001000000100001100111000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001010000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000110000100100000000000000000000000000000000000000000000000000 +00100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000100110000000000001001000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000100100000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000010011000000000100001000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000001100001001000000000100011000000000000000000000000000000000000000000001000100000 +00000000000001000100000000000000000000000000000000000000000000000000000000000000100011000000000000001000010001001010000000000000 +00000000000000000000000000010000000000000000000000100000000000000000000000000000000000000000000000000000000000000000010000100000 +00000000000010000000010010000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000011000010010000000110001010000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000100110100111000000000000000000000000010011000000000100010 +00000000000000000000100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000010101000000000000 +00000000000000010010000000000100000000000000000000000001001000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000001000010000000000000000000000000000000000000000000000000000000100010 +00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000 +00000000000001000000000000000000000000000000000000000001000110000000000000000000000000000000000100001000001001100010001000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000010010100000000000000000000000000000000000100 +01100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000101101000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000100100000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001100000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000001001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000001001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000101101000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000010001100000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001010000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101000000000001001010101001000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000110010010001000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000010010000001001110000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000010001010011100 +00000000000001001100000000000000000000000000000000000000000000000000000000000000000010000110011100000000000000000100011000000000 +00000000000000000000000010000100000000000010011000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000010010100000000000000000000000000000000000100110000000000000000100011000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000010010000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001000000000000000000 +00000000000000000000000010010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000 +11100000000000000000000000000000000000000000000000010010000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000001000010000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000010010000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000010001000000000000000000000000000000000000000000000000000000000000000000 +01001110000010010100000000000000000000000000000000000000000000000000000000000011000001110000000000000000000000000000000000000000 +00000000010000000000000000000000100001000000100100000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000010010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000101010000000000000010001000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000110000010000100000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000001001000000000010000110011100100111000000000010 +11000000010010100000100000000000000000000000000000000000000000000000000000000000000000000000000001000101001110000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000011100000 +00010010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000100001100111001000110000000010011100000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000001000100100111000010010100000001000100000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000011000001110000000000111001100000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000100010010011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000000000000 +00000011100000101001110000000000000000010001100010001000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000001000000000000000000000010000100000000000000000000000100000000000000000000000000000000000100011000000000000 +00000000000000010010000000000000000000000000000000000000000000000000000000000000000000000000000000001001010000000000000000000000 +00000000000010010100000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001100 +00010011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000010001000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000010110100000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000001000010000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100110000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +01001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000101111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000001010111001110000000000000000100010000001010111001110 +00000000000000000000010101110011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000100101001011000000100010000000000000100010001010110010011100000010001000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000001001011000110001000011101000101010011110011101000011001100000 +10000110011001001110010000110011010011000010000110011000100111000000000010011100000010011100000000000100011000010001100000000000 +00000000000000000001001010000000000000000000000000000000000000000110011000010011101001110000100110100001100001000100110000100011 +01001100000001000110101100000000000000000100001000000100001000000000000000001001010000000000000000000000000000010001100000000000 +00000000000000000000000001100010100100000000001000001000010000100000000010011010000000001100110000010001100000000000000000000000 +00000000000000010010100000000000000000000000000000000001001011000110000000000000000000000000000000000000001000100001001010000000 +00000000000010010001000100010011100010101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000011010000101001100010010000010011010011100100001100110010001000100001100110010000001000101000011101001001010011 +10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001000000000000000000000010011000 +00000000010011001000001011000010011001011000001001100000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000001000000000000000000000000011000101010000000110001010000010000000000100000001000100011100001010001000100000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001100000000011000100101010110100000 +11010010101001111100001110100000001000110001011000101010000111010100011000100101001111011100100100010000100000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000001101000011000000001000011001110000100111010000 +10000010110111000010010010011100010011000100001000100100000000000100000000010110100000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000001100010010111010000001000111000010100000000010011100100101000000100110010010 +01101011000010110011000010011000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000001000011001110000000001101000100000001000100010001001000110110100101011010000011001100100000110100000100000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000110100100000001001010100010 +10011101010100001001110101010000100111001100011010110001001011011000001001010100110010011010010110011100000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000011100010000100011000001110000100000000000100001 +00000010101110011111100001000100100100110100011001001100000000000000000000000000000000000000000000000000000000000000010011000000 +00000000000000000000000000000000011100000100110001010000000000001000101001110100001000001000011010010011000100011101000010000100 +00100111010001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001010 +00000100010110001010000000000010000100000010001010001100010010010000010000100000000000000000000000000000000000000000000000000000 +00000000000100011000000000000000000000000000000000000000000000010001110100111000110000100000001010101000100111000010100110101010 +01110000100011100001011000010010001011000011101010110111000100010010001000111001100000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000110011100000100001100101010011101000010110010100101001100100011011000 +01001010011001000110111010000000010001100000100101000001000011001110000000000000000000000000000000000000000000000000000000000000 +00000000000000001010100000000000000000000000001001100010110100100011010011010100101000101110001000010011001001000001001100110001 +00101100100100100000111000001010010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000100010000100010100010100010000100101010010001001010001001000100101000100110100000000100000001001110000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111001000111001001011000000100100010 +00011110000001010010010101010001001001111001111001001010101000100111000010110011000011100001101101010101000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101010000111001001001001110100101010 +01101000111000110100110010011001000110001001100000010000100100000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000010000000100000010011100100101100011100100110100001001001001110000100100011011010 +00010101001010011110001100100100100100010010011100001000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000100000100100000010000010010100100000100100010010100010010001001011000000011000010011 +00000111000100001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +01000001010000011100100000100001010010010100011111111001101001001110011111111111111001110010010110011111111111111001101001001110 +01111111111111100111001001011001111111011011010011110101010110011000001110111111110000011000111100110010000110100000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010100000010010100100100101000011000011 +01001110110000001100001101001110110000010100010001111101000101100110000011101111111100001111100011001001001010000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000101101001010111111011110110000100 +10000110000110100111011000000110000110100111011000001111111100110000110011000111010110011010001010000010100010010011011001100000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010001010101000000 +10000111001111111111111100110100000111001111111111111100111000001011001111111111111100110100000111001111111111111100111000001011 +00111111111111110010101011000111011111110000010000111110010000011111110111000011101100110000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000001011011001001000111011110011000010010010001011011010001000001111 +01001110010010001111110001001101101000100000111101001110010010001111110001001101101000100000111101001110010010000010011000000111 +00001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000110 +01110010000010000001100000110000100101000010000111001000011000000100110001000101001010001001000101011000000000000000000000000000 +01000100000000000000000000000000000000000001010010000000000000000000000000000000000000000000000100111101110110100001010000100100 +11110000100001001101000011101000010110001001010111001001001000011101000100010011110011110101011001000101101000010000000010011100 +00000000000000010001110001100010000010001100000000000000000000000000000100011000000000000100110000000000010001000000000000000000 +00000000100000010001110011010011100001001111000111010010101100011010001000100101000100110100111100001000010011100000000000000000 +00000000000001001010000000000000000000000000000000000010011010011000000000000000000010000000000000000000000000000000100001110001 +00011000001000110010011100000100011100000100001000010000010000110001110001101100110000101011100000100011000001000100000000000000 +00000100110100101000000000000000000000000000000000010011000000100100100100000000000000000000000000000000000000000000000100101100 +10001011001101011000101001100000001011000000100000010000001001111000100001000000000100000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000001000110000000000001001001100000110110100010110001101000101001111000010 +00101101010000110000110010110000100110100001010011010010101000010000100001000001001110000000000000000000000000000000000000000000 +00000000000000000000000000000001000100000000000000000001001010000000000001011001100100100110100001011100001001011111100101010111 +00001000100101000100001110010010011011000010000101001101001001101000100001010010000000000000000000000000000000000000000000000000 +00000000000000000000110000111100000000010000000000000000000000000000000000000100000100001000000000011100000011000111001010100010 +01000001000011001010110001000101100101001100001000000100010000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000101111100010001001010111100100010010011000100101000101110010010010111101000101001011001000 +01101000010110100010000110000110110110010000111000100101111101001010001110011101000110000000001001000101001000000000001000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000011011001010100111100000100101111010000011100100 +10010001110110110001000100001110110000010001110010010100110001001001100100100100110011100001001001101000110000010000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100100111110000100110011110111 +00100110100000101100001001000101101111000010010011110010010011011000010011010111001110100010111010000010011011101000101000111001 +10111000100000000000000000000000000000100001000000000000000000000000000000000000000011000011110000000000000000000000000000000000 +00000010001100010111011011000000110001001010001010000010011011100001000100000010000110111010011101000001000111001100010010001100 +00100110000110000010001010011001001100000000001001100000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000001001100101001100010110000011010010101000111101010101100000100011100110001101000010100111111000100011010001 +00001001001000001001001010100111010000011000010010100001010011100000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000010001100001001000100100010011101001100110110010010011100100100111000100011000010010110 +00110001001111001001001010100001101011100101001100011001010001100000000000000000000000000000000000000000000000000000000000000100 +00100000000000000000000000000000000000000000001001001001100110010010010010110011100010000100100101111010100010000111111001001000 +00100110010011010100101101110001111000000110101010011010010110110011110010001000010000000000000000000000000000000010000110011100 +00000000000000000000000000000000000000000000000000000000000000000010011000001101100000010000101001000111010000010001011100010001 +11000000111011100001001001001010100001100110000010000101100001100100100100101100010100001010011000000000000000000000000000000000 +00000000000000000000000000000001001110000000000000100111000000000000000000000000000000000000010011110011010111010010110100110010 +11000101000111100000110011101000011001110101001011010101001001110100100100000100101111000010010000110010110100101000011110001000 +00000010010001000000000000000000000000000000000000000000000000000000000100000000001100001111000000000000000000000000000000000000 +00000001000110101011010011101100001001010111100100011100101011110000101001100010110011100000100011000100010100001000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000110010001001101101000 +00110100110000110011010110100100101101010100100001110010000100100011000100101100100001010010100110100010010011001001010100011000 +00001000010000000000000000000000000000000000000000000000000000100010000000000000000000000000000000000000000000000000000001100000 +11010101000100101011010001101001101101000100001000101100000110100000100111100000111000100010110010000101110010000010011010001111 +00101001100100111001000010011000000100110000000000000000000000000000000000000000000000000000000000000110000111100100110001001101 +10001010000000000000000000000000000010011000001001010100010100011100111011010000101001010100110100110011110000011001101000001000 +00110001001001000011000000100000100110101011100100010010001100100110110111000000000000000000000000000000000000000000000000000000 +00000000000000000000000000001000110001001110000000000000000000000000000010010010010001000011001011110010000010011110101011000101 +00110000100111100100101000111000010010010111100110010100100100110101100001101010010100101010101100000000000000000000000000000000 +00000000000000000000000000000000000000000000010011000000000000000000000000000000000001000001101001001010100101100010001100011001 +11000100011001100001000100110001000111000100010010001000000010010111010001101100100100100110000000000000000000000000000000000000 +00000000000000000000000000000000010011110010000100011010001000000000000000000000000001001110000100001001001000010001110010010011 +01100000110000010001010001010011111100001001000011001011000111000011001010100110001001101000000000000000000000000000000000000000 +00000000000000000000000000000000000000000101111000000000000000000000000000000000000011110011001010000111001100110100001010001011 +11100001111101110110100001111111101101000100001101000111000100010011010100010000010000101110001000100110110010001011111100001000 +01111001000011111111011001100000000000000000000000000000000000000000000000000000000000000000000001001100000000000000000000000000 +00000000000110000011001110111011110110000011111100111110111111101110110111111110111110010011000100011111110000100011111111100111 +01111111100100101000010001110100001001001011011110001000100011110010001001001001110010011101000101100000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000011000001101100001111111010101011011100001110011001 +11110011001100001110110011001110100010010011000011001111111101001110101000110011000011000011011101111111110000110001000001001001 +11111000011011001101000110111010110010010000100011000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000001100110011111111110010000111001100111110001110100110101000110111111110000111001111111010000100000 +11111111011000011100011101101000101010011110011011000011111110000110110011010011010000111000011001000011111001100100001101010000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110110010010001110111100 +11000100101110100000011100001110010000000110100010100110001101110010010001111110001010011000110010100011111100011100110001100000 +00000000000000000000000000000000000000000000000000000000000000000000000001011110000000000000000000000000000000110011100000001000 +10100100000010000001101000100010011110000010000010000100111000100001011010100011000010010100000000000000000000000000000000000000 +00000000000000000000000000000000000000000100111000000000000000000000000000000000010001100111011000001001110010001011010010101000 +01111000001001000010011001000101100001100100111000110010001010011010101001001110110100101011010011011000111001110000000000000000 +00000000000000100011000000000000000000000000000000000000000000000010011000000000000000000000000000000010011010000111000110001001 +11001011110000100001111001000010010111001000010100010111000011001000111011110100011010011100010011000101100100110100111000000000 +00000000000000000000010001110010100000000000000000000000000000000000100110000000000000000000000000000000000000000001000010010000 +10100000000010011010000010001100011101100001101000001100000010010110001000001100010100011001110001000001000011000100000000000000 +00000000000000000100101000000000000000000000000000000000000100100000000000000000000000000000000000000000001100100100100000010010 +10100011001100100010100001100001100111100010000001001111010111001011000100010011110000010010010001000000000000100100000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000001000110000000100001100111010010001001101000011 +11000001010010100100011110100001011110010011000011001110110011000010000111001000100100000001000011000100010011101101001010110100 +00100000000000000000000000000010001100000000000000000000000000000000000000000000000000100010100010000001000100000000000000000000 +00111000010001011000100110011100000011001011111001000111100101001001010001010011000111000011001011110100000101100100110100001011 +01100100100111100011000100110010011010011000001001010000000000000000000000000000000000000000000000000000010110000000001011010000 +00000010000010000000000100000000000000000100101000000011000101010000100100100000010010100101111101011000011010000100100000100011 +01001001000011110000001010011110011000110010010110000001001001001000000000000000000000000010010100000000000000000000000000000000 +00000000000000000000000000000000000000000000000000100001100111100111111000100010100110000001000010010110010010010001110000010000 +10101111010010010001010010001110101000110001001011010000100100101110100101010010010000110000001001001000011001000000000000000000 +00000000000000000000000000000000000000000000000000000000001001000000000000000000000000000000001000010100001000000110100101011000 +00111100000110100001011001000111010011100011000100110110001001110010110010111100000101000011001101000110100011110110010111000010 +01010011010010110011101100110010100110000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000010000110011100000000010001100100111101001000100000100001000101001100011100001110001101001000111000011100010001110101000110 +00011001101000011010111000110100101100100000100000111010000000100001000000000000000000000000000000000000000000000000000000000000 +00001011010000000000000000000000000000000000000000010000000010001000101001010011111100010101011011001101001011001101010101001011 +00111101001100110100101010011110000000100111101111110001001110001010000101001011011110100000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000010001000111000100001000111000111000010110110010011110110001000 +10110011000001001011000111010010000100001011101000000100011110000011001001010011000100011101100000110100001000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000110100110100001111001000010011000111001 +00001001011101000001110010010111011000000111001000010101111100000011110000110111010000010001101010111100110000100100110010010110 +01001000011001101010010100011000000000000000000000000000000000000000000000000000000000000000000000000000000111001000000000000000 +01000011001110000000000000000000100110011001001001100100011100000001001110010011101101000100001000011100011000110100000110011110 +01011010011000011110000110100101010110010001100010101010100100000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000010000110011111100000101001100010001110011110001010011010000110010110000011000011001011101010110 +11101100000010000110010011001000010100101100111010000011010001001001110110000110110111001000000000000000000000000000000000000000 +00000000000000000000000000000000000000000010011100000000000000001000101110001000000000000001001110100100100000000010000111100010 +10100111010110010001110010011000101101100100010010110001010101001101101100110110110001101001110100011110000100100010001110010110 +01101001000000000000000000000000000000000000000000000000000000000000000000000101101000000000000000010011100000000100110000000000 +01000010111010000010011100100111010010101110100000100101001100100011010011101001101001110010111010001000100101111000010000010000 +00010000110011011100100000010010000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100000100 +00110011100000000000000101100010010101001010100000001000100001100010100100101110100000111001011001000010100100100110100111100000 +10111010110010001010000011101000001000000011000101010100000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000100011010000010011111010110000010000111001000100101010101101010000110001010000010001110 +00001001001110010100110010011001001111110000010100110100010010010000010011010001001001110010011000000000000000000000000000000000 +00000000000000000000000000000000101101000000010001101100100010000000000000000000000100111010000000100111111000000110011010010100 +10000110011111010001000110010100110010110111010001111010000101110000001100110100011010010110001001000010100001100011100011010110 +10000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011100000000100011000000000001000100010 +00010100011100010001001110010011111100000011000001001011000001000111001011000001101000100100010000100010100001001110100000100110 +11001000011000001001110100101100110100000100100000000000000000000000000000000000000000000000000000000000000010000000000000000000 +00000100101011010010010000000000000000000000000010101000110010010010000100100001010011000111000000111000110011000001100001011110 +10110000100010100111101011111010000010100110001010000001100001001010011010101110001110000111011000011000110000000000000000000000 +00000000000000000000000000000000000000010010000000000000001001000010110000000000001001100000000000000000001000011001011001101111 +01000010101011001011000100101001010011110101000100110100100101001010001001101000100000110010001010001110000011011000001001011001 +00100110000100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010001 +11000100000111111101110011011000011111111001010001100000110100110101000101000100001010100010011001100101110011111011111011110100 +00010100001100001111111001100101011011111110000010100011100010001001100000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000001010000001111111001110010111011010101011111001010110110000001100000110110000111 +01101011111111111111010001010011111111111011100101110101110111110111011011101001100100011101111110000011001010001001001111101110 +11100010011000111011011100010001100100101000111000100010001100000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000100010010001010010101111110001110000111010110110111011011000000110000100111000011101010001111001 +01011011101001010001101000100110000111010001110100011011100001111111011111111000011001011101100100010111111001111001100001100101 +01111110111011000101010001111001100100100010001110001100000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000001110111111001111110011101010111111001111111110100011111110011010101111110111111100101010000111 +11011111111101110110101001110111111100001101000101000101010110010001011111100110110010101111110111010110010001111101000001000010 +11010011001010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110111 +00110000110000110010111100110001101110010010001110111100110001101110010011000011001111000011001100011010111010000011000011001111 +00010000100001111010000010000011010001000010110110010010001111110001000011000110000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000100000000000111010000000100101100011101011001000101001100100001 +10010110011100001000000000000000000000000100100000000000000000000000000000000000000000000000100010100111000000000000000000000000 +00000000000000000000000100010010011100000101110100101000111010001010001010011000111001000011010000101001100000100001010000100000 +00000000000000000000000000100011000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000000101 +00100110100110011010001001011111001000011100010000110001001010111000001001010000000000000000000000000000000000000000000000000000 +00000000000000010011000000000000000000000000000000000000000000001110000001000000100000000100011100000100001101010010000110010110 +10110000000000000000000000000001001010000000000010010100000000000000000000000000000000001001000000000000000000000000000000000000 +00000000000001011100101011010001000001001110100001100111001001100010011100000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000010001000010011011001001101001010010011110001001110000100100101000110100 +00101001101000110100001000100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000001011000000000010011110011100000000000010010100000100011000000000000000000000000000000000000000000000000000000000000 +00000000110000110000000000000000000000000000000000000000000000000100000000101010100000100010100111000110100000110111010010101000 +10100111100010010010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000010010100001000011001101001000010010111010011001001101000101100100010111000010110000110011001000011000000110001001000001101 +00010001000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +01000101101010010110011010000001001101010111100000110011100000111110010011011101000001111000100100010100110010111111000110101001 +10110110000000000000000010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000100110001100110000010100110001111010001001001011000101001001000101000011101000100001001001000111000111011000111001000010 +11000000000000000000000000000000000000000000000000000000000000000000000000001100001100000000000000000000000000000000000000000000 +10001110000101110000001100011010011111000100011100010001101010100111010010010000110101111100110010100000100010100000100110101101 +00101011001000000000000010110100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00100010000000000010010110001011100001101011100100011101101111000100010000011010110100100110100111010001100000010000100000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000001001100000010011010 +01101000110100110101010011100001000101001100100100100000100010100011001001110000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000001000100010010000001011111001001000011101100000101011101100100101100 +00100110101010010011110011000001001100100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000010011100000010010001010011000000011000100101001101100110101110010000100100101010011000100111000100 +01000000000000000000000000000000000000000000000000000000000000000000000000100111000000000000000001001000000000000000100010000100 +11001001010001000011011101000101010110010111101010011011100100111001001111000110001001110010101100000000000000000000000000000000 +00000000000000000000000000000000000011000011000000000000000000000000000000000000000000000001000100010011110010111000010011000010 +01110000100111011000010000011000011000100011000000010011101000100010001100000000000100011000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000010010000001000000010100110010011001100011110001100100111010000010000011110 +10010110100000100011001100001010110011000101011000010110000011000010010100000000000100101000000000000000000000000000000000000000 +00000000000000000000000000000000000010011000000000000000100111000010010000001100110000011100010101001110100011100100100001100011 +10010010001110000010011001000110000000010011100000000000000000000000000000000000000000000000000000000000000000011000011000000000 +00000000000000000000000000000000000000010010101000011001101001100001000101110010000100011100110001100001001101011100000100001001 +00100111000000111100100000000010000100000000000000000000000000000000000000000000000000000000000000000000000001000110000000000000 +00000000000000000001000010000100100010000101100100010100000100110000010001010001001011001011011100001001100010100010000000000000 +00000000000000000000000000000000000000000000000000000000000000000000100100100010000000000000000000000000000000001000011001000100 +00000000110100001010010110001100011001100001101000010100001010010000110000100110011010011100000000000000000000000000000000000000 +00000000000000000000000000000000000000000010010001001011100110000000000000000000000000000000000000000100101001001000100010101110 +10011110001110010010011110001000111011000011100010011001110010001100000100000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000001010000110001010111101000000111111110110100001101111111001111 +11110111000111011001101010000100001101000111111111010011000100001110111111100000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000110111011100111010000011011100001010001111011111100011101000100010100 +01010100011000111011100001110111110111101001001100110011101000101100001100010100110111111100000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000011101011001100101100101000111010000011011000001000111 +11101111101010001000111001001111011111101111110000111010100001001001100010001101000100011001001001101100110000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001110101100100110111101111100010100001 +10111111110100010000110100010111110101011010101010100001110001000111111111001010100010000111011001100000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101110011000010101110011000100000 +01000101001100011000110111001000110000011100110001100000101011000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000010001010011100000000000000000100100000000000000000000000010001010011100000000000000000000 +00000001000101001110000000000000000000000000000000000000000000000000000000000000000000000000000000010010100000000000000000000000 +00000000000010001100000100011000000000001000110000010001100000000000000000000000000000000000000000000000000000000000000000000000 +10011100010001000000000000010001010010100000000000000000000010001010011010011100000000000000000000001001010000000000000000010011 +00000000000000000000000000000000000000000000000000000001000010000100000000000100011000000100111000000000000000000000011100100100 +00001001010000010011000000000000000000100110000000000001001000000000000000000011001100001100110000000000000000000000000000000000 +00000000000000000000000000000000000000000000100100000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000010010100000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000010001100000000000100101000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000100011000000000000010010010111000100111000001000000000001 +00110010011000000010001001001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +00111100111000000000001001111001111000000010010110001100001000010010001000000100011000000100101010010000100010000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000001000110000010001000000100001001001010010101010010 +10000000100000000100100000000001000110100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000011010001000000001001110000000000000000000000011001100000000000010010101001000001001110000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000010011000000100110000001010010000000000000000000000000001 +00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011000001000110000000 +00100011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +10001100100010001101000100000100111010001100000101110100111000010000110011100000000000000000000000000001000011001110000000000000 +00010001010011100000000000000000000000000000000000000000000000000000000000000000100101000100111011000010010010000100100101000100 +10101001010000000000101001000000000010010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000001010010000000001001100000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000100111000000010001000100110000100111000000000000000000000000000000010001000010011000000 +00000000000000000000000000000000000000000000000000000000000000000000000010110000000000000000001000000000010000100100011000100100 +00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100 +00000000011000101010000010010100000101011000000000000000000000000000100011000000000000000000000000000000000000000000000000000000 +00000000000000000000000111000100000000000000000000100110000001000101001110000000000000010010001001100000000000000000000000000000 +01001010000000000000000000000000000000000000000000000000011011010000000000000010001001001010000000000000000000010011010011101000 +10000000000000100011001100011000010001100000000000100011000000000000000001001100000000000000000000000000000000000000000000000000 +01000100000000000010010100000000000000010001010001100100010001100010010000000000100011000001001010000100111000000000000000000000 +00000000100110000000000000000000000000000000000000000000000000000000000000000001001100000000000000011101000000011010110001001110 +00010000000000010010100000000100010010010100000000000100111000000000000000001001000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000010000100000000000000000000000100001000000000000000000000001000010000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000001100110000000000000000000000000001100110000000000000000000000000001 +10011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101100001000000 +00000000001001011000010000000000000000000000100101100001000000000001000010000000000000000100101100001000000000000000000000000000 +00000000000000000000000010011000000000000100110000000000000000000000000000000000000000001001100000000000000000000000000000000000 +00000000000000000000000000000000000000000000000010011100000000000000000000000000000000000000000000000000000100111000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011100000000000000000010111000000000 +00000000000000011000111100000000000000000000000000000000000000000011000101000100000100000000000000000000000000000000000000000000 +00000000000101110000000000000000001011100000000000000000000000011000111100000000010000100000000000000000000110001010001000001000 +00000000001100010100010000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00010000110001101001111001110100001100011010011110011100000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000010000110001101001111001110000000100001100011010011110011101000011000110100111100111000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001110000001000110000010001101 +00111100011000000000000010011110001101001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000100101000000000000000111000101000000000000000000 +00000000000000000000010011100000000000000000100111000000000000000001001110000000000000000000000010011100000000000000000100111000 +00000000000000100111000000000000000001001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000100011101111110111111111111111111111111111111111111111111111111 +11111111111111111100001010000000000000000000000000000000000000000000000000000000001010101010011100100010000000000000000000000000 +01000000000000000000000000000000111111111111111111111111111111111111111111111111111111111111111101011110000000000000000000000000 +11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 +* +NOTE END CONFIG DATA* +L62976 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +* +C680B* +NOTE FEATURE_ROW* +E0000000000000000000000000000000000000000000000000000000000000000 +0000010001100000* +NOTE User Electronic Signature Data* +UH00000000* +8380 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.log b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.log new file mode 100644 index 0000000..d0353b8 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.log @@ -0,0 +1,4 @@ +---- MParTrce Tool Log File ---- + +==== Par Standard Out ==== +==== End of Par Standard Out ==== diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf new file mode 100644 index 0000000..2743d95 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf @@ -0,0 +1,4 @@ +#BLOCK ASYNCPATHS; +#BLOCK RESETPATHS; + +#FREQUENCY 200.000000 MHz; diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lsedata b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lsedata new file mode 100644 index 0000000..558a037 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lsedata @@ -0,0 +1,6331 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp new file mode 100644 index 0000000..8e79120 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp @@ -0,0 +1,402 @@ + + Lattice Mapping Report File for Design Module 'RAM2GS' + + +Design Information +------------------ + +Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial + RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr + RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf D:/O + neDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200 + HC_impl1.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RA + M2GS_LCMXO2_1200HC.lpf -c 0 -gui -msgset + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml +Target Vendor: LATTICE +Target Device: LCMXO2-1200HCTQFP100 +Target Performance: 4 +Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 +Mapped on: 08/15/23 05:03:26 + +Design Summary +-------------- + + Number of registers: 102 out of 1520 (7%) + PFU registers: 102 out of 1280 (8%) + PIO registers: 0 out of 240 (0%) + Number of SLICEs: 75 out of 640 (12%) + SLICEs as Logic/ROM: 75 out of 640 (12%) + SLICEs as RAM: 0 out of 480 (0%) + SLICEs as Carry: 10 out of 640 (2%) + Number of LUT4s: 143 out of 1280 (11%) + Number used as logic LUTs: 123 + Number used as distributed RAM: 0 + Number used as ripple logic: 20 + Number used as shift registers: 0 + Number of PIO sites used: 67 + 4(JTAG) out of 80 (89%) + Number of block RAMs: 0 out of 7 (0%) + Number of GSRs: 0 out of 1 (0%) + EFB used : No + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + POR : On + Bandgap : On + Number of Power Controller: 0 out of 1 (0%) + Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) + Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) + Number of DCCA: 0 out of 8 (0%) + Number of DCMA: 0 out of 2 (0%) + Number of PLLs: 0 out of 1 (0%) + Number of DQSDLLs: 0 out of 2 (0%) + Number of CLKDIVC: 0 out of 4 (0%) + Number of ECLKSYNCA: 0 out of 4 (0%) + Number of ECLKBRIDGECS: 0 out of 2 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of + distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and + ripple logic. + Number of clocks: 4 + Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) + + Page 1 + + + + +Design: RAM2GS Date: 08/15/23 05:03:26 + +Design Summary (cont) +--------------------- + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Number of Clock Enables: 14 + Net RCLK_c_enable_6: 4 loads, 4 LSLICEs + Net RCLK_c_enable_5: 2 loads, 2 LSLICEs + Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs + Net RCLK_c_enable_27: 8 loads, 8 LSLICEs + Net RCLK_c_enable_10: 3 loads, 3 LSLICEs + Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_16: 1 loads, 1 LSLICEs + Net RCLK_c_enable_28: 1 loads, 1 LSLICEs + Net RCLK_c_enable_15: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs + Net Ready_N_292: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs + Number of LSRs: 7 + Net RASr2: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net nRWE_N_177: 1 loads, 1 LSLICEs + Net C1Submitted_N_237: 2 loads, 2 LSLICEs + Net n2366: 2 loads, 2 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 18 loads + Net InitReady: 15 loads + Net RASr2: 15 loads + Net nRowColSel_N_35: 13 loads + Net nRowColSel: 12 loads + Net Din_c_4: 10 loads + Net MAin_c_1: 10 loads + Net Din_c_5: 9 loads + Net MAin_c_0: 9 loads + Net Din_c_0: 8 loads + + + + + Number of warnings: 0 + Number of errors: 0 + + +Design Errors/Warnings +---------------------- + + No errors or warnings present. + +IO (PIO) Attributes +------------------- + ++---------------------+-----------+-----------+------------+ +| IO Name | Direction | Levelmode | IO | + + Page 2 + + + + +Design: RAM2GS Date: 08/15/23 05:03:26 + +IO (PIO) Attributes (cont) +-------------------------- +| | | IO_TYPE | Register | ++---------------------+-----------+-----------+------------+ +| RD[7] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[6] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[5] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[4] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[3] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[2] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[1] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[0] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[7] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[6] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[5] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[4] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[3] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[2] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[1] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[0] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| LED | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RBA[1] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RBA[0] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[11] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[10] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[9] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[8] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[7] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[6] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[5] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[4] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ + + Page 3 + + + + +Design: RAM2GS Date: 08/15/23 05:03:26 + +IO (PIO) Attributes (cont) +-------------------------- +| RA[3] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[2] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[1] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[0] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nRCS | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RCKE | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nRWE | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nRRAS | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nRCAS | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RDQMH | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RDQML | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nUFMCS | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| UFMCLK | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| UFMSDI | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| PHI2 | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[9] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[8] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[7] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[6] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[5] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[4] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[3] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[2] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[1] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[0] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| CROW[1] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| CROW[0] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[7] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ + + Page 4 + + + + +Design: RAM2GS Date: 08/15/23 05:03:26 + +IO (PIO) Attributes (cont) +-------------------------- +| Din[6] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[5] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[4] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[3] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[2] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[1] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[0] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nCCAS | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nCRAS | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nFWE | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RCLK | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| UFMSDO | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ + +Removed logic +------------- + +Block i2 undriven or does not drive anything - clipped. +Block GSR_INST undriven or does not drive anything - clipped. +Signal PHI2_N_120 was merged into signal PHI2_c +Signal n1407 was merged into signal nRowColSel_N_34 +Signal n2380 was merged into signal Ready +Signal n1408 was merged into signal nRowColSel_N_35 +Signal nRWE_N_176 was merged into signal nRWE_N_177 +Signal GND_net undriven or does not drive anything - clipped. +Signal VCC_net undriven or does not drive anything - clipped. +Signal FS_610_add_4_19/S1 undriven or does not drive anything - clipped. +Signal FS_610_add_4_19/CO undriven or does not drive anything - clipped. +Signal FS_610_add_4_1/S0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_1/CI undriven or does not drive anything - clipped. +Block i2046 was optimized away. +Block i1118_1_lut was optimized away. +Block i637_1_lut_rep_31 was optimized away. +Block i1119_1_lut was optimized away. +Block nRWE_I_50_1_lut was optimized away. +Block i1 was optimized away. + + + +Run Time and Memory Usage +------------------------- + + Total CPU Time: 0 secs + Total REAL Time: 0 secs + Peak Memory Usage: 41 MB + + Page 5 + + + + +Design: RAM2GS Date: 08/15/23 05:03:26 + +Run Time and Memory Usage (cont) +-------------------------------- + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Page 6 + + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. + Copyright (c) 1995 AT&T Corp. All rights reserved. + Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. + Copyright (c) 2001 Agere Systems All rights reserved. + Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights + reserved. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mt b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mt new file mode 100644 index 0000000..2d70ad1 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.mt @@ -0,0 +1,9 @@ +-v +1 + + +-gt + + +-mapchkpnt 0 +-sethld diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.ncd b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.ncd new file mode 100644 index 0000000..c492e5d Binary files /dev/null and b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.ncd differ diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.ngd b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.ngd new file mode 100644 index 0000000..49ddeec Binary files /dev/null and b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.ngd differ diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p2t b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p2t new file mode 100644 index 0000000..16daf53 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p2t @@ -0,0 +1,9 @@ +-w +-l 5 +-i 6 +-n 1 +-t 1 +-s 1 +-c 0 +-e 0 +-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p3t b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p3t new file mode 100644 index 0000000..1635283 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.p3t @@ -0,0 +1,5 @@ +-rem +-distrce +-log "RAM2GS_LCMXO2_1200HC_impl1.log" +-o "RAM2GS_LCMXO2_1200HC_impl1.csv" +-pr "RAM2GS_LCMXO2_1200HC_impl1.prf" diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad new file mode 100644 index 0000000..dd18c97 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad @@ -0,0 +1,309 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO2-1200HC +Performance Grade: 4 +PACKAGE: TQFP100 +Package Status: Final Version 1.44 + +Tue Aug 15 05:03:35 2023 + +Pinout by Port Name: ++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | ++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ +| CROW[0] | 10/3 | LVCMOS25_IN | PL4B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| CROW[1] | 16/3 | LVCMOS25_IN | PL8A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[0] | 3/3 | LVCMOS25_IN | PL3A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[1] | 96/0 | LVCMOS25_IN | PT10B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[2] | 88/0 | LVCMOS25_IN | PT12A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[3] | 97/0 | LVCMOS25_IN | PT10A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[4] | 99/0 | LVCMOS25_IN | PT9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[5] | 98/0 | LVCMOS25_IN | PT9B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[6] | 2/3 | LVCMOS25_IN | PL2D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[7] | 1/3 | LVCMOS25_IN | PL2C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Dout[0] | 76/0 | LVCMOS25_OUT | PT17D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[1] | 86/0 | LVCMOS25_OUT | PT12C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[2] | 87/0 | LVCMOS25_OUT | PT12B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[3] | 85/0 | LVCMOS25_OUT | PT12D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[4] | 83/0 | LVCMOS25_OUT | PT15B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[5] | 84/0 | LVCMOS25_OUT | PT15A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[6] | 78/0 | LVCMOS25_OUT | PT16C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[7] | 82/0 | LVCMOS25_OUT | PT15C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| LED | 34/2 | LVCMOS25_OUT | PB9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| MAin[0] | 14/3 | LVCMOS25_IN | PL5C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[1] | 12/3 | LVCMOS25_IN | PL5A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[2] | 13/3 | LVCMOS25_IN | PL5B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[3] | 21/3 | LVCMOS25_IN | PL9B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[4] | 20/3 | LVCMOS25_IN | PL9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[5] | 19/3 | LVCMOS25_IN | PL8D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[6] | 24/3 | LVCMOS25_IN | PL10C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[7] | 18/3 | LVCMOS25_IN | PL8C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[8] | 25/3 | LVCMOS25_IN | PL10D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[9] | 32/2 | LVCMOS25_IN | PB6D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| PHI2 | 8/3 | LVCMOS25_IN | PL3D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| RA[0] | 66/1 | LVCMOS25_OUT | PR4D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[10] | 64/1 | LVCMOS25_OUT | PR5B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[11] | 59/1 | LVCMOS25_OUT | PR8D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[1] | 67/1 | LVCMOS25_OUT | PR4C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[2] | 69/1 | LVCMOS25_OUT | PR4A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[3] | 71/1 | LVCMOS25_OUT | PR3A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[4] | 74/1 | LVCMOS25_OUT | PR2B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[5] | 70/1 | LVCMOS25_OUT | PR3B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[6] | 68/1 | LVCMOS25_OUT | PR4B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[7] | 75/1 | LVCMOS25_OUT | PR2A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[8] | 65/1 | LVCMOS25_OUT | PR5A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[9] | 63/1 | LVCMOS25_OUT | PR5C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RBA[0] | 58/1 | LVCMOS25_OUT | PR9A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RBA[1] | 60/1 | LVCMOS25_OUT | PR8C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RCKE | 53/1 | LVCMOS25_OUT | PR9D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RCLK | 62/1 | LVCMOS25_IN | PR5D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| RDQMH | 51/1 | LVCMOS25_OUT | PR10D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RDQML | 48/2 | LVCMOS25_OUT | PB20C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RD[0] | 36/2 | LVCMOS25_BIDI | PB11C | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[1] | 37/2 | LVCMOS25_BIDI | PB11D | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[2] | 38/2 | LVCMOS25_BIDI | PB11A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[3] | 39/2 | LVCMOS25_BIDI | PB11B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[4] | 40/2 | LVCMOS25_BIDI | PB15A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[5] | 41/2 | LVCMOS25_BIDI | PB15B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[6] | 42/2 | LVCMOS25_BIDI | PB18A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[7] | 43/2 | LVCMOS25_BIDI | PB18B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| UFMCLK | 29/2 | LVCMOS25_OUT | PB6A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| UFMSDI | 30/2 | LVCMOS25_OUT | PB6B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| UFMSDO | 27/2 | LVCMOS25_IN | PB4C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nCCAS | 9/3 | LVCMOS25_IN | PL4A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nCRAS | 17/3 | LVCMOS25_IN | PL8B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nFWE | 28/2 | LVCMOS25_IN | PB4D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nRCAS | 52/1 | LVCMOS25_OUT | PR10C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nRCS | 57/1 | LVCMOS25_OUT | PR9B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nRRAS | 54/1 | LVCMOS25_OUT | PR9C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nRWE | 49/2 | LVCMOS25_OUT | PB20D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nUFMCS | 47/2 | LVCMOS25_OUT | PB18D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | ++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 2.5V | +| 1 | 2.5V | +| 2 | 2.5V | +| 3 | 2.5V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| 1/3 | Din[7] | LOCATED | LVCMOS25_IN | PL2C | L_GPLLT_IN | | | +| 2/3 | Din[6] | LOCATED | LVCMOS25_IN | PL2D | L_GPLLC_IN | | | +| 3/3 | Din[0] | LOCATED | LVCMOS25_IN | PL3A | PCLKT3_2 | | | +| 4/3 | unused, PULL:DOWN | | | PL3B | PCLKC3_2 | | | +| 7/3 | unused, PULL:DOWN | | | PL3C | | | | +| 8/3 | PHI2 | LOCATED | LVCMOS25_IN | PL3D | | | | +| 9/3 | nCCAS | LOCATED | LVCMOS25_IN | PL4A | | | | +| 10/3 | CROW[0] | LOCATED | LVCMOS25_IN | PL4B | | | | +| 12/3 | MAin[1] | LOCATED | LVCMOS25_IN | PL5A | PCLKT3_1 | | | +| 13/3 | MAin[2] | LOCATED | LVCMOS25_IN | PL5B | PCLKC3_1 | | | +| 14/3 | MAin[0] | LOCATED | LVCMOS25_IN | PL5C | | | | +| 15/3 | unused, PULL:DOWN | | | PL5D | | | | +| 16/3 | CROW[1] | LOCATED | LVCMOS25_IN | PL8A | | | | +| 17/3 | nCRAS | LOCATED | LVCMOS25_IN | PL8B | | | | +| 18/3 | MAin[7] | LOCATED | LVCMOS25_IN | PL8C | | | | +| 19/3 | MAin[5] | LOCATED | LVCMOS25_IN | PL8D | | | | +| 20/3 | MAin[4] | LOCATED | LVCMOS25_IN | PL9A | PCLKT3_0 | | | +| 21/3 | MAin[3] | LOCATED | LVCMOS25_IN | PL9B | PCLKC3_0 | | | +| 24/3 | MAin[6] | LOCATED | LVCMOS25_IN | PL10C | | | | +| 25/3 | MAin[8] | LOCATED | LVCMOS25_IN | PL10D | | | | +| 27/2 | UFMSDO | LOCATED | LVCMOS25_IN | PB4C | CSSPIN | | | +| 28/2 | nFWE | LOCATED | LVCMOS25_IN | PB4D | | | | +| 29/2 | UFMCLK | LOCATED | LVCMOS25_OUT | PB6A | | | | +| 30/2 | UFMSDI | LOCATED | LVCMOS25_OUT | PB6B | | | | +| 31/2 | unused, PULL:DOWN | | | PB6C | MCLK/CCLK | | | +| 32/2 | MAin[9] | LOCATED | LVCMOS25_IN | PB6D | SO/SPISO | | | +| 34/2 | LED | LOCATED | LVCMOS25_OUT | PB9A | PCLKT2_0 | | | +| 35/2 | unused, PULL:DOWN | | | PB9B | PCLKC2_0 | | | +| 36/2 | RD[0] | LOCATED | LVCMOS25_BIDI | PB11C | | | | +| 37/2 | RD[1] | LOCATED | LVCMOS25_BIDI | PB11D | | | | +| 38/2 | RD[2] | LOCATED | LVCMOS25_BIDI | PB11A | PCLKT2_1 | | | +| 39/2 | RD[3] | LOCATED | LVCMOS25_BIDI | PB11B | PCLKC2_1 | | | +| 40/2 | RD[4] | LOCATED | LVCMOS25_BIDI | PB15A | | | | +| 41/2 | RD[5] | LOCATED | LVCMOS25_BIDI | PB15B | | | | +| 42/2 | RD[6] | LOCATED | LVCMOS25_BIDI | PB18A | | | | +| 43/2 | RD[7] | LOCATED | LVCMOS25_BIDI | PB18B | | | | +| 45/2 | unused, PULL:DOWN | | | PB18C | | | | +| 47/2 | nUFMCS | | LVCMOS25_OUT | PB18D | | | | +| 48/2 | RDQML | LOCATED | LVCMOS25_OUT | PB20C | SN | | | +| 49/2 | nRWE | LOCATED | LVCMOS25_OUT | PB20D | SI/SISPI | | | +| 51/1 | RDQMH | LOCATED | LVCMOS25_OUT | PR10D | DQ1 | | | +| 52/1 | nRCAS | LOCATED | LVCMOS25_OUT | PR10C | DQ1 | | | +| 53/1 | RCKE | LOCATED | LVCMOS25_OUT | PR9D | DQ1 | | | +| 54/1 | nRRAS | LOCATED | LVCMOS25_OUT | PR9C | DQ1 | | | +| 57/1 | nRCS | LOCATED | LVCMOS25_OUT | PR9B | DQ1 | | | +| 58/1 | RBA[0] | LOCATED | LVCMOS25_OUT | PR9A | DQ1 | | | +| 59/1 | RA[11] | LOCATED | LVCMOS25_OUT | PR8D | DQ1 | | | +| 60/1 | RBA[1] | LOCATED | LVCMOS25_OUT | PR8C | DQ1 | | | +| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | | +| 62/1 | RCLK | LOCATED | LVCMOS25_IN | PR5D | PCLKC1_0/DQ0 | | | +| 63/1 | RA[9] | LOCATED | LVCMOS25_OUT | PR5C | PCLKT1_0/DQ0 | | | +| 64/1 | RA[10] | LOCATED | LVCMOS25_OUT | PR5B | DQS0N | | | +| 65/1 | RA[8] | LOCATED | LVCMOS25_OUT | PR5A | DQS0 | | | +| 66/1 | RA[0] | LOCATED | LVCMOS25_OUT | PR4D | DQ0 | | | +| 67/1 | RA[1] | LOCATED | LVCMOS25_OUT | PR4C | DQ0 | | | +| 68/1 | RA[6] | LOCATED | LVCMOS25_OUT | PR4B | DQ0 | | | +| 69/1 | RA[2] | LOCATED | LVCMOS25_OUT | PR4A | DQ0 | | | +| 70/1 | RA[5] | LOCATED | LVCMOS25_OUT | PR3B | DQ0 | | | +| 71/1 | RA[3] | LOCATED | LVCMOS25_OUT | PR3A | DQ0 | | | +| 74/1 | RA[4] | LOCATED | LVCMOS25_OUT | PR2B | DQ0 | | | +| 75/1 | RA[7] | LOCATED | LVCMOS25_OUT | PR2A | DQ0 | | | +| 76/0 | Dout[0] | LOCATED | LVCMOS25_OUT | PT17D | DONE | | | +| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | | +| 78/0 | Dout[6] | LOCATED | LVCMOS25_OUT | PT16C | | | | +| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | | +| 82/0 | Dout[7] | LOCATED | LVCMOS25_OUT | PT15C | JTAGENB | | | +| 83/0 | Dout[4] | LOCATED | LVCMOS25_OUT | PT15B | | | | +| 84/0 | Dout[5] | LOCATED | LVCMOS25_OUT | PT15A | | | | +| 85/0 | Dout[3] | LOCATED | LVCMOS25_OUT | PT12D | SDA/PCLKC0_0 | | | +| 86/0 | Dout[1] | LOCATED | LVCMOS25_OUT | PT12C | SCL/PCLKT0_0 | | | +| 87/0 | Dout[2] | LOCATED | LVCMOS25_OUT | PT12B | PCLKC0_1 | | | +| 88/0 | Din[2] | LOCATED | LVCMOS25_IN | PT12A | PCLKT0_1 | | | +| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | | +| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | | +| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | | +| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | | +| 96/0 | Din[1] | LOCATED | LVCMOS25_IN | PT10B | | | | +| 97/0 | Din[3] | LOCATED | LVCMOS25_IN | PT10A | | | | +| 98/0 | Din[5] | LOCATED | LVCMOS25_IN | PT9B | | | | +| 99/0 | Din[4] | LOCATED | LVCMOS25_IN | PT9A | | | | +| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | | +| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | | +| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | | +| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | | +| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | | +| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | | +| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | | +| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | | +| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | | +| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | | +| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | | +| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | | +| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | | +| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | | +| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | | +| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | | +| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | | +| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | | +| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | | +| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | | +| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | | +| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | | +| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | +| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | | +| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | | +| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | | +| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | | +| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ + +sysCONFIG Pins: ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | +| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | +| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | +| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | ++----------+--------------------+--------------------+----------+-------------+-------------------+ + +Dedicated sysCONFIG Pins: + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "10"; +LOCATE COMP "CROW[1]" SITE "16"; +LOCATE COMP "Din[0]" SITE "3"; +LOCATE COMP "Din[1]" SITE "96"; +LOCATE COMP "Din[2]" SITE "88"; +LOCATE COMP "Din[3]" SITE "97"; +LOCATE COMP "Din[4]" SITE "99"; +LOCATE COMP "Din[5]" SITE "98"; +LOCATE COMP "Din[6]" SITE "2"; +LOCATE COMP "Din[7]" SITE "1"; +LOCATE COMP "Dout[0]" SITE "76"; +LOCATE COMP "Dout[1]" SITE "86"; +LOCATE COMP "Dout[2]" SITE "87"; +LOCATE COMP "Dout[3]" SITE "85"; +LOCATE COMP "Dout[4]" SITE "83"; +LOCATE COMP "Dout[5]" SITE "84"; +LOCATE COMP "Dout[6]" SITE "78"; +LOCATE COMP "Dout[7]" SITE "82"; +LOCATE COMP "LED" SITE "34"; +LOCATE COMP "MAin[0]" SITE "14"; +LOCATE COMP "MAin[1]" SITE "12"; +LOCATE COMP "MAin[2]" SITE "13"; +LOCATE COMP "MAin[3]" SITE "21"; +LOCATE COMP "MAin[4]" SITE "20"; +LOCATE COMP "MAin[5]" SITE "19"; +LOCATE COMP "MAin[6]" SITE "24"; +LOCATE COMP "MAin[7]" SITE "18"; +LOCATE COMP "MAin[8]" SITE "25"; +LOCATE COMP "MAin[9]" SITE "32"; +LOCATE COMP "PHI2" SITE "8"; +LOCATE COMP "RA[0]" SITE "66"; +LOCATE COMP "RA[10]" SITE "64"; +LOCATE COMP "RA[11]" SITE "59"; +LOCATE COMP "RA[1]" SITE "67"; +LOCATE COMP "RA[2]" SITE "69"; +LOCATE COMP "RA[3]" SITE "71"; +LOCATE COMP "RA[4]" SITE "74"; +LOCATE COMP "RA[5]" SITE "70"; +LOCATE COMP "RA[6]" SITE "68"; +LOCATE COMP "RA[7]" SITE "75"; +LOCATE COMP "RA[8]" SITE "65"; +LOCATE COMP "RA[9]" SITE "63"; +LOCATE COMP "RBA[0]" SITE "58"; +LOCATE COMP "RBA[1]" SITE "60"; +LOCATE COMP "RCKE" SITE "53"; +LOCATE COMP "RCLK" SITE "62"; +LOCATE COMP "RDQMH" SITE "51"; +LOCATE COMP "RDQML" SITE "48"; +LOCATE COMP "RD[0]" SITE "36"; +LOCATE COMP "RD[1]" SITE "37"; +LOCATE COMP "RD[2]" SITE "38"; +LOCATE COMP "RD[3]" SITE "39"; +LOCATE COMP "RD[4]" SITE "40"; +LOCATE COMP "RD[5]" SITE "41"; +LOCATE COMP "RD[6]" SITE "42"; +LOCATE COMP "RD[7]" SITE "43"; +LOCATE COMP "UFMCLK" SITE "29"; +LOCATE COMP "UFMSDI" SITE "30"; +LOCATE COMP "UFMSDO" SITE "27"; +LOCATE COMP "nCCAS" SITE "9"; +LOCATE COMP "nCRAS" SITE "17"; +LOCATE COMP "nFWE" SITE "28"; +LOCATE COMP "nRCAS" SITE "52"; +LOCATE COMP "nRCS" SITE "57"; +LOCATE COMP "nRRAS" SITE "54"; +LOCATE COMP "nRWE" SITE "49"; +LOCATE COMP "nUFMCS" SITE "47"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:38 2023 + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.par b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.par new file mode 100644 index 0000000..89d3d6a --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.par @@ -0,0 +1,329 @@ +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:31 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t +RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir +RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml + + +Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 -4.650 391939 0.304 0 08 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 8 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" +Tue Aug 15 05:03:31 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67+4(JTAG)/108 66% used + 67+4(JTAG)/80 89% bonded + + SLICE 75/640 11% used + + + +Number of Signals: 285 +Number of Connections: 674 +WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors. + +Pin Constraint Summary: + 66 out of 67 pins locked (98% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + +WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + +WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +No signal is selected as Global Set/Reset. +. +Starting Placer Phase 0. +.......... +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +................... +Placer score = 143529. +Finished Placer Phase 1. REAL time: 4 secs + +Starting Placer Phase 2. +. +Placer score = 143450 +Finished Placer Phase 2. REAL time: 4 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 0 out of 8 (0%) + General PIO: 3 out of 108 (2%) + PLL : 0 out of 1 (0%) + DCM : 0 out of 2 (0%) + DCC : 0 out of 8 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 8 (25%) + SECONDARY: 1 out of 8 (12%) + +Edge Clocks: + No edge clock selected. + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 + 4(JTAG) out of 108 (65.7%) PIO sites used. + 67 + 4(JTAG) out of 80 (88.8%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+-----------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref | ++----------+----------------+------------+-----------+ +| 0 | 13 / 19 ( 68%) | 2.5V | - | +| 1 | 20 / 21 ( 95%) | 2.5V | - | +| 2 | 17 / 20 ( 85%) | 2.5V | - | +| 3 | 17 / 20 ( 85%) | 2.5V | - | ++----------+----------------+------------+-----------+ + +Total placer CPU time: 4 secs + +Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. + +0 connections routed; 674 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. +WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=6 clock_loads=4 + +Completed router resource preassignment. Real time: 7 secs + +Start NBR router at 05:03:38 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:38 08/15/23 + +Start NBR section for initial routing at 05:03:38 08/15/23 +Level 1, iteration 1 +2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score; +Estimated worst slack/total negative slack: -5.186ns/-468.418ns; real time: 7 secs +Level 2, iteration 1 +11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-377.051ns; real time: 8 secs +Level 3, iteration 1 +20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-373.496ns; real time: 8 secs +Level 4, iteration 1 +11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-386.255ns; real time: 8 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:39 08/15/23 +Level 1, iteration 1 +7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-379.537ns; real time: 8 secs +Level 4, iteration 1 +9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-380.800ns; real time: 8 secs +Level 4, iteration 2 +6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-390.587ns; real time: 8 secs +Level 4, iteration 3 +6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs +Level 4, iteration 4 +6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs +Level 4, iteration 5 +4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs +Level 4, iteration 6 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs +Level 4, iteration 7 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs +Level 4, iteration 8 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs +Level 4, iteration 9 +2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs +Level 4, iteration 10 +3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs +Level 4, iteration 11 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs +Level 4, iteration 12 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs +Level 4, iteration 13 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs +Level 4, iteration 14 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs +Level 4, iteration 15 +2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 16 +3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 17 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs +Level 4, iteration 18 +1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs +Level 4, iteration 19 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 20 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 21 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 22 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 23 +1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs +Level 4, iteration 24 +1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs +Level 4, iteration 25 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:39 08/15/23 +Level 4, iteration 1 +1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-405.830ns; real time: 8 secs +Level 4, iteration 2 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for re-routing at 05:03:39 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for post-routing at 05:03:39 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 254 (37.69%) + Estimated worst slack : -4.650ns + Timing score : 391939 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=6 clock_loads=4 + +Total CPU time 7 secs +Total REAL time: 8 secs +Completely routed. +End of route. 674 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 391939 + +Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -4.650 +PAR_SUMMARY::Timing score> = 391.939 +PAR_SUMMARY::Worst slack> = 0.304 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 8 secs +Total REAL time to completion: 8 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf new file mode 100644 index 0000000..0fcb3d2 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf @@ -0,0 +1,80 @@ +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:27 2023 + +SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "RD[7]" SITE "43" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[9]" SITE "63" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[7]" SITE "75" ; +LOCATE COMP "RA[6]" SITE "68" ; +LOCATE COMP "RA[5]" SITE "70" ; +LOCATE COMP "RA[4]" SITE "74" ; +LOCATE COMP "RA[3]" SITE "71" ; +LOCATE COMP "RA[2]" SITE "69" ; +LOCATE COMP "RA[1]" SITE "67" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "nRCS" SITE "57" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "UFMCLK" SITE "29" ; +LOCATE COMP "UFMSDI" SITE "30" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "MAin[9]" SITE "32" ; +LOCATE COMP "MAin[8]" SITE "25" ; +LOCATE COMP "MAin[7]" SITE "18" ; +LOCATE COMP "MAin[6]" SITE "24" ; +LOCATE COMP "MAin[5]" SITE "19" ; +LOCATE COMP "MAin[4]" SITE "20" ; +LOCATE COMP "MAin[3]" SITE "21" ; +LOCATE COMP "MAin[2]" SITE "13" ; +LOCATE COMP "MAin[1]" SITE "12" ; +LOCATE COMP "MAin[0]" SITE "14" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "CROW[0]" SITE "10" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "nFWE" SITE "28" ; +LOCATE COMP "RCLK" SITE "62" ; +LOCATE COMP "UFMSDO" SITE "27" ; +SCHEMATIC END ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +COMMERCIAL ; + +// No timing preferences found. TRCE invokes auto-generation of timing preferences +// Section Autogen +FREQUENCY NET "RCLK_c" 299.401 MHz ; +FREQUENCY NET "PHI2_c" 99.079 MHz ; +// End Section Autogen diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pt b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pt new file mode 100644 index 0000000..e5e32de --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.pt @@ -0,0 +1,10 @@ +-v +10 + + + + +-gt +-sethld +-sp 4 +-sphld m diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.t2b b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.t2b new file mode 100644 index 0000000..f5d2846 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.t2b @@ -0,0 +1,5 @@ + + +-g RamCfg:Reset + +-path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC" diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 new file mode 100644 index 0000000..278d419 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.tw1 @@ -0,0 +1,349 @@ + +Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:28 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd +Preference file: ram2gs_lcmxo2_1200hc_impl1.prf +Device,speed: LCMXO2-1200HC,4 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + 459 items scored, 245 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 3.815ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i13 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 6.873ns (28.2% logic, 71.8% route), 4 logic levels. + + Constraint Details: + + 6.873ns physical path delay SLICE_0 to SLICE_57 exceeds + 3.340ns delay constraint less + 0.282ns CE_SET requirement (totaling 3.058ns) by 3.815ns + + Physical Path Details: + + Data path SLICE_0 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 SLICE_0.CLK to SLICE_0.Q0 SLICE_0 (from RCLK_c) +ROUTE 3 e 1.234 SLICE_0.Q0 to SLICE_85.B0 FS_13 +CTOF_DEL --- 0.495 SLICE_85.B0 to SLICE_85.F0 SLICE_85 +ROUTE 5 e 1.234 SLICE_85.F0 to SLICE_57.A1 n10 +CTOF_DEL --- 0.495 SLICE_57.A1 to SLICE_57.F1 SLICE_57 +ROUTE 2 e 1.234 SLICE_57.F1 to SLICE_84.A0 n2367 +CTOF_DEL --- 0.495 SLICE_84.A0 to SLICE_84.F0 SLICE_84 +ROUTE 1 e 1.234 SLICE_84.F0 to SLICE_57.CE RCLK_c_enable_15 (to RCLK_c) + -------- + 6.873 (28.2% logic, 71.8% route), 4 logic levels. + +Warning: 139.762MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + 113 items scored, 104 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 4.837ns (weighted slack = -9.674ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels. + + Constraint Details: + + 9.577ns physical path delay SLICE_101 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.307ns CE_SET requirement (totaling 4.740ns) by 4.837ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 SLICE_101.CLK to SLICE_101.Q1 SLICE_101 (from PHI2_c) +ROUTE 1 e 1.234 SLICE_101.Q1 to SLICE_100.C1 Bank_7 +CTOF_DEL --- 0.495 SLICE_100.C1 to SLICE_100.F1 SLICE_100 +ROUTE 1 e 1.234 SLICE_100.F1 to SLICE_74.B1 n2277 +CTOF_DEL --- 0.495 SLICE_74.B1 to SLICE_74.F1 SLICE_74 +ROUTE 8 e 1.234 SLICE_74.F1 to SLICE_91.B1 n26 +CTOF_DEL --- 0.495 SLICE_91.B1 to SLICE_91.F1 SLICE_91 +ROUTE 1 e 1.234 SLICE_91.F1 to SLICE_88.D0 n2362 +CTOF_DEL --- 0.495 SLICE_88.D0 to SLICE_88.F0 SLICE_88 +ROUTE 3 e 0.480 SLICE_88.F0 to SLICE_88.C1 C1Submitted_N_237 +CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88 +ROUTE 1 e 1.234 SLICE_88.F1 to SLICE_19.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 9.577 (30.6% logic, 69.4% route), 6 logic levels. + +Warning: 50.592MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 299.401 MHz| 139.762 MHz| 4 * + | | | +FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 99.079 MHz| 50.592 MHz| 6 * + | | | +---------------------------------------------------------------------------- + + +2 preferences(marked by "*" above) not met. + +---------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +---------------------------------------------------------------------------- +n26 | 8| 78| 22.35% + | | | +---------------------------------------------------------------------------- + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 349 Score: 848079 +Cumulative negative slack: 584487 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:28 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd +Preference file: ram2gs_lcmxo2_1200hc_impl1.prf +Device,speed: LCMXO2-1200HC,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + 459 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.351ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i4 (from RCLK_c +) + Destination: FF Data in IS_FSM__i5 (to RCLK_c +) + + Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels. + + Constraint Details: + + 0.332ns physical path delay SLICE_106 to SLICE_106 meets + -0.019ns M_HLD and + 0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns + + Physical Path Details: + + Data path SLICE_106 to SLICE_106: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 SLICE_106.CLK to SLICE_106.Q0 SLICE_106 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_106.Q0 to SLICE_106.M1 n736 (to RCLK_c) + -------- + 0.332 (40.1% logic, 59.9% route), 1 logic levels. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + 113 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.447ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels. + + Constraint Details: + + 0.434ns physical path delay SLICE_15 to SLICE_15 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns + + Physical Path Details: + + Data path SLICE_15 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 SLICE_15.CLK to SLICE_15.Q0 SLICE_15 (from PHI2_c) +ROUTE 2 e 0.199 SLICE_15.Q0 to SLICE_15.C0 C1Submitted +CTOF_DEL --- 0.101 SLICE_15.C0 to SLICE_15.F0 SLICE_15 +ROUTE 1 e 0.001 SLICE_15.F0 to SLICE_15.DI0 n1398 (to PHI2_c) + -------- + 0.434 (53.9% logic, 46.1% route), 2 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 0.000 ns| 0.351 ns| 1 + | | | +FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 0.000 ns| 0.447 ns| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 349 (setup), 0 (hold) +Score: 848079 (setup), 0 (hold) +Cumulative negative slack: 584487 (584487+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr new file mode 100644 index 0000000..7c6f2bd --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.twr @@ -0,0 +1,2163 @@ + +Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:40 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Design file: ram2gs_lcmxo2_1200hc_impl1.ncd +Preference file: ram2gs_lcmxo2_1200hc_impl1.prf +Device,speed: LCMXO2-1200HC,4 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + 459 items scored, 247 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 2.400ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 5.574ns (43.6% logic, 56.4% route), 5 logic levels. + + Constraint Details: + + 5.574ns physical path delay SLICE_1 to SLICE_44 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.400ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C15C.CLK to R7C15C.Q1 SLICE_1 (from RCLK_c) +ROUTE 5 1.440 R7C15C.Q1 to R8C15A.B0 FS_12 +CTOF_DEL --- 0.495 R8C15A.B0 to R8C15A.F0 SLICE_105 +ROUTE 1 0.626 R8C15A.F0 to R8C15D.D1 n12 +CTOF_DEL --- 0.495 R8C15D.D1 to R8C15D.F1 SLICE_82 +ROUTE 3 0.640 R8C15D.F1 to R8C16B.D1 n13_adj_6 +CTOF_DEL --- 0.495 R8C16B.D1 to R8C16B.F1 SLICE_44 +ROUTE 1 0.436 R8C16B.F1 to R8C16B.C0 n1893 +CTOF_DEL --- 0.495 R8C16B.C0 to R8C16B.F0 SLICE_44 +ROUTE 1 0.000 R8C16B.F0 to R8C16B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 5.574 (43.6% logic, 56.4% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C15C.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R8C16B.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.383ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in InitReady_394 (to RCLK_c +) + + Delay: 5.441ns (35.6% logic, 64.4% route), 4 logic levels. + + Constraint Details: + + 5.441ns physical path delay SLICE_1 to SLICE_26 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.282ns CE_SET requirement (totaling 3.058ns) by 2.383ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_26: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C15C.CLK to R7C15C.Q1 SLICE_1 (from RCLK_c) +ROUTE 5 1.440 R7C15C.Q1 to R8C15A.B0 FS_12 +CTOF_DEL --- 0.495 R8C15A.B0 to R8C15A.F0 SLICE_105 +ROUTE 1 0.626 R8C15A.F0 to R8C15D.D1 n12 +CTOF_DEL --- 0.495 R8C15D.D1 to R8C15D.F1 SLICE_82 +ROUTE 3 0.453 R8C15D.F1 to R8C15D.C0 n13_adj_6 +CTOF_DEL --- 0.495 R8C15D.C0 to R8C15D.F0 SLICE_82 +ROUTE 1 0.985 R8C15D.F0 to R8C13D.CE RCLK_c_enable_28 (to RCLK_c) + -------- + 5.441 (35.6% logic, 64.4% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C15C.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_26: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R8C13D.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.217ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i16 (from RCLK_c +) + Destination: FF Data in nUFMCS_415 (to RCLK_c +) + + Delay: 5.391ns (45.1% logic, 54.9% route), 5 logic levels. + + Constraint Details: + + 5.391ns physical path delay SLICE_9 to SLICE_70 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.217ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_70: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q1 SLICE_9 (from RCLK_c) +ROUTE 3 1.017 R7C16A.Q1 to R7C16D.B0 FS_16 +CTOF_DEL --- 0.495 R7C16D.B0 to R7C16D.F0 SLICE_85 +ROUTE 5 0.340 R7C16D.F0 to R7C17A.D1 n10 +CTOF_DEL --- 0.495 R7C17A.D1 to R7C17A.F1 SLICE_76 +ROUTE 2 0.635 R7C17A.F1 to R7C17D.D1 n2368 +CTOF_DEL --- 0.495 R7C17D.D1 to R7C17D.F1 SLICE_70 +ROUTE 1 0.967 R7C17D.F1 to R7C17D.A0 n64 +CTOF_DEL --- 0.495 R7C17D.A0 to R7C17D.F0 SLICE_70 +ROUTE 1 0.000 R7C17D.F0 to R7C17D.DI0 nUFMCS_N_199 (to RCLK_c) + -------- + 5.391 (45.1% logic, 54.9% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_70: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C17D.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.180ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in nUFMCS_415 (to RCLK_c +) + + Delay: 5.354ns (45.4% logic, 54.6% route), 5 logic levels. + + Constraint Details: + + 5.354ns physical path delay SLICE_9 to SLICE_70 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.180ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_70: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q0 SLICE_9 (from RCLK_c) +ROUTE 3 0.980 R7C16A.Q0 to R7C16D.A0 FS_15 +CTOF_DEL --- 0.495 R7C16D.A0 to R7C16D.F0 SLICE_85 +ROUTE 5 0.340 R7C16D.F0 to R7C17A.D1 n10 +CTOF_DEL --- 0.495 R7C17A.D1 to R7C17A.F1 SLICE_76 +ROUTE 2 0.635 R7C17A.F1 to R7C17D.D1 n2368 +CTOF_DEL --- 0.495 R7C17D.D1 to R7C17D.F1 SLICE_70 +ROUTE 1 0.967 R7C17D.F1 to R7C17D.A0 n64 +CTOF_DEL --- 0.495 R7C17D.A0 to R7C17D.F0 SLICE_70 +ROUTE 1 0.000 R7C17D.F0 to R7C17D.DI0 nUFMCS_N_199 (to RCLK_c) + -------- + 5.354 (45.4% logic, 54.6% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_70: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C17D.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.166ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i16 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 5.340ns (45.5% logic, 54.5% route), 5 logic levels. + + Constraint Details: + + 5.340ns physical path delay SLICE_9 to SLICE_44 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.166ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q1 SLICE_9 (from RCLK_c) +ROUTE 3 1.206 R7C16A.Q1 to R8C15A.C0 FS_16 +CTOF_DEL --- 0.495 R8C15A.C0 to R8C15A.F0 SLICE_105 +ROUTE 1 0.626 R8C15A.F0 to R8C15D.D1 n12 +CTOF_DEL --- 0.495 R8C15D.D1 to R8C15D.F1 SLICE_82 +ROUTE 3 0.640 R8C15D.F1 to R8C16B.D1 n13_adj_6 +CTOF_DEL --- 0.495 R8C16B.D1 to R8C16B.F1 SLICE_44 +ROUTE 1 0.436 R8C16B.F1 to R8C16B.C0 n1893 +CTOF_DEL --- 0.495 R8C16B.C0 to R8C16B.F0 SLICE_44 +ROUTE 1 0.000 R8C16B.F0 to R8C16B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 5.340 (45.5% logic, 54.5% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R8C16B.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.158ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i16 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 5.332ns (45.6% logic, 54.4% route), 5 logic levels. + + Constraint Details: + + 5.332ns physical path delay SLICE_9 to SLICE_44 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.158ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q1 SLICE_9 (from RCLK_c) +ROUTE 3 1.017 R7C16A.Q1 to R7C16D.B0 FS_16 +CTOF_DEL --- 0.495 R7C16D.B0 to R7C16D.F0 SLICE_85 +ROUTE 5 0.461 R7C16D.F0 to R7C16D.C1 n10 +CTOF_DEL --- 0.495 R7C16D.C1 to R7C16D.F1 SLICE_85 +ROUTE 1 0.986 R7C16D.F1 to R8C16B.A1 n2267 +CTOF_DEL --- 0.495 R8C16B.A1 to R8C16B.F1 SLICE_44 +ROUTE 1 0.436 R8C16B.F1 to R8C16B.C0 n1893 +CTOF_DEL --- 0.495 R8C16B.C0 to R8C16B.F0 SLICE_44 +ROUTE 1 0.000 R8C16B.F0 to R8C16B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 5.332 (45.6% logic, 54.4% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R8C16B.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.149ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i16 (from RCLK_c +) + Destination: FF Data in InitReady_394 (to RCLK_c +) + + Delay: 5.207ns (37.2% logic, 62.8% route), 4 logic levels. + + Constraint Details: + + 5.207ns physical path delay SLICE_9 to SLICE_26 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.282ns CE_SET requirement (totaling 3.058ns) by 2.149ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_26: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q1 SLICE_9 (from RCLK_c) +ROUTE 3 1.206 R7C16A.Q1 to R8C15A.C0 FS_16 +CTOF_DEL --- 0.495 R8C15A.C0 to R8C15A.F0 SLICE_105 +ROUTE 1 0.626 R8C15A.F0 to R8C15D.D1 n12 +CTOF_DEL --- 0.495 R8C15D.D1 to R8C15D.F1 SLICE_82 +ROUTE 3 0.453 R8C15D.F1 to R8C15D.C0 n13_adj_6 +CTOF_DEL --- 0.495 R8C15D.C0 to R8C15D.F0 SLICE_82 +ROUTE 1 0.985 R8C15D.F0 to R8C13D.CE RCLK_c_enable_28 (to RCLK_c) + -------- + 5.207 (37.2% logic, 62.8% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_26: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R8C13D.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.131ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i7 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 5.189ns (37.3% logic, 62.7% route), 4 logic levels. + + Constraint Details: + + 5.189ns physical path delay SLICE_2 to SLICE_57 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.282ns CE_SET requirement (totaling 3.058ns) by 2.131ns + + Physical Path Details: + + Data path SLICE_2 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C15A.CLK to R7C15A.Q0 SLICE_2 (from RCLK_c) +ROUTE 3 1.086 R7C15A.Q0 to R8C14D.D0 FS_7 +CTOF_DEL --- 0.495 R8C14D.D0 to R8C14D.F0 SLICE_95 +ROUTE 1 0.747 R8C14D.F0 to R8C14A.C0 n15 +CTOF_DEL --- 0.495 R8C14A.C0 to R8C14A.F0 SLICE_86 +ROUTE 1 0.766 R8C14A.F0 to R8C16C.C0 n4_adj_7 +CTOF_DEL --- 0.495 R8C16C.C0 to R8C16C.F0 SLICE_84 +ROUTE 1 0.653 R8C16C.F0 to R8C16A.CE RCLK_c_enable_15 (to RCLK_c) + -------- + 5.189 (37.3% logic, 62.7% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_2: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C15A.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R8C16A.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.121ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 5.295ns (45.9% logic, 54.1% route), 5 logic levels. + + Constraint Details: + + 5.295ns physical path delay SLICE_9 to SLICE_44 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.121ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C16A.CLK to R7C16A.Q0 SLICE_9 (from RCLK_c) +ROUTE 3 0.980 R7C16A.Q0 to R7C16D.A0 FS_15 +CTOF_DEL --- 0.495 R7C16D.A0 to R7C16D.F0 SLICE_85 +ROUTE 5 0.461 R7C16D.F0 to R7C16D.C1 n10 +CTOF_DEL --- 0.495 R7C16D.C1 to R7C16D.F1 SLICE_85 +ROUTE 1 0.986 R7C16D.F1 to R8C16B.A1 n2267 +CTOF_DEL --- 0.495 R8C16B.A1 to R8C16B.F1 SLICE_44 +ROUTE 1 0.436 R8C16B.F1 to R8C16B.C0 n1893 +CTOF_DEL --- 0.495 R8C16B.C0 to R8C16B.F0 SLICE_44 +ROUTE 1 0.000 R8C16B.F0 to R8C16B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 5.295 (45.9% logic, 54.1% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C16A.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R8C16B.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.087ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in UFMSDI_417 (to RCLK_c +) + + Delay: 5.261ns (46.2% logic, 53.8% route), 5 logic levels. + + Constraint Details: + + 5.261ns physical path delay SLICE_1 to SLICE_45 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.087ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_45: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R7C15C.CLK to R7C15C.Q1 SLICE_1 (from RCLK_c) +ROUTE 5 0.786 R7C15C.Q1 to R8C15C.C1 FS_12 +CTOF_DEL --- 0.495 R8C15C.C1 to R8C15C.F1 SLICE_80 +ROUTE 3 0.640 R8C15C.F1 to R8C14D.D1 n2375 +CTOF_DEL --- 0.495 R8C14D.D1 to R8C14D.F1 SLICE_95 +ROUTE 1 0.967 R8C14D.F1 to R8C14C.A1 n7 +CTOF_DEL --- 0.495 R8C14C.A1 to R8C14C.F1 SLICE_45 +ROUTE 1 0.436 R8C14C.F1 to R8C14C.C0 n2174 +CTOF_DEL --- 0.495 R8C14C.C0 to R8C14C.F0 SLICE_45 +ROUTE 1 0.000 R8C14C.F0 to R8C14C.DI0 UFMSDI_N_231 (to RCLK_c) + -------- + 5.261 (46.2% logic, 53.8% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R7C15C.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_45: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 4.865 62.PADDI to R8C14C.CLK RCLK_c + -------- + 4.865 (0.0% logic, 100.0% route), 0 logic levels. + +Warning: 174.216MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + 113 items scored, 88 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 2.325ns (weighted slack = -4.650ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 7.065ns (41.4% logic, 58.6% route), 6 logic levels. + + Constraint Details: + + 7.065ns physical path delay SLICE_101 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 2.325ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16C.CLK to R9C16C.Q0 SLICE_101 (from PHI2_c) +ROUTE 1 0.986 R9C16C.Q0 to R9C14A.A0 Bank_6 +CTOF_DEL --- 0.495 R9C14A.A0 to R9C14A.F0 SLICE_68 +ROUTE 1 0.766 R9C14A.F0 to R9C15B.C1 n2287 +CTOF_DEL --- 0.495 R9C15B.C1 to R9C15B.F1 SLICE_74 +ROUTE 8 0.662 R9C15B.F1 to R9C14D.D1 n26 +CTOF_DEL --- 0.495 R9C14D.D1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 0.445 R9C14C.F0 to R9C14C.C1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R9C14C.C1 to R9C14C.F1 SLICE_88 +ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 7.065 (41.4% logic, 58.6% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16C.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.287ns (weighted slack = -4.574ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i1 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 7.027ns (41.7% logic, 58.3% route), 6 logic levels. + + Constraint Details: + + 7.027ns physical path delay SLICE_93 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 2.287ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16A.CLK to R9C16A.Q1 SLICE_93 (from PHI2_c) +ROUTE 1 0.744 R9C16A.Q1 to R9C15C.C1 Bank_1 +CTOF_DEL --- 0.495 R9C15C.C1 to R9C15C.F1 SLICE_99 +ROUTE 2 0.635 R9C15C.F1 to R9C15D.D1 n22 +CTOF_DEL --- 0.495 R9C15D.D1 to R9C15D.F1 SLICE_79 +ROUTE 7 0.997 R9C15D.F1 to R9C14D.A1 n2369 +CTOF_DEL --- 0.495 R9C14D.A1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 0.445 R9C14C.F0 to R9C14C.C1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R9C14C.C1 to R9C14C.F1 SLICE_88 +ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 7.027 (41.7% logic, 58.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16A.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.166ns (weighted slack = -4.332ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i4 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.906ns (42.4% logic, 57.6% route), 6 logic levels. + + Constraint Details: + + 6.906ns physical path delay SLICE_102 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 2.166ns + + Physical Path Details: + + Data path SLICE_102 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R8C15B.CLK to R8C15B.Q0 SLICE_102 (from PHI2_c) +ROUTE 1 0.623 R8C15B.Q0 to R9C15C.D1 Bank_4 +CTOF_DEL --- 0.495 R9C15C.D1 to R9C15C.F1 SLICE_99 +ROUTE 2 0.635 R9C15C.F1 to R9C15D.D1 n22 +CTOF_DEL --- 0.495 R9C15D.D1 to R9C15D.F1 SLICE_79 +ROUTE 7 0.997 R9C15D.F1 to R9C14D.A1 n2369 +CTOF_DEL --- 0.495 R9C14D.A1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 0.445 R9C14C.F0 to R9C14C.C1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R9C14C.C1 to R9C14C.F1 SLICE_88 +ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.906 (42.4% logic, 57.6% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_102: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R8C15B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.984ns (weighted slack = -3.968ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i3 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.724ns (43.5% logic, 56.5% route), 6 logic levels. + + Constraint Details: + + 6.724ns physical path delay SLICE_103 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 1.984ns + + Physical Path Details: + + Data path SLICE_103 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16D.CLK to R9C16D.Q1 SLICE_103 (from PHI2_c) +ROUTE 1 0.645 R9C16D.Q1 to R9C14A.D0 Bank_3 +CTOF_DEL --- 0.495 R9C14A.D0 to R9C14A.F0 SLICE_68 +ROUTE 1 0.766 R9C14A.F0 to R9C15B.C1 n2287 +CTOF_DEL --- 0.495 R9C15B.C1 to R9C15B.F1 SLICE_74 +ROUTE 8 0.662 R9C15B.F1 to R9C14D.D1 n26 +CTOF_DEL --- 0.495 R9C14D.D1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 0.445 R9C14C.F0 to R9C14C.C1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R9C14C.C1 to R9C14C.F1 SLICE_88 +ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.724 (43.5% logic, 56.5% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_103: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16D.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.874ns (weighted slack = -3.748ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.614ns (44.3% logic, 55.7% route), 6 logic levels. + + Constraint Details: + + 6.614ns physical path delay SLICE_101 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 1.874ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16C.CLK to R9C16C.Q1 SLICE_101 (from PHI2_c) +ROUTE 1 0.986 R9C16C.Q1 to R9C15A.A1 Bank_7 +CTOF_DEL --- 0.495 R9C15A.A1 to R9C15A.F1 SLICE_100 +ROUTE 1 0.315 R9C15A.F1 to R9C15B.D1 n2277 +CTOF_DEL --- 0.495 R9C15B.D1 to R9C15B.F1 SLICE_74 +ROUTE 8 0.662 R9C15B.F1 to R9C14D.D1 n26 +CTOF_DEL --- 0.495 R9C14D.D1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 0.445 R9C14C.F0 to R9C14C.C1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R9C14C.C1 to R9C14C.F1 SLICE_88 +ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.614 (44.3% logic, 55.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16C.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.803ns (weighted slack = -3.606ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 6.565ns (37.0% logic, 63.0% route), 5 logic levels. + + Constraint Details: + + 6.565ns physical path delay SLICE_101 to SLICE_10 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.803ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16C.CLK to R9C16C.Q0 SLICE_101 (from PHI2_c) +ROUTE 1 0.986 R9C16C.Q0 to R9C14A.A0 Bank_6 +CTOF_DEL --- 0.495 R9C14A.A0 to R9C14A.F0 SLICE_68 +ROUTE 1 0.766 R9C14A.F0 to R9C15B.C1 n2287 +CTOF_DEL --- 0.495 R9C15B.C1 to R9C15B.F1 SLICE_74 +ROUTE 8 0.662 R9C15B.F1 to R9C14D.D1 n26 +CTOF_DEL --- 0.495 R9C14D.D1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 1.093 R9C14C.F0 to R10C14B.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 6.565 (37.0% logic, 63.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16C.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R10C14B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.803ns (weighted slack = -3.606ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 6.565ns (37.0% logic, 63.0% route), 5 logic levels. + + Constraint Details: + + 6.565ns physical path delay SLICE_101 to SLICE_15 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.803ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16C.CLK to R9C16C.Q0 SLICE_101 (from PHI2_c) +ROUTE 1 0.986 R9C16C.Q0 to R9C14A.A0 Bank_6 +CTOF_DEL --- 0.495 R9C14A.A0 to R9C14A.F0 SLICE_68 +ROUTE 1 0.766 R9C14A.F0 to R9C15B.C1 n2287 +CTOF_DEL --- 0.495 R9C15B.C1 to R9C15B.F1 SLICE_74 +ROUTE 8 0.662 R9C15B.F1 to R9C14D.D1 n26 +CTOF_DEL --- 0.495 R9C14D.D1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 1.093 R9C14C.F0 to R10C14C.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 6.565 (37.0% logic, 63.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16C.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R10C14C.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.765ns (weighted slack = -3.530ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i1 (from PHI2_c +) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 6.527ns (37.3% logic, 62.7% route), 5 logic levels. + + Constraint Details: + + 6.527ns physical path delay SLICE_93 to SLICE_10 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.765ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16A.CLK to R9C16A.Q1 SLICE_93 (from PHI2_c) +ROUTE 1 0.744 R9C16A.Q1 to R9C15C.C1 Bank_1 +CTOF_DEL --- 0.495 R9C15C.C1 to R9C15C.F1 SLICE_99 +ROUTE 2 0.635 R9C15C.F1 to R9C15D.D1 n22 +CTOF_DEL --- 0.495 R9C15D.D1 to R9C15D.F1 SLICE_79 +ROUTE 7 0.997 R9C15D.F1 to R9C14D.A1 n2369 +CTOF_DEL --- 0.495 R9C14D.A1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 1.093 R9C14C.F0 to R10C14B.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 6.527 (37.3% logic, 62.7% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16A.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R10C14B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.765ns (weighted slack = -3.530ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i1 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 6.527ns (37.3% logic, 62.7% route), 5 logic levels. + + Constraint Details: + + 6.527ns physical path delay SLICE_93 to SLICE_15 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.765ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16A.CLK to R9C16A.Q1 SLICE_93 (from PHI2_c) +ROUTE 1 0.744 R9C16A.Q1 to R9C15C.C1 Bank_1 +CTOF_DEL --- 0.495 R9C15C.C1 to R9C15C.F1 SLICE_99 +ROUTE 2 0.635 R9C15C.F1 to R9C15D.D1 n22 +CTOF_DEL --- 0.495 R9C15D.D1 to R9C15D.F1 SLICE_79 +ROUTE 7 0.997 R9C15D.F1 to R9C14D.A1 n2369 +CTOF_DEL --- 0.495 R9C14D.A1 to R9C14D.F1 SLICE_91 +ROUTE 1 0.626 R9C14D.F1 to R9C14C.D0 n2362 +CTOF_DEL --- 0.495 R9C14C.D0 to R9C14C.F0 SLICE_88 +ROUTE 3 1.093 R9C14C.F0 to R10C14C.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 6.527 (37.3% logic, 62.7% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16A.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R10C14C.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.750ns (weighted slack = -3.500ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.490ns (37.5% logic, 62.5% route), 5 logic levels. + + Constraint Details: + + 6.490ns physical path delay SLICE_101 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 1.750ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R9C16C.CLK to R9C16C.Q0 SLICE_101 (from PHI2_c) +ROUTE 1 0.986 R9C16C.Q0 to R9C14A.A0 Bank_6 +CTOF_DEL --- 0.495 R9C14A.A0 to R9C14A.F0 SLICE_68 +ROUTE 1 0.766 R9C14A.F0 to R9C15B.C1 n2287 +CTOF_DEL --- 0.495 R9C15B.C1 to R9C15B.F1 SLICE_74 +ROUTE 8 0.688 R9C15B.F1 to R10C15C.D0 n26 +CTOF_DEL --- 0.495 R10C15C.D0 to R10C15C.F0 SLICE_104 +ROUTE 2 0.965 R10C15C.F0 to R9C14C.D1 n2363 +CTOF_DEL --- 0.495 R9C14C.D1 to R9C14C.F1 SLICE_88 +ROUTE 1 0.653 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.490 (37.5% logic, 62.5% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C16C.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.498 8.PADDI to R9C14B.CLK PHI2_c + -------- + 3.498 (0.0% logic, 100.0% route), 0 logic levels. + +Warning: 67.833MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 299.401 MHz| 174.216 MHz| 5 * + | | | +FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 99.079 MHz| 67.833 MHz| 6 * + | | | +---------------------------------------------------------------------------- + + +2 preferences(marked by "*" above) not met. + +---------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +---------------------------------------------------------------------------- +n26 | 8| 64| 19.10% + | | | +n1996 | 1| 49| 14.63% + | | | +n1997 | 1| 46| 13.73% + | | | +n1995 | 1| 45| 13.43% + | | | +n1998 | 1| 38| 11.34% + | | | +n1994 | 1| 37| 11.04% + | | | +---------------------------------------------------------------------------- + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 335 Score: 391939 +Cumulative negative slack: 304509 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:40 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Design file: ram2gs_lcmxo2_1200hc_impl1.ncd +Preference file: ram2gs_lcmxo2_1200hc_impl1.prf +Device,speed: LCMXO2-1200HC,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + 459 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i4 (from RCLK_c +) + Destination: FF Data in IS_FSM__i5 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_106 to SLICE_106 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_106 to SLICE_106: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R10C13B.CLK to R10C13B.Q0 SLICE_106 (from RCLK_c) +ROUTE 1 0.152 R10C13B.Q0 to R10C13B.M1 n736 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_106: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R10C13B.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_106: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R10C13B.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CASr_382 (from RCLK_c +) + Destination: FF Data in CASr2_383 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_16 to SLICE_16 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_16 to SLICE_16: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R7C12B.CLK to R7C12B.Q0 SLICE_16 (from RCLK_c) +ROUTE 1 0.152 R7C12B.Q0 to R7C12B.M1 CASr (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_16: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R7C12B.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_16: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R7C12B.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i8 (from RCLK_c +) + Destination: FF Data in IS_FSM__i9 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_75 to SLICE_75 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_75 to SLICE_75: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R10C13D.CLK to R10C13D.Q0 SLICE_75 (from RCLK_c) +ROUTE 1 0.152 R10C13D.Q0 to R10C13D.M1 n732 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R10C13D.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R10C13D.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i12 (from RCLK_c +) + Destination: FF Data in IS_FSM__i13 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_78 to SLICE_78 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_78 to SLICE_78: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R8C12B.CLK to R8C12B.Q0 SLICE_78 (from RCLK_c) +ROUTE 1 0.152 R8C12B.Q0 to R8C12B.M1 n728 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_78: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C12B.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_78: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C12B.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i14 (from RCLK_c +) + Destination: FF Data in IS_FSM__i15 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_81 to SLICE_81 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_81 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R9C12A.CLK to R9C12A.Q0 SLICE_81 (from RCLK_c) +ROUTE 1 0.152 R9C12A.Q0 to R9C12A.M1 n726 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R9C12A.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R9C12A.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i2 (from RCLK_c +) + Destination: FF Data in IS_FSM__i3 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_84 to SLICE_84 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_84 to SLICE_84: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R8C16C.CLK to R8C16C.Q0 SLICE_84 (from RCLK_c) +ROUTE 1 0.152 R8C16C.Q0 to R8C16C.M1 n738 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_84: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C16C.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_84: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C16C.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i6 (from RCLK_c +) + Destination: FF Data in IS_FSM__i7 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_97 to SLICE_97 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_97 to SLICE_97: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R10C14A.CLK to R10C14A.Q0 SLICE_97 (from RCLK_c) +ROUTE 1 0.152 R10C14A.Q0 to R10C14A.M1 n734 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_97: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R10C14A.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_97: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R10C14A.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.306ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr_379 (from RCLK_c +) + Destination: FF Data in RASr2_380 (to RCLK_c +) + + Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. + + Constraint Details: + + 0.287ns physical path delay SLICE_30 to SLICE_30 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.306ns + + Physical Path Details: + + Data path SLICE_30 to SLICE_30: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R8C13B.CLK to R8C13B.Q0 SLICE_30 (from RCLK_c) +ROUTE 2 0.154 R8C13B.Q0 to R8C13B.M1 RASr (to RCLK_c) + -------- + 0.287 (46.3% logic, 53.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_30: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C13B.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_30: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C13B.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.306ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i1 (from RCLK_c +) + Destination: FF Data in IS_FSM__i2 (to RCLK_c +) + + Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. + + Constraint Details: + + 0.287ns physical path delay SLICE_98 to SLICE_84 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.306ns + + Physical Path Details: + + Data path SLICE_98 to SLICE_84: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R8C16D.CLK to R8C16D.Q1 SLICE_98 (from RCLK_c) +ROUTE 4 0.154 R8C16D.Q1 to R8C16C.M0 nRCAS_N_165 (to RCLK_c) + -------- + 0.287 (46.3% logic, 53.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_98: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C16D.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_84: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C16C.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.306ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i0 (from RCLK_c +) + Destination: FF Data in IS_FSM__i1 (to RCLK_c +) + + Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. + + Constraint Details: + + 0.287ns physical path delay SLICE_98 to SLICE_98 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.306ns + + Physical Path Details: + + Data path SLICE_98 to SLICE_98: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R8C16D.CLK to R8C16D.Q0 SLICE_98 (from RCLK_c) +ROUTE 4 0.154 R8C16D.Q0 to R8C16D.M1 nRCS_N_139 (to RCLK_c) + -------- + 0.287 (46.3% logic, 53.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_98: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C16D.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_98: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.668 62.PADDI to R8C16D.CLK RCLK_c + -------- + 1.668 (0.0% logic, 100.0% route), 0 logic levels. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + 113 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_15 to SLICE_15 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_15 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R10C14C.CLK to R10C14C.Q0 SLICE_15 (from PHI2_c) +ROUTE 2 0.132 R10C14C.Q0 to R10C14C.A0 C1Submitted +CTOF_DEL --- 0.101 R10C14C.A0 to R10C14C.F0 SLICE_15 +ROUTE 1 0.000 R10C14C.F0 to R10C14C.DI0 n1398 (to PHI2_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R10C14C.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R10C14C.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.629ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_407 (from PHI2_c -) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 0.601ns (38.9% logic, 61.1% route), 2 logic levels. + + Constraint Details: + + 0.601ns physical path delay SLICE_10 to SLICE_19 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.629ns + + Physical Path Details: + + Data path SLICE_10 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R10C14B.CLK to R10C14B.Q0 SLICE_10 (from PHI2_c) +ROUTE 1 0.224 R10C14B.Q0 to R9C14C.B1 ADSubmitted +CTOF_DEL --- 0.101 R9C14C.B1 to R9C14C.F1 SLICE_88 +ROUTE 1 0.143 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 0.601 (38.9% logic, 61.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R10C14B.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.715ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in XOR8MEG_408 (to PHI2_c -) + + Delay: 0.687ns (34.1% logic, 65.9% route), 2 logic levels. + + Constraint Details: + + 0.687ns physical path delay SLICE_19 to SLICE_50 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.715ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_50: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R9C14B.CLK to R9C14B.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.310 R9C14B.Q0 to R10C15B.B1 CmdEnable +CTOF_DEL --- 0.101 R10C15B.B1 to R10C15B.F1 SLICE_83 +ROUTE 1 0.143 R10C15B.F1 to R10C15D.CE PHI2_N_120_enable_3 (to PHI2_c) + -------- + 0.687 (34.1% logic, 65.9% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_50: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R10C15D.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.873ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) + FF CmdUFMCLK_413 + + Delay: 0.845ns (39.6% logic, 60.4% route), 3 logic levels. + + Constraint Details: + + 0.845ns physical path delay SLICE_19 to SLICE_100 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.873ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R9C14B.CLK to R9C14B.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.224 R9C14B.Q0 to R10C15A.C0 CmdEnable +CTOF_DEL --- 0.101 R10C15A.C0 to R10C15A.F0 SLICE_73 +ROUTE 2 0.138 R10C15A.F0 to R10C15A.C1 n2204 +CTOF_DEL --- 0.101 R10C15A.C1 to R10C15A.F1 SLICE_73 +ROUTE 2 0.148 R10C15A.F1 to R9C15A.CE PHI2_N_120_enable_8 (to PHI2_c) + -------- + 0.845 (39.6% logic, 60.4% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C15A.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.873ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) + + Delay: 0.845ns (39.6% logic, 60.4% route), 3 logic levels. + + Constraint Details: + + 0.845ns physical path delay SLICE_19 to SLICE_99 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.873ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R9C14B.CLK to R9C14B.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.224 R9C14B.Q0 to R10C15A.C0 CmdEnable +CTOF_DEL --- 0.101 R10C15A.C0 to R10C15A.F0 SLICE_73 +ROUTE 2 0.138 R10C15A.F0 to R10C15A.C1 n2204 +CTOF_DEL --- 0.101 R10C15A.C1 to R10C15A.F1 SLICE_73 +ROUTE 2 0.148 R10C15A.F1 to R9C15C.CE PHI2_N_120_enable_8 (to PHI2_c) + -------- + 0.845 (39.6% logic, 60.4% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C15C.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.252ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 1.224ns (35.6% logic, 64.4% route), 4 logic levels. + + Constraint Details: + + 1.224ns physical path delay SLICE_15 to SLICE_19 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 1.252ns + + Physical Path Details: + + Data path SLICE_15 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R10C14C.CLK to R10C14C.Q0 SLICE_15 (from PHI2_c) +ROUTE 2 0.212 R10C14C.Q0 to R10C14D.A1 C1Submitted +CTOF_DEL --- 0.101 R10C14D.A1 to R10C14D.F1 SLICE_77 +ROUTE 1 0.222 R10C14D.F1 to R10C14A.B1 n2210 +CTOF_DEL --- 0.101 R10C14A.B1 to R10C14A.F1 SLICE_97 +ROUTE 1 0.211 R10C14A.F1 to R9C14C.A1 n7_adj_5 +CTOF_DEL --- 0.101 R9C14C.A1 to R9C14C.F1 SLICE_88 +ROUTE 1 0.143 R9C14C.F1 to R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 1.224 (35.6% logic, 64.4% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R10C14C.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.277ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdSubmitted_411 (to PHI2_c -) + + Delay: 1.249ns (34.9% logic, 65.1% route), 4 logic levels. + + Constraint Details: + + 1.249ns physical path delay SLICE_19 to SLICE_20 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 1.277ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R9C14B.CLK to R9C14B.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.224 R9C14B.Q0 to R10C15A.C0 CmdEnable +CTOF_DEL --- 0.101 R10C15A.C0 to R10C15A.F0 SLICE_73 +ROUTE 2 0.225 R10C15A.F0 to R9C15B.B0 n2204 +CTOF_DEL --- 0.101 R9C15B.B0 to R9C15B.F0 SLICE_74 +ROUTE 2 0.221 R9C15B.F0 to R9C17A.D1 n2220 +CTOF_DEL --- 0.101 R9C17A.D1 to R9C17A.F1 SLICE_89 +ROUTE 1 0.143 R9C17A.F1 to R9C17D.CE PHI2_N_120_enable_7 (to PHI2_c) + -------- + 1.249 (34.9% logic, 65.1% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C17D.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.277ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in Cmdn8MEGEN_410 (to PHI2_c -) + + Delay: 1.249ns (34.9% logic, 65.1% route), 4 logic levels. + + Constraint Details: + + 1.249ns physical path delay SLICE_19 to SLICE_24 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 1.277ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R9C14B.CLK to R9C14B.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.224 R9C14B.Q0 to R10C15A.C0 CmdEnable +CTOF_DEL --- 0.101 R10C15A.C0 to R10C15A.F0 SLICE_73 +ROUTE 2 0.225 R10C15A.F0 to R9C15B.B0 n2204 +CTOF_DEL --- 0.101 R9C15B.B0 to R9C15B.F0 SLICE_74 +ROUTE 2 0.221 R9C15B.F0 to R9C17A.D0 n2220 +CTOF_DEL --- 0.101 R9C17A.D0 to R9C17A.F0 SLICE_89 +ROUTE 1 0.143 R9C17A.F0 to R9C17C.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 1.249 (34.9% logic, 65.1% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C14B.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C17C.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 5.431ns (weighted slack = 10.862ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q XOR8MEG_408 (from PHI2_c -) + Destination: FF Data in RA11_385 (to PHI2_c +) + + Delay: 0.371ns (63.1% logic, 36.9% route), 2 logic levels. + + Constraint Details: + + 0.371ns physical path delay SLICE_50 to SLICE_33 meets + -0.013ns DIN_HLD and + -5.047ns delay constraint less + 0.000ns skew requirement (totaling -5.060ns) by 5.431ns + + Physical Path Details: + + Data path SLICE_50 to SLICE_33: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R10C15D.CLK to R10C15D.Q0 SLICE_50 (from PHI2_c) +ROUTE 1 0.137 R10C15D.Q0 to R10C16A.C0 XOR8MEG +CTOF_DEL --- 0.101 R10C16A.C0 to R10C16A.F0 SLICE_33 +ROUTE 1 0.000 R10C16A.F0 to R10C16A.DI0 RA11_N_184 (to PHI2_c) + -------- + 0.371 (63.1% logic, 36.9% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_50: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R10C15D.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_33: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R10C16A.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 5.992ns (weighted slack = 11.984ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) + FF CmdUFMCLK_413 + + Delay: 0.917ns (47.5% logic, 52.5% route), 4 logic levels. + + Constraint Details: + + 0.917ns physical path delay SLICE_93 to SLICE_100 meets + -0.028ns CE_HLD and + -5.047ns delay constraint less + 0.000ns skew requirement (totaling -5.075ns) by 5.992ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R9C16A.CLK to R9C16A.Q0 SLICE_93 (from PHI2_c) +ROUTE 1 0.138 R9C16A.Q0 to R9C15A.C1 Bank_0 +CTOF_DEL --- 0.101 R9C15A.C1 to R9C15A.F1 SLICE_100 +ROUTE 1 0.053 R9C15A.F1 to R9C15B.D1 n2277 +CTOF_DEL --- 0.101 R9C15B.D1 to R9C15B.F1 SLICE_74 +ROUTE 8 0.142 R9C15B.F1 to R10C15A.D1 n26 +CTOF_DEL --- 0.101 R10C15A.D1 to R10C15A.F1 SLICE_73 +ROUTE 2 0.148 R10C15A.F1 to R9C15A.CE PHI2_N_120_enable_8 (to PHI2_c) + -------- + 0.917 (47.5% logic, 52.5% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C16A.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.203 8.PADDI to R9C15A.CLK PHI2_c + -------- + 1.203 (0.0% logic, 100.0% route), 0 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 0.000 ns| 0.304 ns| 1 + | | | +FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 0.000 ns| 0.379 ns| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 335 (setup), 0 (hold) +Score: 391939 (setup), 0 (hold) +Cumulative negative slack: 304509 (304509+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html new file mode 100644 index 0000000..e5f11b0 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_bgn.html @@ -0,0 +1,152 @@ + +Bitgen Report + + +
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:01:23 2023
+
+
+Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed".
+ 
+===========
+UFM Summary.
+===========
+UFM Size:        511 Pages (128*511 Bits).
+UFM Utilization: General Purpose Flash Memory.
+ 
+Available General Purpose Flash Memory:  511 Pages (Page 0 to Page 510).
+Initialized UFM Pages:                     0 Page.
+ 
+Total CPU Time: 1 secs 
+Total REAL Time: 2 secs 
+Peak Memory Usage: 253 MB
+
+
+
+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+
+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html new file mode 100644 index 0000000..1fddacf --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_iotiming.html @@ -0,0 +1,204 @@ + +I/O Timing Report + + +
I/O Timing Report
+Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 6
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd
+// Version: Diamond (64-bit) 3.12.1.454
+// Written on Tue Aug 15 05:03:41 2023
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 6, 5, 4):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F     0.891      4       0.676     4
+CROW[1] nCRAS F     0.281      4       1.216     4
+Din[0]  PHI2  F     7.907      4       0.089     6
+Din[0]  nCCAS F     1.465      4       0.158     4
+Din[1]  PHI2  F     7.300      4       1.026     4
+Din[1]  nCCAS F     1.035      4       0.527     4
+Din[2]  PHI2  F     6.237      4       1.467     4
+Din[2]  nCCAS F     1.719      4      -0.108     M
+Din[3]  PHI2  F     6.623      4       0.176     6
+Din[3]  nCCAS F     0.339      4       0.916     4
+Din[4]  PHI2  F     6.902      4       1.033     4
+Din[4]  nCCAS F     0.687      4       0.951     4
+Din[5]  PHI2  F     6.837      4       1.369     4
+Din[5]  nCCAS F     2.810      4      -0.220     M
+Din[6]  PHI2  F     7.648      4      -0.050     M
+Din[6]  nCCAS F     1.281      4       0.266     4
+Din[7]  PHI2  F     7.823      4      -0.159     M
+Din[7]  nCCAS F     1.810      4      -0.096     M
+MAin[0] PHI2  F     6.751      4      -0.273     M
+MAin[0] nCRAS F     1.765      4      -0.033     4
+MAin[1] PHI2  F     5.718      4       0.117     M
+MAin[1] nCRAS F     1.814      4      -0.051     M
+MAin[2] PHI2  F     5.759      4      -0.021     M
+MAin[2] nCRAS F     1.323      4       0.309     4
+MAin[3] PHI2  F     6.165      4      -0.235     M
+MAin[3] nCRAS F     0.694      4       0.836     4
+MAin[4] PHI2  F     5.236      4      -0.147     M
+MAin[4] nCRAS F     0.730      4       0.835     4
+MAin[5] PHI2  F     6.024      4       0.135     M
+MAin[5] nCRAS F     0.734      4       0.868     4
+MAin[6] PHI2  F     5.689      4      -0.277     M
+MAin[6] nCRAS F     0.288      4       1.210     4
+MAin[7] PHI2  F     6.398      4      -0.307     M
+MAin[7] nCRAS F     1.215      4       0.401     4
+MAin[8] nCRAS F     0.817      4       0.727     4
+MAin[9] nCRAS F     0.941      4       0.601     4
+PHI2    RCLK  R     0.771      4       1.143     4
+UFMSDO  RCLK  R    -0.238      M       2.305     4
+nCCAS   RCLK  R     1.651      4       0.388     4
+nCCAS   nCRAS F     5.028      4      -0.828     M
+nCRAS   RCLK  R     0.593      4       1.309     4
+nFWE    PHI2  F     5.741      4       0.781     4
+nFWE    nCRAS F     0.578      4       0.996     4
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R    14.758         4        4.129          M
+LED    nCRAS F    12.396         4        3.434          M
+RA[0]  RCLK  R    13.780         4        3.894          M
+RA[0]  nCRAS F    11.795         4        3.277          M
+RA[10] RCLK  R    12.425         4        3.587          M
+RA[11] PHI2  R    10.432         4        3.084          M
+RA[1]  RCLK  R    15.081         4        4.198          M
+RA[1]  nCRAS F    12.364         4        3.447          M
+RA[2]  RCLK  R    14.518         4        4.082          M
+RA[2]  nCRAS F    11.696         4        3.275          M
+RA[3]  RCLK  R    13.789         4        3.897          M
+RA[3]  nCRAS F    12.223         4        3.392          M
+RA[4]  RCLK  R    15.175         4        4.228          M
+RA[4]  nCRAS F    12.424         4        3.464          M
+RA[5]  RCLK  R    13.789         4        3.897          M
+RA[5]  nCRAS F    12.359         4        3.437          M
+RA[6]  RCLK  R    15.420         4        4.299          M
+RA[6]  nCRAS F    12.865         4        3.560          M
+RA[7]  RCLK  R    14.672         4        4.127          M
+RA[7]  nCRAS F    12.253         4        3.386          M
+RA[8]  RCLK  R    14.952         4        4.191          M
+RA[8]  nCRAS F    12.244         4        3.383          M
+RA[9]  RCLK  R    14.092         4        3.978          M
+RA[9]  nCRAS F    13.164         4        3.653          M
+RBA[0] nCRAS F    10.278         4        2.970          M
+RBA[1] nCRAS F    10.474         4        3.030          M
+RCKE   RCLK  R    12.407         4        3.610          M
+RDQMH  RCLK  R    13.754         4        3.857          M
+RDQML  RCLK  R    13.482         4        3.833          M
+RD[0]  nCCAS F    10.515         4        3.076          M
+RD[1]  nCCAS F    10.118         4        2.965          M
+RD[2]  nCCAS F     9.759         4        2.886          M
+RD[3]  nCCAS F     9.798         4        2.878          M
+RD[4]  nCCAS F    10.979         4        3.178          M
+RD[5]  nCCAS F    11.063         4        3.207          M
+RD[6]  nCCAS F    10.317         4        3.018          M
+RD[7]  nCCAS F    10.232         4        2.986          M
+UFMCLK RCLK  R    12.402         4        3.606          M
+UFMSDI RCLK  R    11.975         4        3.501          M
+nRCAS  RCLK  R    12.350         4        3.564          M
+nRCS   RCLK  R    11.923         4        3.459          M
+nRRAS  RCLK  R    11.995         4        3.494          M
+nRWE   RCLK  R    11.975         4        3.501          M
+nUFMCS RCLK  R    11.818         4        3.434          M
+WARNING: you must also run trce with hold speed: 4
+WARNING: you must also run trce with hold speed: 6
+WARNING: you must also run trce with setup speed: M
+
+
+
+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+
+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj new file mode 100644 index 0000000..7edeb6a --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj @@ -0,0 +1,41 @@ +-a "MachXO2" +-d LCMXO2-1200HC +-t TQFP100 +-s 4 +-frequency 200 +-optimization_goal Balanced +-bram_utilization 100 +-ramstyle Auto +-romstyle auto +-dsp_utilization 100 +-use_dsp 1 +-use_carry_chain 1 +-carry_chain_length 0 +-force_gsr Auto +-resource_sharing 1 +-propagate_constants 1 +-remove_duplicate_regs 1 +-mux_style Auto +-max_fanout 1000 +-fsm_encoding_style Auto +-twr_paths 3 +-fix_gated_clocks 1 +-loop_limit 1950 + + + +-use_io_insertion 1 +-resolve_mixed_drivers 0 +-use_io_reg auto + + +-lpf 1 +-p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC" +-ver "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v" +-top RAM2GS + + +-p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC" + +-ngd "RAM2GS_LCMXO2_1200HC_impl1.ngd" + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.asd b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.asd new file mode 100644 index 0000000..4f5aca5 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.asd @@ -0,0 +1,15 @@ +[ActiveSupport MAP] +Device = LCMXO2-1200HC; +Package = TQFP100; +Performance = 4; +LUTS_avail = 1280; +LUTS_used = 143; +FF_avail = 1360; +FF_used = 102; +INPUT_LVCMOS25 = 26; +OUTPUT_LVCMOS25 = 33; +BIDI_LVCMOS25 = 8; +IO_avail = 80; +IO_used = 67; +EBR_avail = 7; +EBR_used = 0; diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam new file mode 100644 index 0000000..0e2396b --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.cam @@ -0,0 +1,88 @@ +[ START MERGED ] +n2380 Ready +PHI2_N_120 PHI2_c +nRWE_N_176 nRWE_N_177 +n1407 nRowColSel_N_34 +n1408 nRowColSel_N_35 +[ END MERGED ] +[ START CLIPPED ] +GND_net +VCC_net +FS_610_add_4_19/S1 +FS_610_add_4_19/CO +FS_610_add_4_1/S0 +FS_610_add_4_1/CI +[ END CLIPPED ] +[ START DESIGN PREFS ] +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:27 2023 + +SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "RD[7]" SITE "43" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[9]" SITE "63" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[7]" SITE "75" ; +LOCATE COMP "RA[6]" SITE "68" ; +LOCATE COMP "RA[5]" SITE "70" ; +LOCATE COMP "RA[4]" SITE "74" ; +LOCATE COMP "RA[3]" SITE "71" ; +LOCATE COMP "RA[2]" SITE "69" ; +LOCATE COMP "RA[1]" SITE "67" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "nRCS" SITE "57" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "UFMCLK" SITE "29" ; +LOCATE COMP "UFMSDI" SITE "30" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "MAin[9]" SITE "32" ; +LOCATE COMP "MAin[8]" SITE "25" ; +LOCATE COMP "MAin[7]" SITE "18" ; +LOCATE COMP "MAin[6]" SITE "24" ; +LOCATE COMP "MAin[5]" SITE "19" ; +LOCATE COMP "MAin[4]" SITE "20" ; +LOCATE COMP "MAin[3]" SITE "21" ; +LOCATE COMP "MAin[2]" SITE "13" ; +LOCATE COMP "MAin[1]" SITE "12" ; +LOCATE COMP "MAin[0]" SITE "14" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "CROW[0]" SITE "10" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "nFWE" SITE "28" ; +LOCATE COMP "RCLK" SITE "62" ; +LOCATE COMP "UFMSDO" SITE "27" ; +SCHEMATIC END ; +[ END DESIGN PREFS ] diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.hrr b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.hrr new file mode 100644 index 0000000..a9cd083 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.hrr @@ -0,0 +1,10 @@ +--------------------------------------------------- +Report for cell RAM2GS + Instance path: RAM2GS + Cell usage: + cell count Res Usage(%) + SLIC 75.00 100.0 + LUT4 123.00 100.0 + IOBUF 67 100.0 + PFUREG 102 100.0 + RIPPLE 10 100.0 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.ncd b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.ncd new file mode 100644 index 0000000..331614c Binary files /dev/null and b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_map.ncd differ diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf new file mode 100644 index 0000000..f178e30 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf @@ -0,0 +1,3176 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Tue Aug 15 05:03:31 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7I) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_10") + (INSTANCE SLICE_10I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_15") + (INSTANCE SLICE_15I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_16") + (INSTANCE SLICE_16I) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_20") + (INSTANCE SLICE_20I) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_24") + (INSTANCE SLICE_24I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_25") + (INSTANCE SLICE_25I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_26") + (INSTANCE SLICE_26I) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_27") + (INSTANCE SLICE_27I) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_30") + (INSTANCE SLICE_30I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_33") + (INSTANCE SLICE_33I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_35") + (INSTANCE SLICE_35I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_36") + (INSTANCE SLICE_36I) + (DELAY + (ABSOLUTE + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_37") + (INSTANCE SLICE_37I) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_45") + (INSTANCE SLICE_45I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_50") + (INSTANCE SLICE_50I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_57") + (INSTANCE SLICE_57I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_59") + (INSTANCE SLICE_59I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_61") + (INSTANCE SLICE_61I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_62") + (INSTANCE SLICE_62I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_64") + (INSTANCE SLICE_64I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_65") + (INSTANCE SLICE_65I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_66") + (INSTANCE SLICE_66I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_67") + (INSTANCE SLICE_67I) + (DELAY + (ABSOLUTE + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_68") + (INSTANCE SLICE_68I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_69") + (INSTANCE SLICE_69I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_70") + (INSTANCE SLICE_70I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "i30_SLICE_71") + (INSTANCE i30_SLICE_71I) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (457:589:721)(457:589:721)) + (IOPATH B1 OFX0 (457:589:721)(457:589:721)) + (IOPATH A1 OFX0 (457:589:721)(457:589:721)) + (IOPATH D0 OFX0 (457:589:721)(457:589:721)) + (IOPATH C0 OFX0 (457:589:721)(457:589:721)) + (IOPATH B0 OFX0 (457:589:721)(457:589:721)) + (IOPATH A0 OFX0 (457:589:721)(457:589:721)) + (IOPATH M0 OFX0 (322:349:376)(322:349:376)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_72") + (INSTANCE SLICE_72I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_73") + (INSTANCE SLICE_73I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_74") + (INSTANCE SLICE_74I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_75") + (INSTANCE SLICE_75I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_76") + (INSTANCE SLICE_76I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_80") + (INSTANCE SLICE_80I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_81") + (INSTANCE SLICE_81I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_84") + (INSTANCE SLICE_84I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_85") + (INSTANCE SLICE_85I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_102") + (INSTANCE SLICE_102I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_103") + (INSTANCE SLICE_103I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_104") + (INSTANCE SLICE_104I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_105") + (INSTANCE SLICE_105I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_106") + (INSTANCE SLICE_106I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_7_B") + (INSTANCE RD_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD7 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD7 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD7) (3330:3330:3330)) + (WIDTH (negedge RD7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_6_B") + (INSTANCE RD_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD6 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD6 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD6) (3330:3330:3330)) + (WIDTH (negedge RD6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_5_B") + (INSTANCE RD_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD5 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD5 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD5) (3330:3330:3330)) + (WIDTH (negedge RD5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_4_B") + (INSTANCE RD_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD4 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD4 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD4) (3330:3330:3330)) + (WIDTH (negedge RD4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_3_B") + (INSTANCE RD_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD3 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD3 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD3) (3330:3330:3330)) + (WIDTH (negedge RD3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_2_B") + (INSTANCE RD_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD2 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD2 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD2) (3330:3330:3330)) + (WIDTH (negedge RD2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_1_B") + (INSTANCE RD_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD1 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD1 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD1) (3330:3330:3330)) + (WIDTH (negedge RD1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_0_B") + (INSTANCE RD_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD0 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD0 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD0) (3330:3330:3330)) + (WIDTH (negedge RD0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Dout_7_B") + (INSTANCE Dout_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout7 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_6_B") + (INSTANCE Dout_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout6 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_5_B") + (INSTANCE Dout_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout5 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_4_B") + (INSTANCE Dout_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout4 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_3_B") + (INSTANCE Dout_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout3 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_2_B") + (INSTANCE Dout_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout2 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1_B") + (INSTANCE Dout_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0_B") + (INSTANCE Dout_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "LEDB") + (INSTANCE LEDI) + (DELAY + (ABSOLUTE + (IOPATH PADDO LEDS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_B") + (INSTANCE RBA_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_0_B") + (INSTANCE RBA_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_11_B") + (INSTANCE RA_11_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA11 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_10_B") + (INSTANCE RA_10_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA10 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_9_B") + (INSTANCE RA_9_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA9 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_8_B") + (INSTANCE RA_8_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA8 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_7_B") + (INSTANCE RA_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA7 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_6_B") + (INSTANCE RA_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA6 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_5_B") + (INSTANCE RA_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA5 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_4_B") + (INSTANCE RA_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA4 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_3_B") + (INSTANCE RA_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA3 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_2_B") + (INSTANCE RA_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA2 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_1_B") + (INSTANCE RA_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_0_B") + (INSTANCE RA_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRCSB") + (INSTANCE nRCSI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCSS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RCKEB") + (INSTANCE RCKEI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RCKES (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRWEB") + (INSTANCE nRWEI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRWES (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRRASB") + (INSTANCE nRRASI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRRASS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRCASB") + (INSTANCE nRCASI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCASS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMHB") + (INSTANCE RDQMHI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMHS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMLB") + (INSTANCE RDQMLI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMLS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nUFMCSB") + (INSTANCE nUFMCSI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nUFMCSS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "UFMCLKB") + (INSTANCE UFMCLKI) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMCLKS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "UFMSDIB") + (INSTANCE UFMSDII) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMSDIS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "PHI2B") + (INSTANCE PHI2I) + (DELAY + (ABSOLUTE + (IOPATH PHI2S PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI2S) (3330:3330:3330)) + (WIDTH (negedge PHI2S) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_9_B") + (INSTANCE MAin_9_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (3330:3330:3330)) + (WIDTH (negedge MAin9) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_8_B") + (INSTANCE MAin_8_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (3330:3330:3330)) + (WIDTH (negedge MAin8) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_7_B") + (INSTANCE MAin_7_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (3330:3330:3330)) + (WIDTH (negedge MAin7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_6_B") + (INSTANCE MAin_6_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (3330:3330:3330)) + (WIDTH (negedge MAin6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_5_B") + (INSTANCE MAin_5_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (3330:3330:3330)) + (WIDTH (negedge MAin5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_4_B") + (INSTANCE MAin_4_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (3330:3330:3330)) + (WIDTH (negedge MAin4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_3_B") + (INSTANCE MAin_3_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (3330:3330:3330)) + (WIDTH (negedge MAin3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_2_B") + (INSTANCE MAin_2_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (3330:3330:3330)) + (WIDTH (negedge MAin2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_1_B") + (INSTANCE MAin_1_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (3330:3330:3330)) + (WIDTH (negedge MAin1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_0_B") + (INSTANCE MAin_0_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (3330:3330:3330)) + (WIDTH (negedge MAin0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "CROW_1_B") + (INSTANCE CROW_1_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (3330:3330:3330)) + (WIDTH (negedge CROW1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "CROW_0_B") + (INSTANCE CROW_0_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (3330:3330:3330)) + (WIDTH (negedge CROW0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_7_B") + (INSTANCE Din_7_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (3330:3330:3330)) + (WIDTH (negedge Din7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_6_B") + (INSTANCE Din_6_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (3330:3330:3330)) + (WIDTH (negedge Din6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_5_B") + (INSTANCE Din_5_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (3330:3330:3330)) + (WIDTH (negedge Din5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_4_B") + (INSTANCE Din_4_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (3330:3330:3330)) + (WIDTH (negedge Din4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_3_B") + (INSTANCE Din_3_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (3330:3330:3330)) + (WIDTH (negedge Din3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_2_B") + (INSTANCE Din_2_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (3330:3330:3330)) + (WIDTH (negedge Din2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_1_B") + (INSTANCE Din_1_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (3330:3330:3330)) + (WIDTH (negedge Din1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_0_B") + (INSTANCE Din_0_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (3330:3330:3330)) + (WIDTH (negedge Din0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nCCASB") + (INSTANCE nCCASI) + (DELAY + (ABSOLUTE + (IOPATH nCCASS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCCASS) (3330:3330:3330)) + (WIDTH (negedge nCCASS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nCRASB") + (INSTANCE nCRASI) + (DELAY + (ABSOLUTE + (IOPATH nCRASS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCRASS) (3330:3330:3330)) + (WIDTH (negedge nCRASS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nFWEB") + (INSTANCE nFWEI) + (DELAY + (ABSOLUTE + (IOPATH nFWES PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nFWES) (3330:3330:3330)) + (WIDTH (negedge nFWES) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RCLKB") + (INSTANCE RCLKI) + (DELAY + (ABSOLUTE + (IOPATH RCLKS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RCLKS) (3330:3330:3330)) + (WIDTH (negedge RCLKS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "UFMSDOB") + (INSTANCE UFMSDOI) + (DELAY + (ABSOLUTE + (IOPATH UFMSDOS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge UFMSDOS) (3330:3330:3330)) + (WIDTH (negedge UFMSDOS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_76I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_80I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_82I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_85I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_0I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_85I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_105I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/F1 SLICE_0I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/F0 SLICE_0I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_9I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_16I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_26I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_27I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_30I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_32I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_35I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_36I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_37I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_44I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_45I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_57I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_59I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_61I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_62I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_64I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_65I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_66I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_67I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_68I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_69I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_70I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_75I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_78I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_79I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_81I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_84I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_86I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_97I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_98I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_106I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/FCO SLICE_0I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/FCO SLICE_9I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_1I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_76I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_80I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_85I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_105I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_57I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_70I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_76I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_80I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_82I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_85I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_105I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/F1 SLICE_1I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/F0 SLICE_1I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/FCO SLICE_1I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_45I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_68I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_95I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_95I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/F1 SLICE_2I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/F0 SLICE_2I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/FCO SLICE_2I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/FCO SLICE_6I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_86I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_105I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_95I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_95I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/F1 SLICE_3I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/F0 SLICE_3I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/FCO SLICE_3I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_95I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_44I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_95I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/F1 SLICE_4I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/F0 SLICE_4I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/FCO SLICE_4I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/FCO SLICE_8I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_68I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/F1 SLICE_5I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/Q1 SLICE_5I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/Q1 SLICE_66I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/Q1 SLICE_96I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_96I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_96I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_45I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_57I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_70I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_76I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_82I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_86I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_95I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/F1 SLICE_6I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/F0 SLICE_6I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_82I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_85I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/F0 SLICE_7I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/FCO SLICE_7I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_44I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_86I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_86I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/F1 SLICE_8I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/F0 SLICE_8I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q1 SLICE_9I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q1 SLICE_85I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q1 SLICE_105I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 SLICE_9I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 SLICE_85I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 SLICE_105I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/F1 SLICE_9I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/F0 SLICE_9I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_10I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_24I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_33I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_50I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_89I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_89I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_89I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_90I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_102I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_106I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_10I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_24I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_33I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_33I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_75I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_77I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_88I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_101I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_10I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_50I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_90I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_90I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_90I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_93I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_100I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_10I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_24I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_33I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_88I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_90I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_90I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_101I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106I/F1 SLICE_10I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10I/F1 SLICE_10I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F0 SLICE_10I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_10I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_73I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10I/F0 SLICE_10I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F0 SLICE_10I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F0 SLICE_10I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F0 SLICE_15I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F0 SLICE_88I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_10I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_15I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_19I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_20I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_24I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_33I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_50I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_86I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_93I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_99I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_100I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_101I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_102I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_103I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10I/Q0 SLICE_88I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_15I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_73I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_74I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_79I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_83I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_91I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_91I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_104I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_15I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_79I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_82I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_101I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F1 SLICE_15I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F1 SLICE_79I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_15I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_79I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_91I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_103I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_15I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_19I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_73I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_74I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_79I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_83I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_91I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_91I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_97I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_102I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15I/Q0 SLICE_15I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15I/Q0 SLICE_77I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15I/F1 SLICE_15I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_15I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_25I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_25I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_74I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_79I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_104I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_104I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_106I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15I/F0 SLICE_15I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_16I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_88I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_89I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_90I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_92I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_104I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/F0 SLICE_16I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/F0 SLICE_25I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/Q0 SLICE_16I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/F0 SLICE_19I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_19I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_24I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_25I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_75I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_77I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_89I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_89I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_89I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_102I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F0 SLICE_19I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F0 SLICE_77I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F0 SLICE_19I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F0 SLICE_75I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F1 SLICE_19I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F1 SLICE_19I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F1 SLICE_77I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F0 SLICE_19I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F0 SLICE_88I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F0 SLICE_19I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F1 SLICE_19I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/Q0 SLICE_73I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/Q0 SLICE_83I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20I/F0 SLICE_20I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/F1 SLICE_20I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20I/Q0 SLICE_35I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20I/Q0 SLICE_84I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/F1 SLICE_24I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/F1 SLICE_50I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/F1 SLICE_83I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/Q0 SLICE_24I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/Q0 SLICE_33I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_24I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_50I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_90I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_90I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_90I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_93I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_99I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_106I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/F0 SLICE_24I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/F0 SLICE_24I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/Q0 SLICE_57I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_25I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_50I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_75I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_77I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_89I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_89I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_92I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_103I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F0 SLICE_25I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_25I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_30I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_30I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_74I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_76I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_82I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_87I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_91I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_104I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_65I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 i30_SLICE_71I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 i30_SLICE_71I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_81I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_96I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 SLICE_30I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 SLICE_59I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 i30_SLICE_71I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 i30_SLICE_71I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 SLICE_81I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 SLICE_96I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 SLICE_96I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/F0 SLICE_26I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F0 SLICE_26I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_32I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_35I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_35I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_44I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_45I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_57I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_62I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_70I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_70I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_72I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_76I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_80I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_84I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_92I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_92I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27I/F0 SLICE_27I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F0 SLICE_27I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27I/Q0 SLICE_30I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27I/Q0 SLICE_50I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/F0 SLICE_30I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q0 SLICE_30I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q0 SLICE_36I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/F1 LEDI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_32I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_36I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_59I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_61I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_62I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_66I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_67I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_69I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_69I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 i30_SLICE_71I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_72I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_78I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_86I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_92I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_92I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_32I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_59I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_61I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_62I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_62I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_68I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 i30_SLICE_71I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_78I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_87I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_92I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_92I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_94I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_94I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_32I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_59I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_64I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_84I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_32I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_33I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_35I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_59I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_61I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_62I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_64I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_72I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_74I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_76I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_82I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_87I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_87I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_91I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_92I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_94I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_94I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_104I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/F1 SLICE_32I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_32I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_62I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_92I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_98I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/F0 SLICE_32I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/Q1 SLICE_32I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/Q1 SLICE_64I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/Q1 SLICE_79I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/Q0 RA_10_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50I/Q0 SLICE_33I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33I/F0 SLICE_33I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33I/Q0 RA_11_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33I/F1 SLICE_73I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q1 SLICE_35I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q1 SLICE_69I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q1 SLICE_84I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q1 SLICE_35I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q1 SLICE_84I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT i30_SLICE_71I/OFX0 SLICE_35I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F0 SLICE_35I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F1 SLICE_35I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F1 SLICE_59I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F1 SLICE_61I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F1 SLICE_62I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q0 SLICE_36I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F1 SLICE_44I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F1 SLICE_45I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F1 SLICE_70I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/Q1 SLICE_36I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/F0 SLICE_36I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/Q0 SLICE_36I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_61I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_69I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_78I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 RCKEI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/F0 SLICE_37I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_72I/F1 SLICE_37I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F1 SLICE_44I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F1 SLICE_44I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F1 SLICE_70I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F1 SLICE_82I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/Q0 SLICE_44I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F1 SLICE_44I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F0 SLICE_44I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F0 SLICE_44I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F0 SLICE_45I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/Q0 UFMCLKI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_45I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_57I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_76I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_80I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_85I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/F1 SLICE_45I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 SLICE_45I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/Q0 SLICE_45I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45I/F1 SLICE_45I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45I/F0 SLICE_45I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45I/Q0 UFMSDII/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50I/F1 SLICE_50I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_50I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_77I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_88I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_92I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_97I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_100I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_103I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_106I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50I/F0 SLICE_50I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F1 SLICE_50I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_57I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_80I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_95I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDOI/PADDI SLICE_57I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/F1 SLICE_57I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/F1 SLICE_84I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/F0 SLICE_57I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/F0 SLICE_57I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F0 SLICE_59I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F0 SLICE_61I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59I/F1 SLICE_59I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F0 SLICE_59I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F0 SLICE_64I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59I/F0 SLICE_59I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59I/Q0 nRCASI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/F1 SLICE_61I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62I/F1 SLICE_61I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62I/F1 SLICE_62I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/F0 SLICE_61I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/Q0 nRCSI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F1 SLICE_62I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62I/F0 SLICE_62I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62I/Q0 nRRASI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F1 SLICE_64I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/F1 SLICE_64I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/F0 SLICE_64I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F0 SLICE_64I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F0 SLICE_65I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 nRWEI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_65I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_67I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 i30_SLICE_71I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_81I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_87I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_65I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_66I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_66I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_81I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_87I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F1 SLICE_65I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F1 SLICE_65I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F1 SLICE_78I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F1 SLICE_94I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F1 SLICE_65I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F0 SLICE_65I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_93I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_93I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_98I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_98I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_99I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_100I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_101I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_101I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_102I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_102I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_103I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_103I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_66I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_67I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_72I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_87I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_94I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F0 SLICE_66I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F1 i30_SLICE_71I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/F0 SLICE_67I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/F0 SLICE_68I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/Q1 SLICE_68I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/Q0 SLICE_68I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F0 SLICE_74I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F1 SLICE_86I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F0 SLICE_69I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F1 SLICE_70I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F1 SLICE_76I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/Q1 SLICE_70I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70I/F1 SLICE_70I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70I/F0 SLICE_70I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70I/Q0 nUFMCSI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_72I/F0 SLICE_72I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q1 SLICE_72I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q1 SLICE_98I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73I/F0 SLICE_73I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73I/F0 SLICE_74I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_73I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_74I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_79I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_83I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_91I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_91I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_104I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_73I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_74I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_77I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_83I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_88I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_91I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_97I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_97I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_101I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73I/F1 SLICE_99I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73I/F1 SLICE_100I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/Q1 SLICE_74I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F1 SLICE_74I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/Q0 SLICE_74I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F0 SLICE_89I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F0 SLICE_89I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_101I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q1 SLICE_102I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F0 SLICE_75I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106I/F0 SLICE_75I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106I/F0 SLICE_83I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/Q0 SLICE_75I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/Q1 SLICE_75I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_75I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_78I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_79I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_81I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_84I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_97I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_98I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_106I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F1 SLICE_88I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_76I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_93I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_93I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_98I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_8_I/PADDI SLICE_76I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_8_I/PADDI SLICE_98I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q0 SLICE_98I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q1 SLICE_93I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F1 SLICE_97I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F0 SLICE_78I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F0 SLICE_78I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F0 SLICE_81I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/Q0 SLICE_78I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q1 SLICE_78I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/Q1 SLICE_81I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q0 SLICE_79I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F1 SLICE_81I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q0 SLICE_81I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F0 SLICE_82I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_82I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_100I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_102I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/Q0 SLICE_102I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/Q1 SLICE_101I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F0 SLICE_83I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F0 SLICE_84I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/F1 SLICE_84I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/Q0 SLICE_84I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/Q1 SLICE_106I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F1 SLICE_86I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/F0 SLICE_86I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F0 SLICE_87I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW_1_I/PADDI SLICE_87I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW_0_I/PADDI SLICE_87I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 RBA_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 RBA_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/F1 SLICE_88I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F1 SLICE_88I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/Q0 RD_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/Q1 RD_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/Q0 RD_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/Q1 RD_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/Q0 RD_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/Q1 RD_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_91I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_99I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_103I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q0 SLICE_103I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q1 SLICE_103I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/Q0 RD_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/Q1 RD_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/F0 RA_9_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/Q0 SLICE_100I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/F1 RDQMLI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/Q1 SLICE_99I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/Q0 SLICE_97I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106I/Q1 SLICE_97I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/F0 RA_8_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/F1 RDQMHI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/Q0 SLICE_99I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_99I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_99I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_104I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/Q1 SLICE_99I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F0 RA_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/Q1 SLICE_100I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_100I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_100I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_104I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/Q0 SLICE_100I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F0 RA_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/F0 RA_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/F1 RA_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/F0 RA_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/F1 RA_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/F0 RA_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/F1 RA_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_7_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_6_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_5_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_4_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_3_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_2_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_1_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_0_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106I/Q0 SLICE_106I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT RD_7_I/PADDI Dout_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_6_I/PADDI Dout_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_5_I/PADDI Dout_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_4_I/PADDI Dout_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_3_I/PADDI Dout_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_2_I/PADDI Dout_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_1_I/PADDI Dout_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_0_I/PADDI Dout_0_I/PADDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho new file mode 100644 index 0000000..61a9bb6 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho @@ -0,0 +1,26387 @@ + +-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +-- ldbanno -n VHDL -o RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd +-- Netlist created on Tue Aug 15 05:03:26 2023 +-- Netlist written on Tue Aug 15 05:03:31 2023 +-- Design is for device LCMXO2-1200HC +-- Design is for package TQFP100 +-- Design is for performance grade 4 + +-- entity vmuxregsre + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE; + + end vmuxregsre; + + architecture Structure of vmuxregsre is + begin + INST01: FL1P3DX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity vcc + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vcc is + port (PWR1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE; + + end vcc; + + architecture Structure of vcc is + begin + INST1: VHI + port map (Z=>PWR1); + end Structure; + +-- entity gnd + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity gnd is + port (PWR0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE; + + end gnd; + + architecture Structure of gnd is + begin + INST1: VLO + port map (Z=>PWR0); + end Structure; + +-- entity ccu2B0 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu2B0 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu2B0 : ENTITY IS TRUE; + + end ccu2B0; + + architecture Structure of ccu2B0 is + begin + inst1: CCU2D + generic map (INIT0 => X"faaa", INIT1 => X"faaa", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_0 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_0 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_0"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE; + + end SLICE_0; + + architecture Structure of SLICE_0 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i14: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i13: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_15: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_1 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_1 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_1"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE; + + end SLICE_1; + + architecture Structure of SLICE_1 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i12: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i11: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_13: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_2 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_2 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_2"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE; + + end SLICE_2; + + architecture Structure of SLICE_2 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i8: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i7: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_9: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_3 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_3 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_3"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE; + + end SLICE_3; + + architecture Structure of SLICE_3 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i6: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i5: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_7: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_4 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_4 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_4"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE; + + end SLICE_4; + + architecture Structure of SLICE_4 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i2: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i1: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_3: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity ccu20001 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu20001 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE; + + end ccu20001; + + architecture Structure of ccu20001 is + begin + inst1: CCU2D + generic map (INIT0 => X"F000", INIT1 => X"0555", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_5 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_5 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_5"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; DI1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE; + + end SLICE_5; + + architecture Structure of SLICE_5 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20001 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i0: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CASr3_384: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_1: ccu20001 + port map (A0=>GNDI, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>open, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, DI1_dly, M0_dly, CLK_dly, Q0_out, F1_out, + Q1_out, FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_6 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_6 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_6"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE; + + end SLICE_6; + + architecture Structure of SLICE_6 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i10: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i9: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_11: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity ccu20002 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu20002 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20002 : ENTITY IS TRUE; + + end ccu20002; + + architecture Structure of ccu20002 is + begin + inst1: CCU2D + generic map (INIT0 => X"faaa", INIT1 => X"0000", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_7 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_7 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_7"; + + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE; + + end SLICE_7; + + architecture Structure of SLICE_7 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i17: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_add_4_19: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>GNDI, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>open, + CO1=>open); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A0_ipd, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_8 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_8 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_8"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE; + + end SLICE_8; + + architecture Structure of SLICE_8 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i4: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i3: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_5: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_9 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_9 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_9"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE; + + end SLICE_9; + + architecture Structure of SLICE_9 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i16: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i15: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_17: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut4 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut4 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE; + + end lut4; + + architecture Structure of lut4 is + begin + INST10: ROM16X1A + generic map (initval => X"0002") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40003 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40003 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE; + + end lut40003; + + architecture Structure of lut40003 is + begin + INST10: ROM16X1A + generic map (initval => X"2000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0004 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre0004 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0004 : ENTITY IS TRUE; + + end vmuxregsre0004; + + architecture Structure of vmuxregsre0004 is + begin + INST01: FL1P3IY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity inverter + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity inverter is + port (I: in Std_logic; Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE; + + end inverter; + + architecture Structure of inverter is + begin + INST1: INV + port map (A=>I, Z=>Z); + end Structure; + +-- entity SLICE_10 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_10 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_10"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_10 : ENTITY IS TRUE; + + end SLICE_10; + + architecture Structure of SLICE_10 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40003 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + begin + i3_3_lut_4_lut: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut_adj_4: lut40003 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + ADSubmitted_407: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40005 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40005 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE; + + end lut40005; + + architecture Structure of lut40005 is + begin + INST10: ROM16X1A + generic map (initval => X"FF7F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40006 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40006 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE; + + end lut40006; + + architecture Structure of lut40006 is + begin + INST10: ROM16X1A + generic map (initval => X"E0F0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0007 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre0007 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0007 : ENTITY IS TRUE; + + end vmuxregsre0007; + + architecture Structure of vmuxregsre0007 is + begin + INST01: FL1P3JY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); + end Structure; + +-- entity SLICE_15 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_15 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_15"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_15 : ENTITY IS TRUE; + + end SLICE_15; + + architecture Structure of SLICE_15 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40006 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0007 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + begin + i13_2_lut_rep_16_4_lut: lut40005 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1110_2_lut_3_lut_4_lut: lut40006 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + C1Submitted_406: vmuxregsre0007 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40008 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40008 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE; + + end lut40008; + + architecture Structure of lut40008 is + begin + INST10: ROM16X1A + generic map (initval => X"5555") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_16 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_16 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_16"; + + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_16 : ENTITY IS TRUE; + + end SLICE_16; + + architecture Structure of SLICE_16 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2045: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CASr2_383: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CASr_382: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40009 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40009 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE; + + end lut40009; + + architecture Structure of lut40009 is + begin + INST10: ROM16X1A + generic map (initval => X"C0CA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40010 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40010 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE; + + end lut40010; + + architecture Structure of lut40010 is + begin + INST10: ROM16X1A + generic map (initval => X"4000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_19 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_19 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_19"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE; + + end SLICE_19; + + architecture Structure of SLICE_19 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i26_4_lut: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_3_lut_4_lut: lut40010 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdEnable_405: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40011 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40011 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE; + + end lut40011; + + architecture Structure of lut40011 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_20 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_20 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_20"; + + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE; + + end SLICE_20; + + architecture Structure of SLICE_20 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2447_001_BUF1_BUF1: lut40011 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdSubmitted_411: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40012 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40012 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE; + + end lut40012; + + architecture Structure of lut40012 is + begin + INST10: ROM16X1A + generic map (initval => X"FEFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40013 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40013 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE; + + end lut40013; + + architecture Structure of lut40013 is + begin + INST10: ROM16X1A + generic map (initval => X"CC5C") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_24 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_24 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_24"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_24 : ENTITY IS TRUE; + + end SLICE_24; + + architecture Structure of SLICE_24 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut_adj_15: lut40012 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Cmdn8MEGEN_I_93_4_lut: lut40013 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Cmdn8MEGEN_410: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40014 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40014 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE; + + end lut40014; + + architecture Structure of lut40014 is + begin + INST10: ROM16X1A + generic map (initval => X"4040") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_25 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_25 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_25"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE; + + end SLICE_25; + + architecture Structure of SLICE_25 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_3_lut: lut40014 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_1_lut_rep_24: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + CBR_390: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + FWEr_389: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_26 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_26 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_26"; + + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE; + + end SLICE_26; + + architecture Structure of SLICE_26 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2447_000_BUF1_BUF1: lut40011 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + InitReady_394: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_27 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_27 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_27"; + + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_27 : ENTITY IS TRUE; + + end SLICE_27; + + architecture Structure of SLICE_27 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + m1_lut: lut40011 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + LEDEN_419: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40015 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40015 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE; + + end lut40015; + + architecture Structure of lut40015 is + begin + INST10: ROM16X1A + generic map (initval => X"FBFB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_30 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_30 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_30"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE; + + end SLICE_30; + + architecture Structure of SLICE_30 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2010_3_lut_3_lut: lut40015 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2044: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + RASr2_380: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + RASr_379: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40016 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40016 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE; + + end lut40016; + + architecture Structure of lut40016 is + begin + INST10: ROM16X1A + generic map (initval => X"8080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40017 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40017 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE; + + end lut40017; + + architecture Structure of lut40017 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_32 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_32 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_32"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE; + + end SLICE_32; + + architecture Structure of SLICE_32 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0007 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40017 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_rep_32: lut40016 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_2_lut_3_lut_4_lut: lut40017 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RA10_400: vmuxregsre0007 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40018 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40018 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE; + + end lut40018; + + architecture Structure of lut40018 is + begin + INST10: ROM16X1A + generic map (initval => X"1010") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40019 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40019 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE; + + end lut40019; + + architecture Structure of lut40019 is + begin + INST10: ROM16X1A + generic map (initval => X"C6C6") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_33 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_33 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_33"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE; + + end SLICE_33; + + architecture Structure of SLICE_33 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RA11_I_54_3_lut: lut40019 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RA11_385: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40020 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40020 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE; + + end lut40020; + + architecture Structure of lut40020 is + begin + INST10: ROM16X1A + generic map (initval => X"20FF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40021 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40021 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE; + + end lut40021; + + architecture Structure of lut40021 is + begin + INST10: ROM16X1A + generic map (initval => X"CACA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_35 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_35 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_35"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE; + + end SLICE_35; + + architecture Structure of SLICE_35 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40020 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_4_lut_adj_25: lut40020 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i29_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKEEN_401: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40022 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40022 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE; + + end lut40022; + + architecture Structure of lut40022 is + begin + INST10: ROM16X1A + generic map (initval => X"CFC8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_36 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_36 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_36"; + + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE; + + end SLICE_36; + + architecture Structure of SLICE_36 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40022 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1404_4_lut: lut40022 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + PHI2r2_377: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKE_395: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M1_dly, + CLK_dly, F0_out, Q0_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_37 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_37 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_37"; + + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_37 : ENTITY IS TRUE; + + end SLICE_37; + + architecture Structure of SLICE_37 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2447_002_BUF1_BUF1: lut40011 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Ready_404: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40023 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40023 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE; + + end lut40023; + + architecture Structure of lut40023 is + begin + INST10: ROM16X1A + generic map (initval => X"3A0A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_44 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_44 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_44"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE; + + end SLICE_44; + + architecture Structure of SLICE_44 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40023 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1970_4_lut: lut40023 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1603_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + UFMCLK_416: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40024 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40024 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE; + + end lut40024; + + architecture Structure of lut40024 is + begin + INST10: ROM16X1A + generic map (initval => X"CAC0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_45 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_45 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_45"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_45 : ENTITY IS TRUE; + + end SLICE_45; + + architecture Structure of SLICE_45 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i4_4_lut_adj_17: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1589_4_lut: lut40024 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + UFMSDI_417: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40025 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40025 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE; + + end lut40025; + + architecture Structure of lut40025 is + begin + INST10: ROM16X1A + generic map (initval => X"FEFA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40026 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40026 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE; + + end lut40026; + + architecture Structure of lut40026 is + begin + INST10: ROM16X1A + generic map (initval => X"0008") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_50 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_50 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_50"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE; + + end SLICE_50; + + architecture Structure of SLICE_50 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40025 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1962_4_lut: lut40025 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_3_lut_4_lut_adj_11: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + XOR8MEG_408: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40027 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40027 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE; + + end lut40027; + + architecture Structure of lut40027 is + begin + INST10: ROM16X1A + generic map (initval => X"1000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40028 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40028 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE; + + end lut40028; + + architecture Structure of lut40028 is + begin + INST10: ROM16X1A + generic map (initval => X"BF04") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_57 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_57 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_57"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE; + + end SLICE_57; + + architecture Structure of SLICE_57 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_rep_18_4_lut: lut40027 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + n8MEGEN_I_14_3_lut_4_lut: lut40028 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + n8MEGEN_418: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40029 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40029 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE; + + end lut40029; + + architecture Structure of lut40029 is + begin + INST10: ROM16X1A + generic map (initval => X"3AFA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40030 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40030 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE; + + end lut40030; + + architecture Structure of lut40030 is + begin + INST10: ROM16X1A + generic map (initval => X"FE0E") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0031 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre0031 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0031 : ENTITY IS TRUE; + + end vmuxregsre0031; + + architecture Structure of vmuxregsre0031 is + begin + INST01: FL1P3BX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); + end Structure; + +-- entity SLICE_59 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_59 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_59"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE; + + end SLICE_59; + + architecture Structure of SLICE_59 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40030 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + begin + nRCAS_I_43_4_lut: lut40029 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCAS_I_0_452_3_lut_4_lut: lut40030 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRCAS_398: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40032 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40032 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE; + + end lut40032; + + architecture Structure of lut40032 is + begin + INST10: ROM16X1A + generic map (initval => X"1F10") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_61 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_61 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_61"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE; + + end SLICE_61; + + architecture Structure of SLICE_61 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40032 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRCS_I_31_3_lut_4_lut: lut40032 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCS_I_0_448_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRCS_396: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40033 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40033 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE; + + end lut40033; + + architecture Structure of lut40033 is + begin + INST10: ROM16X1A + generic map (initval => X"BFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_62 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_62 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_62"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE; + + end SLICE_62; + + architecture Structure of SLICE_62 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_4_lut_adj_2: lut40033 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCS_N_137_I_0_4_lut: lut40029 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRRAS_397: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40034 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40034 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE; + + end lut40034; + + architecture Structure of lut40034 is + begin + INST10: ROM16X1A + generic map (initval => X"EEEE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40035 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40035 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE; + + end lut40035; + + architecture Structure of lut40035 is + begin + INST10: ROM16X1A + generic map (initval => X"CFC5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_64 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_64 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_64"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE; + + end SLICE_64; + + architecture Structure of SLICE_64 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40035 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1477_2_lut: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRWE_I_0_455_4_lut: lut40035 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRWE_399: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40036 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40036 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE; + + end lut40036; + + architecture Structure of lut40036 is + begin + INST10: ROM16X1A + generic map (initval => X"3032") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_65 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_65 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_65"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE; + + end SLICE_65; + + architecture Structure of SLICE_65 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40036 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i786_2_lut: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1432_4_lut: lut40036 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRowColSel_402: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40037 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40037 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE; + + end lut40037; + + architecture Structure of lut40037 is + begin + INST10: ROM16X1A + generic map (initval => X"BBBB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_66 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_66 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_66"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE; + + end SLICE_66; + + architecture Structure of SLICE_66 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_23: lut40037 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1439_2_lut: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + S_FSM_i4: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40038 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40038 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE; + + end lut40038; + + architecture Structure of lut40038 is + begin + INST10: ROM16X1A + generic map (initval => X"2222") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_67 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_67 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_67"; + + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE; + + end SLICE_67; + + architecture Structure of SLICE_67 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_10: lut40038 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_FSM_i3: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, + Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40039 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40039 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE; + + end lut40039; + + architecture Structure of lut40039 is + begin + INST10: ROM16X1A + generic map (initval => X"8888") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_68 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_68 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_68"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE; + + end SLICE_68; + + architecture Structure of SLICE_68 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i4_2_lut: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1989_2_lut: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + S_FSM_i2: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, LSR_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_69 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_69 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_69"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE; + + end SLICE_69; + + architecture Structure of SLICE_69 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1491_2_lut_rep_30: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RASr2_I_0_1_lut_rep_25: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + PHI2r3_378: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + S_FSM_i1: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, + F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40040 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40040 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE; + + end lut40040; + + architecture Structure of lut40040 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40041 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40041 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE; + + end lut40041; + + architecture Structure of lut40041 is + begin + INST10: ROM16X1A + generic map (initval => X"3FBB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_70 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_70 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_70"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE; + + end SLICE_70; + + architecture Structure of SLICE_70 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40041 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_4_lut: lut40040 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1448_4_lut: lut40041 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nUFMCS_415: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40042 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40042 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE; + + end lut40042; + + architecture Structure of lut40042 is + begin + INST10: ROM16X1A + generic map (initval => X"1F1F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40043 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40043 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE; + + end lut40043; + + architecture Structure of lut40043 is + begin + INST10: ROM16X1A + generic map (initval => X"5540") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity selmux2 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity selmux2 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE; + + end selmux2; + + architecture Structure of selmux2 is + begin + INST1: MUX21 + port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z); + end Structure; + +-- entity i30_SLICE_71 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity i30_SLICE_71 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "i30_SLICE_71"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF i30_SLICE_71 : ENTITY IS TRUE; + + end i30_SLICE_71; + + architecture Structure of i30_SLICE_71 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal i30_SLICE_71_i30_SLICE_71_K1_H1: Std_logic; + signal i30_SLICE_71_i30_GATE_H0: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40043 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + begin + i30_SLICE_71_K1: lut40042 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, + Z=>i30_SLICE_71_i30_SLICE_71_K1_H1); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i30_GATE: lut40043 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>i30_SLICE_71_i30_GATE_H0); + i30_SLICE_71_K0K1MUX: selmux2 + port map (D0=>i30_SLICE_71_i30_GATE_H0, + D1=>i30_SLICE_71_i30_SLICE_71_K1_H1, SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40044 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40044 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE; + + end lut40044; + + architecture Structure of lut40044 is + begin + INST10: ROM16X1A + generic map (initval => X"FF40") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_72 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_72 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_72"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE; + + end SLICE_72; + + architecture Structure of SLICE_72 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40044 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_4_lut_4_lut_adj_12: lut40044 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_2_lut: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_73 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_73 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_73"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE; + + end SLICE_73; + + architecture Structure of SLICE_73 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40003 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_4_lut_adj_14: lut40003 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i4_4_lut: lut40010 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40045 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40045 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE; + + end lut40045; + + architecture Structure of lut40045 is + begin + INST10: ROM16X1A + generic map (initval => X"0020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_74 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_74 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_74"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE; + + end SLICE_74; + + architecture Structure of SLICE_74 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40045 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i12_4_lut: lut40033 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_3_lut_4_lut: lut40045 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i1: vmuxregsre0004 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i0: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_75 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_75 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_75"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE; + + end SLICE_75; + + architecture Structure of SLICE_75 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_4_lut_adj_18: lut40027 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut: lut40038 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i9: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i8: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_76 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_76 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_76"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE; + + end SLICE_76; + + architecture Structure of SLICE_76 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0007 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_19_3_lut: lut40012 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_rep_15_4_lut: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i9: vmuxregsre0007 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i8: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40046 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40046 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE; + + end lut40046; + + architecture Structure of lut40046 is + begin + INST10: ROM16X1A + generic map (initval => X"0800") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_77 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_77 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_77"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE; + + end SLICE_77; + + architecture Structure of SLICE_77 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40046 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_4_lut_adj_22: lut40046 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut: lut40046 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40047 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40047 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE; + + end lut40047; + + architecture Structure of lut40047 is + begin + INST10: ROM16X1A + generic map (initval => X"F0DD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40048 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40048 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE; + + end lut40048; + + architecture Structure of lut40048 is + begin + INST10: ROM16X1A + generic map (initval => X"DDDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_78 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_78 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_78"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE; + + end SLICE_78; + + architecture Structure of SLICE_78 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40047 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRCS_N_146_bdd_4_lut: lut40047 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1423_2_lut: lut40048 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i13: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i12: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40049 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40049 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE; + + end lut40049; + + architecture Structure of lut40049 is + begin + INST10: ROM16X1A + generic map (initval => X"0200") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_79 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_79 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_79"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE; + + end SLICE_79; + + architecture Structure of SLICE_79 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40049 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i11_3_lut_rep_20: lut40016 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_c_0_bdd_4_lut: lut40049 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i11: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i10: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40050 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40050 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE; + + end lut40050; + + architecture Structure of lut40050 is + begin + INST10: ROM16X1A + generic map (initval => X"0001") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_80 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_80 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_80"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE; + + end SLICE_80; + + architecture Structure of SLICE_80 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40050 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_2_lut_rep_26: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2005_3_lut_rep_17_4_lut: lut40050 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40051 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40051 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE; + + end lut40051; + + architecture Structure of lut40051 is + begin + INST10: ROM16X1A + generic map (initval => X"FCDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_81 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_81 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_81"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE; + + end SLICE_81; + + architecture Structure of SLICE_81 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40051 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_29: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1427_4_lut: lut40051 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i15: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i14: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40052 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40052 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE; + + end lut40052; + + architecture Structure of lut40052 is + begin + INST10: ROM16X1A + generic map (initval => X"8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_82 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_82 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_82"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE; + + end SLICE_82; + + architecture Structure of SLICE_82 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0007 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i6_4_lut: lut40052 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_adj_3: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowA_i5: vmuxregsre0007 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i4: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40053 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40053 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE; + + end lut40053; + + architecture Structure of lut40053 is + begin + INST10: ROM16X1A + generic map (initval => X"0004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40054 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40054 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE; + + end lut40054; + + architecture Structure of lut40054 is + begin + INST10: ROM16X1A + generic map (initval => X"FFDF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_83 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_83 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_83"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE; + + end SLICE_83; + + architecture Structure of SLICE_83 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40053 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40054 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_4_lut_adj_21: lut40053 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_3_lut_4_lut_adj_6: lut40054 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40055 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40055 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE; + + end lut40055; + + architecture Structure of lut40055 is + begin + INST10: ROM16X1A + generic map (initval => X"2020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_84 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_84 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_84"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE; + + end SLICE_84; + + architecture Structure of SLICE_84 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40055 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_rep_28: lut40055 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1573_4_lut: lut40024 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40056 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40056 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE; + + end lut40056; + + architecture Structure of lut40056 is + begin + INST10: ROM16X1A + generic map (initval => X"FFEF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_85 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_85 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_85"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE; + + end SLICE_85; + + architecture Structure of SLICE_85 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40056 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1969_2_lut_3_lut_4_lut: lut40056 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut_adj_7: lut40040 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_86 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_86 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_86"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE; + + end SLICE_86; + + architecture Structure of SLICE_86 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i5_3_lut: lut40012 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_4_lut_adj_8: lut4 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RASr3_381: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + PHI2r_376: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_87 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_87 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_87"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE; + + end SLICE_87; + + architecture Structure of SLICE_87 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i4_4_lut_adj_16: lut40040 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_2_lut: lut40048 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RBA_i2: vmuxregsre0004 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RBA_i1: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40057 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40057 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE; + + end lut40057; + + architecture Structure of lut40057 is + begin + INST10: ROM16X1A + generic map (initval => X"C0C5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_88 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_88 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_88"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE; + + end SLICE_88; + + architecture Structure of SLICE_88 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40053 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40057 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i34_4_lut: lut40057 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut_adj_13: lut40053 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + WRD_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40058 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40058 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE; + + end lut40058; + + architecture Structure of lut40058 is + begin + INST10: ROM16X1A + generic map (initval => X"8088") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40059 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40059 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE; + + end lut40059; + + architecture Structure of lut40059 is + begin + INST10: ROM16X1A + generic map (initval => X"C444") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_89 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_89 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_89"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE; + + end SLICE_89; + + architecture Structure of SLICE_89 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40058 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40059 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_4_lut: lut40058 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut: lut40059 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + WRD_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_90 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_90 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_90"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE; + + end SLICE_90; + + architecture Structure of SLICE_90 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40049 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40055 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut_4_lut_adj_1: lut40049 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_rep_21_3_lut: lut40055 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + WRD_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40060 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40060 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE; + + end lut40060; + + architecture Structure of lut40060 is + begin + INST10: ROM16X1A + generic map (initval => X"DFDF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40061 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40061 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE; + + end lut40061; + + architecture Structure of lut40061 is + begin + INST10: ROM16X1A + generic map (initval => X"DFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_91 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_91 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_91"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE; + + end SLICE_91; + + architecture Structure of SLICE_91 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40060 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_13_3_lut: lut40060 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_3_lut_4_lut_adj_5: lut40061 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i3: vmuxregsre0004 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i2: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40062 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40062 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE; + + end lut40062; + + architecture Structure of lut40062 is + begin + INST10: ROM16X1A + generic map (initval => X"0080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_92 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_92 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_92"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE; + + end SLICE_92; + + architecture Structure of SLICE_92 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40062 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2008_2_lut_4_lut: lut40062 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_rep_22_4_lut: lut40005 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + WRD_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40063 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40063 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE; + + end lut40063; + + architecture Structure of lut40063 is + begin + INST10: ROM16X1A + generic map (initval => X"7777") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_93 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_93 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_93"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE; + + end SLICE_93; + + architecture Structure of SLICE_93 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40063 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2001_2_lut: lut40063 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i10_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40064 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40064 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE; + + end lut40064; + + architecture Structure of lut40064 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_94 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_94 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_94"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE; + + end SLICE_94; + + architecture Structure of SLICE_94 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40064 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i771_2_lut_rep_23_2_lut: lut40048 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_4_lut_4_lut: lut40064 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40065 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40065 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE; + + end lut40065; + + architecture Structure of lut40065 is + begin + INST10: ROM16X1A + generic map (initval => X"1404") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_95 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_95 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_95"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_95 : ENTITY IS TRUE; + + end SLICE_95; + + architecture Structure of SLICE_95 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40065 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_4_lut_adj_20: lut40065 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i6_4_lut_adj_9: lut40040 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_96 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_96 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_96"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_96 : ENTITY IS TRUE; + + end SLICE_96; + + architecture Structure of SLICE_96 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_27: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_4_lut_adj_24: lut40027 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40066 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40066 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE; + + end lut40066; + + architecture Structure of lut40066 is + begin + INST10: ROM16X1A + generic map (initval => X"C5C5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_97 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_97 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_97"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_97 : ENTITY IS TRUE; + + end SLICE_97; + + architecture Structure of SLICE_97 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40066 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i13_3_lut: lut40066 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1956_2_lut: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + IS_FSM_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_98 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_98 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_98"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_98 : ENTITY IS TRUE; + + end SLICE_98; + + architecture Structure of SLICE_98 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1416_2_lut: lut40037 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i9_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + IS_FSM_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_99 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_99 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_99"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_99 : ENTITY IS TRUE; + + end SLICE_99; + + architecture Structure of SLICE_99 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i8_4_lut: lut40052 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + MAin_9_I_0_427_i8_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdUFMSDI_414: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_100 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_100 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_100"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_100 : ENTITY IS TRUE; + + end SLICE_100; + + architecture Structure of SLICE_100 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1979_4_lut: lut40052 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + MAin_9_I_0_427_i7_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdUFMCS_412: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + CmdUFMCLK_413: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_101 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_101 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_101"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_101 : ENTITY IS TRUE; + + end SLICE_101; + + architecture Structure of SLICE_101 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i1_3_lut: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i6_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_102 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_102 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_102"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_102 : ENTITY IS TRUE; + + end SLICE_102; + + architecture Structure of SLICE_102 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i2_3_lut: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i5_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_103 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_103 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_103"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_103 : ENTITY IS TRUE; + + end SLICE_103; + + architecture Structure of SLICE_103 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i3_3_lut: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i4_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40067 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40067 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE; + + end lut40067; + + architecture Structure of lut40067 is + begin + INST10: ROM16X1A + generic map (initval => X"FDFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_104 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_104 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_104"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_104 : ENTITY IS TRUE; + + end SLICE_104; + + architecture Structure of SLICE_104 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40067 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1417_2_lut: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_rep_14_3_lut: lut40067 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RowA_i7: vmuxregsre0004 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i6: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_105 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_105 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_105"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_105 : ENTITY IS TRUE; + + end SLICE_105; + + architecture Structure of SLICE_105 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_19: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i5_4_lut: lut40052 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_106 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_106 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_106"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_106 : ENTITY IS TRUE; + + end SLICE_106; + + architecture Structure of SLICE_106 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_33: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1930_2_lut: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + IS_FSM_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, + CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf is + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf : ENTITY IS TRUE; + + end xo2iobuf; + + architecture Structure of xo2iobuf is + begin + INST1: IBPD + port map (I=>PADI, O=>Z); + INST2: OBZPD + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity RD_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_7_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD7 : VitalDelayType := 0 ns; + tpw_RD7_posedge : VitalDelayType := 0 ns; + tpw_RD7_negedge : VitalDelayType := 0 ns; + tpd_RD7_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD7: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE; + + end RD_7_B; + + architecture Structure of RD_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD7_ipd : std_logic := 'X'; + signal RD7_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_7_713: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, + PADI=>RD7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD7_ipd, RD7, tipd_RD7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD7_zd : std_logic := 'X'; + VARIABLE RD7_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD7_RD7 : x01 := '0'; + VARIABLE periodcheckinfo_RD7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD7_ipd, + TestSignalName => "RD7", + Period => tperiod_RD7, + PulseWidthHigh => tpw_RD7_posedge, + PulseWidthLow => tpw_RD7_negedge, + PeriodData => periodcheckinfo_RD7, + Violation => tviol_RD7_RD7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD7_zd := RD7_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD7_ipd'last_event, + PathDelay => tpd_RD7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD7, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD7, + PathCondition => TRUE)), + GlitchData => RD7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_6_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD6 : VitalDelayType := 0 ns; + tpw_RD6_posedge : VitalDelayType := 0 ns; + tpw_RD6_negedge : VitalDelayType := 0 ns; + tpd_RD6_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD6: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE; + + end RD_6_B; + + architecture Structure of RD_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD6_ipd : std_logic := 'X'; + signal RD6_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_6_714: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, + PADI=>RD6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD6_ipd, RD6, tipd_RD6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD6_zd : std_logic := 'X'; + VARIABLE RD6_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD6_RD6 : x01 := '0'; + VARIABLE periodcheckinfo_RD6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD6_ipd, + TestSignalName => "RD6", + Period => tperiod_RD6, + PulseWidthHigh => tpw_RD6_posedge, + PulseWidthLow => tpw_RD6_negedge, + PeriodData => periodcheckinfo_RD6, + Violation => tviol_RD6_RD6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD6_zd := RD6_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD6_ipd'last_event, + PathDelay => tpd_RD6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD6, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD6, + PathCondition => TRUE)), + GlitchData => RD6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_5_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD5 : VitalDelayType := 0 ns; + tpw_RD5_posedge : VitalDelayType := 0 ns; + tpw_RD5_negedge : VitalDelayType := 0 ns; + tpd_RD5_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD5: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE; + + end RD_5_B; + + architecture Structure of RD_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD5_ipd : std_logic := 'X'; + signal RD5_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_5_715: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, + PADI=>RD5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD5_ipd, RD5, tipd_RD5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD5_zd : std_logic := 'X'; + VARIABLE RD5_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD5_RD5 : x01 := '0'; + VARIABLE periodcheckinfo_RD5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD5_ipd, + TestSignalName => "RD5", + Period => tperiod_RD5, + PulseWidthHigh => tpw_RD5_posedge, + PulseWidthLow => tpw_RD5_negedge, + PeriodData => periodcheckinfo_RD5, + Violation => tviol_RD5_RD5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD5_zd := RD5_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD5_ipd'last_event, + PathDelay => tpd_RD5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD5, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD5, + PathCondition => TRUE)), + GlitchData => RD5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_4_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD4 : VitalDelayType := 0 ns; + tpw_RD4_posedge : VitalDelayType := 0 ns; + tpw_RD4_negedge : VitalDelayType := 0 ns; + tpd_RD4_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD4: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE; + + end RD_4_B; + + architecture Structure of RD_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD4_ipd : std_logic := 'X'; + signal RD4_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_4_716: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, + PADI=>RD4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD4_ipd, RD4, tipd_RD4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD4_zd : std_logic := 'X'; + VARIABLE RD4_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD4_RD4 : x01 := '0'; + VARIABLE periodcheckinfo_RD4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD4_ipd, + TestSignalName => "RD4", + Period => tperiod_RD4, + PulseWidthHigh => tpw_RD4_posedge, + PulseWidthLow => tpw_RD4_negedge, + PeriodData => periodcheckinfo_RD4, + Violation => tviol_RD4_RD4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD4_zd := RD4_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD4_ipd'last_event, + PathDelay => tpd_RD4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD4, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD4, + PathCondition => TRUE)), + GlitchData => RD4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_3_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD3 : VitalDelayType := 0 ns; + tpw_RD3_posedge : VitalDelayType := 0 ns; + tpw_RD3_negedge : VitalDelayType := 0 ns; + tpd_RD3_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD3: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE; + + end RD_3_B; + + architecture Structure of RD_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD3_ipd : std_logic := 'X'; + signal RD3_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_3_717: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, + PADI=>RD3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD3_ipd, RD3, tipd_RD3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD3_zd : std_logic := 'X'; + VARIABLE RD3_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD3_RD3 : x01 := '0'; + VARIABLE periodcheckinfo_RD3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD3_ipd, + TestSignalName => "RD3", + Period => tperiod_RD3, + PulseWidthHigh => tpw_RD3_posedge, + PulseWidthLow => tpw_RD3_negedge, + PeriodData => periodcheckinfo_RD3, + Violation => tviol_RD3_RD3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD3_zd := RD3_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD3_ipd'last_event, + PathDelay => tpd_RD3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD3, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD3, + PathCondition => TRUE)), + GlitchData => RD3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_2_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD2 : VitalDelayType := 0 ns; + tpw_RD2_posedge : VitalDelayType := 0 ns; + tpw_RD2_negedge : VitalDelayType := 0 ns; + tpd_RD2_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD2: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE; + + end RD_2_B; + + architecture Structure of RD_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD2_ipd : std_logic := 'X'; + signal RD2_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_2_718: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, + PADI=>RD2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD2_ipd, RD2, tipd_RD2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD2_zd : std_logic := 'X'; + VARIABLE RD2_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD2_RD2 : x01 := '0'; + VARIABLE periodcheckinfo_RD2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD2_ipd, + TestSignalName => "RD2", + Period => tperiod_RD2, + PulseWidthHigh => tpw_RD2_posedge, + PulseWidthLow => tpw_RD2_negedge, + PeriodData => periodcheckinfo_RD2, + Violation => tviol_RD2_RD2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD2_zd := RD2_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD2_ipd'last_event, + PathDelay => tpd_RD2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD2, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD2, + PathCondition => TRUE)), + GlitchData => RD2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_1_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD1 : VitalDelayType := 0 ns; + tpw_RD1_posedge : VitalDelayType := 0 ns; + tpw_RD1_negedge : VitalDelayType := 0 ns; + tpd_RD1_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD1: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE; + + end RD_1_B; + + architecture Structure of RD_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD1_ipd : std_logic := 'X'; + signal RD1_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_1_719: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, + PADI=>RD1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD1_ipd, RD1, tipd_RD1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD1_zd : std_logic := 'X'; + VARIABLE RD1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD1_RD1 : x01 := '0'; + VARIABLE periodcheckinfo_RD1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD1_ipd, + TestSignalName => "RD1", + Period => tperiod_RD1, + PulseWidthHigh => tpw_RD1_posedge, + PulseWidthLow => tpw_RD1_negedge, + PeriodData => periodcheckinfo_RD1, + Violation => tviol_RD1_RD1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD1_zd := RD1_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD1_ipd'last_event, + PathDelay => tpd_RD1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD1, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD1, + PathCondition => TRUE)), + GlitchData => RD1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_0_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD0 : VitalDelayType := 0 ns; + tpw_RD0_posedge : VitalDelayType := 0 ns; + tpw_RD0_negedge : VitalDelayType := 0 ns; + tpd_RD0_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD0: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE; + + end RD_0_B; + + architecture Structure of RD_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD0_ipd : std_logic := 'X'; + signal RD0_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_0_720: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, + PADI=>RD0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD0_ipd, RD0, tipd_RD0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD0_zd : std_logic := 'X'; + VARIABLE RD0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD0_RD0 : x01 := '0'; + VARIABLE periodcheckinfo_RD0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD0_ipd, + TestSignalName => "RD0", + Period => tperiod_RD0, + PulseWidthHigh => tpw_RD0_posedge, + PulseWidthLow => tpw_RD0_negedge, + PeriodData => periodcheckinfo_RD0, + Violation => tviol_RD0_RD0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD0_zd := RD0_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD0_ipd'last_event, + PathDelay => tpd_RD0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD0, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD0, + PathCondition => TRUE)), + GlitchData => RD0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0068 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0068 is + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0068 : ENTITY IS TRUE; + + end xo2iobuf0068; + + architecture Structure of xo2iobuf0068 is + begin + INST5: OBZPD + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity Dout_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout7 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE; + + end Dout_7_B; + + architecture Structure of Dout_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout7_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_7: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout7_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout7_out) + VARIABLE Dout7_zd : std_logic := 'X'; + VARIABLE Dout7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout7_zd := Dout7_out; + + VitalPathDelay01 ( + OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout7, + PathCondition => TRUE)), + GlitchData => Dout7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout6 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE; + + end Dout_6_B; + + architecture Structure of Dout_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout6_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_6: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout6_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout6_out) + VARIABLE Dout6_zd : std_logic := 'X'; + VARIABLE Dout6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout6_zd := Dout6_out; + + VitalPathDelay01 ( + OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout6, + PathCondition => TRUE)), + GlitchData => Dout6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout5 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE; + + end Dout_5_B; + + architecture Structure of Dout_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout5_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_5: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout5_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout5_out) + VARIABLE Dout5_zd : std_logic := 'X'; + VARIABLE Dout5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout5_zd := Dout5_out; + + VitalPathDelay01 ( + OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout5, + PathCondition => TRUE)), + GlitchData => Dout5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout4 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE; + + end Dout_4_B; + + architecture Structure of Dout_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout4_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_4: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout4_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout4_out) + VARIABLE Dout4_zd : std_logic := 'X'; + VARIABLE Dout4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout4_zd := Dout4_out; + + VitalPathDelay01 ( + OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout4, + PathCondition => TRUE)), + GlitchData => Dout4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout3 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE; + + end Dout_3_B; + + architecture Structure of Dout_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout3_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_3: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout3_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout3_out) + VARIABLE Dout3_zd : std_logic := 'X'; + VARIABLE Dout3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout3_zd := Dout3_out; + + VitalPathDelay01 ( + OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout3, + PathCondition => TRUE)), + GlitchData => Dout3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout2 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE; + + end Dout_2_B; + + architecture Structure of Dout_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout2_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_2: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout2_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout2_out) + VARIABLE Dout2_zd : std_logic := 'X'; + VARIABLE Dout2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout2_zd := Dout2_out; + + VitalPathDelay01 ( + OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout2, + PathCondition => TRUE)), + GlitchData => Dout2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE; + + end Dout_1_B; + + architecture Structure of Dout_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_1: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout1_out) + VARIABLE Dout1_zd : std_logic := 'X'; + VARIABLE Dout1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout1_zd := Dout1_out; + + VitalPathDelay01 ( + OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout1, + PathCondition => TRUE)), + GlitchData => Dout1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE; + + end Dout_0_B; + + architecture Structure of Dout_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_0: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout0_out) + VARIABLE Dout0_zd : std_logic := 'X'; + VARIABLE Dout0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout0_zd := Dout0_out; + + VitalPathDelay01 ( + OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout0, + PathCondition => TRUE)), + GlitchData => Dout0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity LEDB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity LEDB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "LEDB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_LEDS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; LEDS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE; + + end LEDB; + + architecture Structure of LEDB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal LEDS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + LED_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>LEDS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, LEDS_out) + VARIABLE LEDS_zd : std_logic := 'X'; + VARIABLE LEDS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + LEDS_zd := LEDS_out; + + VitalPathDelay01 ( + OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_LEDS, + PathCondition => TRUE)), + GlitchData => LEDS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RBA1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RBA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE; + + end RBA_1_B; + + architecture Structure of RBA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RBA1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_1: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RBA1_out) + VARIABLE RBA1_zd : std_logic := 'X'; + VARIABLE RBA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA1_zd := RBA1_out; + + VitalPathDelay01 ( + OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RBA1, + PathCondition => TRUE)), + GlitchData => RBA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RBA0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RBA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE; + + end RBA_0_B; + + architecture Structure of RBA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RBA0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_0: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RBA0_out) + VARIABLE RBA0_zd : std_logic := 'X'; + VARIABLE RBA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA0_zd := RBA0_out; + + VitalPathDelay01 ( + OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RBA0, + PathCondition => TRUE)), + GlitchData => RBA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_11_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_11_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_11_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA11 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA11: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE; + + end RA_11_B; + + architecture Structure of RA_11_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA11_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_11: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA11_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA11_out) + VARIABLE RA11_zd : std_logic := 'X'; + VARIABLE RA11_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA11_zd := RA11_out; + + VitalPathDelay01 ( + OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA11, + PathCondition => TRUE)), + GlitchData => RA11_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_10_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_10_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_10_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA10 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA10: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE; + + end RA_10_B; + + architecture Structure of RA_10_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA10_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_10: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA10_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA10_out) + VARIABLE RA10_zd : std_logic := 'X'; + VARIABLE RA10_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA10_zd := RA10_out; + + VitalPathDelay01 ( + OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA10, + PathCondition => TRUE)), + GlitchData => RA10_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_9_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_9_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA9 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA9: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE; + + end RA_9_B; + + architecture Structure of RA_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA9_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_9: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA9_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA9_out) + VARIABLE RA9_zd : std_logic := 'X'; + VARIABLE RA9_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA9_zd := RA9_out; + + VitalPathDelay01 ( + OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA9, + PathCondition => TRUE)), + GlitchData => RA9_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_8_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_8_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA8 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA8: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE; + + end RA_8_B; + + architecture Structure of RA_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA8_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_8: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA8_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA8_out) + VARIABLE RA8_zd : std_logic := 'X'; + VARIABLE RA8_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA8_zd := RA8_out; + + VitalPathDelay01 ( + OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA8, + PathCondition => TRUE)), + GlitchData => RA8_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA7 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE; + + end RA_7_B; + + architecture Structure of RA_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA7_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_7: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA7_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA7_out) + VARIABLE RA7_zd : std_logic := 'X'; + VARIABLE RA7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA7_zd := RA7_out; + + VitalPathDelay01 ( + OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA7, + PathCondition => TRUE)), + GlitchData => RA7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA6 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE; + + end RA_6_B; + + architecture Structure of RA_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA6_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_6: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA6_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA6_out) + VARIABLE RA6_zd : std_logic := 'X'; + VARIABLE RA6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA6_zd := RA6_out; + + VitalPathDelay01 ( + OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA6, + PathCondition => TRUE)), + GlitchData => RA6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA5 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE; + + end RA_5_B; + + architecture Structure of RA_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA5_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_5: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA5_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA5_out) + VARIABLE RA5_zd : std_logic := 'X'; + VARIABLE RA5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA5_zd := RA5_out; + + VitalPathDelay01 ( + OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA5, + PathCondition => TRUE)), + GlitchData => RA5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA4 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE; + + end RA_4_B; + + architecture Structure of RA_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA4_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_4: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA4_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA4_out) + VARIABLE RA4_zd : std_logic := 'X'; + VARIABLE RA4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA4_zd := RA4_out; + + VitalPathDelay01 ( + OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA4, + PathCondition => TRUE)), + GlitchData => RA4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA3 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE; + + end RA_3_B; + + architecture Structure of RA_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA3_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_3: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA3_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA3_out) + VARIABLE RA3_zd : std_logic := 'X'; + VARIABLE RA3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA3_zd := RA3_out; + + VitalPathDelay01 ( + OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA3, + PathCondition => TRUE)), + GlitchData => RA3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA2 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE; + + end RA_2_B; + + architecture Structure of RA_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA2_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_2: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA2_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA2_out) + VARIABLE RA2_zd : std_logic := 'X'; + VARIABLE RA2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA2_zd := RA2_out; + + VitalPathDelay01 ( + OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA2, + PathCondition => TRUE)), + GlitchData => RA2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE; + + end RA_1_B; + + architecture Structure of RA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_1: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA1_out) + VARIABLE RA1_zd : std_logic := 'X'; + VARIABLE RA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA1_zd := RA1_out; + + VitalPathDelay01 ( + OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA1, + PathCondition => TRUE)), + GlitchData => RA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE; + + end RA_0_B; + + architecture Structure of RA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_0: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA0_out) + VARIABLE RA0_zd : std_logic := 'X'; + VARIABLE RA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA0_zd := RA0_out; + + VitalPathDelay01 ( + OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA0, + PathCondition => TRUE)), + GlitchData => RA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCSB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCSB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRCSS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nRCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE; + + end nRCSB; + + architecture Structure of nRCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRCSS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCS_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCSS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out) + VARIABLE nRCSS_zd : std_logic := 'X'; + VARIABLE nRCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCSS_zd := nRCSS_out; + + VitalPathDelay01 ( + OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRCSS, + PathCondition => TRUE)), + GlitchData => nRCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCKEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RCKEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCKEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RCKES : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RCKES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE; + + end RCKEB; + + architecture Structure of RCKEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RCKES_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RCKE_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RCKES_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RCKES_out) + VARIABLE RCKES_zd : std_logic := 'X'; + VARIABLE RCKES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RCKES_zd := RCKES_out; + + VitalPathDelay01 ( + OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RCKES, + PathCondition => TRUE)), + GlitchData => RCKES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRWEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRWEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRWES : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nRWES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE; + + end nRWEB; + + architecture Structure of nRWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRWES_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRWE_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRWES_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRWES_out) + VARIABLE nRWES_zd : std_logic := 'X'; + VARIABLE nRWES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRWES_zd := nRWES_out; + + VitalPathDelay01 ( + OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRWES, + PathCondition => TRUE)), + GlitchData => nRWES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRRASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRRASB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRRASS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nRRASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE; + + end nRRASB; + + architecture Structure of nRRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRRASS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRRAS_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRRASS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out) + VARIABLE nRRASS_zd : std_logic := 'X'; + VARIABLE nRRASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRRASS_zd := nRRASS_out; + + VitalPathDelay01 ( + OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRRASS, + PathCondition => TRUE)), + GlitchData => nRRASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCASB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRCASS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nRCASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE; + + end nRCASB; + + architecture Structure of nRCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRCASS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCAS_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCASS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out) + VARIABLE nRCASS_zd : std_logic := 'X'; + VARIABLE nRCASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCASS_zd := nRCASS_out; + + VitalPathDelay01 ( + OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRCASS, + PathCondition => TRUE)), + GlitchData => nRCASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMHB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RDQMHB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMHB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMHS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE; + + end RDQMHB; + + architecture Structure of RDQMHB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMHS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQMH_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMHS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out) + VARIABLE RDQMHS_zd : std_logic := 'X'; + VARIABLE RDQMHS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMHS_zd := RDQMHS_out; + + VitalPathDelay01 ( + OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMHS, + PathCondition => TRUE)), + GlitchData => RDQMHS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMLB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RDQMLB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMLB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMLS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE; + + end RDQMLB; + + architecture Structure of RDQMLB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMLS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQML_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMLS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out) + VARIABLE RDQMLS_zd : std_logic := 'X'; + VARIABLE RDQMLS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMLS_zd := RDQMLS_out; + + VitalPathDelay01 ( + OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMLS, + PathCondition => TRUE)), + GlitchData => RDQMLS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nUFMCSB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nUFMCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nUFMCSB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nUFMCSS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE; + + end nUFMCSB; + + architecture Structure of nUFMCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nUFMCSS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nUFMCS_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nUFMCSS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out) + VARIABLE nUFMCSS_zd : std_logic := 'X'; + VARIABLE nUFMCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nUFMCSS_zd := nUFMCSS_out; + + VitalPathDelay01 ( + OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nUFMCSS, + PathCondition => TRUE)), + GlitchData => nUFMCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMCLKB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMCLKB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_UFMCLKS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE; + + end UFMCLKB; + + architecture Structure of UFMCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal UFMCLKS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMCLK_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMCLKS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out) + VARIABLE UFMCLKS_zd : std_logic := 'X'; + VARIABLE UFMCLKS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMCLKS_zd := UFMCLKS_out; + + VitalPathDelay01 ( + OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_UFMCLKS, + PathCondition => TRUE)), + GlitchData => UFMCLKS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDIB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMSDIB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDIB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_UFMSDIS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE; + + end UFMSDIB; + + architecture Structure of UFMSDIB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal UFMSDIS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMSDI_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMSDIS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out) + VARIABLE UFMSDIS_zd : std_logic := 'X'; + VARIABLE UFMSDIS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMSDIS_zd := UFMSDIS_out; + + VitalPathDelay01 ( + OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_UFMSDIS, + PathCondition => TRUE)), + GlitchData => UFMSDIS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0069 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0069 is + port (Z: out Std_logic; PAD: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0069 : ENTITY IS TRUE; + + end xo2iobuf0069; + + architecture Structure of xo2iobuf0069 is + begin + INST1: IBPD + port map (I=>PAD, O=>Z); + end Structure; + +-- entity PHI2B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity PHI2B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "PHI2B"; + + tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns); + tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_PHI2S : VitalDelayType := 0 ns; + tpw_PHI2S_posedge : VitalDelayType := 0 ns; + tpw_PHI2S_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; PHI2S: in Std_logic); + + ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE; + + end PHI2B; + + architecture Structure of PHI2B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PHI2S_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + PHI2_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>PHI2S_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_PHI2S_PHI2S : x01 := '0'; + VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => PHI2S_ipd, + TestSignalName => "PHI2S", + Period => tperiod_PHI2S, + PulseWidthHigh => tpw_PHI2S_posedge, + PulseWidthLow => tpw_PHI2S_negedge, + PeriodData => periodcheckinfo_PHI2S, + Violation => tviol_PHI2S_PHI2S, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event, + PathDelay => tpd_PHI2S_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_9_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_9_B"; + + tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin9 : VitalDelayType := 0 ns; + tpw_MAin9_posedge : VitalDelayType := 0 ns; + tpw_MAin9_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin9: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE; + + end MAin_9_B; + + architecture Structure of MAin_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin9_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_9: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin9_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin9_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin9_MAin9 : x01 := '0'; + VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin9_ipd, + TestSignalName => "MAin9", + Period => tperiod_MAin9, + PulseWidthHigh => tpw_MAin9_posedge, + PulseWidthLow => tpw_MAin9_negedge, + PeriodData => periodcheckinfo_MAin9, + Violation => tviol_MAin9_MAin9, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin9_ipd'last_event, + PathDelay => tpd_MAin9_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_8_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_8_B"; + + tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin8 : VitalDelayType := 0 ns; + tpw_MAin8_posedge : VitalDelayType := 0 ns; + tpw_MAin8_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin8: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE; + + end MAin_8_B; + + architecture Structure of MAin_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin8_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_8: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin8_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin8_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin8_MAin8 : x01 := '0'; + VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin8_ipd, + TestSignalName => "MAin8", + Period => tperiod_MAin8, + PulseWidthHigh => tpw_MAin8_posedge, + PulseWidthLow => tpw_MAin8_negedge, + PeriodData => periodcheckinfo_MAin8, + Violation => tviol_MAin8_MAin8, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin8_ipd'last_event, + PathDelay => tpd_MAin8_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_7_B"; + + tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin7 : VitalDelayType := 0 ns; + tpw_MAin7_posedge : VitalDelayType := 0 ns; + tpw_MAin7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE; + + end MAin_7_B; + + architecture Structure of MAin_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin7_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_7: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin7_MAin7 : x01 := '0'; + VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin7_ipd, + TestSignalName => "MAin7", + Period => tperiod_MAin7, + PulseWidthHigh => tpw_MAin7_posedge, + PulseWidthLow => tpw_MAin7_negedge, + PeriodData => periodcheckinfo_MAin7, + Violation => tviol_MAin7_MAin7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin7_ipd'last_event, + PathDelay => tpd_MAin7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_6_B"; + + tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin6 : VitalDelayType := 0 ns; + tpw_MAin6_posedge : VitalDelayType := 0 ns; + tpw_MAin6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE; + + end MAin_6_B; + + architecture Structure of MAin_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin6_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_6: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin6_MAin6 : x01 := '0'; + VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin6_ipd, + TestSignalName => "MAin6", + Period => tperiod_MAin6, + PulseWidthHigh => tpw_MAin6_posedge, + PulseWidthLow => tpw_MAin6_negedge, + PeriodData => periodcheckinfo_MAin6, + Violation => tviol_MAin6_MAin6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin6_ipd'last_event, + PathDelay => tpd_MAin6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_5_B"; + + tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin5 : VitalDelayType := 0 ns; + tpw_MAin5_posedge : VitalDelayType := 0 ns; + tpw_MAin5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE; + + end MAin_5_B; + + architecture Structure of MAin_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin5_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_5: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin5_MAin5 : x01 := '0'; + VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin5_ipd, + TestSignalName => "MAin5", + Period => tperiod_MAin5, + PulseWidthHigh => tpw_MAin5_posedge, + PulseWidthLow => tpw_MAin5_negedge, + PeriodData => periodcheckinfo_MAin5, + Violation => tviol_MAin5_MAin5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin5_ipd'last_event, + PathDelay => tpd_MAin5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_4_B"; + + tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin4 : VitalDelayType := 0 ns; + tpw_MAin4_posedge : VitalDelayType := 0 ns; + tpw_MAin4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE; + + end MAin_4_B; + + architecture Structure of MAin_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin4_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_4: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin4_MAin4 : x01 := '0'; + VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin4_ipd, + TestSignalName => "MAin4", + Period => tperiod_MAin4, + PulseWidthHigh => tpw_MAin4_posedge, + PulseWidthLow => tpw_MAin4_negedge, + PeriodData => periodcheckinfo_MAin4, + Violation => tviol_MAin4_MAin4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin4_ipd'last_event, + PathDelay => tpd_MAin4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_3_B"; + + tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin3 : VitalDelayType := 0 ns; + tpw_MAin3_posedge : VitalDelayType := 0 ns; + tpw_MAin3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE; + + end MAin_3_B; + + architecture Structure of MAin_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin3_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_3: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin3_MAin3 : x01 := '0'; + VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin3_ipd, + TestSignalName => "MAin3", + Period => tperiod_MAin3, + PulseWidthHigh => tpw_MAin3_posedge, + PulseWidthLow => tpw_MAin3_negedge, + PeriodData => periodcheckinfo_MAin3, + Violation => tviol_MAin3_MAin3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin3_ipd'last_event, + PathDelay => tpd_MAin3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_2_B"; + + tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin2 : VitalDelayType := 0 ns; + tpw_MAin2_posedge : VitalDelayType := 0 ns; + tpw_MAin2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE; + + end MAin_2_B; + + architecture Structure of MAin_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin2_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_2: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin2_MAin2 : x01 := '0'; + VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin2_ipd, + TestSignalName => "MAin2", + Period => tperiod_MAin2, + PulseWidthHigh => tpw_MAin2_posedge, + PulseWidthLow => tpw_MAin2_negedge, + PeriodData => periodcheckinfo_MAin2, + Violation => tviol_MAin2_MAin2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin2_ipd'last_event, + PathDelay => tpd_MAin2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_1_B"; + + tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin1 : VitalDelayType := 0 ns; + tpw_MAin1_posedge : VitalDelayType := 0 ns; + tpw_MAin1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE; + + end MAin_1_B; + + architecture Structure of MAin_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin1_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_1: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin1_MAin1 : x01 := '0'; + VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin1_ipd, + TestSignalName => "MAin1", + Period => tperiod_MAin1, + PulseWidthHigh => tpw_MAin1_posedge, + PulseWidthLow => tpw_MAin1_negedge, + PeriodData => periodcheckinfo_MAin1, + Violation => tviol_MAin1_MAin1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin1_ipd'last_event, + PathDelay => tpd_MAin1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_0_B"; + + tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin0 : VitalDelayType := 0 ns; + tpw_MAin0_posedge : VitalDelayType := 0 ns; + tpw_MAin0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE; + + end MAin_0_B; + + architecture Structure of MAin_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin0_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_0: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin0_MAin0 : x01 := '0'; + VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin0_ipd, + TestSignalName => "MAin0", + Period => tperiod_MAin0, + PulseWidthHigh => tpw_MAin0_posedge, + PulseWidthLow => tpw_MAin0_negedge, + PeriodData => periodcheckinfo_MAin0, + Violation => tviol_MAin0_MAin0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin0_ipd'last_event, + PathDelay => tpd_MAin0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity CROW_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_1_B"; + + tipd_CROW1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW1 : VitalDelayType := 0 ns; + tpw_CROW1_posedge : VitalDelayType := 0 ns; + tpw_CROW1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE; + + end CROW_1_B; + + architecture Structure of CROW_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW1_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_1: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>CROW1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW1_CROW1 : x01 := '0'; + VARIABLE periodcheckinfo_CROW1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW1_ipd, + TestSignalName => "CROW1", + Period => tperiod_CROW1, + PulseWidthHigh => tpw_CROW1_posedge, + PulseWidthLow => tpw_CROW1_negedge, + PeriodData => periodcheckinfo_CROW1, + Violation => tviol_CROW1_CROW1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW1_ipd'last_event, + PathDelay => tpd_CROW1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity CROW_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_0_B"; + + tipd_CROW0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW0 : VitalDelayType := 0 ns; + tpw_CROW0_posedge : VitalDelayType := 0 ns; + tpw_CROW0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE; + + end CROW_0_B; + + architecture Structure of CROW_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW0_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_0: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>CROW0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW0_CROW0 : x01 := '0'; + VARIABLE periodcheckinfo_CROW0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW0_ipd, + TestSignalName => "CROW0", + Period => tperiod_CROW0, + PulseWidthHigh => tpw_CROW0_posedge, + PulseWidthLow => tpw_CROW0_negedge, + PeriodData => periodcheckinfo_CROW0, + Violation => tviol_CROW0_CROW0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW0_ipd'last_event, + PathDelay => tpd_CROW0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_7_B"; + + tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din7 : VitalDelayType := 0 ns; + tpw_Din7_posedge : VitalDelayType := 0 ns; + tpw_Din7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE; + + end Din_7_B; + + architecture Structure of Din_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din7_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_7: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din7_ipd, Din7, tipd_Din7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din7_Din7 : x01 := '0'; + VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din7_ipd, + TestSignalName => "Din7", + Period => tperiod_Din7, + PulseWidthHigh => tpw_Din7_posedge, + PulseWidthLow => tpw_Din7_negedge, + PeriodData => periodcheckinfo_Din7, + Violation => tviol_Din7_Din7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din7_ipd'last_event, + PathDelay => tpd_Din7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_6_B"; + + tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din6 : VitalDelayType := 0 ns; + tpw_Din6_posedge : VitalDelayType := 0 ns; + tpw_Din6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE; + + end Din_6_B; + + architecture Structure of Din_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din6_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_6: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din6_ipd, Din6, tipd_Din6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din6_Din6 : x01 := '0'; + VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din6_ipd, + TestSignalName => "Din6", + Period => tperiod_Din6, + PulseWidthHigh => tpw_Din6_posedge, + PulseWidthLow => tpw_Din6_negedge, + PeriodData => periodcheckinfo_Din6, + Violation => tviol_Din6_Din6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din6_ipd'last_event, + PathDelay => tpd_Din6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_5_B"; + + tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din5 : VitalDelayType := 0 ns; + tpw_Din5_posedge : VitalDelayType := 0 ns; + tpw_Din5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE; + + end Din_5_B; + + architecture Structure of Din_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din5_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_5: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din5_ipd, Din5, tipd_Din5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din5_Din5 : x01 := '0'; + VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din5_ipd, + TestSignalName => "Din5", + Period => tperiod_Din5, + PulseWidthHigh => tpw_Din5_posedge, + PulseWidthLow => tpw_Din5_negedge, + PeriodData => periodcheckinfo_Din5, + Violation => tviol_Din5_Din5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din5_ipd'last_event, + PathDelay => tpd_Din5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_4_B"; + + tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din4 : VitalDelayType := 0 ns; + tpw_Din4_posedge : VitalDelayType := 0 ns; + tpw_Din4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE; + + end Din_4_B; + + architecture Structure of Din_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din4_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_4: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din4_ipd, Din4, tipd_Din4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din4_Din4 : x01 := '0'; + VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din4_ipd, + TestSignalName => "Din4", + Period => tperiod_Din4, + PulseWidthHigh => tpw_Din4_posedge, + PulseWidthLow => tpw_Din4_negedge, + PeriodData => periodcheckinfo_Din4, + Violation => tviol_Din4_Din4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din4_ipd'last_event, + PathDelay => tpd_Din4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_3_B"; + + tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din3 : VitalDelayType := 0 ns; + tpw_Din3_posedge : VitalDelayType := 0 ns; + tpw_Din3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE; + + end Din_3_B; + + architecture Structure of Din_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din3_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_3: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din3_ipd, Din3, tipd_Din3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din3_Din3 : x01 := '0'; + VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din3_ipd, + TestSignalName => "Din3", + Period => tperiod_Din3, + PulseWidthHigh => tpw_Din3_posedge, + PulseWidthLow => tpw_Din3_negedge, + PeriodData => periodcheckinfo_Din3, + Violation => tviol_Din3_Din3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din3_ipd'last_event, + PathDelay => tpd_Din3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_2_B"; + + tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din2 : VitalDelayType := 0 ns; + tpw_Din2_posedge : VitalDelayType := 0 ns; + tpw_Din2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE; + + end Din_2_B; + + architecture Structure of Din_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din2_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_2: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din2_ipd, Din2, tipd_Din2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din2_Din2 : x01 := '0'; + VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din2_ipd, + TestSignalName => "Din2", + Period => tperiod_Din2, + PulseWidthHigh => tpw_Din2_posedge, + PulseWidthLow => tpw_Din2_negedge, + PeriodData => periodcheckinfo_Din2, + Violation => tviol_Din2_Din2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din2_ipd'last_event, + PathDelay => tpd_Din2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_1_B"; + + tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din1 : VitalDelayType := 0 ns; + tpw_Din1_posedge : VitalDelayType := 0 ns; + tpw_Din1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE; + + end Din_1_B; + + architecture Structure of Din_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din1_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_1: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din1_ipd, Din1, tipd_Din1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din1_Din1 : x01 := '0'; + VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din1_ipd, + TestSignalName => "Din1", + Period => tperiod_Din1, + PulseWidthHigh => tpw_Din1_posedge, + PulseWidthLow => tpw_Din1_negedge, + PeriodData => periodcheckinfo_Din1, + Violation => tviol_Din1_Din1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din1_ipd'last_event, + PathDelay => tpd_Din1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_0_B"; + + tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din0 : VitalDelayType := 0 ns; + tpw_Din0_posedge : VitalDelayType := 0 ns; + tpw_Din0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE; + + end Din_0_B; + + architecture Structure of Din_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din0_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_0: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din0_ipd, Din0, tipd_Din0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din0_Din0 : x01 := '0'; + VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din0_ipd, + TestSignalName => "Din0", + Period => tperiod_Din0, + PulseWidthHigh => tpw_Din0_posedge, + PulseWidthLow => tpw_Din0_negedge, + PeriodData => periodcheckinfo_Din0, + Violation => tviol_Din0_Din0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din0_ipd'last_event, + PathDelay => tpd_Din0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCCASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nCCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCCASB"; + + tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCCASS : VitalDelayType := 0 ns; + tpw_nCCASS_posedge : VitalDelayType := 0 ns; + tpw_nCCASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCCASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE; + + end nCCASB; + + architecture Structure of nCCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCCASS_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCCAS_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>nCCASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCCASS_nCCASS : x01 := '0'; + VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCCASS_ipd, + TestSignalName => "nCCASS", + Period => tperiod_nCCASS, + PulseWidthHigh => tpw_nCCASS_posedge, + PulseWidthLow => tpw_nCCASS_negedge, + PeriodData => periodcheckinfo_nCCASS, + Violation => tviol_nCCASS_nCCASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event, + PathDelay => tpd_nCCASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCRASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nCRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCRASB"; + + tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCRASS : VitalDelayType := 0 ns; + tpw_nCRASS_posedge : VitalDelayType := 0 ns; + tpw_nCRASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCRASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE; + + end nCRASB; + + architecture Structure of nCRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCRASS_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCRAS_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>nCRASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCRASS_nCRASS : x01 := '0'; + VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCRASS_ipd, + TestSignalName => "nCRASS", + Period => tperiod_nCRASS, + PulseWidthHigh => tpw_nCRASS_posedge, + PulseWidthLow => tpw_nCRASS_negedge, + PeriodData => periodcheckinfo_nCRASS, + Violation => tviol_nCRASS_nCRASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event, + PathDelay => tpd_nCRASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nFWEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nFWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nFWEB"; + + tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns); + tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nFWES : VitalDelayType := 0 ns; + tpw_nFWES_posedge : VitalDelayType := 0 ns; + tpw_nFWES_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nFWES: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE; + + end nFWEB; + + architecture Structure of nFWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nFWES_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nFWE_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>nFWES_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nFWES_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nFWES_nFWES : x01 := '0'; + VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nFWES_ipd, + TestSignalName => "nFWES", + Period => tperiod_nFWES, + PulseWidthHigh => tpw_nFWES_posedge, + PulseWidthLow => tpw_nFWES_negedge, + PeriodData => periodcheckinfo_nFWES, + Violation => tviol_nFWES_nFWES, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nFWES_ipd'last_event, + PathDelay => tpd_nFWES_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCLKB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCLKB"; + + tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns); + tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RCLKS : VitalDelayType := 0 ns; + tpw_RCLKS_posedge : VitalDelayType := 0 ns; + tpw_RCLKS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; RCLKS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE; + + end RCLKB; + + architecture Structure of RCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal RCLKS_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + RCLK_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>RCLKS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RCLKS_RCLKS : x01 := '0'; + VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RCLKS_ipd, + TestSignalName => "RCLKS", + Period => tperiod_RCLKS, + PulseWidthHigh => tpw_RCLKS_posedge, + PulseWidthLow => tpw_RCLKS_negedge, + PeriodData => periodcheckinfo_RCLKS, + Violation => tviol_RCLKS_RCLKS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event, + PathDelay => tpd_RCLKS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDOB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMSDOB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDOB"; + + tipd_UFMSDOS : VitalDelayType01 := (0 ns, 0 ns); + tpd_UFMSDOS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_UFMSDOS : VitalDelayType := 0 ns; + tpw_UFMSDOS_posedge : VitalDelayType := 0 ns; + tpw_UFMSDOS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE; + + end UFMSDOB; + + architecture Structure of UFMSDOB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal UFMSDOS_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + UFMSDO_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_UFMSDOS_UFMSDOS : x01 := '0'; + VARIABLE periodcheckinfo_UFMSDOS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => UFMSDOS_ipd, + TestSignalName => "UFMSDOS", + Period => tperiod_UFMSDOS, + PulseWidthHigh => tpw_UFMSDOS_posedge, + PulseWidthLow => tpw_UFMSDOS_negedge, + PeriodData => periodcheckinfo_UFMSDOS, + Violation => tviol_UFMSDOS_UFMSDOS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => UFMSDOS_ipd'last_event, + PathDelay => tpd_UFMSDOS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RAM2GS + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RAM2GS is + port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); + CROW: in Std_logic_vector (1 downto 0); + Din: in Std_logic_vector (7 downto 0); + Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; + nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; + RBA: out Std_logic_vector (1 downto 0); + RA: out Std_logic_vector (11 downto 0); + RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; + RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; + nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; + RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; + UFMSDI: out Std_logic; UFMSDO: in Std_logic); + + + + end RAM2GS; + + architecture Structure of RAM2GS is + signal FS_14: Std_logic; + signal FS_13: Std_logic; + signal n81: Std_logic; + signal n82: Std_logic; + signal RCLK_c: Std_logic; + signal n1998: Std_logic; + signal n1999: Std_logic; + signal FS_12: Std_logic; + signal FS_11: Std_logic; + signal n83: Std_logic; + signal n84: Std_logic; + signal n1997: Std_logic; + signal FS_8: Std_logic; + signal FS_7: Std_logic; + signal n87: Std_logic; + signal n88: Std_logic; + signal n1995: Std_logic; + signal n1996: Std_logic; + signal FS_6: Std_logic; + signal FS_5: Std_logic; + signal n89: Std_logic; + signal n90: Std_logic; + signal n1994: Std_logic; + signal FS_2: Std_logic; + signal FS_1: Std_logic; + signal n93: Std_logic; + signal n94: Std_logic; + signal n1992: Std_logic; + signal n1993: Std_logic; + signal FS_0: Std_logic; + signal n95: Std_logic; + signal CASr2: Std_logic; + signal CASr3: Std_logic; + signal FS_10: Std_logic; + signal FS_9: Std_logic; + signal n85: Std_logic; + signal n86: Std_logic; + signal FS_17: Std_logic; + signal n78: Std_logic; + signal n2000: Std_logic; + signal FS_4: Std_logic; + signal FS_3: Std_logic; + signal n91: Std_logic; + signal n92: Std_logic; + signal FS_16: Std_logic; + signal FS_15: Std_logic; + signal n79: Std_logic; + signal n80: Std_logic; + signal Din_c_4: Std_logic; + signal Din_c_6: Std_logic; + signal Din_c_1: Std_logic; + signal Din_c_7: Std_logic; + signal n2382: Std_logic; + signal n8: Std_logic; + signal n2225: Std_logic; + signal n2180: Std_logic; + signal ADSubmitted_N_246: Std_logic; + signal PHI2_N_120_enable_2: Std_logic; + signal C1Submitted_N_237: Std_logic; + signal PHI2_c: Std_logic; + signal ADSubmitted: Std_logic; + signal n26: Std_logic; + signal MAin_c_5: Std_logic; + signal n22: Std_logic; + signal MAin_c_2: Std_logic; + signal MAin_c_1: Std_logic; + signal C1Submitted: Std_logic; + signal n2365: Std_logic; + signal nFWE_c: Std_logic; + signal n1398: Std_logic; + signal nCCAS_c: Std_logic; + signal nCCAS_N_3: Std_logic; + signal CASr: Std_logic; + signal n2254: Std_logic; + signal Din_c_5: Std_logic; + signal n2191: Std_logic; + signal n2183: Std_logic; + signal n15_adj_1: Std_logic; + signal n2208: Std_logic; + signal n2363: Std_logic; + signal CmdEnable_N_248: Std_logic; + signal PHI2_N_120_enable_1: Std_logic; + signal CmdEnable: Std_logic; + signal n2447_001_BUF1: Std_logic; + signal PHI2_N_120_enable_7: Std_logic; + signal CmdSubmitted: Std_logic; + signal n1314: Std_logic; + signal n8MEGEN: Std_logic; + signal Din_c_0: Std_logic; + signal Cmdn8MEGEN_N_264: Std_logic; + signal PHI2_N_120_enable_6: Std_logic; + signal Cmdn8MEGEN: Std_logic; + signal Din_c_3: Std_logic; + signal n2373: Std_logic; + signal nCRAS_c: Std_logic; + signal FWEr: Std_logic; + signal CBR: Std_logic; + signal n2447_000_BUF1: Std_logic; + signal RCLK_c_enable_28: Std_logic; + signal InitReady: Std_logic; + signal n2447: Std_logic; + signal RCLK_c_enable_16: Std_logic; + signal LEDEN: Std_logic; + signal nCRAS_c_inv: Std_logic; + signal RASr: Std_logic; + signal LED_c: Std_logic; + signal RASr2: Std_logic; + signal nRowColSel_N_35: Std_logic; + signal nRCAS_N_165: Std_logic; + signal Ready: Std_logic; + signal n2381: Std_logic; + signal nRCS_N_139: Std_logic; + signal n2036: Std_logic; + signal nRWE_N_177: Std_logic; + signal RA_0S: Std_logic; + signal XOR8MEG: Std_logic; + signal RA11_N_184: Std_logic; + signal RA_c: Std_logic; + signal n6_adj_2: Std_logic; + signal PHI2r2: Std_logic; + signal PHI2r3: Std_logic; + signal n15_adj_4: Std_logic; + signal RCKEEN_N_121: Std_logic; + signal RCLK_c_enable_6: Std_logic; + signal RCKEEN: Std_logic; + signal RCLK_c_enable_10: Std_logic; + signal RASr3: Std_logic; + signal RCKE_N_132: Std_logic; + signal PHI2r: Std_logic; + signal RCKE_c: Std_logic; + signal n2447_002_BUF1: Std_logic; + signal Ready_N_292: Std_logic; + signal n2267: Std_logic; + signal n13_adj_6: Std_logic; + signal CmdUFMCLK: Std_logic; + signal n1893: Std_logic; + signal UFMCLK_N_224: Std_logic; + signal n2366: Std_logic; + signal UFMCLK_c: Std_logic; + signal n10: Std_logic; + signal n7: Std_logic; + signal n4: Std_logic; + signal CmdUFMSDI: Std_logic; + signal n2174: Std_logic; + signal UFMSDI_N_231: Std_logic; + signal UFMSDI_c: Std_logic; + signal n2260: Std_logic; + signal Din_c_2: Std_logic; + signal XOR8MEG_N_110: Std_logic; + signal PHI2_N_120_enable_3: Std_logic; + signal n2375: Std_logic; + signal UFMSDO_c: Std_logic; + signal n2367: Std_logic; + signal n8MEGEN_N_91: Std_logic; + signal RCLK_c_enable_15: Std_logic; + signal nRCS_N_142: Std_logic; + signal nRCAS_N_166: Std_logic; + signal n2371: Std_logic; + signal nRCAS_N_161: Std_logic; + signal nRCAS_c: Std_logic; + signal nRCS_N_141: Std_logic; + signal nRCS_N_137: Std_logic; + signal nRCS_N_136: Std_logic; + signal nRCS_c: Std_logic; + signal n2379: Std_logic; + signal nRRAS_N_156: Std_logic; + signal nRRAS_c: Std_logic; + signal nRWE_N_178: Std_logic; + signal n1765: Std_logic; + signal nRWE_N_171: Std_logic; + signal RCLK_c_enable_5: Std_logic; + signal nRWE_c: Std_logic; + signal nRowColSel_N_34: Std_logic; + signal nRowColSel_N_33: Std_logic; + signal n2376: Std_logic; + signal n1060: Std_logic; + signal n2372: Std_logic; + signal n917: Std_logic; + signal nRowColSel: Std_logic; + signal nRowColSel_N_32: Std_logic; + signal n827: Std_logic; + signal n2227: Std_logic; + signal n1406: Std_logic; + signal Bank_3: Std_logic; + signal Bank_6: Std_logic; + signal n2287: Std_logic; + signal n13: Std_logic; + signal n2374: Std_logic; + signal n2368: Std_logic; + signal CmdUFMCS: Std_logic; + signal n64: Std_logic; + signal nUFMCS_N_199: Std_logic; + signal nUFMCS_c: Std_logic; + signal n6_adj_3: Std_logic; + signal Ready_N_296: Std_logic; + signal n2204: Std_logic; + signal n2369: Std_logic; + signal MAin_c_0: Std_logic; + signal PHI2_N_120_enable_8: Std_logic; + signal Bank_5: Std_logic; + signal n2277: Std_logic; + signal Bank_2: Std_logic; + signal n2220: Std_logic; + signal RowA_0: Std_logic; + signal RowA_1: Std_logic; + signal n2370: Std_logic; + signal n2228: Std_logic; + signal n732: Std_logic; + signal n733: Std_logic; + signal RCLK_c_enable_27: Std_logic; + signal n2055: Std_logic; + signal MAin_c_9: Std_logic; + signal MAin_c_8: Std_logic; + signal RowA_8: Std_logic; + signal RowA_9: Std_logic; + signal n2210: Std_logic; + signal nRWE_N_182: Std_logic; + signal nRCS_N_146: Std_logic; + signal n728: Std_logic; + signal n729: Std_logic; + signal n727: Std_logic; + signal n730: Std_logic; + signal n2378: Std_logic; + signal n726: Std_logic; + signal n12: Std_logic; + signal MAin_c_4: Std_logic; + signal RowA_4: Std_logic; + signal RowA_5: Std_logic; + signal n1277: Std_logic; + signal n4_adj_7: Std_logic; + signal n2377: Std_logic; + signal n738: Std_logic; + signal n737: Std_logic; + signal n14: Std_logic; + signal n15: Std_logic; + signal n6: Std_logic; + signal CROW_c_1: Std_logic; + signal CROW_c_0: Std_logic; + signal RBA_c_0: Std_logic; + signal RBA_c_1: Std_logic; + signal n7_adj_5: Std_logic; + signal n2362: Std_logic; + signal WRD_6: Std_logic; + signal WRD_7: Std_logic; + signal WRD_4: Std_logic; + signal WRD_5: Std_logic; + signal WRD_0: Std_logic; + signal WRD_1: Std_logic; + signal MAin_c_3: Std_logic; + signal RowA_2: Std_logic; + signal RowA_3: Std_logic; + signal WRD_2: Std_logic; + signal WRD_3: Std_logic; + signal RA_1_9: Std_logic; + signal Bank_0: Std_logic; + signal RDQML_c: Std_logic; + signal Bank_1: Std_logic; + signal n734: Std_logic; + signal n735: Std_logic; + signal RA_1_8: Std_logic; + signal RDQMH_c: Std_logic; + signal Bank_4: Std_logic; + signal MAin_c_7: Std_logic; + signal RowA_7: Std_logic; + signal RA_1_7: Std_logic; + signal Bank_7: Std_logic; + signal MAin_c_6: Std_logic; + signal RowA_6: Std_logic; + signal RA_1_6: Std_logic; + signal RA_1_5: Std_logic; + signal RA_1_0: Std_logic; + signal RA_1_4: Std_logic; + signal RA_1_1: Std_logic; + signal RA_1_3: Std_logic; + signal RA_1_2: Std_logic; + signal n984: Std_logic; + signal n736: Std_logic; + signal Dout_c: Std_logic; + signal Dout_0S: Std_logic; + signal Dout_1S: Std_logic; + signal Dout_2S: Std_logic; + signal Dout_3S: Std_logic; + signal Dout_4S: Std_logic; + signal Dout_5S: Std_logic; + signal Dout_6S: Std_logic; + signal VCCI: Std_logic; + component SLICE_0 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_1 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_2 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_3 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_4 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_5 + port (A1: in Std_logic; DI1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_6 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_7 + port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_8 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_9 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_10 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_15 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_16 + port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_19 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_20 + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_24 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_25 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_26 + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_27 + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_30 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_32 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_33 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_35 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_36 + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_37 + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_44 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_45 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_50 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_57 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_59 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_61 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_62 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_64 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_65 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_66 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_67 + port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic); + end component; + component SLICE_68 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_69 + port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_70 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component i30_SLICE_71 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + end component; + component SLICE_72 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_73 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_74 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_75 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_76 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_77 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_78 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_79 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_80 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_81 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_82 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_83 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_84 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_85 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_86 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_87 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_88 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_89 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_90 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_91 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_92 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_93 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_94 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_95 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_96 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_97 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_98 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_99 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_100 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_101 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_102 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_103 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_104 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_105 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_106 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component RD_7_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD7: inout Std_logic); + end component; + component RD_6_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD6: inout Std_logic); + end component; + component RD_5_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD5: inout Std_logic); + end component; + component RD_4_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD4: inout Std_logic); + end component; + component RD_3_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD3: inout Std_logic); + end component; + component RD_2_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD2: inout Std_logic); + end component; + component RD_1_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD1: inout Std_logic); + end component; + component RD_0_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD0: inout Std_logic); + end component; + component Dout_7_B + port (PADDO: in Std_logic; Dout7: out Std_logic); + end component; + component Dout_6_B + port (PADDO: in Std_logic; Dout6: out Std_logic); + end component; + component Dout_5_B + port (PADDO: in Std_logic; Dout5: out Std_logic); + end component; + component Dout_4_B + port (PADDO: in Std_logic; Dout4: out Std_logic); + end component; + component Dout_3_B + port (PADDO: in Std_logic; Dout3: out Std_logic); + end component; + component Dout_2_B + port (PADDO: in Std_logic; Dout2: out Std_logic); + end component; + component Dout_1_B + port (PADDO: in Std_logic; Dout1: out Std_logic); + end component; + component Dout_0_B + port (PADDO: in Std_logic; Dout0: out Std_logic); + end component; + component LEDB + port (PADDO: in Std_logic; LEDS: out Std_logic); + end component; + component RBA_1_B + port (PADDO: in Std_logic; RBA1: out Std_logic); + end component; + component RBA_0_B + port (PADDO: in Std_logic; RBA0: out Std_logic); + end component; + component RA_11_B + port (PADDO: in Std_logic; RA11: out Std_logic); + end component; + component RA_10_B + port (PADDO: in Std_logic; RA10: out Std_logic); + end component; + component RA_9_B + port (PADDO: in Std_logic; RA9: out Std_logic); + end component; + component RA_8_B + port (PADDO: in Std_logic; RA8: out Std_logic); + end component; + component RA_7_B + port (PADDO: in Std_logic; RA7: out Std_logic); + end component; + component RA_6_B + port (PADDO: in Std_logic; RA6: out Std_logic); + end component; + component RA_5_B + port (PADDO: in Std_logic; RA5: out Std_logic); + end component; + component RA_4_B + port (PADDO: in Std_logic; RA4: out Std_logic); + end component; + component RA_3_B + port (PADDO: in Std_logic; RA3: out Std_logic); + end component; + component RA_2_B + port (PADDO: in Std_logic; RA2: out Std_logic); + end component; + component RA_1_B + port (PADDO: in Std_logic; RA1: out Std_logic); + end component; + component RA_0_B + port (PADDO: in Std_logic; RA0: out Std_logic); + end component; + component nRCSB + port (PADDO: in Std_logic; nRCSS: out Std_logic); + end component; + component RCKEB + port (PADDO: in Std_logic; RCKES: out Std_logic); + end component; + component nRWEB + port (PADDO: in Std_logic; nRWES: out Std_logic); + end component; + component nRRASB + port (PADDO: in Std_logic; nRRASS: out Std_logic); + end component; + component nRCASB + port (PADDO: in Std_logic; nRCASS: out Std_logic); + end component; + component RDQMHB + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + end component; + component RDQMLB + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + end component; + component nUFMCSB + port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + end component; + component UFMCLKB + port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + end component; + component UFMSDIB + port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + end component; + component PHI2B + port (PADDI: out Std_logic; PHI2S: in Std_logic); + end component; + component MAin_9_B + port (PADDI: out Std_logic; MAin9: in Std_logic); + end component; + component MAin_8_B + port (PADDI: out Std_logic; MAin8: in Std_logic); + end component; + component MAin_7_B + port (PADDI: out Std_logic; MAin7: in Std_logic); + end component; + component MAin_6_B + port (PADDI: out Std_logic; MAin6: in Std_logic); + end component; + component MAin_5_B + port (PADDI: out Std_logic; MAin5: in Std_logic); + end component; + component MAin_4_B + port (PADDI: out Std_logic; MAin4: in Std_logic); + end component; + component MAin_3_B + port (PADDI: out Std_logic; MAin3: in Std_logic); + end component; + component MAin_2_B + port (PADDI: out Std_logic; MAin2: in Std_logic); + end component; + component MAin_1_B + port (PADDI: out Std_logic; MAin1: in Std_logic); + end component; + component MAin_0_B + port (PADDI: out Std_logic; MAin0: in Std_logic); + end component; + component CROW_1_B + port (PADDI: out Std_logic; CROW1: in Std_logic); + end component; + component CROW_0_B + port (PADDI: out Std_logic; CROW0: in Std_logic); + end component; + component Din_7_B + port (PADDI: out Std_logic; Din7: in Std_logic); + end component; + component Din_6_B + port (PADDI: out Std_logic; Din6: in Std_logic); + end component; + component Din_5_B + port (PADDI: out Std_logic; Din5: in Std_logic); + end component; + component Din_4_B + port (PADDI: out Std_logic; Din4: in Std_logic); + end component; + component Din_3_B + port (PADDI: out Std_logic; Din3: in Std_logic); + end component; + component Din_2_B + port (PADDI: out Std_logic; Din2: in Std_logic); + end component; + component Din_1_B + port (PADDI: out Std_logic; Din1: in Std_logic); + end component; + component Din_0_B + port (PADDI: out Std_logic; Din0: in Std_logic); + end component; + component nCCASB + port (PADDI: out Std_logic; nCCASS: in Std_logic); + end component; + component nCRASB + port (PADDI: out Std_logic; nCRASS: in Std_logic); + end component; + component nFWEB + port (PADDI: out Std_logic; nFWES: in Std_logic); + end component; + component RCLKB + port (PADDI: out Std_logic; RCLKS: in Std_logic); + end component; + component UFMSDOB + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + end component; + begin + SLICE_0I: SLICE_0 + port map (A1=>FS_14, A0=>FS_13, DI1=>n81, DI0=>n82, CLK=>RCLK_c, + FCI=>n1998, F0=>n82, Q0=>FS_13, F1=>n81, Q1=>FS_14, FCO=>n1999); + SLICE_1I: SLICE_1 + port map (A1=>FS_12, A0=>FS_11, DI1=>n83, DI0=>n84, CLK=>RCLK_c, + FCI=>n1997, F0=>n84, Q0=>FS_11, F1=>n83, Q1=>FS_12, FCO=>n1998); + SLICE_2I: SLICE_2 + port map (A1=>FS_8, A0=>FS_7, DI1=>n87, DI0=>n88, CLK=>RCLK_c, + FCI=>n1995, F0=>n88, Q0=>FS_7, F1=>n87, Q1=>FS_8, FCO=>n1996); + SLICE_3I: SLICE_3 + port map (A1=>FS_6, A0=>FS_5, DI1=>n89, DI0=>n90, CLK=>RCLK_c, + FCI=>n1994, F0=>n90, Q0=>FS_5, F1=>n89, Q1=>FS_6, FCO=>n1995); + SLICE_4I: SLICE_4 + port map (A1=>FS_2, A0=>FS_1, DI1=>n93, DI0=>n94, CLK=>RCLK_c, + FCI=>n1992, F0=>n94, Q0=>FS_1, F1=>n93, Q1=>FS_2, FCO=>n1993); + SLICE_5I: SLICE_5 + port map (A1=>FS_0, DI1=>n95, M0=>CASr2, CLK=>RCLK_c, Q0=>CASr3, F1=>n95, + Q1=>FS_0, FCO=>n1992); + SLICE_6I: SLICE_6 + port map (A1=>FS_10, A0=>FS_9, DI1=>n85, DI0=>n86, CLK=>RCLK_c, + FCI=>n1996, F0=>n86, Q0=>FS_9, F1=>n85, Q1=>FS_10, FCO=>n1997); + SLICE_7I: SLICE_7 + port map (A0=>FS_17, DI0=>n78, CLK=>RCLK_c, FCI=>n2000, F0=>n78, + Q0=>FS_17); + SLICE_8I: SLICE_8 + port map (A1=>FS_4, A0=>FS_3, DI1=>n91, DI0=>n92, CLK=>RCLK_c, + FCI=>n1993, F0=>n92, Q0=>FS_3, F1=>n91, Q1=>FS_4, FCO=>n1994); + SLICE_9I: SLICE_9 + port map (A1=>FS_16, A0=>FS_15, DI1=>n79, DI0=>n80, CLK=>RCLK_c, + FCI=>n1999, F0=>n80, Q0=>FS_15, F1=>n79, Q1=>FS_16, FCO=>n2000); + SLICE_10I: SLICE_10 + port map (D1=>Din_c_4, C1=>Din_c_6, B1=>Din_c_1, A1=>Din_c_7, D0=>n2382, + C0=>n8, B0=>n2225, A0=>n2180, DI0=>ADSubmitted_N_246, + CE=>PHI2_N_120_enable_2, LSR=>C1Submitted_N_237, CLK=>PHI2_c, + F0=>ADSubmitted_N_246, Q0=>ADSubmitted, F1=>n8); + SLICE_15I: SLICE_15 + port map (D1=>n26, C1=>MAin_c_5, B1=>n22, A1=>MAin_c_2, D0=>MAin_c_1, + C0=>C1Submitted, B0=>n2365, A0=>nFWE_c, DI0=>n1398, + LSR=>C1Submitted_N_237, CLK=>PHI2_c, F0=>n1398, + Q0=>C1Submitted, F1=>n2365); + SLICE_16I: SLICE_16 + port map (A0=>nCCAS_c, DI0=>nCCAS_N_3, M1=>CASr, CLK=>RCLK_c, + F0=>nCCAS_N_3, Q0=>CASr, Q1=>CASr2); + SLICE_19I: SLICE_19 + port map (D1=>n2254, C1=>Din_c_5, B1=>n2191, A1=>n2183, D0=>n15_adj_1, + C0=>n2208, B0=>MAin_c_1, A0=>n2363, DI0=>CmdEnable_N_248, + CE=>PHI2_N_120_enable_1, CLK=>PHI2_c, F0=>CmdEnable_N_248, + Q0=>CmdEnable, F1=>n15_adj_1); + SLICE_20I: SLICE_20 + port map (DI0=>n2447_001_BUF1, CE=>PHI2_N_120_enable_7, CLK=>PHI2_c, + F0=>n2447_001_BUF1, Q0=>CmdSubmitted); + SLICE_24I: SLICE_24 + port map (C1=>Din_c_5, B1=>Din_c_7, A1=>Din_c_6, D0=>n1314, C0=>Din_c_4, + B0=>n8MEGEN, A0=>Din_c_0, DI0=>Cmdn8MEGEN_N_264, + CE=>PHI2_N_120_enable_6, CLK=>PHI2_c, F0=>Cmdn8MEGEN_N_264, + Q0=>Cmdn8MEGEN, F1=>n1314); + SLICE_25I: SLICE_25 + port map (C1=>Din_c_3, B1=>Din_c_5, A1=>nFWE_c, A0=>nFWE_c, DI0=>n2373, + M1=>nCCAS_N_3, CLK=>nCRAS_c, F0=>n2373, Q0=>FWEr, F1=>n2180, + Q1=>CBR); + SLICE_26I: SLICE_26 + port map (DI0=>n2447_000_BUF1, CE=>RCLK_c_enable_28, CLK=>RCLK_c, + F0=>n2447_000_BUF1, Q0=>InitReady); + SLICE_27I: SLICE_27 + port map (DI0=>n2447, CE=>RCLK_c_enable_16, CLK=>RCLK_c, F0=>n2447, + Q0=>LEDEN); + SLICE_30I: SLICE_30 + port map (C1=>CBR, B1=>LEDEN, A1=>nCRAS_c, A0=>nCRAS_c, DI0=>nCRAS_c_inv, + M1=>RASr, CLK=>RCLK_c, F0=>nCRAS_c_inv, Q0=>RASr, F1=>LED_c, + Q1=>RASr2); + SLICE_32I: SLICE_32 + port map (C1=>nRowColSel_N_35, B1=>InitReady, A1=>RASr2, D0=>nRCAS_N_165, + C0=>Ready, B0=>n2381, A0=>nRCS_N_139, DI0=>n2036, + LSR=>nRWE_N_177, CLK=>RCLK_c, F0=>n2036, Q0=>RA_0S, F1=>n2381); + SLICE_33I: SLICE_33 + port map (C1=>Din_c_4, B1=>Din_c_7, A1=>Din_c_6, C0=>n8MEGEN, + B0=>XOR8MEG, A0=>Din_c_6, DI0=>RA11_N_184, LSR=>Ready, + CLK=>PHI2_c, F0=>RA11_N_184, Q0=>RA_c, F1=>n6_adj_2); + SLICE_35I: SLICE_35 + port map (D1=>InitReady, C1=>CmdSubmitted, B1=>PHI2r2, A1=>PHI2r3, + C0=>Ready, B0=>n15_adj_4, A0=>InitReady, DI0=>RCKEEN_N_121, + CE=>RCLK_c_enable_6, CLK=>RCLK_c, F0=>RCKEEN_N_121, Q0=>RCKEEN, + F1=>RCLK_c_enable_10); + SLICE_36I: SLICE_36 + port map (D0=>RASr3, C0=>RASr2, B0=>RCKEEN, A0=>RASr, DI0=>RCKE_N_132, + M1=>PHI2r, CLK=>RCLK_c, F0=>RCKE_N_132, Q0=>RCKE_c, Q1=>PHI2r2); + SLICE_37I: SLICE_37 + port map (DI0=>n2447_002_BUF1, CE=>Ready_N_292, CLK=>RCLK_c, + F0=>n2447_002_BUF1, Q0=>Ready); + SLICE_44I: SLICE_44 + port map (D1=>FS_1, C1=>n2267, B1=>n13_adj_6, A1=>FS_4, C0=>InitReady, + B0=>CmdUFMCLK, A0=>n1893, DI0=>UFMCLK_N_224, + CE=>RCLK_c_enable_10, LSR=>n2366, CLK=>RCLK_c, + F0=>UFMCLK_N_224, Q0=>UFMCLK_c, F1=>n1893); + SLICE_45I: SLICE_45 + port map (D1=>n10, C1=>FS_10, B1=>FS_8, A1=>n7, D0=>n4, C0=>InitReady, + B0=>CmdUFMSDI, A0=>n2174, DI0=>UFMSDI_N_231, + CE=>RCLK_c_enable_10, LSR=>n2366, CLK=>RCLK_c, + F0=>UFMSDI_N_231, Q0=>UFMSDI_c, F1=>n2174); + SLICE_50I: SLICE_50 + port map (D1=>LEDEN, C1=>n1314, B1=>Din_c_1, A1=>Din_c_4, D0=>Din_c_3, + C0=>n2260, B0=>Din_c_2, A0=>Din_c_0, DI0=>XOR8MEG_N_110, + CE=>PHI2_N_120_enable_3, CLK=>PHI2_c, F0=>XOR8MEG_N_110, + Q0=>XOR8MEG, F1=>n2260); + SLICE_57I: SLICE_57 + port map (D1=>FS_10, C1=>FS_11, B1=>n2375, A1=>n10, D0=>Cmdn8MEGEN, + C0=>UFMSDO_c, B0=>n2367, A0=>InitReady, DI0=>n8MEGEN_N_91, + CE=>RCLK_c_enable_15, CLK=>RCLK_c, F0=>n8MEGEN_N_91, + Q0=>n8MEGEN, F1=>n2367); + SLICE_59I: SLICE_59 + port map (D1=>CBR, C1=>nRowColSel_N_35, B1=>RASr2, A1=>nRCS_N_142, + D0=>nRCAS_N_166, C0=>Ready, B0=>nRCAS_N_165, A0=>n2371, + DI0=>nRCAS_N_161, CE=>RCLK_c_enable_6, CLK=>RCLK_c, + F0=>nRCAS_N_161, Q0=>nRCAS_c, F1=>nRCAS_N_166); + SLICE_61I: SLICE_61 + port map (D1=>nRCS_N_142, C1=>nRowColSel_N_35, B1=>RASr2, A1=>RCKE_c, + C0=>Ready, B0=>nRCS_N_141, A0=>nRCS_N_137, DI0=>nRCS_N_136, + CE=>RCLK_c_enable_6, CLK=>RCLK_c, F0=>nRCS_N_136, Q0=>nRCS_c, + F1=>nRCS_N_141); + SLICE_62I: SLICE_62 + port map (D1=>RASr2, C1=>nRowColSel_N_35, B1=>InitReady, A1=>nRCS_N_139, + D0=>nRowColSel_N_35, C0=>Ready, B0=>n2379, A0=>nRCS_N_137, + DI0=>nRRAS_N_156, CE=>RCLK_c_enable_6, CLK=>RCLK_c, + F0=>nRRAS_N_156, Q0=>nRRAS_c, F1=>nRCS_N_137); + SLICE_64I: SLICE_64 + port map (B1=>nRCAS_N_165, A1=>nRWE_N_177, D0=>n2371, C0=>Ready, + B0=>nRWE_N_178, A0=>n1765, DI0=>nRWE_N_171, + CE=>RCLK_c_enable_5, CLK=>RCLK_c, F0=>nRWE_N_171, Q0=>nRWE_c, + F1=>n1765); + SLICE_65I: SLICE_65 + port map (B1=>nRowColSel_N_34, A1=>nRowColSel_N_33, D0=>n2376, C0=>n1060, + B0=>n2372, A0=>FWEr, DI0=>n917, CE=>RCLK_c_enable_5, + CLK=>RCLK_c, F0=>n917, Q0=>nRowColSel, F1=>n1060); + SLICE_66I: SLICE_66 + port map (B1=>CASr2, A1=>nRowColSel_N_33, B0=>nRowColSel_N_32, + A0=>nRowColSel_N_33, DI0=>n827, LSR=>RASr2, CLK=>RCLK_c, + F0=>n827, Q0=>nRowColSel_N_32, F1=>n2227); + SLICE_67I: SLICE_67 + port map (B0=>nRowColSel_N_32, A0=>RASr2, DI0=>n1406, + LSR=>nRowColSel_N_34, CLK=>RCLK_c, F0=>n1406, + Q0=>nRowColSel_N_33); + SLICE_68I: SLICE_68 + port map (B1=>FS_0, A1=>FS_8, B0=>Bank_3, A0=>Bank_6, M0=>n1406, + LSR=>nRowColSel_N_35, CLK=>RCLK_c, F0=>n2287, + Q0=>nRowColSel_N_34, F1=>n13); + SLICE_69I: SLICE_69 + port map (B1=>RASr2, A1=>RCKE_c, A0=>RASr2, DI0=>n2374, M1=>PHI2r2, + CLK=>RCLK_c, F0=>n2374, Q0=>nRowColSel_N_35, F1=>n2379, + Q1=>PHI2r3); + SLICE_70I: SLICE_70 + port map (D1=>FS_10, C1=>InitReady, B1=>n2368, A1=>FS_11, D0=>InitReady, + C0=>CmdUFMCS, B0=>n64, A0=>n13_adj_6, DI0=>nUFMCS_N_199, + CE=>RCLK_c_enable_10, CLK=>RCLK_c, F0=>nUFMCS_N_199, + Q0=>nUFMCS_c, F1=>n64); + i30_SLICE_71I: i30_SLICE_71 + port map (C1=>RASr2, B1=>FWEr, A1=>CBR, D0=>nRowColSel_N_34, C0=>FWEr, + B0=>n2227, A0=>CBR, M0=>nRowColSel_N_35, OFX0=>n15_adj_4); + SLICE_72I: SLICE_72 + port map (D1=>Ready, C1=>nRowColSel_N_32, B1=>n6_adj_3, A1=>RASr2, + B0=>Ready_N_296, A0=>InitReady, F0=>n6_adj_3, F1=>Ready_N_292); + SLICE_73I: SLICE_73 + port map (D1=>n2204, C1=>n2180, B1=>n26, A1=>n2369, D0=>n6_adj_2, + C0=>CmdEnable, B0=>MAin_c_0, A0=>MAin_c_1, F0=>n2204, + F1=>PHI2_N_120_enable_8); + SLICE_74I: SLICE_74 + port map (D1=>Bank_5, C1=>n2287, B1=>n2277, A1=>Bank_2, D0=>nFWE_c, + C0=>n2204, B0=>n26, A0=>n2369, M1=>MAin_c_1, M0=>MAin_c_0, + LSR=>Ready, CLK=>nCRAS_c, F0=>n2220, Q0=>RowA_0, F1=>n26, + Q1=>RowA_1); + SLICE_75I: SLICE_75 + port map (D1=>n2370, C1=>n2183, B1=>n2228, A1=>Din_c_5, B0=>Din_c_3, + A0=>Din_c_6, M1=>n732, M0=>n733, CE=>RCLK_c_enable_27, + CLK=>RCLK_c, F0=>n2183, Q0=>n732, F1=>n2055, Q1=>nRWE_N_177); + SLICE_76I: SLICE_76 + port map (C1=>n10, B1=>FS_14, A1=>FS_12, D0=>InitReady, C0=>n2368, + B0=>FS_11, A0=>FS_10, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready, + CLK=>nCRAS_c, F0=>RCLK_c_enable_16, Q0=>RowA_8, F1=>n2368, + Q1=>RowA_9); + SLICE_77I: SLICE_77 + port map (D1=>n2208, C1=>C1Submitted, B1=>n2191, A1=>Din_c_5, + D0=>MAin_c_0, C0=>Din_c_6, B0=>Din_c_3, A0=>Din_c_2, F0=>n2191, + F1=>n2210); + SLICE_78I: SLICE_78 + port map (D1=>nRowColSel_N_35, C1=>nRWE_N_182, B1=>n1060, A1=>nRCS_N_146, + B0=>RASr2, A0=>RCKE_c, M1=>n728, M0=>n729, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>nRWE_N_182, Q0=>n728, + F1=>nRWE_N_178, Q1=>n727); + SLICE_79I: SLICE_79 + port map (C1=>MAin_c_5, B1=>n22, A1=>MAin_c_2, D0=>MAin_c_1, C0=>nFWE_c, + B0=>n26, A0=>n2369, M1=>n730, M0=>nRWE_N_177, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>PHI2_N_120_enable_2, + Q0=>n730, F1=>n2369, Q1=>n729); + SLICE_80I: SLICE_80 + port map (B1=>FS_14, A1=>FS_12, D0=>FS_11, C0=>InitReady, B0=>n2375, + A0=>n10, F0=>n2366, F1=>n2375); + SLICE_81I: SLICE_81 + port map (B1=>CBR, A1=>FWEr, D0=>nRowColSel_N_33, C0=>n2378, + B0=>nRowColSel_N_34, A0=>nRCS_N_146, M1=>n726, M0=>n727, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>nRCS_N_142, Q0=>n726, + F1=>n2378, Q1=>Ready_N_296); + SLICE_82I: SLICE_82 + port map (D1=>FS_17, C1=>FS_14, B1=>n12, A1=>FS_11, B0=>n13_adj_6, + A0=>FS_10, M1=>MAin_c_5, M0=>MAin_c_4, LSR=>Ready, + CLK=>nCRAS_c, F0=>RCLK_c_enable_28, Q0=>RowA_4, F1=>n13_adj_6, + Q1=>RowA_5); + SLICE_83I: SLICE_83 + port map (D1=>n1314, C1=>n1277, B1=>CmdEnable, A1=>n2228, D0=>MAin_c_1, + C0=>MAin_c_0, B0=>n26, A0=>n2369, F0=>n1277, + F1=>PHI2_N_120_enable_3); + SLICE_84I: SLICE_84 + port map (C1=>CmdSubmitted, B1=>PHI2r2, A1=>PHI2r3, D0=>n4_adj_7, + C0=>InitReady, B0=>n2377, A0=>n2367, M1=>n738, M0=>nRCAS_N_165, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>RCLK_c_enable_15, + Q0=>n738, F1=>n2377, Q1=>n737); + SLICE_85I: SLICE_85 + port map (D1=>n10, C1=>FS_11, B1=>FS_14, A1=>FS_12, D0=>FS_16, C0=>FS_15, + B0=>FS_13, A0=>FS_17, F0=>n10, F1=>n2267); + SLICE_86I: SLICE_86 + port map (C1=>FS_6, B1=>FS_9, A1=>FS_3, D0=>n14, C0=>n13, B0=>n15, + A0=>FS_4, M1=>RASr2, M0=>PHI2_c, CLK=>RCLK_c, F0=>n4_adj_7, + Q0=>PHI2r, F1=>n14, Q1=>RASr3); + SLICE_87I: SLICE_87 + port map (D1=>n6, C1=>nRowColSel_N_32, B1=>nRowColSel_N_33, + A1=>nRowColSel_N_35, B0=>nRowColSel_N_34, A0=>Ready, + M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready, CLK=>nCRAS_c, F0=>n6, + Q0=>RBA_c_0, F1=>RCLK_c_enable_6, Q1=>RBA_c_1); + SLICE_88I: SLICE_88 + port map (D1=>n2363, C1=>C1Submitted_N_237, B1=>ADSubmitted, + A1=>n7_adj_5, D0=>n2362, C0=>MAin_c_0, B0=>n2055, A0=>Din_c_2, + M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, F0=>C1Submitted_N_237, + Q0=>WRD_6, F1=>PHI2_N_120_enable_1, Q1=>WRD_7); + SLICE_89I: SLICE_89 + port map (D1=>Din_c_5, C1=>Din_c_3, B1=>Din_c_4, A1=>n2220, D0=>Din_c_3, + C0=>Din_c_4, B0=>n2220, A0=>Din_c_5, M1=>Din_c_5, M0=>Din_c_4, + CLK=>nCCAS_c, F0=>PHI2_N_120_enable_6, Q0=>WRD_4, + F1=>PHI2_N_120_enable_7, Q1=>WRD_5); + SLICE_90I: SLICE_90 + port map (D1=>Din_c_0, C1=>Din_c_4, B1=>Din_c_1, A1=>Din_c_7, + C0=>Din_c_0, B0=>Din_c_1, A0=>Din_c_7, M1=>Din_c_1, + M0=>Din_c_0, CLK=>nCCAS_c, F0=>n2370, Q0=>WRD_0, F1=>n2208, + Q1=>WRD_1); + SLICE_91I: SLICE_91 + port map (C1=>MAin_c_1, B1=>n26, A1=>n2369, D0=>MAin_c_1, C0=>MAin_c_0, + B0=>n26, A0=>n2369, M1=>MAin_c_3, M0=>MAin_c_2, LSR=>Ready, + CLK=>nCRAS_c, F0=>n2225, Q0=>RowA_2, F1=>n2362, Q1=>RowA_3); + SLICE_92I: SLICE_92 + port map (D1=>Ready, C1=>nRowColSel_N_35, B1=>InitReady, A1=>RASr2, + D0=>nRCS_N_139, C0=>nRowColSel_N_35, B0=>InitReady, A0=>RASr2, + M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, F0=>n2371, Q0=>WRD_2, + F1=>RCLK_c_enable_27, Q1=>WRD_3); + SLICE_93I: SLICE_93 + port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>MAin_c_9, + A0=>RowA_9, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, F0=>RA_1_9, + Q0=>Bank_0, F1=>RDQML_c, Q1=>Bank_1); + SLICE_94I: SLICE_94 + port map (B1=>nRowColSel_N_35, A1=>Ready, D0=>nRowColSel_N_35, + C0=>nRowColSel_N_32, B0=>n1060, A0=>Ready, F0=>RCLK_c_enable_5, + F1=>n2372); + SLICE_95I: SLICE_95 + port map (D1=>FS_5, C1=>FS_9, B1=>FS_7, A1=>n2375, D0=>FS_2, C0=>FS_1, + B0=>FS_7, A0=>FS_5, F0=>n15, F1=>n7); + SLICE_96I: SLICE_96 + port map (B1=>CASr3, A1=>CBR, D0=>CASr2, C0=>FWEr, B0=>CASr3, A0=>CBR, + F0=>nRCS_N_146, F1=>n2376); + SLICE_97I: SLICE_97 + port map (C1=>MAin_c_1, B1=>n2210, A1=>MAin_c_0, B0=>Din_c_2, + A0=>MAin_c_0, M1=>n734, M0=>n735, CE=>RCLK_c_enable_27, + CLK=>RCLK_c, F0=>n2254, Q0=>n734, F1=>n7_adj_5, Q1=>n733); + SLICE_98I: SLICE_98 + port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>MAin_c_8, + A0=>RowA_8, M1=>nRCS_N_139, M0=>Ready_N_296, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>RA_1_8, Q0=>nRCS_N_139, + F1=>RDQMH_c, Q1=>nRCAS_N_165); + SLICE_99I: SLICE_99 + port map (D1=>Bank_1, C1=>Bank_4, B1=>MAin_c_3, A1=>MAin_c_7, + C0=>nRowColSel, B0=>MAin_c_7, A0=>RowA_7, M0=>Din_c_0, + CE=>PHI2_N_120_enable_8, CLK=>PHI2_c, F0=>RA_1_7, + Q0=>CmdUFMSDI, F1=>n22); + SLICE_100I: SLICE_100 + port map (D1=>Bank_0, C1=>Bank_7, B1=>MAin_c_4, A1=>MAin_c_6, + C0=>nRowColSel, B0=>MAin_c_6, A0=>RowA_6, M1=>Din_c_2, + M0=>Din_c_1, CE=>PHI2_N_120_enable_8, CLK=>PHI2_c, F0=>RA_1_6, + Q0=>CmdUFMCLK, F1=>n2277, Q1=>CmdUFMCS); + SLICE_101I: SLICE_101 + port map (C1=>nRowColSel, B1=>MAin_c_0, A1=>RowA_0, C0=>nRowColSel, + B0=>MAin_c_5, A0=>RowA_5, M1=>Din_c_7, M0=>Din_c_6, + CLK=>PHI2_c, F0=>RA_1_5, Q0=>Bank_6, F1=>RA_1_0, Q1=>Bank_7); + SLICE_102I: SLICE_102 + port map (C1=>nRowColSel, B1=>MAin_c_1, A1=>RowA_1, C0=>nRowColSel, + B0=>MAin_c_4, A0=>RowA_4, M1=>Din_c_5, M0=>Din_c_4, + CLK=>PHI2_c, F0=>RA_1_4, Q0=>Bank_4, F1=>RA_1_1, Q1=>Bank_5); + SLICE_103I: SLICE_103 + port map (C1=>nRowColSel, B1=>MAin_c_2, A1=>RowA_2, C0=>nRowColSel, + B0=>MAin_c_3, A0=>RowA_3, M1=>Din_c_3, M0=>Din_c_2, + CLK=>PHI2_c, F0=>RA_1_3, Q0=>Bank_2, F1=>RA_1_2, Q1=>Bank_3); + SLICE_104I: SLICE_104 + port map (B1=>nFWE_c, A1=>nCCAS_c, C0=>nFWE_c, B0=>n26, A0=>n2369, + M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready, CLK=>nCRAS_c, + F0=>n2363, Q0=>RowA_6, F1=>n984, Q1=>RowA_7); + SLICE_105I: SLICE_105 + port map (B1=>FS_6, A1=>FS_11, D0=>FS_16, C0=>FS_15, B0=>FS_12, + A0=>FS_13, F0=>n12, F1=>n4); + SLICE_106I: SLICE_106 + port map (B1=>Din_c_2, A1=>Din_c_0, B0=>Din_c_4, A0=>nFWE_c, M1=>n736, + M0=>n737, CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>n2228, + Q0=>n736, F1=>n2382, Q1=>n735); + RD_7_I: RD_7_B + port map (PADDI=>Dout_c, PADDT=>n984, PADDO=>WRD_7, RD7=>RD(7)); + RD_6_I: RD_6_B + port map (PADDI=>Dout_0S, PADDT=>n984, PADDO=>WRD_6, RD6=>RD(6)); + RD_5_I: RD_5_B + port map (PADDI=>Dout_1S, PADDT=>n984, PADDO=>WRD_5, RD5=>RD(5)); + RD_4_I: RD_4_B + port map (PADDI=>Dout_2S, PADDT=>n984, PADDO=>WRD_4, RD4=>RD(4)); + RD_3_I: RD_3_B + port map (PADDI=>Dout_3S, PADDT=>n984, PADDO=>WRD_3, RD3=>RD(3)); + RD_2_I: RD_2_B + port map (PADDI=>Dout_4S, PADDT=>n984, PADDO=>WRD_2, RD2=>RD(2)); + RD_1_I: RD_1_B + port map (PADDI=>Dout_5S, PADDT=>n984, PADDO=>WRD_1, RD1=>RD(1)); + RD_0_I: RD_0_B + port map (PADDI=>Dout_6S, PADDT=>n984, PADDO=>WRD_0, RD0=>RD(0)); + Dout_7_I: Dout_7_B + port map (PADDO=>Dout_c, Dout7=>Dout(7)); + Dout_6_I: Dout_6_B + port map (PADDO=>Dout_0S, Dout6=>Dout(6)); + Dout_5_I: Dout_5_B + port map (PADDO=>Dout_1S, Dout5=>Dout(5)); + Dout_4_I: Dout_4_B + port map (PADDO=>Dout_2S, Dout4=>Dout(4)); + Dout_3_I: Dout_3_B + port map (PADDO=>Dout_3S, Dout3=>Dout(3)); + Dout_2_I: Dout_2_B + port map (PADDO=>Dout_4S, Dout2=>Dout(2)); + Dout_1_I: Dout_1_B + port map (PADDO=>Dout_5S, Dout1=>Dout(1)); + Dout_0_I: Dout_0_B + port map (PADDO=>Dout_6S, Dout0=>Dout(0)); + LEDI: LEDB + port map (PADDO=>LED_c, LEDS=>LED); + RBA_1_I: RBA_1_B + port map (PADDO=>RBA_c_1, RBA1=>RBA(1)); + RBA_0_I: RBA_0_B + port map (PADDO=>RBA_c_0, RBA0=>RBA(0)); + RA_11_I: RA_11_B + port map (PADDO=>RA_c, RA11=>RA(11)); + RA_10_I: RA_10_B + port map (PADDO=>RA_0S, RA10=>RA(10)); + RA_9_I: RA_9_B + port map (PADDO=>RA_1_9, RA9=>RA(9)); + RA_8_I: RA_8_B + port map (PADDO=>RA_1_8, RA8=>RA(8)); + RA_7_I: RA_7_B + port map (PADDO=>RA_1_7, RA7=>RA(7)); + RA_6_I: RA_6_B + port map (PADDO=>RA_1_6, RA6=>RA(6)); + RA_5_I: RA_5_B + port map (PADDO=>RA_1_5, RA5=>RA(5)); + RA_4_I: RA_4_B + port map (PADDO=>RA_1_4, RA4=>RA(4)); + RA_3_I: RA_3_B + port map (PADDO=>RA_1_3, RA3=>RA(3)); + RA_2_I: RA_2_B + port map (PADDO=>RA_1_2, RA2=>RA(2)); + RA_1_I: RA_1_B + port map (PADDO=>RA_1_1, RA1=>RA(1)); + RA_0_I: RA_0_B + port map (PADDO=>RA_1_0, RA0=>RA(0)); + nRCSI: nRCSB + port map (PADDO=>nRCS_c, nRCSS=>nRCS); + RCKEI: RCKEB + port map (PADDO=>RCKE_c, RCKES=>RCKE); + nRWEI: nRWEB + port map (PADDO=>nRWE_c, nRWES=>nRWE); + nRRASI: nRRASB + port map (PADDO=>nRRAS_c, nRRASS=>nRRAS); + nRCASI: nRCASB + port map (PADDO=>nRCAS_c, nRCASS=>nRCAS); + RDQMHI: RDQMHB + port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH); + RDQMLI: RDQMLB + port map (PADDO=>RDQML_c, RDQMLS=>RDQML); + nUFMCSI: nUFMCSB + port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS); + UFMCLKI: UFMCLKB + port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK); + UFMSDII: UFMSDIB + port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI); + PHI2I: PHI2B + port map (PADDI=>PHI2_c, PHI2S=>PHI2); + MAin_9_I: MAin_9_B + port map (PADDI=>MAin_c_9, MAin9=>MAin(9)); + MAin_8_I: MAin_8_B + port map (PADDI=>MAin_c_8, MAin8=>MAin(8)); + MAin_7_I: MAin_7_B + port map (PADDI=>MAin_c_7, MAin7=>MAin(7)); + MAin_6_I: MAin_6_B + port map (PADDI=>MAin_c_6, MAin6=>MAin(6)); + MAin_5_I: MAin_5_B + port map (PADDI=>MAin_c_5, MAin5=>MAin(5)); + MAin_4_I: MAin_4_B + port map (PADDI=>MAin_c_4, MAin4=>MAin(4)); + MAin_3_I: MAin_3_B + port map (PADDI=>MAin_c_3, MAin3=>MAin(3)); + MAin_2_I: MAin_2_B + port map (PADDI=>MAin_c_2, MAin2=>MAin(2)); + MAin_1_I: MAin_1_B + port map (PADDI=>MAin_c_1, MAin1=>MAin(1)); + MAin_0_I: MAin_0_B + port map (PADDI=>MAin_c_0, MAin0=>MAin(0)); + CROW_1_I: CROW_1_B + port map (PADDI=>CROW_c_1, CROW1=>CROW(1)); + CROW_0_I: CROW_0_B + port map (PADDI=>CROW_c_0, CROW0=>CROW(0)); + Din_7_I: Din_7_B + port map (PADDI=>Din_c_7, Din7=>Din(7)); + Din_6_I: Din_6_B + port map (PADDI=>Din_c_6, Din6=>Din(6)); + Din_5_I: Din_5_B + port map (PADDI=>Din_c_5, Din5=>Din(5)); + Din_4_I: Din_4_B + port map (PADDI=>Din_c_4, Din4=>Din(4)); + Din_3_I: Din_3_B + port map (PADDI=>Din_c_3, Din3=>Din(3)); + Din_2_I: Din_2_B + port map (PADDI=>Din_c_2, Din2=>Din(2)); + Din_1_I: Din_1_B + port map (PADDI=>Din_c_1, Din1=>Din(1)); + Din_0_I: Din_0_B + port map (PADDI=>Din_c_0, Din0=>Din(0)); + nCCASI: nCCASB + port map (PADDI=>nCCAS_c, nCCASS=>nCCAS); + nCRASI: nCRASB + port map (PADDI=>nCRAS_c, nCRASS=>nCRAS); + nFWEI: nFWEB + port map (PADDI=>nFWE_c, nFWES=>nFWE); + RCLKI: RCLKB + port map (PADDI=>RCLK_c, RCLKS=>RCLK); + UFMSDOI: UFMSDOB + port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO); + VHI_INST: VHI + port map (Z=>VCCI); + PUR_INST: PUR + port map (PUR=>VCCI); + GSR_INST: GSR + port map (GSR=>VCCI); + end Structure; + + + + library IEEE, vital2000, MACHXO2; + configuration Structure_CON of RAM2GS is + for Structure + end for; + end Structure_CON; + + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf new file mode 100644 index 0000000..357899e --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf @@ -0,0 +1,3176 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Tue Aug 15 05:03:30 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_10") + (INSTANCE SLICE_10) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_15") + (INSTANCE SLICE_15) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_16") + (INSTANCE SLICE_16) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_20") + (INSTANCE SLICE_20) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_24") + (INSTANCE SLICE_24) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_25") + (INSTANCE SLICE_25) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_26") + (INSTANCE SLICE_26) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_27") + (INSTANCE SLICE_27) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_30") + (INSTANCE SLICE_30) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_33") + (INSTANCE SLICE_33) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_35") + (INSTANCE SLICE_35) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_36") + (INSTANCE SLICE_36) + (DELAY + (ABSOLUTE + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_37") + (INSTANCE SLICE_37) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_45") + (INSTANCE SLICE_45) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_50") + (INSTANCE SLICE_50) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_57") + (INSTANCE SLICE_57) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_59") + (INSTANCE SLICE_59) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_61") + (INSTANCE SLICE_61) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_62") + (INSTANCE SLICE_62) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_64") + (INSTANCE SLICE_64) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_65") + (INSTANCE SLICE_65) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_66") + (INSTANCE SLICE_66) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_67") + (INSTANCE SLICE_67) + (DELAY + (ABSOLUTE + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_68") + (INSTANCE SLICE_68) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_69") + (INSTANCE SLICE_69) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_70") + (INSTANCE SLICE_70) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "i30_SLICE_71") + (INSTANCE i30\/SLICE_71) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (457:589:721)(457:589:721)) + (IOPATH B1 OFX0 (457:589:721)(457:589:721)) + (IOPATH A1 OFX0 (457:589:721)(457:589:721)) + (IOPATH D0 OFX0 (457:589:721)(457:589:721)) + (IOPATH C0 OFX0 (457:589:721)(457:589:721)) + (IOPATH B0 OFX0 (457:589:721)(457:589:721)) + (IOPATH A0 OFX0 (457:589:721)(457:589:721)) + (IOPATH M0 OFX0 (322:349:376)(322:349:376)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_72") + (INSTANCE SLICE_72) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_73") + (INSTANCE SLICE_73) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_74") + (INSTANCE SLICE_74) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_75") + (INSTANCE SLICE_75) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_76") + (INSTANCE SLICE_76) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_80") + (INSTANCE SLICE_80) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_81") + (INSTANCE SLICE_81) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_84") + (INSTANCE SLICE_84) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_85") + (INSTANCE SLICE_85) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_102") + (INSTANCE SLICE_102) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_103") + (INSTANCE SLICE_103) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_104") + (INSTANCE SLICE_104) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_105") + (INSTANCE SLICE_105) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_106") + (INSTANCE SLICE_106) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_7_") + (INSTANCE RD\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD7 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD7 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD7) (3330:3330:3330)) + (WIDTH (negedge RD7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_6_") + (INSTANCE RD\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD6 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD6 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD6) (3330:3330:3330)) + (WIDTH (negedge RD6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_5_") + (INSTANCE RD\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD5 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD5 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD5) (3330:3330:3330)) + (WIDTH (negedge RD5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_4_") + (INSTANCE RD\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD4 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD4 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD4) (3330:3330:3330)) + (WIDTH (negedge RD4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_3_") + (INSTANCE RD\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD3 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD3 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD3) (3330:3330:3330)) + (WIDTH (negedge RD3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_2_") + (INSTANCE RD\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD2 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD2 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD2) (3330:3330:3330)) + (WIDTH (negedge RD2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_1_") + (INSTANCE RD\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD1 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD1 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD1) (3330:3330:3330)) + (WIDTH (negedge RD1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_0_") + (INSTANCE RD\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD0 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD0 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD0) (3330:3330:3330)) + (WIDTH (negedge RD0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Dout_7_") + (INSTANCE Dout\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout7 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_6_") + (INSTANCE Dout\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout6 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_5_") + (INSTANCE Dout\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout5 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_4_") + (INSTANCE Dout\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout4 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_3_") + (INSTANCE Dout\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout3 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_2_") + (INSTANCE Dout\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout2 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1_") + (INSTANCE Dout\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0_") + (INSTANCE Dout\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "LED") + (INSTANCE LED_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO LED (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_") + (INSTANCE RBA\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_0_") + (INSTANCE RBA\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_11_") + (INSTANCE RA\[11\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA11 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_10_") + (INSTANCE RA\[10\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA10 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_9_") + (INSTANCE RA\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA9 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_8_") + (INSTANCE RA\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA8 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_7_") + (INSTANCE RA\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA7 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_6_") + (INSTANCE RA\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA6 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_5_") + (INSTANCE RA\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA5 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_4_") + (INSTANCE RA\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA4 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_3_") + (INSTANCE RA\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA3 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_2_") + (INSTANCE RA\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA2 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_1_") + (INSTANCE RA\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_0_") + (INSTANCE RA\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRCS") + (INSTANCE nRCS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RCKE") + (INSTANCE RCKE_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RCKE (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRWE") + (INSTANCE nRWE_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRWE (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRRAS") + (INSTANCE nRRAS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRRAS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRCAS") + (INSTANCE nRCAS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCAS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMH") + (INSTANCE RDQMH_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMH (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RDQML") + (INSTANCE RDQML_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQML (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nUFMCS") + (INSTANCE nUFMCS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nUFMCS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "UFMCLK") + (INSTANCE UFMCLK_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMCLK (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "UFMSDI") + (INSTANCE UFMSDI_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMSDI (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "PHI2") + (INSTANCE PHI2_I) + (DELAY + (ABSOLUTE + (IOPATH PHI2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI2) (3330:3330:3330)) + (WIDTH (negedge PHI2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_9_") + (INSTANCE MAin\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (3330:3330:3330)) + (WIDTH (negedge MAin9) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_8_") + (INSTANCE MAin\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (3330:3330:3330)) + (WIDTH (negedge MAin8) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_7_") + (INSTANCE MAin\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (3330:3330:3330)) + (WIDTH (negedge MAin7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_6_") + (INSTANCE MAin\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (3330:3330:3330)) + (WIDTH (negedge MAin6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_5_") + (INSTANCE MAin\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (3330:3330:3330)) + (WIDTH (negedge MAin5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_4_") + (INSTANCE MAin\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (3330:3330:3330)) + (WIDTH (negedge MAin4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_3_") + (INSTANCE MAin\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (3330:3330:3330)) + (WIDTH (negedge MAin3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_2_") + (INSTANCE MAin\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (3330:3330:3330)) + (WIDTH (negedge MAin2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_1_") + (INSTANCE MAin\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (3330:3330:3330)) + (WIDTH (negedge MAin1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_0_") + (INSTANCE MAin\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (3330:3330:3330)) + (WIDTH (negedge MAin0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "CROW_1_") + (INSTANCE CROW\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (3330:3330:3330)) + (WIDTH (negedge CROW1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "CROW_0_") + (INSTANCE CROW\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (3330:3330:3330)) + (WIDTH (negedge CROW0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_7_") + (INSTANCE Din\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (3330:3330:3330)) + (WIDTH (negedge Din7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_6_") + (INSTANCE Din\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (3330:3330:3330)) + (WIDTH (negedge Din6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_5_") + (INSTANCE Din\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (3330:3330:3330)) + (WIDTH (negedge Din5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_4_") + (INSTANCE Din\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (3330:3330:3330)) + (WIDTH (negedge Din4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_3_") + (INSTANCE Din\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (3330:3330:3330)) + (WIDTH (negedge Din3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_2_") + (INSTANCE Din\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (3330:3330:3330)) + (WIDTH (negedge Din2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_1_") + (INSTANCE Din\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (3330:3330:3330)) + (WIDTH (negedge Din1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_0_") + (INSTANCE Din\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (3330:3330:3330)) + (WIDTH (negedge Din0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nCCAS") + (INSTANCE nCCAS_I) + (DELAY + (ABSOLUTE + (IOPATH nCCAS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCCAS) (3330:3330:3330)) + (WIDTH (negedge nCCAS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nCRAS") + (INSTANCE nCRAS_I) + (DELAY + (ABSOLUTE + (IOPATH nCRAS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCRAS) (3330:3330:3330)) + (WIDTH (negedge nCRAS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nFWE") + (INSTANCE nFWE_I) + (DELAY + (ABSOLUTE + (IOPATH nFWE PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nFWE) (3330:3330:3330)) + (WIDTH (negedge nFWE) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RCLK") + (INSTANCE RCLK_I) + (DELAY + (ABSOLUTE + (IOPATH RCLK PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RCLK) (3330:3330:3330)) + (WIDTH (negedge RCLK) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "UFMSDO") + (INSTANCE UFMSDO_I) + (DELAY + (ABSOLUTE + (IOPATH UFMSDO PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge UFMSDO) (3330:3330:3330)) + (WIDTH (negedge UFMSDO) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_76/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_80/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_82/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_85/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_85/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_105/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/F0 SLICE_0/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_16/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_27/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_35/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_37/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_45/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_57/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_61/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_62/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_65/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_66/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_67/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_68/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_69/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_70/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_75/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_78/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_79/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_81/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_84/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_86/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_97/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_98/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_106/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/FCO SLICE_0/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/FCO SLICE_9/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_76/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_80/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_85/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_105/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_57/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_70/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_76/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_80/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_82/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_85/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_105/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/F1 SLICE_1/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/FCO SLICE_1/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_45/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_68/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_95/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_95/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/FCO SLICE_6/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_86/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_105/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_95/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_95/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/FCO SLICE_3/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_95/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_44/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_95/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/F1 SLICE_4/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/F0 SLICE_4/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/FCO SLICE_8/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_68/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/F1 SLICE_5/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q1 SLICE_5/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q1 SLICE_66/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q1 SLICE_96/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_96/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_96/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_45/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_57/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_70/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_76/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_82/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_86/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_95/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/F1 SLICE_6/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/F0 SLICE_6/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_82/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_85/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/F0 SLICE_7/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/FCO SLICE_7/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_44/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_86/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_86/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/F1 SLICE_8/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/F0 SLICE_8/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q1 SLICE_9/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q1 SLICE_85/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q1 SLICE_105/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 SLICE_9/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 SLICE_85/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 SLICE_105/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F1 SLICE_9/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_10/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_24/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_33/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_50/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_89/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_89/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_89/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_90/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_102/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_106/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_10/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_24/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_33/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_33/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_75/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_88/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_101/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_10/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_50/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_90/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_90/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_90/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_93/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_100/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_10/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_24/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_33/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_88/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_90/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_90/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_101/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/F1 SLICE_10/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10/F1 SLICE_10/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F0 SLICE_10/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_10/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_73/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10/F0 SLICE_10/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F0 SLICE_10/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_10/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_15/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_88/C1 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_10/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_15/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_20/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_24/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_33/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_50/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_86/M0 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_93/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_99/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_100/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_101/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_102/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_103/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10/Q0 SLICE_88/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_15/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_73/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_74/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_79/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_83/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_91/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_91/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_104/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_15/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_79/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_82/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_101/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F1 SLICE_15/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F1 SLICE_79/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_15/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_79/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_91/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_103/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_15/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_19/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_73/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_74/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_79/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_83/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_97/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_102/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15/Q0 SLICE_15/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15/Q0 SLICE_77/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15/F1 SLICE_15/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_15/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_25/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_25/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_74/D0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_79/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_104/B1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_104/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_106/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15/F0 SLICE_15/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_16/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_88/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_89/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_90/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_92/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_104/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/F0 SLICE_16/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/F0 SLICE_25/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q0 SLICE_16/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F0 SLICE_19/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_19/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_24/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_25/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_75/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_77/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_89/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_89/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_89/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_102/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F0 SLICE_19/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F0 SLICE_77/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_19/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_75/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F1 SLICE_19/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F1 SLICE_19/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F1 SLICE_77/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F0 SLICE_19/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F0 SLICE_88/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F1 SLICE_19/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_73/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_83/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20/F0 SLICE_20/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F1 SLICE_20/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20/Q0 SLICE_35/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20/Q0 SLICE_84/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F1 SLICE_24/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F1 SLICE_50/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F1 SLICE_83/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/Q0 SLICE_24/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/Q0 SLICE_33/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_24/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_50/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_90/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_90/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_90/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_93/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_99/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_106/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F0 SLICE_24/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F0 SLICE_24/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/Q0 SLICE_57/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_25/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_50/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_75/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_77/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_89/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_89/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_92/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_103/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_25/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_30/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_30/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_74/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_76/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_82/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_87/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_91/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_104/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_65/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 i30\/SLICE_71/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 i30\/SLICE_71/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_81/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_96/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_30/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_59/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 i30\/SLICE_71/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 i30\/SLICE_71/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_81/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_96/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_96/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F0 SLICE_26/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_32/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_35/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_35/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_44/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_45/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_57/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_62/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_70/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_70/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_72/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_76/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_80/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_84/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_92/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_92/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27/F0 SLICE_27/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F0 SLICE_27/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27/Q0 SLICE_30/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27/Q0 SLICE_50/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q0 SLICE_30/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q0 SLICE_36/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/F1 LED_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_32/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_36/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_59/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_61/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_62/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_66/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_67/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_69/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_69/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 i30\/SLICE_71/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_72/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_78/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_86/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_92/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_92/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_32/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_59/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_61/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_62/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_62/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_68/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 i30\/SLICE_71/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_78/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_87/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_92/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_92/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_94/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_94/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_32/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_59/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_64/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_84/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_32/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_33/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_35/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_59/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_61/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_62/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_64/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_72/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_74/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_76/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_82/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_87/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_87/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_91/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_92/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_94/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_94/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_104/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/F1 SLICE_32/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_32/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_62/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_92/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_98/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q1 SLICE_32/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q1 SLICE_64/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q1 SLICE_79/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/Q0 RA\[10\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50/Q0 SLICE_33/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33/Q0 RA\[11\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33/F1 SLICE_73/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q1 SLICE_35/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q1 SLICE_69/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q1 SLICE_84/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q1 SLICE_35/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q1 SLICE_84/A1 (0:0:0)(0:0:0)) + (INTERCONNECT i30\/SLICE_71/OFX0 SLICE_35/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F0 SLICE_35/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_35/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_59/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_61/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_62/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q0 SLICE_36/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F1 SLICE_44/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F1 SLICE_45/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F1 SLICE_70/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/Q1 SLICE_36/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/F0 SLICE_36/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/Q0 SLICE_36/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_61/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_69/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_78/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 RCKE_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/F0 SLICE_37/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_72/F1 SLICE_37/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F1 SLICE_44/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_44/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_70/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_82/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/Q0 SLICE_44/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F1 SLICE_44/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F0 SLICE_44/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F0 SLICE_45/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 UFMCLK_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_45/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_57/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_76/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_80/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_85/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F1 SLICE_45/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 SLICE_45/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/Q0 SLICE_45/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45/F1 SLICE_45/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45/F0 SLICE_45/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45/Q0 UFMSDI_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50/F1 SLICE_50/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_50/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_77/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_88/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_92/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_97/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_100/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_103/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_106/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50/F0 SLICE_50/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F1 SLICE_50/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_57/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_80/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_95/A1 (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDO_I/PADDI SLICE_57/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/F1 SLICE_57/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/F1 SLICE_84/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/F0 SLICE_57/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F0 SLICE_57/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_59/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_61/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59/F1 SLICE_59/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F0 SLICE_59/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F0 SLICE_64/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59/F0 SLICE_59/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59/Q0 nRCAS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/F1 SLICE_61/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F1 SLICE_61/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F1 SLICE_62/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/F0 SLICE_61/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/Q0 nRCS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_62/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F0 SLICE_62/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/Q0 nRRAS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_64/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F1 SLICE_64/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F0 SLICE_64/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F0 SLICE_64/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F0 SLICE_65/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 nRWE_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_65/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_67/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 i30\/SLICE_71/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_81/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_87/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_65/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_66/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_66/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_81/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_87/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F1 SLICE_65/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_65/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_78/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_94/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_65/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F0 SLICE_65/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_93/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_93/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_98/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_98/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_99/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_100/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_101/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_101/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_102/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_102/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_103/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_103/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_66/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_67/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_72/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_87/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_94/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F0 SLICE_66/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 i30\/SLICE_71/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F0 SLICE_67/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F0 SLICE_68/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/Q1 SLICE_68/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/Q0 SLICE_68/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F0 SLICE_74/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F1 SLICE_86/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F0 SLICE_69/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_70/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_76/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/Q1 SLICE_70/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70/F1 SLICE_70/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70/F0 SLICE_70/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70/Q0 nUFMCS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_72/F0 SLICE_72/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q1 SLICE_72/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q1 SLICE_98/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F0 SLICE_73/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F0 SLICE_74/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_73/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_74/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_79/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_83/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_91/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_91/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_104/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_73/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_74/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_77/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_83/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_88/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_91/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_97/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_97/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_101/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F1 SLICE_99/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F1 SLICE_100/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/Q1 SLICE_74/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 SLICE_74/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/Q0 SLICE_74/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F0 SLICE_89/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F0 SLICE_89/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_101/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q1 SLICE_102/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F0 SLICE_75/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/F0 SLICE_75/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/F0 SLICE_83/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q0 SLICE_75/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/Q1 SLICE_75/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_75/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_78/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_79/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_81/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_84/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_97/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_98/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_106/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F1 SLICE_88/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_76/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_93/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_93/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_98/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_76/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_98/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q0 SLICE_98/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_93/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_97/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F0 SLICE_78/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F0 SLICE_78/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F0 SLICE_81/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/Q0 SLICE_78/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_78/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/Q1 SLICE_81/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q0 SLICE_79/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F1 SLICE_81/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q0 SLICE_81/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F0 SLICE_82/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_82/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_100/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_102/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q0 SLICE_102/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q1 SLICE_101/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F0 SLICE_83/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F0 SLICE_84/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F1 SLICE_84/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q0 SLICE_84/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q1 SLICE_106/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_86/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F0 SLICE_86/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F0 SLICE_87/D1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_87/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_87/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 RBA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 RBA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F1 SLICE_88/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F1 SLICE_88/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/Q0 RD\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/Q1 RD\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q0 RD\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q1 RD\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q0 RD\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q1 RD\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_91/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_99/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_103/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q0 SLICE_103/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q1 SLICE_103/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/Q0 RD\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/Q1 RD\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F0 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/Q0 SLICE_100/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/Q1 SLICE_99/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/Q0 SLICE_97/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/Q1 SLICE_97/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F1 RDQMH_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/Q0 SLICE_99/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_99/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_99/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_104/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/Q1 SLICE_99/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F0 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/Q1 SLICE_100/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_100/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_100/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_104/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/Q0 SLICE_100/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 RA\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F0 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F1 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F0 RA\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F1 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F0 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F1 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[7\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[6\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[5\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[4\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[3\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[2\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[1\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[0\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/Q0 SLICE_106/M1 (0:0:0)(0:0:0)) + (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo new file mode 100644 index 0000000..ec046df --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo @@ -0,0 +1,3692 @@ + +// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +// ldbanno -n Verilog -o RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd +// Netlist created on Tue Aug 15 05:03:26 2023 +// Netlist written on Tue Aug 15 05:03:29 2023 +// Design is for device LCMXO2-1200HC +// Design is for package TQFP100 +// Design is for performance grade 4 + +`timescale 1 ns / 1 ps + +module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, + RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, + UFMCLK, UFMSDI, UFMSDO ); + input PHI2; + input [9:0] MAin; + input [1:0] CROW; + input [7:0] Din; + input nCCAS, nCRAS, nFWE, RCLK, UFMSDO; + output [7:0] Dout; + output LED; + output [1:0] RBA; + output [11:0] RA; + output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI; + inout [7:0] RD; + wire FS_14, FS_13, n81, n82, RCLK_c, n1998, n1999, FS_12, FS_11, n83, n84, + n1997, FS_8, FS_7, n87, n88, n1995, n1996, FS_6, FS_5, n89, n90, + n1994, FS_2, FS_1, n93, n94, n1992, n1993, FS_0, n95, CASr2, CASr3, + FS_10, FS_9, n85, n86, FS_17, n78, n2000, FS_4, FS_3, n91, n92, FS_16, + FS_15, n79, n80, Din_c_4, Din_c_6, Din_c_1, Din_c_7, n2382, n8, n2225, + n2180, ADSubmitted_N_246, PHI2_N_120_enable_2, C1Submitted_N_237, + PHI2_c, ADSubmitted, n26, MAin_c_5, n22, MAin_c_2, MAin_c_1, + C1Submitted, n2365, nFWE_c, n1398, nCCAS_c, nCCAS_N_3, CASr, n2254, + Din_c_5, n2191, n2183, n15_adj_1, n2208, n2363, CmdEnable_N_248, + PHI2_N_120_enable_1, CmdEnable, \n2447\001/BUF1 , PHI2_N_120_enable_7, + CmdSubmitted, n1314, n8MEGEN, Din_c_0, Cmdn8MEGEN_N_264, + PHI2_N_120_enable_6, Cmdn8MEGEN, Din_c_3, n2373, nCRAS_c, FWEr, CBR, + \n2447\000/BUF1 , RCLK_c_enable_28, InitReady, n2447, + RCLK_c_enable_16, LEDEN, nCRAS_c__inv, RASr, LED_c, RASr2, + nRowColSel_N_35, nRCAS_N_165, Ready, n2381, nRCS_N_139, n2036, + nRWE_N_177, RA_0, XOR8MEG, RA11_N_184, RA_c, n6_adj_2, PHI2r2, PHI2r3, + n15_adj_4, RCKEEN_N_121, RCLK_c_enable_6, RCKEEN, RCLK_c_enable_10, + RASr3, RCKE_N_132, PHI2r, RCKE_c, \n2447\002/BUF1 , Ready_N_292, + n2267, n13_adj_6, CmdUFMCLK, n1893, UFMCLK_N_224, n2366, UFMCLK_c, + n10, n7, n4, CmdUFMSDI, n2174, UFMSDI_N_231, UFMSDI_c, n2260, Din_c_2, + XOR8MEG_N_110, PHI2_N_120_enable_3, n2375, UFMSDO_c, n2367, + n8MEGEN_N_91, RCLK_c_enable_15, nRCS_N_142, nRCAS_N_166, n2371, + nRCAS_N_161, nRCAS_c, nRCS_N_141, nRCS_N_137, nRCS_N_136, nRCS_c, + n2379, nRRAS_N_156, nRRAS_c, nRWE_N_178, n1765, nRWE_N_171, + RCLK_c_enable_5, nRWE_c, nRowColSel_N_34, nRowColSel_N_33, n2376, + n1060, n2372, n917, nRowColSel, nRowColSel_N_32, n827, n2227, n1406, + Bank_3, Bank_6, n2287, n13, n2374, n2368, CmdUFMCS, n64, nUFMCS_N_199, + nUFMCS_c, n6_adj_3, Ready_N_296, n2204, n2369, MAin_c_0, + PHI2_N_120_enable_8, Bank_5, n2277, Bank_2, n2220, RowA_0, RowA_1, + n2370, n2228, n732, n733, RCLK_c_enable_27, n2055, MAin_c_9, MAin_c_8, + RowA_8, RowA_9, n2210, nRWE_N_182, nRCS_N_146, n728, n729, n727, n730, + n2378, n726, n12, MAin_c_4, RowA_4, RowA_5, n1277, n4_adj_7, n2377, + n738, n737, n14, n15, n6, CROW_c_1, CROW_c_0, RBA_c_0, RBA_c_1, + n7_adj_5, n2362, WRD_6, WRD_7, WRD_4, WRD_5, WRD_0, WRD_1, MAin_c_3, + RowA_2, RowA_3, WRD_2, WRD_3, RA_1_9, Bank_0, RDQML_c, Bank_1, n734, + n735, RA_1_8, RDQMH_c, Bank_4, MAin_c_7, RowA_7, RA_1_7, Bank_7, + MAin_c_6, RowA_6, RA_1_6, RA_1_5, RA_1_0, RA_1_4, RA_1_1, RA_1_3, + RA_1_2, n984, n736, Dout_c, Dout_0, Dout_1, Dout_2, Dout_3, Dout_4, + Dout_5, Dout_6, VCCI; + + SLICE_0 SLICE_0( .A1(FS_14), .A0(FS_13), .DI1(n81), .DI0(n82), .CLK(RCLK_c), + .FCI(n1998), .F0(n82), .Q0(FS_13), .F1(n81), .Q1(FS_14), .FCO(n1999)); + SLICE_1 SLICE_1( .A1(FS_12), .A0(FS_11), .DI1(n83), .DI0(n84), .CLK(RCLK_c), + .FCI(n1997), .F0(n84), .Q0(FS_11), .F1(n83), .Q1(FS_12), .FCO(n1998)); + SLICE_2 SLICE_2( .A1(FS_8), .A0(FS_7), .DI1(n87), .DI0(n88), .CLK(RCLK_c), + .FCI(n1995), .F0(n88), .Q0(FS_7), .F1(n87), .Q1(FS_8), .FCO(n1996)); + SLICE_3 SLICE_3( .A1(FS_6), .A0(FS_5), .DI1(n89), .DI0(n90), .CLK(RCLK_c), + .FCI(n1994), .F0(n90), .Q0(FS_5), .F1(n89), .Q1(FS_6), .FCO(n1995)); + SLICE_4 SLICE_4( .A1(FS_2), .A0(FS_1), .DI1(n93), .DI0(n94), .CLK(RCLK_c), + .FCI(n1992), .F0(n94), .Q0(FS_1), .F1(n93), .Q1(FS_2), .FCO(n1993)); + SLICE_5 SLICE_5( .A1(FS_0), .DI1(n95), .M0(CASr2), .CLK(RCLK_c), .Q0(CASr3), + .F1(n95), .Q1(FS_0), .FCO(n1992)); + SLICE_6 SLICE_6( .A1(FS_10), .A0(FS_9), .DI1(n85), .DI0(n86), .CLK(RCLK_c), + .FCI(n1996), .F0(n86), .Q0(FS_9), .F1(n85), .Q1(FS_10), .FCO(n1997)); + SLICE_7 SLICE_7( .A0(FS_17), .DI0(n78), .CLK(RCLK_c), .FCI(n2000), .F0(n78), + .Q0(FS_17)); + SLICE_8 SLICE_8( .A1(FS_4), .A0(FS_3), .DI1(n91), .DI0(n92), .CLK(RCLK_c), + .FCI(n1993), .F0(n92), .Q0(FS_3), .F1(n91), .Q1(FS_4), .FCO(n1994)); + SLICE_9 SLICE_9( .A1(FS_16), .A0(FS_15), .DI1(n79), .DI0(n80), .CLK(RCLK_c), + .FCI(n1999), .F0(n80), .Q0(FS_15), .F1(n79), .Q1(FS_16), .FCO(n2000)); + SLICE_10 SLICE_10( .D1(Din_c_4), .C1(Din_c_6), .B1(Din_c_1), .A1(Din_c_7), + .D0(n2382), .C0(n8), .B0(n2225), .A0(n2180), .DI0(ADSubmitted_N_246), + .CE(PHI2_N_120_enable_2), .LSR(C1Submitted_N_237), .CLK(PHI2_c), + .F0(ADSubmitted_N_246), .Q0(ADSubmitted), .F1(n8)); + SLICE_15 SLICE_15( .D1(n26), .C1(MAin_c_5), .B1(n22), .A1(MAin_c_2), + .D0(MAin_c_1), .C0(C1Submitted), .B0(n2365), .A0(nFWE_c), .DI0(n1398), + .LSR(C1Submitted_N_237), .CLK(PHI2_c), .F0(n1398), .Q0(C1Submitted), + .F1(n2365)); + SLICE_16 SLICE_16( .A0(nCCAS_c), .DI0(nCCAS_N_3), .M1(CASr), .CLK(RCLK_c), + .F0(nCCAS_N_3), .Q0(CASr), .Q1(CASr2)); + SLICE_19 SLICE_19( .D1(n2254), .C1(Din_c_5), .B1(n2191), .A1(n2183), + .D0(n15_adj_1), .C0(n2208), .B0(MAin_c_1), .A0(n2363), + .DI0(CmdEnable_N_248), .CE(PHI2_N_120_enable_1), .CLK(PHI2_c), + .F0(CmdEnable_N_248), .Q0(CmdEnable), .F1(n15_adj_1)); + SLICE_20 SLICE_20( .DI0(\n2447\001/BUF1 ), .CE(PHI2_N_120_enable_7), + .CLK(PHI2_c), .F0(\n2447\001/BUF1 ), .Q0(CmdSubmitted)); + SLICE_24 SLICE_24( .C1(Din_c_5), .B1(Din_c_7), .A1(Din_c_6), .D0(n1314), + .C0(Din_c_4), .B0(n8MEGEN), .A0(Din_c_0), .DI0(Cmdn8MEGEN_N_264), + .CE(PHI2_N_120_enable_6), .CLK(PHI2_c), .F0(Cmdn8MEGEN_N_264), + .Q0(Cmdn8MEGEN), .F1(n1314)); + SLICE_25 SLICE_25( .C1(Din_c_3), .B1(Din_c_5), .A1(nFWE_c), .A0(nFWE_c), + .DI0(n2373), .M1(nCCAS_N_3), .CLK(nCRAS_c), .F0(n2373), .Q0(FWEr), + .F1(n2180), .Q1(CBR)); + SLICE_26 SLICE_26( .DI0(\n2447\000/BUF1 ), .CE(RCLK_c_enable_28), + .CLK(RCLK_c), .F0(\n2447\000/BUF1 ), .Q0(InitReady)); + SLICE_27 SLICE_27( .DI0(n2447), .CE(RCLK_c_enable_16), .CLK(RCLK_c), + .F0(n2447), .Q0(LEDEN)); + SLICE_30 SLICE_30( .C1(CBR), .B1(LEDEN), .A1(nCRAS_c), .A0(nCRAS_c), + .DI0(nCRAS_c__inv), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c__inv), .Q0(RASr), + .F1(LED_c), .Q1(RASr2)); + SLICE_32 SLICE_32( .C1(nRowColSel_N_35), .B1(InitReady), .A1(RASr2), + .D0(nRCAS_N_165), .C0(Ready), .B0(n2381), .A0(nRCS_N_139), .DI0(n2036), + .LSR(nRWE_N_177), .CLK(RCLK_c), .F0(n2036), .Q0(RA_0), .F1(n2381)); + SLICE_33 SLICE_33( .C1(Din_c_4), .B1(Din_c_7), .A1(Din_c_6), .C0(n8MEGEN), + .B0(XOR8MEG), .A0(Din_c_6), .DI0(RA11_N_184), .LSR(Ready), .CLK(PHI2_c), + .F0(RA11_N_184), .Q0(RA_c), .F1(n6_adj_2)); + SLICE_35 SLICE_35( .D1(InitReady), .C1(CmdSubmitted), .B1(PHI2r2), + .A1(PHI2r3), .C0(Ready), .B0(n15_adj_4), .A0(InitReady), + .DI0(RCKEEN_N_121), .CE(RCLK_c_enable_6), .CLK(RCLK_c), .F0(RCKEEN_N_121), + .Q0(RCKEEN), .F1(RCLK_c_enable_10)); + SLICE_36 SLICE_36( .D0(RASr3), .C0(RASr2), .B0(RCKEEN), .A0(RASr), + .DI0(RCKE_N_132), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKE_N_132), .Q0(RCKE_c), + .Q1(PHI2r2)); + SLICE_37 SLICE_37( .DI0(\n2447\002/BUF1 ), .CE(Ready_N_292), .CLK(RCLK_c), + .F0(\n2447\002/BUF1 ), .Q0(Ready)); + SLICE_44 SLICE_44( .D1(FS_1), .C1(n2267), .B1(n13_adj_6), .A1(FS_4), + .C0(InitReady), .B0(CmdUFMCLK), .A0(n1893), .DI0(UFMCLK_N_224), + .CE(RCLK_c_enable_10), .LSR(n2366), .CLK(RCLK_c), .F0(UFMCLK_N_224), + .Q0(UFMCLK_c), .F1(n1893)); + SLICE_45 SLICE_45( .D1(n10), .C1(FS_10), .B1(FS_8), .A1(n7), .D0(n4), + .C0(InitReady), .B0(CmdUFMSDI), .A0(n2174), .DI0(UFMSDI_N_231), + .CE(RCLK_c_enable_10), .LSR(n2366), .CLK(RCLK_c), .F0(UFMSDI_N_231), + .Q0(UFMSDI_c), .F1(n2174)); + SLICE_50 SLICE_50( .D1(LEDEN), .C1(n1314), .B1(Din_c_1), .A1(Din_c_4), + .D0(Din_c_3), .C0(n2260), .B0(Din_c_2), .A0(Din_c_0), .DI0(XOR8MEG_N_110), + .CE(PHI2_N_120_enable_3), .CLK(PHI2_c), .F0(XOR8MEG_N_110), .Q0(XOR8MEG), + .F1(n2260)); + SLICE_57 SLICE_57( .D1(FS_10), .C1(FS_11), .B1(n2375), .A1(n10), + .D0(Cmdn8MEGEN), .C0(UFMSDO_c), .B0(n2367), .A0(InitReady), + .DI0(n8MEGEN_N_91), .CE(RCLK_c_enable_15), .CLK(RCLK_c), .F0(n8MEGEN_N_91), + .Q0(n8MEGEN), .F1(n2367)); + SLICE_59 SLICE_59( .D1(CBR), .C1(nRowColSel_N_35), .B1(RASr2), + .A1(nRCS_N_142), .D0(nRCAS_N_166), .C0(Ready), .B0(nRCAS_N_165), + .A0(n2371), .DI0(nRCAS_N_161), .CE(RCLK_c_enable_6), .CLK(RCLK_c), + .F0(nRCAS_N_161), .Q0(nRCAS_c), .F1(nRCAS_N_166)); + SLICE_61 SLICE_61( .D1(nRCS_N_142), .C1(nRowColSel_N_35), .B1(RASr2), + .A1(RCKE_c), .C0(Ready), .B0(nRCS_N_141), .A0(nRCS_N_137), + .DI0(nRCS_N_136), .CE(RCLK_c_enable_6), .CLK(RCLK_c), .F0(nRCS_N_136), + .Q0(nRCS_c), .F1(nRCS_N_141)); + SLICE_62 SLICE_62( .D1(RASr2), .C1(nRowColSel_N_35), .B1(InitReady), + .A1(nRCS_N_139), .D0(nRowColSel_N_35), .C0(Ready), .B0(n2379), + .A0(nRCS_N_137), .DI0(nRRAS_N_156), .CE(RCLK_c_enable_6), .CLK(RCLK_c), + .F0(nRRAS_N_156), .Q0(nRRAS_c), .F1(nRCS_N_137)); + SLICE_64 SLICE_64( .B1(nRCAS_N_165), .A1(nRWE_N_177), .D0(n2371), .C0(Ready), + .B0(nRWE_N_178), .A0(n1765), .DI0(nRWE_N_171), .CE(RCLK_c_enable_5), + .CLK(RCLK_c), .F0(nRWE_N_171), .Q0(nRWE_c), .F1(n1765)); + SLICE_65 SLICE_65( .B1(nRowColSel_N_34), .A1(nRowColSel_N_33), .D0(n2376), + .C0(n1060), .B0(n2372), .A0(FWEr), .DI0(n917), .CE(RCLK_c_enable_5), + .CLK(RCLK_c), .F0(n917), .Q0(nRowColSel), .F1(n1060)); + SLICE_66 SLICE_66( .B1(CASr2), .A1(nRowColSel_N_33), .B0(nRowColSel_N_32), + .A0(nRowColSel_N_33), .DI0(n827), .LSR(RASr2), .CLK(RCLK_c), .F0(n827), + .Q0(nRowColSel_N_32), .F1(n2227)); + SLICE_67 SLICE_67( .B0(nRowColSel_N_32), .A0(RASr2), .DI0(n1406), + .LSR(nRowColSel_N_34), .CLK(RCLK_c), .F0(n1406), .Q0(nRowColSel_N_33)); + SLICE_68 SLICE_68( .B1(FS_0), .A1(FS_8), .B0(Bank_3), .A0(Bank_6), + .M0(n1406), .LSR(nRowColSel_N_35), .CLK(RCLK_c), .F0(n2287), + .Q0(nRowColSel_N_34), .F1(n13)); + SLICE_69 SLICE_69( .B1(RASr2), .A1(RCKE_c), .A0(RASr2), .DI0(n2374), + .M1(PHI2r2), .CLK(RCLK_c), .F0(n2374), .Q0(nRowColSel_N_35), .F1(n2379), + .Q1(PHI2r3)); + SLICE_70 SLICE_70( .D1(FS_10), .C1(InitReady), .B1(n2368), .A1(FS_11), + .D0(InitReady), .C0(CmdUFMCS), .B0(n64), .A0(n13_adj_6), + .DI0(nUFMCS_N_199), .CE(RCLK_c_enable_10), .CLK(RCLK_c), .F0(nUFMCS_N_199), + .Q0(nUFMCS_c), .F1(n64)); + i30_SLICE_71 \i30/SLICE_71 ( .C1(RASr2), .B1(FWEr), .A1(CBR), + .D0(nRowColSel_N_34), .C0(FWEr), .B0(n2227), .A0(CBR), + .M0(nRowColSel_N_35), .OFX0(n15_adj_4)); + SLICE_72 SLICE_72( .D1(Ready), .C1(nRowColSel_N_32), .B1(n6_adj_3), + .A1(RASr2), .B0(Ready_N_296), .A0(InitReady), .F0(n6_adj_3), + .F1(Ready_N_292)); + SLICE_73 SLICE_73( .D1(n2204), .C1(n2180), .B1(n26), .A1(n2369), + .D0(n6_adj_2), .C0(CmdEnable), .B0(MAin_c_0), .A0(MAin_c_1), .F0(n2204), + .F1(PHI2_N_120_enable_8)); + SLICE_74 SLICE_74( .D1(Bank_5), .C1(n2287), .B1(n2277), .A1(Bank_2), + .D0(nFWE_c), .C0(n2204), .B0(n26), .A0(n2369), .M1(MAin_c_1), + .M0(MAin_c_0), .LSR(Ready), .CLK(nCRAS_c), .F0(n2220), .Q0(RowA_0), + .F1(n26), .Q1(RowA_1)); + SLICE_75 SLICE_75( .D1(n2370), .C1(n2183), .B1(n2228), .A1(Din_c_5), + .B0(Din_c_3), .A0(Din_c_6), .M1(n732), .M0(n733), .CE(RCLK_c_enable_27), + .CLK(RCLK_c), .F0(n2183), .Q0(n732), .F1(n2055), .Q1(nRWE_N_177)); + SLICE_76 SLICE_76( .C1(n10), .B1(FS_14), .A1(FS_12), .D0(InitReady), + .C0(n2368), .B0(FS_11), .A0(FS_10), .M1(MAin_c_9), .M0(MAin_c_8), + .LSR(Ready), .CLK(nCRAS_c), .F0(RCLK_c_enable_16), .Q0(RowA_8), .F1(n2368), + .Q1(RowA_9)); + SLICE_77 SLICE_77( .D1(n2208), .C1(C1Submitted), .B1(n2191), .A1(Din_c_5), + .D0(MAin_c_0), .C0(Din_c_6), .B0(Din_c_3), .A0(Din_c_2), .F0(n2191), + .F1(n2210)); + SLICE_78 SLICE_78( .D1(nRowColSel_N_35), .C1(nRWE_N_182), .B1(n1060), + .A1(nRCS_N_146), .B0(RASr2), .A0(RCKE_c), .M1(n728), .M0(n729), + .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(nRWE_N_182), .Q0(n728), + .F1(nRWE_N_178), .Q1(n727)); + SLICE_79 SLICE_79( .C1(MAin_c_5), .B1(n22), .A1(MAin_c_2), .D0(MAin_c_1), + .C0(nFWE_c), .B0(n26), .A0(n2369), .M1(n730), .M0(nRWE_N_177), + .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(PHI2_N_120_enable_2), .Q0(n730), + .F1(n2369), .Q1(n729)); + SLICE_80 SLICE_80( .B1(FS_14), .A1(FS_12), .D0(FS_11), .C0(InitReady), + .B0(n2375), .A0(n10), .F0(n2366), .F1(n2375)); + SLICE_81 SLICE_81( .B1(CBR), .A1(FWEr), .D0(nRowColSel_N_33), .C0(n2378), + .B0(nRowColSel_N_34), .A0(nRCS_N_146), .M1(n726), .M0(n727), + .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(nRCS_N_142), .Q0(n726), + .F1(n2378), .Q1(Ready_N_296)); + SLICE_82 SLICE_82( .D1(FS_17), .C1(FS_14), .B1(n12), .A1(FS_11), + .B0(n13_adj_6), .A0(FS_10), .M1(MAin_c_5), .M0(MAin_c_4), .LSR(Ready), + .CLK(nCRAS_c), .F0(RCLK_c_enable_28), .Q0(RowA_4), .F1(n13_adj_6), + .Q1(RowA_5)); + SLICE_83 SLICE_83( .D1(n1314), .C1(n1277), .B1(CmdEnable), .A1(n2228), + .D0(MAin_c_1), .C0(MAin_c_0), .B0(n26), .A0(n2369), .F0(n1277), + .F1(PHI2_N_120_enable_3)); + SLICE_84 SLICE_84( .C1(CmdSubmitted), .B1(PHI2r2), .A1(PHI2r3), + .D0(n4_adj_7), .C0(InitReady), .B0(n2377), .A0(n2367), .M1(n738), + .M0(nRCAS_N_165), .CE(RCLK_c_enable_27), .CLK(RCLK_c), + .F0(RCLK_c_enable_15), .Q0(n738), .F1(n2377), .Q1(n737)); + SLICE_85 SLICE_85( .D1(n10), .C1(FS_11), .B1(FS_14), .A1(FS_12), .D0(FS_16), + .C0(FS_15), .B0(FS_13), .A0(FS_17), .F0(n10), .F1(n2267)); + SLICE_86 SLICE_86( .C1(FS_6), .B1(FS_9), .A1(FS_3), .D0(n14), .C0(n13), + .B0(n15), .A0(FS_4), .M1(RASr2), .M0(PHI2_c), .CLK(RCLK_c), .F0(n4_adj_7), + .Q0(PHI2r), .F1(n14), .Q1(RASr3)); + SLICE_87 SLICE_87( .D1(n6), .C1(nRowColSel_N_32), .B1(nRowColSel_N_33), + .A1(nRowColSel_N_35), .B0(nRowColSel_N_34), .A0(Ready), .M1(CROW_c_1), + .M0(CROW_c_0), .LSR(Ready), .CLK(nCRAS_c), .F0(n6), .Q0(RBA_c_0), + .F1(RCLK_c_enable_6), .Q1(RBA_c_1)); + SLICE_88 SLICE_88( .D1(n2363), .C1(C1Submitted_N_237), .B1(ADSubmitted), + .A1(n7_adj_5), .D0(n2362), .C0(MAin_c_0), .B0(n2055), .A0(Din_c_2), + .M1(Din_c_7), .M0(Din_c_6), .CLK(nCCAS_c), .F0(C1Submitted_N_237), + .Q0(WRD_6), .F1(PHI2_N_120_enable_1), .Q1(WRD_7)); + SLICE_89 SLICE_89( .D1(Din_c_5), .C1(Din_c_3), .B1(Din_c_4), .A1(n2220), + .D0(Din_c_3), .C0(Din_c_4), .B0(n2220), .A0(Din_c_5), .M1(Din_c_5), + .M0(Din_c_4), .CLK(nCCAS_c), .F0(PHI2_N_120_enable_6), .Q0(WRD_4), + .F1(PHI2_N_120_enable_7), .Q1(WRD_5)); + SLICE_90 SLICE_90( .D1(Din_c_0), .C1(Din_c_4), .B1(Din_c_1), .A1(Din_c_7), + .C0(Din_c_0), .B0(Din_c_1), .A0(Din_c_7), .M1(Din_c_1), .M0(Din_c_0), + .CLK(nCCAS_c), .F0(n2370), .Q0(WRD_0), .F1(n2208), .Q1(WRD_1)); + SLICE_91 SLICE_91( .C1(MAin_c_1), .B1(n26), .A1(n2369), .D0(MAin_c_1), + .C0(MAin_c_0), .B0(n26), .A0(n2369), .M1(MAin_c_3), .M0(MAin_c_2), + .LSR(Ready), .CLK(nCRAS_c), .F0(n2225), .Q0(RowA_2), .F1(n2362), + .Q1(RowA_3)); + SLICE_92 SLICE_92( .D1(Ready), .C1(nRowColSel_N_35), .B1(InitReady), + .A1(RASr2), .D0(nRCS_N_139), .C0(nRowColSel_N_35), .B0(InitReady), + .A0(RASr2), .M1(Din_c_3), .M0(Din_c_2), .CLK(nCCAS_c), .F0(n2371), + .Q0(WRD_2), .F1(RCLK_c_enable_27), .Q1(WRD_3)); + SLICE_93 SLICE_93( .B1(nRowColSel), .A1(MAin_c_9), .C0(nRowColSel), + .B0(MAin_c_9), .A0(RowA_9), .M1(Din_c_1), .M0(Din_c_0), .CLK(PHI2_c), + .F0(RA_1_9), .Q0(Bank_0), .F1(RDQML_c), .Q1(Bank_1)); + SLICE_94 SLICE_94( .B1(nRowColSel_N_35), .A1(Ready), .D0(nRowColSel_N_35), + .C0(nRowColSel_N_32), .B0(n1060), .A0(Ready), .F0(RCLK_c_enable_5), + .F1(n2372)); + SLICE_95 SLICE_95( .D1(FS_5), .C1(FS_9), .B1(FS_7), .A1(n2375), .D0(FS_2), + .C0(FS_1), .B0(FS_7), .A0(FS_5), .F0(n15), .F1(n7)); + SLICE_96 SLICE_96( .B1(CASr3), .A1(CBR), .D0(CASr2), .C0(FWEr), .B0(CASr3), + .A0(CBR), .F0(nRCS_N_146), .F1(n2376)); + SLICE_97 SLICE_97( .C1(MAin_c_1), .B1(n2210), .A1(MAin_c_0), .B0(Din_c_2), + .A0(MAin_c_0), .M1(n734), .M0(n735), .CE(RCLK_c_enable_27), .CLK(RCLK_c), + .F0(n2254), .Q0(n734), .F1(n7_adj_5), .Q1(n733)); + SLICE_98 SLICE_98( .B1(nRowColSel), .A1(MAin_c_9), .C0(nRowColSel), + .B0(MAin_c_8), .A0(RowA_8), .M1(nRCS_N_139), .M0(Ready_N_296), + .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(RA_1_8), .Q0(nRCS_N_139), + .F1(RDQMH_c), .Q1(nRCAS_N_165)); + SLICE_99 SLICE_99( .D1(Bank_1), .C1(Bank_4), .B1(MAin_c_3), .A1(MAin_c_7), + .C0(nRowColSel), .B0(MAin_c_7), .A0(RowA_7), .M0(Din_c_0), + .CE(PHI2_N_120_enable_8), .CLK(PHI2_c), .F0(RA_1_7), .Q0(CmdUFMSDI), + .F1(n22)); + SLICE_100 SLICE_100( .D1(Bank_0), .C1(Bank_7), .B1(MAin_c_4), .A1(MAin_c_6), + .C0(nRowColSel), .B0(MAin_c_6), .A0(RowA_6), .M1(Din_c_2), .M0(Din_c_1), + .CE(PHI2_N_120_enable_8), .CLK(PHI2_c), .F0(RA_1_6), .Q0(CmdUFMCLK), + .F1(n2277), .Q1(CmdUFMCS)); + SLICE_101 SLICE_101( .C1(nRowColSel), .B1(MAin_c_0), .A1(RowA_0), + .C0(nRowColSel), .B0(MAin_c_5), .A0(RowA_5), .M1(Din_c_7), .M0(Din_c_6), + .CLK(PHI2_c), .F0(RA_1_5), .Q0(Bank_6), .F1(RA_1_0), .Q1(Bank_7)); + SLICE_102 SLICE_102( .C1(nRowColSel), .B1(MAin_c_1), .A1(RowA_1), + .C0(nRowColSel), .B0(MAin_c_4), .A0(RowA_4), .M1(Din_c_5), .M0(Din_c_4), + .CLK(PHI2_c), .F0(RA_1_4), .Q0(Bank_4), .F1(RA_1_1), .Q1(Bank_5)); + SLICE_103 SLICE_103( .C1(nRowColSel), .B1(MAin_c_2), .A1(RowA_2), + .C0(nRowColSel), .B0(MAin_c_3), .A0(RowA_3), .M1(Din_c_3), .M0(Din_c_2), + .CLK(PHI2_c), .F0(RA_1_3), .Q0(Bank_2), .F1(RA_1_2), .Q1(Bank_3)); + SLICE_104 SLICE_104( .B1(nFWE_c), .A1(nCCAS_c), .C0(nFWE_c), .B0(n26), + .A0(n2369), .M1(MAin_c_7), .M0(MAin_c_6), .LSR(Ready), .CLK(nCRAS_c), + .F0(n2363), .Q0(RowA_6), .F1(n984), .Q1(RowA_7)); + SLICE_105 SLICE_105( .B1(FS_6), .A1(FS_11), .D0(FS_16), .C0(FS_15), + .B0(FS_12), .A0(FS_13), .F0(n12), .F1(n4)); + SLICE_106 SLICE_106( .B1(Din_c_2), .A1(Din_c_0), .B0(Din_c_4), .A0(nFWE_c), + .M1(n736), .M0(n737), .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(n2228), + .Q0(n736), .F1(n2382), .Q1(n735)); + RD_7_ \RD[7]_I ( .PADDI(Dout_c), .PADDT(n984), .PADDO(WRD_7), .RD7(RD[7])); + RD_6_ \RD[6]_I ( .PADDI(Dout_0), .PADDT(n984), .PADDO(WRD_6), .RD6(RD[6])); + RD_5_ \RD[5]_I ( .PADDI(Dout_1), .PADDT(n984), .PADDO(WRD_5), .RD5(RD[5])); + RD_4_ \RD[4]_I ( .PADDI(Dout_2), .PADDT(n984), .PADDO(WRD_4), .RD4(RD[4])); + RD_3_ \RD[3]_I ( .PADDI(Dout_3), .PADDT(n984), .PADDO(WRD_3), .RD3(RD[3])); + RD_2_ \RD[2]_I ( .PADDI(Dout_4), .PADDT(n984), .PADDO(WRD_2), .RD2(RD[2])); + RD_1_ \RD[1]_I ( .PADDI(Dout_5), .PADDT(n984), .PADDO(WRD_1), .RD1(RD[1])); + RD_0_ \RD[0]_I ( .PADDI(Dout_6), .PADDT(n984), .PADDO(WRD_0), .RD0(RD[0])); + Dout_7_ \Dout[7]_I ( .PADDO(Dout_c), .Dout7(Dout[7])); + Dout_6_ \Dout[6]_I ( .PADDO(Dout_0), .Dout6(Dout[6])); + Dout_5_ \Dout[5]_I ( .PADDO(Dout_1), .Dout5(Dout[5])); + Dout_4_ \Dout[4]_I ( .PADDO(Dout_2), .Dout4(Dout[4])); + Dout_3_ \Dout[3]_I ( .PADDO(Dout_3), .Dout3(Dout[3])); + Dout_2_ \Dout[2]_I ( .PADDO(Dout_4), .Dout2(Dout[2])); + Dout_1_ \Dout[1]_I ( .PADDO(Dout_5), .Dout1(Dout[1])); + Dout_0_ \Dout[0]_I ( .PADDO(Dout_6), .Dout0(Dout[0])); + LED LED_I( .PADDO(LED_c), .LED(LED)); + RBA_1_ \RBA[1]_I ( .PADDO(RBA_c_1), .RBA1(RBA[1])); + RBA_0_ \RBA[0]_I ( .PADDO(RBA_c_0), .RBA0(RBA[0])); + RA_11_ \RA[11]_I ( .PADDO(RA_c), .RA11(RA[11])); + RA_10_ \RA[10]_I ( .PADDO(RA_0), .RA10(RA[10])); + RA_9_ \RA[9]_I ( .PADDO(RA_1_9), .RA9(RA[9])); + RA_8_ \RA[8]_I ( .PADDO(RA_1_8), .RA8(RA[8])); + RA_7_ \RA[7]_I ( .PADDO(RA_1_7), .RA7(RA[7])); + RA_6_ \RA[6]_I ( .PADDO(RA_1_6), .RA6(RA[6])); + RA_5_ \RA[5]_I ( .PADDO(RA_1_5), .RA5(RA[5])); + RA_4_ \RA[4]_I ( .PADDO(RA_1_4), .RA4(RA[4])); + RA_3_ \RA[3]_I ( .PADDO(RA_1_3), .RA3(RA[3])); + RA_2_ \RA[2]_I ( .PADDO(RA_1_2), .RA2(RA[2])); + RA_1_ \RA[1]_I ( .PADDO(RA_1_1), .RA1(RA[1])); + RA_0_ \RA[0]_I ( .PADDO(RA_1_0), .RA0(RA[0])); + nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS)); + RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE)); + nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE)); + nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS)); + nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS)); + RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH)); + RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML)); + nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS)); + UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK)); + UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI)); + PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2)); + MAin_9_ \MAin[9]_I ( .PADDI(MAin_c_9), .MAin9(MAin[9])); + MAin_8_ \MAin[8]_I ( .PADDI(MAin_c_8), .MAin8(MAin[8])); + MAin_7_ \MAin[7]_I ( .PADDI(MAin_c_7), .MAin7(MAin[7])); + MAin_6_ \MAin[6]_I ( .PADDI(MAin_c_6), .MAin6(MAin[6])); + MAin_5_ \MAin[5]_I ( .PADDI(MAin_c_5), .MAin5(MAin[5])); + MAin_4_ \MAin[4]_I ( .PADDI(MAin_c_4), .MAin4(MAin[4])); + MAin_3_ \MAin[3]_I ( .PADDI(MAin_c_3), .MAin3(MAin[3])); + MAin_2_ \MAin[2]_I ( .PADDI(MAin_c_2), .MAin2(MAin[2])); + MAin_1_ \MAin[1]_I ( .PADDI(MAin_c_1), .MAin1(MAin[1])); + MAin_0_ \MAin[0]_I ( .PADDI(MAin_c_0), .MAin0(MAin[0])); + CROW_1_ \CROW[1]_I ( .PADDI(CROW_c_1), .CROW1(CROW[1])); + CROW_0_ \CROW[0]_I ( .PADDI(CROW_c_0), .CROW0(CROW[0])); + Din_7_ \Din[7]_I ( .PADDI(Din_c_7), .Din7(Din[7])); + Din_6_ \Din[6]_I ( .PADDI(Din_c_6), .Din6(Din[6])); + Din_5_ \Din[5]_I ( .PADDI(Din_c_5), .Din5(Din[5])); + Din_4_ \Din[4]_I ( .PADDI(Din_c_4), .Din4(Din[4])); + Din_3_ \Din[3]_I ( .PADDI(Din_c_3), .Din3(Din[3])); + Din_2_ \Din[2]_I ( .PADDI(Din_c_2), .Din2(Din[2])); + Din_1_ \Din[1]_I ( .PADDI(Din_c_1), .Din1(Din[1])); + Din_0_ \Din[0]_I ( .PADDI(Din_c_0), .Din0(Din[0])); + nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS)); + nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS)); + nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE)); + RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK)); + UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO)); + VHI VHI_INST( .Z(VCCI)); + PUR PUR_INST( .PUR(VCCI)); + GSR GSR_INST( .GSR(VCCI)); +endmodule + +module SLICE_0 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i14( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i13( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_15( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module vcc ( output PWR1 ); + + VHI INST1( .Z(PWR1)); +endmodule + +module gnd ( output PWR0 ); + + VLO INST1( .Z(PWR0)); +endmodule + +module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'hfaaa; + defparam inst1.INIT1 = 16'hfaaa; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_1 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i12( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_13( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i8( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i7( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_9( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i6( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i5( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_7( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i2( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i1( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_3( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_5 ( input A1, DI1, M0, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, M0_dly; + + vmuxregsre FS_610__i0( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CASr3_384( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 FS_610_add_4_1( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'hF000; + defparam inst1.INIT1 = 16'h0555; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i10( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i9( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_11( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_7 ( input A0, DI0, CLK, FCI, output F0, Q0 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + vmuxregsre FS_610__i17( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu20002 FS_610_add_4_19( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), + .CO1()); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'hfaaa; + defparam inst1.INIT1 = 16'h0000; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i4( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_5( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_9 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i16( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i15( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_17( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_10 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut4 i3_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40003 i1_4_lut_adj_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 ADSubmitted_407( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut4 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40003 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + +module SLICE_15 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40005 i13_2_lut_rep_16_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40006 i1110_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0007 C1Submitted_406( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40005 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40006 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE0F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_16 ( input A0, DI0, M1, CLK, output F0, Q0, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40008 i2045( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CASr2_383( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre CASr_382( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40008 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_19 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40009 i26_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 i2_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdEnable_405( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40009 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0CA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40010 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_20 ( input DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40011 \n2447\001/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdSubmitted_411( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40011 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_24 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40012 i1_2_lut_3_lut_adj_15( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40013 Cmdn8MEGEN_I_93_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Cmdn8MEGEN_410( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40013 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCC5C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_25 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly; + + lut40014 i2_3_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 i2_1_lut_rep_24( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre CBR_390( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre FWEr_389( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + endspecify + +endmodule + +module lut40014 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_26 ( input DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 \n2447\000/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre InitReady_394( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_27 ( input DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 m1_lut( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre LEDEN_419( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_30 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40015 i2010_3_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 i2044( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre RASr2_380( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RASr_379( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40015 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_32 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40016 i2_3_lut_rep_32( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40017 i2_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0007 RA10_400( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40016 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_33 ( input C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40018 i1_2_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40019 RA11_I_54_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0004 RA11_385( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40018 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_35 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40020 i1_2_lut_4_lut_adj_25( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 i29_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre RCKEEN_401( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h20FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_36 ( input D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, Q1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; + + lut40022 i1404_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre PHI2r2_377( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre RCKE_395( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40022 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCFC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_37 ( input DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 \n2447\002/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre Ready_404( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_44 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40023 i1970_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 i1603_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 UFMCLK_416( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut4 i4_4_lut_adj_17( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40024 i1589_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 UFMSDI_417( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40025 i1962_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40026 i2_3_lut_4_lut_adj_11( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre XOR8MEG_408( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40026 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40027 i2_3_lut_rep_18_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40028 n8MEGEN_I_14_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre n8MEGEN_418( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40028 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBF04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40029 nRCAS_I_43_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40030 nRCAS_I_0_452_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0031 nRCAS_398( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3AFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40030 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFE0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0031 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_61 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40032 nRCS_I_31_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 nRCS_I_0_448_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0031 nRCS_396( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1F10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40033 i3_4_lut_adj_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40029 nRCS_N_137_I_0_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0031 nRRAS_397( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_64 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40034 i1477_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40035 nRWE_I_0_455_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0031 nRWE_399( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCFC5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_65 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40034 i786_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40036 i1432_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre nRowColSel_402( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40036 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_66 ( input B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40037 i1_2_lut_adj_23( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 i1439_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0004 S_FSM_i4( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input B0, A0, DI0, LSR, CLK, output F0, Q0 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40038 i1_2_lut_adj_10( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 S_FSM_i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40038 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_68 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; + + lut40034 i4_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 i1989_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0004 S_FSM_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_69 ( input B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40034 i1491_2_lut_rep_30( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 RASr2_I_0_1_lut_rep_25( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre PHI2r3_378( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre S_FSM_i1( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40040 i1_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40041 i1448_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0031 nUFMCS_415( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3FBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module i30_SLICE_71 ( input C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); + wire GNDI, \i30/SLICE_71/i30/SLICE_71_K1_H1 , \i30/SLICE_71/i30/GATE_H0 ; + + lut40042 \i30/SLICE_71_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\i30/SLICE_71/i30/SLICE_71_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40043 \i30/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\i30/SLICE_71/i30/GATE_H0 )); + selmux2 \i30/SLICE_71_K0K1MUX ( .D0(\i30/SLICE_71/i30/GATE_H0 ), + .D1(\i30/SLICE_71/i30/SLICE_71_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40042 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1F1F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40043 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5540) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module SLICE_72 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40044 i1_4_lut_4_lut_adj_12( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 i2_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40044 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40003 i2_3_lut_4_lut_adj_14( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 i4_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40033 i12_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40045 i1_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 RowA_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_75 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40027 i3_4_lut_adj_18( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 i1_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_76 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40012 i1_2_lut_rep_19_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40026 i1_2_lut_rep_15_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0007 RowA_i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40046 i3_4_lut_adj_22( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40046 i3_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40046 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40047 nRCS_N_146_bdd_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40048 i1423_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i13( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i12( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40047 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40016 i11_3_lut_rep_20( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40049 MAin_c_0_bdd_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i11( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i10( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_80 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40034 i3_2_lut_rep_26( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40050 i2005_3_lut_rep_17_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_81 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40034 i1_2_lut_rep_29( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40051 i1427_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i15( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i14( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFCDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_82 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40052 i6_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 i1_2_lut_adj_3( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0007 RowA_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40053 i2_4_lut_adj_21( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40054 i2_3_lut_4_lut_adj_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_84 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40055 i2_3_lut_rep_28( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40024 i1573_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40056 i1969_2_lut_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 i3_4_lut_adj_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_86 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40012 i5_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut4 i1_4_lut_adj_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr3_381( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre PHI2r_376( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_87 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40040 i4_4_lut_adj_16( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40048 i1_2_lut_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 RBA__i2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RBA__i1( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40057 i34_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40053 i1_4_lut_adj_13( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre WRD_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0C5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40058 i2_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40059 i1_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre WRD_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_90 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40049 i1_2_lut_3_lut_4_lut_adj_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40055 i1_2_lut_rep_21_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre WRD_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_91 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40060 i1_2_lut_rep_13_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40061 i1_2_lut_3_lut_4_lut_adj_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 RowA_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40060 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40061 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40062 i2008_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40005 i1_2_lut_rep_22_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre WRD_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_93 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40063 i2001_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i10_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40048 i771_2_lut_rep_23_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40064 i2_3_lut_4_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40065 i2_4_lut_adj_20( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 i6_4_lut_adj_9( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_96 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40034 i1_2_lut_rep_27( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40027 i2_3_lut_4_lut_adj_24( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_97 ( input C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40066 i13_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 i1956_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre IS_FSM__i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC5C5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_98 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40037 i1416_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i9_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre IS_FSM__i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_99 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40052 i8_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 MAin_9__I_0_427_i8_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdUFMSDI_414( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_100 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40052 i1979_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 MAin_9__I_0_427_i7_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdUFMCS_412( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CmdUFMCLK_413( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_101 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40021 MAin_9__I_0_427_i1_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i6_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_102 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40021 MAin_9__I_0_427_i2_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i5_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_103 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40021 MAin_9__I_0_427_i3_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i4_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_104 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40034 i1417_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40067 i1_2_lut_rep_14_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0004 RowA_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_105 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40039 i1_2_lut_adj_19( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40052 i5_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_106 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40039 i1_2_lut_rep_33( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 i1930_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre IS_FSM__i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); + + xo2iobuf Dout_pad_7__713( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), + .PADI(RD7)); + + specify + (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD7) = (0:0:0,0:0:0); + (RD7 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD7, 0:0:0); + $width (negedge RD7, 0:0:0); + endspecify + +endmodule + +module xo2iobuf ( input I, T, output Z, PAD, input PADI ); + + IBPD INST1( .I(PADI), .O(Z)); + OBZPD INST2( .I(I), .T(T), .O(PAD)); +endmodule + +module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); + + xo2iobuf Dout_pad_6__714( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), + .PADI(RD6)); + + specify + (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD6) = (0:0:0,0:0:0); + (RD6 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD6, 0:0:0); + $width (negedge RD6, 0:0:0); + endspecify + +endmodule + +module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); + + xo2iobuf Dout_pad_5__715( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), + .PADI(RD5)); + + specify + (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD5) = (0:0:0,0:0:0); + (RD5 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD5, 0:0:0); + $width (negedge RD5, 0:0:0); + endspecify + +endmodule + +module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); + + xo2iobuf Dout_pad_4__716( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), + .PADI(RD4)); + + specify + (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD4) = (0:0:0,0:0:0); + (RD4 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD4, 0:0:0); + $width (negedge RD4, 0:0:0); + endspecify + +endmodule + +module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); + + xo2iobuf Dout_pad_3__717( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), + .PADI(RD3)); + + specify + (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD3) = (0:0:0,0:0:0); + (RD3 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD3, 0:0:0); + $width (negedge RD3, 0:0:0); + endspecify + +endmodule + +module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); + + xo2iobuf Dout_pad_2__718( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), + .PADI(RD2)); + + specify + (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD2) = (0:0:0,0:0:0); + (RD2 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD2, 0:0:0); + $width (negedge RD2, 0:0:0); + endspecify + +endmodule + +module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); + + xo2iobuf Dout_pad_1__719( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), + .PADI(RD1)); + + specify + (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD1) = (0:0:0,0:0:0); + (RD1 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD1, 0:0:0); + $width (negedge RD1, 0:0:0); + endspecify + +endmodule + +module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); + + xo2iobuf Dout_pad_0__720( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), + .PADI(RD0)); + + specify + (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD0) = (0:0:0,0:0:0); + (RD0 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD0, 0:0:0); + $width (negedge RD0, 0:0:0); + endspecify + +endmodule + +module Dout_7_ ( input PADDO, output Dout7 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_7( .I(PADDO), .T(GNDI), .PAD(Dout7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0068 ( input I, T, output PAD ); + + OBZPD INST5( .I(I), .T(T), .O(PAD)); +endmodule + +module Dout_6_ ( input PADDO, output Dout6 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_6( .I(PADDO), .T(GNDI), .PAD(Dout6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_5_ ( input PADDO, output Dout5 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_5( .I(PADDO), .T(GNDI), .PAD(Dout5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_4_ ( input PADDO, output Dout4 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_4( .I(PADDO), .T(GNDI), .PAD(Dout4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_3_ ( input PADDO, output Dout3 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_3( .I(PADDO), .T(GNDI), .PAD(Dout3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_2_ ( input PADDO, output Dout2 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_2( .I(PADDO), .T(GNDI), .PAD(Dout2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_1_ ( input PADDO, output Dout1 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_1( .I(PADDO), .T(GNDI), .PAD(Dout1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_0_ ( input PADDO, output Dout0 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_0( .I(PADDO), .T(GNDI), .PAD(Dout0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module LED ( input PADDO, output LED ); + wire GNDI; + + xo2iobuf0068 LED_pad( .I(PADDO), .T(GNDI), .PAD(LED)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => LED) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_1_ ( input PADDO, output RBA1 ); + wire GNDI; + + xo2iobuf0068 RBA_pad_1( .I(PADDO), .T(GNDI), .PAD(RBA1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RBA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_0_ ( input PADDO, output RBA0 ); + wire GNDI; + + xo2iobuf0068 RBA_pad_0( .I(PADDO), .T(GNDI), .PAD(RBA0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RBA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_11_ ( input PADDO, output RA11 ); + wire GNDI; + + xo2iobuf0068 RA_pad_11( .I(PADDO), .T(GNDI), .PAD(RA11)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_10_ ( input PADDO, output RA10 ); + wire GNDI; + + xo2iobuf0068 RA_pad_10( .I(PADDO), .T(GNDI), .PAD(RA10)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_9_ ( input PADDO, output RA9 ); + wire GNDI; + + xo2iobuf0068 RA_pad_9( .I(PADDO), .T(GNDI), .PAD(RA9)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_8_ ( input PADDO, output RA8 ); + wire GNDI; + + xo2iobuf0068 RA_pad_8( .I(PADDO), .T(GNDI), .PAD(RA8)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_7_ ( input PADDO, output RA7 ); + wire GNDI; + + xo2iobuf0068 RA_pad_7( .I(PADDO), .T(GNDI), .PAD(RA7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_6_ ( input PADDO, output RA6 ); + wire GNDI; + + xo2iobuf0068 RA_pad_6( .I(PADDO), .T(GNDI), .PAD(RA6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_5_ ( input PADDO, output RA5 ); + wire GNDI; + + xo2iobuf0068 RA_pad_5( .I(PADDO), .T(GNDI), .PAD(RA5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_4_ ( input PADDO, output RA4 ); + wire GNDI; + + xo2iobuf0068 RA_pad_4( .I(PADDO), .T(GNDI), .PAD(RA4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_3_ ( input PADDO, output RA3 ); + wire GNDI; + + xo2iobuf0068 RA_pad_3( .I(PADDO), .T(GNDI), .PAD(RA3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2_ ( input PADDO, output RA2 ); + wire GNDI; + + xo2iobuf0068 RA_pad_2( .I(PADDO), .T(GNDI), .PAD(RA2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_1_ ( input PADDO, output RA1 ); + wire GNDI; + + xo2iobuf0068 RA_pad_1( .I(PADDO), .T(GNDI), .PAD(RA1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_0_ ( input PADDO, output RA0 ); + wire GNDI; + + xo2iobuf0068 RA_pad_0( .I(PADDO), .T(GNDI), .PAD(RA0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCS ( input PADDO, output nRCS ); + wire GNDI; + + xo2iobuf0068 nRCS_pad( .I(PADDO), .T(GNDI), .PAD(nRCS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RCKE ( input PADDO, output RCKE ); + wire GNDI; + + xo2iobuf0068 RCKE_pad( .I(PADDO), .T(GNDI), .PAD(RCKE)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RCKE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRWE ( input PADDO, output nRWE ); + wire GNDI; + + xo2iobuf0068 nRWE_pad( .I(PADDO), .T(GNDI), .PAD(nRWE)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRWE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRRAS ( input PADDO, output nRRAS ); + wire GNDI; + + xo2iobuf0068 nRRAS_pad( .I(PADDO), .T(GNDI), .PAD(nRRAS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRRAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCAS ( input PADDO, output nRCAS ); + wire GNDI; + + xo2iobuf0068 nRCAS_pad( .I(PADDO), .T(GNDI), .PAD(nRCAS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRCAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQMH ( input PADDO, output RDQMH ); + wire GNDI; + + xo2iobuf0068 RDQMH_pad( .I(PADDO), .T(GNDI), .PAD(RDQMH)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RDQMH) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQML ( input PADDO, output RDQML ); + wire GNDI; + + xo2iobuf0068 RDQML_pad( .I(PADDO), .T(GNDI), .PAD(RDQML)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RDQML) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nUFMCS ( input PADDO, output nUFMCS ); + wire GNDI; + + xo2iobuf0068 nUFMCS_pad( .I(PADDO), .T(GNDI), .PAD(nUFMCS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nUFMCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module UFMCLK ( input PADDO, output UFMCLK ); + wire GNDI; + + xo2iobuf0068 UFMCLK_pad( .I(PADDO), .T(GNDI), .PAD(UFMCLK)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => UFMCLK) = (0:0:0,0:0:0); + endspecify + +endmodule + +module UFMSDI ( input PADDO, output UFMSDI ); + wire GNDI; + + xo2iobuf0068 UFMSDI_pad( .I(PADDO), .T(GNDI), .PAD(UFMSDI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => UFMSDI) = (0:0:0,0:0:0); + endspecify + +endmodule + +module PHI2 ( output PADDI, input PHI2 ); + + xo2iobuf0069 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + + specify + (PHI2 => PADDI) = (0:0:0,0:0:0); + $width (posedge PHI2, 0:0:0); + $width (negedge PHI2, 0:0:0); + endspecify + +endmodule + +module xo2iobuf0069 ( output Z, input PAD ); + + IBPD INST1( .I(PAD), .O(Z)); +endmodule + +module MAin_9_ ( output PADDI, input MAin9 ); + + xo2iobuf0069 MAin_pad_9( .Z(PADDI), .PAD(MAin9)); + + specify + (MAin9 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin9, 0:0:0); + $width (negedge MAin9, 0:0:0); + endspecify + +endmodule + +module MAin_8_ ( output PADDI, input MAin8 ); + + xo2iobuf0069 MAin_pad_8( .Z(PADDI), .PAD(MAin8)); + + specify + (MAin8 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin8, 0:0:0); + $width (negedge MAin8, 0:0:0); + endspecify + +endmodule + +module MAin_7_ ( output PADDI, input MAin7 ); + + xo2iobuf0069 MAin_pad_7( .Z(PADDI), .PAD(MAin7)); + + specify + (MAin7 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin7, 0:0:0); + $width (negedge MAin7, 0:0:0); + endspecify + +endmodule + +module MAin_6_ ( output PADDI, input MAin6 ); + + xo2iobuf0069 MAin_pad_6( .Z(PADDI), .PAD(MAin6)); + + specify + (MAin6 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin6, 0:0:0); + $width (negedge MAin6, 0:0:0); + endspecify + +endmodule + +module MAin_5_ ( output PADDI, input MAin5 ); + + xo2iobuf0069 MAin_pad_5( .Z(PADDI), .PAD(MAin5)); + + specify + (MAin5 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin5, 0:0:0); + $width (negedge MAin5, 0:0:0); + endspecify + +endmodule + +module MAin_4_ ( output PADDI, input MAin4 ); + + xo2iobuf0069 MAin_pad_4( .Z(PADDI), .PAD(MAin4)); + + specify + (MAin4 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin4, 0:0:0); + $width (negedge MAin4, 0:0:0); + endspecify + +endmodule + +module MAin_3_ ( output PADDI, input MAin3 ); + + xo2iobuf0069 MAin_pad_3( .Z(PADDI), .PAD(MAin3)); + + specify + (MAin3 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin3, 0:0:0); + $width (negedge MAin3, 0:0:0); + endspecify + +endmodule + +module MAin_2_ ( output PADDI, input MAin2 ); + + xo2iobuf0069 MAin_pad_2( .Z(PADDI), .PAD(MAin2)); + + specify + (MAin2 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin2, 0:0:0); + $width (negedge MAin2, 0:0:0); + endspecify + +endmodule + +module MAin_1_ ( output PADDI, input MAin1 ); + + xo2iobuf0069 MAin_pad_1( .Z(PADDI), .PAD(MAin1)); + + specify + (MAin1 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin1, 0:0:0); + $width (negedge MAin1, 0:0:0); + endspecify + +endmodule + +module MAin_0_ ( output PADDI, input MAin0 ); + + xo2iobuf0069 MAin_pad_0( .Z(PADDI), .PAD(MAin0)); + + specify + (MAin0 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin0, 0:0:0); + $width (negedge MAin0, 0:0:0); + endspecify + +endmodule + +module CROW_1_ ( output PADDI, input CROW1 ); + + xo2iobuf0069 CROW_pad_1( .Z(PADDI), .PAD(CROW1)); + + specify + (CROW1 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW1, 0:0:0); + $width (negedge CROW1, 0:0:0); + endspecify + +endmodule + +module CROW_0_ ( output PADDI, input CROW0 ); + + xo2iobuf0069 CROW_pad_0( .Z(PADDI), .PAD(CROW0)); + + specify + (CROW0 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW0, 0:0:0); + $width (negedge CROW0, 0:0:0); + endspecify + +endmodule + +module Din_7_ ( output PADDI, input Din7 ); + + xo2iobuf0069 Din_pad_7( .Z(PADDI), .PAD(Din7)); + + specify + (Din7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din7, 0:0:0); + $width (negedge Din7, 0:0:0); + endspecify + +endmodule + +module Din_6_ ( output PADDI, input Din6 ); + + xo2iobuf0069 Din_pad_6( .Z(PADDI), .PAD(Din6)); + + specify + (Din6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din6, 0:0:0); + $width (negedge Din6, 0:0:0); + endspecify + +endmodule + +module Din_5_ ( output PADDI, input Din5 ); + + xo2iobuf0069 Din_pad_5( .Z(PADDI), .PAD(Din5)); + + specify + (Din5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din5, 0:0:0); + $width (negedge Din5, 0:0:0); + endspecify + +endmodule + +module Din_4_ ( output PADDI, input Din4 ); + + xo2iobuf0069 Din_pad_4( .Z(PADDI), .PAD(Din4)); + + specify + (Din4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din4, 0:0:0); + $width (negedge Din4, 0:0:0); + endspecify + +endmodule + +module Din_3_ ( output PADDI, input Din3 ); + + xo2iobuf0069 Din_pad_3( .Z(PADDI), .PAD(Din3)); + + specify + (Din3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din3, 0:0:0); + $width (negedge Din3, 0:0:0); + endspecify + +endmodule + +module Din_2_ ( output PADDI, input Din2 ); + + xo2iobuf0069 Din_pad_2( .Z(PADDI), .PAD(Din2)); + + specify + (Din2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din2, 0:0:0); + $width (negedge Din2, 0:0:0); + endspecify + +endmodule + +module Din_1_ ( output PADDI, input Din1 ); + + xo2iobuf0069 Din_pad_1( .Z(PADDI), .PAD(Din1)); + + specify + (Din1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din1, 0:0:0); + $width (negedge Din1, 0:0:0); + endspecify + +endmodule + +module Din_0_ ( output PADDI, input Din0 ); + + xo2iobuf0069 Din_pad_0( .Z(PADDI), .PAD(Din0)); + + specify + (Din0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din0, 0:0:0); + $width (negedge Din0, 0:0:0); + endspecify + +endmodule + +module nCCAS ( output PADDI, input nCCAS ); + + xo2iobuf0069 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + + specify + (nCCAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCCAS, 0:0:0); + $width (negedge nCCAS, 0:0:0); + endspecify + +endmodule + +module nCRAS ( output PADDI, input nCRAS ); + + xo2iobuf0069 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + + specify + (nCRAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCRAS, 0:0:0); + $width (negedge nCRAS, 0:0:0); + endspecify + +endmodule + +module nFWE ( output PADDI, input nFWE ); + + xo2iobuf0069 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + + specify + (nFWE => PADDI) = (0:0:0,0:0:0); + $width (posedge nFWE, 0:0:0); + $width (negedge nFWE, 0:0:0); + endspecify + +endmodule + +module RCLK ( output PADDI, input RCLK ); + + xo2iobuf0069 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + + specify + (RCLK => PADDI) = (0:0:0,0:0:0); + $width (posedge RCLK, 0:0:0); + $width (negedge RCLK, 0:0:0); + endspecify + +endmodule + +module UFMSDO ( output PADDI, input UFMSDO ); + + xo2iobuf0069 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); + + specify + (UFMSDO => PADDI) = (0:0:0,0:0:0); + $width (posedge UFMSDO, 0:0:0); + $width (negedge UFMSDO, 0:0:0); + endspecify + +endmodule diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html new file mode 100644 index 0000000..bf146ce --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_mrp.html @@ -0,0 +1,425 @@ + +Project Summary + + +

+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+
+Design Information
+
+Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
+     RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr
+     RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf D:/O
+     neDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200
+     HC_impl1.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RA
+     M2GS_LCMXO2_1200HC.lpf -c 0 -gui -msgset
+     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-1200HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
+Mapped on:  08/15/23  05:03:26
+
+
+Design Summary
+   Number of registers:    102 out of  1520 (7%)
+      PFU registers:          102 out of  1280 (8%)
+      PIO registers:            0 out of   240 (0%)
+   Number of SLICEs:        75 out of   640 (12%)
+      SLICEs as Logic/ROM:     75 out of   640 (12%)
+      SLICEs as RAM:            0 out of   480 (0%)
+      SLICEs as Carry:         10 out of   640 (2%)
+   Number of LUT4s:        143 out of  1280 (11%)
+      Number used as logic LUTs:        123
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       20
+      Number used as shift registers:     0
+   Number of PIO sites used: 67 + 4(JTAG) out of 80 (89%)
+   Number of block RAMs:  0 out of 7 (0%)
+   Number of GSRs:        0 out of 1 (0%)
+   EFB used :        No
+   JTAG used :       No
+   Readback used :   No
+   Oscillator used : No
+   Startup used :    No
+   POR :             On
+   Bandgap :         On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Number of PLLs:  0 out of 1 (0%)
+   Number of DQSDLLs:  0 out of 2 (0%)
+   Number of CLKDIVC:  0 out of 4 (0%)
+   Number of ECLKSYNCA:  0 out of 4 (0%)
+   Number of ECLKBRIDGECS:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  4
+     Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK )
+
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+   Number of Clock Enables:  14
+     Net RCLK_c_enable_6: 4 loads, 4 LSLICEs
+     Net RCLK_c_enable_5: 2 loads, 2 LSLICEs
+     Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
+     Net RCLK_c_enable_10: 3 loads, 3 LSLICEs
+     Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_16: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_15: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs
+     Net Ready_N_292: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs
+   Number of LSRs:  7
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+     Net nRWE_N_177: 1 loads, 1 LSLICEs
+     Net C1Submitted_N_237: 2 loads, 2 LSLICEs
+     Net n2366: 2 loads, 2 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net Ready: 18 loads
+     Net InitReady: 15 loads
+     Net RASr2: 15 loads
+     Net nRowColSel_N_35: 13 loads
+     Net nRowColSel: 12 loads
+     Net Din_c_4: 10 loads
+     Net MAin_c_1: 10 loads
+     Net Din_c_5: 9 loads
+     Net MAin_c_0: 9 loads
+     Net Din_c_0: 8 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+   No errors or warnings present.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| RD[7]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[6]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[5]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[4]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[3]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[2]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[1]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[0]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[7]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[6]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[5]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[4]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[3]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[2]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[1]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[0]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| LED                 | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RBA[1]              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RBA[0]              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[11]              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[10]              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[9]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[8]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[7]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[6]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[5]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[4]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+| RA[3]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[2]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[1]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[0]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nRCS                | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RCKE                | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nRWE                | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nRRAS               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nRCAS               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RDQMH               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RDQML               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nUFMCS              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| UFMCLK              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| UFMSDI              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| PHI2                | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[9]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[8]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[7]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[6]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[5]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[4]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[3]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[2]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[1]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[0]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| CROW[1]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| CROW[0]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[7]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+| Din[6]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[5]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[4]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[3]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[2]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[1]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[0]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nCCAS               | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nCRAS               | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nFWE                | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RCLK                | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| UFMSDO              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+
+
+Removed logic
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal PHI2_N_120 was merged into signal PHI2_c
+Signal n1407 was merged into signal nRowColSel_N_34
+Signal n2380 was merged into signal Ready
+Signal n1408 was merged into signal nRowColSel_N_35
+Signal nRWE_N_176 was merged into signal nRWE_N_177
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_610_add_4_19/S1 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_19/CO undriven or does not drive anything - clipped.
+Signal FS_610_add_4_1/S0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_1/CI undriven or does not drive anything - clipped.
+Block i2046 was optimized away.
+Block i1118_1_lut was optimized away.
+Block i637_1_lut_rep_31 was optimized away.
+Block i1119_1_lut was optimized away.
+Block nRWE_I_50_1_lut was optimized away.
+Block i1 was optimized away.
+
+     
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 41 MB
+
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+
+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html new file mode 100644 index 0000000..b2d8069 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_pad.html @@ -0,0 +1,374 @@ + +PAD Specification File + + +
PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-1200HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.44
+
+Tue Aug 15 05:03:35 2023
+
+Pinout by Port Name:
++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site  | PG Enable | BC Enable | Properties                                               |
++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
+| CROW[0]   | 10/3     | LVCMOS25_IN   | PL4B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| CROW[1]   | 16/3     | LVCMOS25_IN   | PL8A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[0]    | 3/3      | LVCMOS25_IN   | PL3A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[1]    | 96/0     | LVCMOS25_IN   | PT10B |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[2]    | 88/0     | LVCMOS25_IN   | PT12A |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[3]    | 97/0     | LVCMOS25_IN   | PT10A |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[4]    | 99/0     | LVCMOS25_IN   | PT9A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[5]    | 98/0     | LVCMOS25_IN   | PT9B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[6]    | 2/3      | LVCMOS25_IN   | PL2D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[7]    | 1/3      | LVCMOS25_IN   | PL2C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Dout[0]   | 76/0     | LVCMOS25_OUT  | PT17D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[1]   | 86/0     | LVCMOS25_OUT  | PT12C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[2]   | 87/0     | LVCMOS25_OUT  | PT12B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[3]   | 85/0     | LVCMOS25_OUT  | PT12D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[4]   | 83/0     | LVCMOS25_OUT  | PT15B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[5]   | 84/0     | LVCMOS25_OUT  | PT15A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[6]   | 78/0     | LVCMOS25_OUT  | PT16C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[7]   | 82/0     | LVCMOS25_OUT  | PT15C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| LED       | 34/2     | LVCMOS25_OUT  | PB9A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| MAin[0]   | 14/3     | LVCMOS25_IN   | PL5C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[1]   | 12/3     | LVCMOS25_IN   | PL5A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[2]   | 13/3     | LVCMOS25_IN   | PL5B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[3]   | 21/3     | LVCMOS25_IN   | PL9B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[4]   | 20/3     | LVCMOS25_IN   | PL9A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[5]   | 19/3     | LVCMOS25_IN   | PL8D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[6]   | 24/3     | LVCMOS25_IN   | PL10C |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[7]   | 18/3     | LVCMOS25_IN   | PL8C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[8]   | 25/3     | LVCMOS25_IN   | PL10D |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[9]   | 32/2     | LVCMOS25_IN   | PB6D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| PHI2      | 8/3      | LVCMOS25_IN   | PL3D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| RA[0]     | 66/1     | LVCMOS25_OUT  | PR4D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[10]    | 64/1     | LVCMOS25_OUT  | PR5B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[11]    | 59/1     | LVCMOS25_OUT  | PR8D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[1]     | 67/1     | LVCMOS25_OUT  | PR4C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[2]     | 69/1     | LVCMOS25_OUT  | PR4A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[3]     | 71/1     | LVCMOS25_OUT  | PR3A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[4]     | 74/1     | LVCMOS25_OUT  | PR2B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[5]     | 70/1     | LVCMOS25_OUT  | PR3B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[6]     | 68/1     | LVCMOS25_OUT  | PR4B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[7]     | 75/1     | LVCMOS25_OUT  | PR2A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[8]     | 65/1     | LVCMOS25_OUT  | PR5A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[9]     | 63/1     | LVCMOS25_OUT  | PR5C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RBA[0]    | 58/1     | LVCMOS25_OUT  | PR9A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RBA[1]    | 60/1     | LVCMOS25_OUT  | PR8C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RCKE      | 53/1     | LVCMOS25_OUT  | PR9D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RCLK      | 62/1     | LVCMOS25_IN   | PR5D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| RDQMH     | 51/1     | LVCMOS25_OUT  | PR10D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RDQML     | 48/2     | LVCMOS25_OUT  | PB20C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RD[0]     | 36/2     | LVCMOS25_BIDI | PB11C |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[1]     | 37/2     | LVCMOS25_BIDI | PB11D |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[2]     | 38/2     | LVCMOS25_BIDI | PB11A |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[3]     | 39/2     | LVCMOS25_BIDI | PB11B |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[4]     | 40/2     | LVCMOS25_BIDI | PB15A |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[5]     | 41/2     | LVCMOS25_BIDI | PB15B |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[6]     | 42/2     | LVCMOS25_BIDI | PB18A |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[7]     | 43/2     | LVCMOS25_BIDI | PB18B |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| UFMCLK    | 29/2     | LVCMOS25_OUT  | PB6A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| UFMSDI    | 30/2     | LVCMOS25_OUT  | PB6B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| UFMSDO    | 27/2     | LVCMOS25_IN   | PB4C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| nCCAS     | 9/3      | LVCMOS25_IN   | PL4A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| nCRAS     | 17/3     | LVCMOS25_IN   | PL8B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| nFWE      | 28/2     | LVCMOS25_IN   | PB4D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| nRCAS     | 52/1     | LVCMOS25_OUT  | PR10C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| nRCS      | 57/1     | LVCMOS25_OUT  | PR9B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| nRRAS     | 54/1     | LVCMOS25_OUT  | PR9C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| nRWE      | 49/2     | LVCMOS25_OUT  | PB20D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| nUFMCS    | 47/2     | LVCMOS25_OUT  | PB18D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 2.5V  |
+| 1    | 2.5V  |
+| 2    | 2.5V  |
+| 3    | 2.5V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type   | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| 1/3      | Din[7]                | LOCATED    | LVCMOS25_IN   | PL2C  | L_GPLLT_IN    |           |           |
+| 2/3      | Din[6]                | LOCATED    | LVCMOS25_IN   | PL2D  | L_GPLLC_IN    |           |           |
+| 3/3      | Din[0]                | LOCATED    | LVCMOS25_IN   | PL3A  | PCLKT3_2      |           |           |
+| 4/3      |     unused, PULL:DOWN |            |               | PL3B  | PCLKC3_2      |           |           |
+| 7/3      |     unused, PULL:DOWN |            |               | PL3C  |               |           |           |
+| 8/3      | PHI2                  | LOCATED    | LVCMOS25_IN   | PL3D  |               |           |           |
+| 9/3      | nCCAS                 | LOCATED    | LVCMOS25_IN   | PL4A  |               |           |           |
+| 10/3     | CROW[0]               | LOCATED    | LVCMOS25_IN   | PL4B  |               |           |           |
+| 12/3     | MAin[1]               | LOCATED    | LVCMOS25_IN   | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | MAin[2]               | LOCATED    | LVCMOS25_IN   | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | MAin[0]               | LOCATED    | LVCMOS25_IN   | PL5C  |               |           |           |
+| 15/3     |     unused, PULL:DOWN |            |               | PL5D  |               |           |           |
+| 16/3     | CROW[1]               | LOCATED    | LVCMOS25_IN   | PL8A  |               |           |           |
+| 17/3     | nCRAS                 | LOCATED    | LVCMOS25_IN   | PL8B  |               |           |           |
+| 18/3     | MAin[7]               | LOCATED    | LVCMOS25_IN   | PL8C  |               |           |           |
+| 19/3     | MAin[5]               | LOCATED    | LVCMOS25_IN   | PL8D  |               |           |           |
+| 20/3     | MAin[4]               | LOCATED    | LVCMOS25_IN   | PL9A  | PCLKT3_0      |           |           |
+| 21/3     | MAin[3]               | LOCATED    | LVCMOS25_IN   | PL9B  | PCLKC3_0      |           |           |
+| 24/3     | MAin[6]               | LOCATED    | LVCMOS25_IN   | PL10C |               |           |           |
+| 25/3     | MAin[8]               | LOCATED    | LVCMOS25_IN   | PL10D |               |           |           |
+| 27/2     | UFMSDO                | LOCATED    | LVCMOS25_IN   | PB4C  | CSSPIN        |           |           |
+| 28/2     | nFWE                  | LOCATED    | LVCMOS25_IN   | PB4D  |               |           |           |
+| 29/2     | UFMCLK                | LOCATED    | LVCMOS25_OUT  | PB6A  |               |           |           |
+| 30/2     | UFMSDI                | LOCATED    | LVCMOS25_OUT  | PB6B  |               |           |           |
+| 31/2     |     unused, PULL:DOWN |            |               | PB6C  | MCLK/CCLK     |           |           |
+| 32/2     | MAin[9]               | LOCATED    | LVCMOS25_IN   | PB6D  | SO/SPISO      |           |           |
+| 34/2     | LED                   | LOCATED    | LVCMOS25_OUT  | PB9A  | PCLKT2_0      |           |           |
+| 35/2     |     unused, PULL:DOWN |            |               | PB9B  | PCLKC2_0      |           |           |
+| 36/2     | RD[0]                 | LOCATED    | LVCMOS25_BIDI | PB11C |               |           |           |
+| 37/2     | RD[1]                 | LOCATED    | LVCMOS25_BIDI | PB11D |               |           |           |
+| 38/2     | RD[2]                 | LOCATED    | LVCMOS25_BIDI | PB11A | PCLKT2_1      |           |           |
+| 39/2     | RD[3]                 | LOCATED    | LVCMOS25_BIDI | PB11B | PCLKC2_1      |           |           |
+| 40/2     | RD[4]                 | LOCATED    | LVCMOS25_BIDI | PB15A |               |           |           |
+| 41/2     | RD[5]                 | LOCATED    | LVCMOS25_BIDI | PB15B |               |           |           |
+| 42/2     | RD[6]                 | LOCATED    | LVCMOS25_BIDI | PB18A |               |           |           |
+| 43/2     | RD[7]                 | LOCATED    | LVCMOS25_BIDI | PB18B |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |               | PB18C |               |           |           |
+| 47/2     | nUFMCS                |            | LVCMOS25_OUT  | PB18D |               |           |           |
+| 48/2     | RDQML                 | LOCATED    | LVCMOS25_OUT  | PB20C | SN            |           |           |
+| 49/2     | nRWE                  | LOCATED    | LVCMOS25_OUT  | PB20D | SI/SISPI      |           |           |
+| 51/1     | RDQMH                 | LOCATED    | LVCMOS25_OUT  | PR10D | DQ1           |           |           |
+| 52/1     | nRCAS                 | LOCATED    | LVCMOS25_OUT  | PR10C | DQ1           |           |           |
+| 53/1     | RCKE                  | LOCATED    | LVCMOS25_OUT  | PR9D  | DQ1           |           |           |
+| 54/1     | nRRAS                 | LOCATED    | LVCMOS25_OUT  | PR9C  | DQ1           |           |           |
+| 57/1     | nRCS                  | LOCATED    | LVCMOS25_OUT  | PR9B  | DQ1           |           |           |
+| 58/1     | RBA[0]                | LOCATED    | LVCMOS25_OUT  | PR9A  | DQ1           |           |           |
+| 59/1     | RA[11]                | LOCATED    | LVCMOS25_OUT  | PR8D  | DQ1           |           |           |
+| 60/1     | RBA[1]                | LOCATED    | LVCMOS25_OUT  | PR8C  | DQ1           |           |           |
+| 61/1     |     unused, PULL:DOWN |            |               | PR8A  | DQS1          |           |           |
+| 62/1     | RCLK                  | LOCATED    | LVCMOS25_IN   | PR5D  | PCLKC1_0/DQ0  |           |           |
+| 63/1     | RA[9]                 | LOCATED    | LVCMOS25_OUT  | PR5C  | PCLKT1_0/DQ0  |           |           |
+| 64/1     | RA[10]                | LOCATED    | LVCMOS25_OUT  | PR5B  | DQS0N         |           |           |
+| 65/1     | RA[8]                 | LOCATED    | LVCMOS25_OUT  | PR5A  | DQS0          |           |           |
+| 66/1     | RA[0]                 | LOCATED    | LVCMOS25_OUT  | PR4D  | DQ0           |           |           |
+| 67/1     | RA[1]                 | LOCATED    | LVCMOS25_OUT  | PR4C  | DQ0           |           |           |
+| 68/1     | RA[6]                 | LOCATED    | LVCMOS25_OUT  | PR4B  | DQ0           |           |           |
+| 69/1     | RA[2]                 | LOCATED    | LVCMOS25_OUT  | PR4A  | DQ0           |           |           |
+| 70/1     | RA[5]                 | LOCATED    | LVCMOS25_OUT  | PR3B  | DQ0           |           |           |
+| 71/1     | RA[3]                 | LOCATED    | LVCMOS25_OUT  | PR3A  | DQ0           |           |           |
+| 74/1     | RA[4]                 | LOCATED    | LVCMOS25_OUT  | PR2B  | DQ0           |           |           |
+| 75/1     | RA[7]                 | LOCATED    | LVCMOS25_OUT  | PR2A  | DQ0           |           |           |
+| 76/0     | Dout[0]               | LOCATED    | LVCMOS25_OUT  | PT17D | DONE          |           |           |
+| 77/0     |     unused, PULL:DOWN |            |               | PT17C | INITN         |           |           |
+| 78/0     | Dout[6]               | LOCATED    | LVCMOS25_OUT  | PT16C |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |               | PT15D | PROGRAMN      |           |           |
+| 82/0     | Dout[7]               | LOCATED    | LVCMOS25_OUT  | PT15C | JTAGENB       |           |           |
+| 83/0     | Dout[4]               | LOCATED    | LVCMOS25_OUT  | PT15B |               |           |           |
+| 84/0     | Dout[5]               | LOCATED    | LVCMOS25_OUT  | PT15A |               |           |           |
+| 85/0     | Dout[3]               | LOCATED    | LVCMOS25_OUT  | PT12D | SDA/PCLKC0_0  |           |           |
+| 86/0     | Dout[1]               | LOCATED    | LVCMOS25_OUT  | PT12C | SCL/PCLKT0_0  |           |           |
+| 87/0     | Dout[2]               | LOCATED    | LVCMOS25_OUT  | PT12B | PCLKC0_1      |           |           |
+| 88/0     | Din[2]                | LOCATED    | LVCMOS25_IN   | PT12A | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |               | PT11D | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |               | PT11C | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |               | PT10D | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |               | PT10C | TDO           |           |           |
+| 96/0     | Din[1]                | LOCATED    | LVCMOS25_IN   | PT10B |               |           |           |
+| 97/0     | Din[3]                | LOCATED    | LVCMOS25_IN   | PT10A |               |           |           |
+| 98/0     | Din[5]                | LOCATED    | LVCMOS25_IN   | PT9B  |               |           |           |
+| 99/0     | Din[4]                | LOCATED    | LVCMOS25_IN   | PT9A  |               |           |           |
+| PB4A/2   |     unused, PULL:DOWN |            |               | PB4A  |               |           |           |
+| PB4B/2   |     unused, PULL:DOWN |            |               | PB4B  |               |           |           |
+| PB9C/2   |     unused, PULL:DOWN |            |               | PB9C  |               |           |           |
+| PB9D/2   |     unused, PULL:DOWN |            |               | PB9D  |               |           |           |
+| PB15C/2  |     unused, PULL:DOWN |            |               | PB15C |               |           |           |
+| PB15D/2  |     unused, PULL:DOWN |            |               | PB15D |               |           |           |
+| PB20A/2  |     unused, PULL:DOWN |            |               | PB20A |               |           |           |
+| PB20B/2  |     unused, PULL:DOWN |            |               | PB20B |               |           |           |
+| PL2A/3   |     unused, PULL:DOWN |            |               | PL2A  | L_GPLLT_FB    |           |           |
+| PL2B/3   |     unused, PULL:DOWN |            |               | PL2B  | L_GPLLC_FB    |           |           |
+| PL4C/3   |     unused, PULL:DOWN |            |               | PL4C  |               |           |           |
+| PL4D/3   |     unused, PULL:DOWN |            |               | PL4D  |               |           |           |
+| PL10A/3  |     unused, PULL:DOWN |            |               | PL10A |               |           |           |
+| PL10B/3  |     unused, PULL:DOWN |            |               | PL10B |               |           |           |
+| PR2C/1   |     unused, PULL:DOWN |            |               | PR2C  | DQ0           |           |           |
+| PR2D/1   |     unused, PULL:DOWN |            |               | PR2D  | DQ0           |           |           |
+| PR8B/1   |     unused, PULL:DOWN |            |               | PR8B  | DQS1N         |           |           |
+| PR10A/1  |     unused, PULL:DOWN |            |               | PR10A | DQ1           |           |           |
+| PR10B/1  |     unused, PULL:DOWN |            |               | PR10B | DQ1           |           |           |
+| PT9C/0   |     unused, PULL:DOWN |            |               | PT9C  |               |           |           |
+| PT9D/0   |     unused, PULL:DOWN |            |               | PT9D  |               |           |           |
+| PT11A/0  |     unused, PULL:DOWN |            |               | PT11A |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |               | PT11B |               |           |           |
+| PT16A/0  |     unused, PULL:DOWN |            |               | PT16A |               |           |           |
+| PT16B/0  |     unused, PULL:DOWN |            |               | PT16B |               |           |           |
+| PT16D/0  |     unused, PULL:DOWN |            |               | PT16D |               |           |           |
+| PT17A/0  |     unused, PULL:DOWN |            |               | PT17A |               |           |           |
+| PT17B/0  |     unused, PULL:DOWN |            |               | PT17B |               |           |           |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT11D    | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT11C    | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT10D    | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT10C    | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "10";
+LOCATE  COMP  "CROW[1]"  SITE  "16";
+LOCATE  COMP  "Din[0]"  SITE  "3";
+LOCATE  COMP  "Din[1]"  SITE  "96";
+LOCATE  COMP  "Din[2]"  SITE  "88";
+LOCATE  COMP  "Din[3]"  SITE  "97";
+LOCATE  COMP  "Din[4]"  SITE  "99";
+LOCATE  COMP  "Din[5]"  SITE  "98";
+LOCATE  COMP  "Din[6]"  SITE  "2";
+LOCATE  COMP  "Din[7]"  SITE  "1";
+LOCATE  COMP  "Dout[0]"  SITE  "76";
+LOCATE  COMP  "Dout[1]"  SITE  "86";
+LOCATE  COMP  "Dout[2]"  SITE  "87";
+LOCATE  COMP  "Dout[3]"  SITE  "85";
+LOCATE  COMP  "Dout[4]"  SITE  "83";
+LOCATE  COMP  "Dout[5]"  SITE  "84";
+LOCATE  COMP  "Dout[6]"  SITE  "78";
+LOCATE  COMP  "Dout[7]"  SITE  "82";
+LOCATE  COMP  "LED"  SITE  "34";
+LOCATE  COMP  "MAin[0]"  SITE  "14";
+LOCATE  COMP  "MAin[1]"  SITE  "12";
+LOCATE  COMP  "MAin[2]"  SITE  "13";
+LOCATE  COMP  "MAin[3]"  SITE  "21";
+LOCATE  COMP  "MAin[4]"  SITE  "20";
+LOCATE  COMP  "MAin[5]"  SITE  "19";
+LOCATE  COMP  "MAin[6]"  SITE  "24";
+LOCATE  COMP  "MAin[7]"  SITE  "18";
+LOCATE  COMP  "MAin[8]"  SITE  "25";
+LOCATE  COMP  "MAin[9]"  SITE  "32";
+LOCATE  COMP  "PHI2"  SITE  "8";
+LOCATE  COMP  "RA[0]"  SITE  "66";
+LOCATE  COMP  "RA[10]"  SITE  "64";
+LOCATE  COMP  "RA[11]"  SITE  "59";
+LOCATE  COMP  "RA[1]"  SITE  "67";
+LOCATE  COMP  "RA[2]"  SITE  "69";
+LOCATE  COMP  "RA[3]"  SITE  "71";
+LOCATE  COMP  "RA[4]"  SITE  "74";
+LOCATE  COMP  "RA[5]"  SITE  "70";
+LOCATE  COMP  "RA[6]"  SITE  "68";
+LOCATE  COMP  "RA[7]"  SITE  "75";
+LOCATE  COMP  "RA[8]"  SITE  "65";
+LOCATE  COMP  "RA[9]"  SITE  "63";
+LOCATE  COMP  "RBA[0]"  SITE  "58";
+LOCATE  COMP  "RBA[1]"  SITE  "60";
+LOCATE  COMP  "RCKE"  SITE  "53";
+LOCATE  COMP  "RCLK"  SITE  "62";
+LOCATE  COMP  "RDQMH"  SITE  "51";
+LOCATE  COMP  "RDQML"  SITE  "48";
+LOCATE  COMP  "RD[0]"  SITE  "36";
+LOCATE  COMP  "RD[1]"  SITE  "37";
+LOCATE  COMP  "RD[2]"  SITE  "38";
+LOCATE  COMP  "RD[3]"  SITE  "39";
+LOCATE  COMP  "RD[4]"  SITE  "40";
+LOCATE  COMP  "RD[5]"  SITE  "41";
+LOCATE  COMP  "RD[6]"  SITE  "42";
+LOCATE  COMP  "RD[7]"  SITE  "43";
+LOCATE  COMP  "UFMCLK"  SITE  "29";
+LOCATE  COMP  "UFMSDI"  SITE  "30";
+LOCATE  COMP  "UFMSDO"  SITE  "27";
+LOCATE  COMP  "nCCAS"  SITE  "9";
+LOCATE  COMP  "nCRAS"  SITE  "17";
+LOCATE  COMP  "nFWE"  SITE  "28";
+LOCATE  COMP  "nRCAS"  SITE  "52";
+LOCATE  COMP  "nRCS"  SITE  "57";
+LOCATE  COMP  "nRRAS"  SITE  "54";
+LOCATE  COMP  "nRWE"  SITE  "49";
+LOCATE  COMP  "nUFMCS"  SITE  "47";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:38 2023
+
+
+
+
+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+
+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html new file mode 100644 index 0000000..2db9546 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_par.html @@ -0,0 +1,397 @@ + +Place & Route Report + + +
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:31 2023
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
+RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
+RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset
+D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
+
+
+Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            -4.650       391939       0.304        0            08           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 8 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd"
+Tue Aug 15 05:03:31 2023
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
+Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)   67+4(JTAG)/108     66% used
+                  67+4(JTAG)/80      89% bonded
+
+   SLICE             75/640          11% used
+
+
+
+Number of Signals: 285
+Number of Connections: 674
+WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors.
+
+Pin Constraint Summary:
+   66 out of 67 pins locked (98% locked).
+
+The following 2 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 40)
+    PHI2_c (driver: PHI2, clk load #: 13)
+
+WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0)
+
+WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+No signal is selected as Global Set/Reset.
+.
+Starting Placer Phase 0.
+..........
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+...................
+Placer score = 143529.
+Finished Placer Phase 1.  REAL time: 4 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  143450
+Finished Placer Phase 2.  REAL time: 4 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 0 out of 8 (0%)
+  General PIO: 3 out of 108 (2%)
+  PLL        : 0 out of 1 (0%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 13
+  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 7, ce load = 0, sr load = 0
+
+  PRIMARY  : 2 out of 8 (25%)
+  SECONDARY: 1 out of 8 (12%)
+
+Edge Clocks:
+  No edge clock selected.
+
+
+
+
+I/O Usage Summary (final):
+   67 + 4(JTAG) out of 108 (65.7%) PIO sites used.
+   67 + 4(JTAG) out of 80 (88.8%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 13 / 19 ( 68%) | 2.5V       | -         |
+| 1        | 20 / 21 ( 95%) | 2.5V       | -         |
+| 2        | 17 / 20 ( 85%) | 2.5V       | -         |
+| 3        | 17 / 20 ( 85%) | 2.5V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 4 secs 
+
+Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
+
+0 connections routed; 674 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=6 clock_loads=4
+
+Completed router resource preassignment. Real time: 7 secs 
+
+Start NBR router at 05:03:38 08/15/23
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 05:03:38 08/15/23
+
+Start NBR section for initial routing at 05:03:38 08/15/23
+Level 1, iteration 1
+2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -5.186ns/-468.418ns; real time: 7 secs 
+Level 2, iteration 1
+11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-377.051ns; real time: 8 secs 
+Level 3, iteration 1
+20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-373.496ns; real time: 8 secs 
+Level 4, iteration 1
+11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-386.255ns; real time: 8 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 05:03:39 08/15/23
+Level 1, iteration 1
+7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-379.537ns; real time: 8 secs 
+Level 4, iteration 1
+9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-380.800ns; real time: 8 secs 
+Level 4, iteration 2
+6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-390.587ns; real time: 8 secs 
+Level 4, iteration 3
+6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 8 secs 
+Level 4, iteration 4
+6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-384.719ns; real time: 8 secs 
+Level 4, iteration 5
+4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 8 secs 
+Level 4, iteration 6
+3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.014ns; real time: 8 secs 
+Level 4, iteration 7
+3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 8 secs 
+Level 4, iteration 8
+3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.875ns; real time: 8 secs 
+Level 4, iteration 9
+2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 8 secs 
+Level 4, iteration 10
+3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-409.289ns; real time: 8 secs 
+Level 4, iteration 11
+3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 8 secs 
+Level 4, iteration 12
+3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.364ns/-393.036ns; real time: 8 secs 
+Level 4, iteration 13
+2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 8 secs 
+Level 4, iteration 14
+2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.574ns/-404.327ns; real time: 8 secs 
+Level 4, iteration 15
+2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Level 4, iteration 16
+3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Level 4, iteration 17
+2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 8 secs 
+Level 4, iteration 18
+1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.574ns/-404.669ns; real time: 8 secs 
+Level 4, iteration 19
+1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Level 4, iteration 20
+1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Level 4, iteration 21
+1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Level 4, iteration 22
+1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.534ns; real time: 8 secs 
+Level 4, iteration 23
+1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 8 secs 
+Level 4, iteration 24
+1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.277ns; real time: 8 secs 
+Level 4, iteration 25
+0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs 
+
+Start NBR section for performance tuning (iteration 1) at 05:03:39 08/15/23
+Level 4, iteration 1
+1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-405.830ns; real time: 8 secs 
+Level 4, iteration 2
+0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs 
+
+Start NBR section for re-routing at 05:03:39 08/15/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.650ns/-411.953ns; real time: 8 secs 
+
+Start NBR section for post-routing at 05:03:39 08/15/23
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 254 (37.69%)
+  Estimated worst slack<setup> : -4.650ns
+  Timing score<setup> : 391939
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=6 clock_loads=4
+
+Total CPU time 7 secs 
+Total REAL time: 8 secs 
+Completely routed.
+End of route.  674 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 391939 
+
+Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = -4.650
+PAR_SUMMARY::Timing score<setup/<ns>> = 391.939
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.304
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 8 secs 
+Total REAL time to completion: 8 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+
+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+
+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html new file mode 100644 index 0000000..affe710 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_summary.html @@ -0,0 +1,83 @@ + +Project Summary + + +

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
RAM2GS_LCMXO2_1200HC project summary
Module Name:RAM2GS_LCMXO2_1200HCSynthesis:Lattice LSE
Implementation Name:impl1Strategy Name:Strategy1
Last Process:JEDEC FileState:Passed
Target Device:LCMXO2-1200HC-4TG100CDevice Family:MachXO2
Device Type:LCMXO2-1200HCPackage Type:TQFP100
Performance grade:4Operating conditions:COM
Logic preference file:RAM2GS_LCMXO2_1200HC.lpf
Physical Preference file:impl1/RAM2GS_LCMXO2_1200HC_impl1.prf
Product Version:3.12.1.454Patch Version:
Updated:2023/08/15 05:03:45
Implementation Location:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1
Project File:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf

+

+

+

+

+

+
+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html new file mode 100644 index 0000000..2254cfa --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_tw1.html @@ -0,0 +1,430 @@ + +Lattice Map TRACE Report + + +
Map TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:28 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_1200hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
+Device,speed:    LCMXO2-1200HC,4
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (245 errors)
    • 
+                459 items scored, 245 timing errors detected.
+Warning: 139.762MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (104 errors)
    • 
+                113 items scored, 104 timing errors detected.
+Warning:  50.592MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+            459 items scored, 245 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 3.815ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i13  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               6.873ns  (28.2% logic, 71.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      6.873ns physical path delay SLICE_0 to SLICE_57 exceeds
+      3.340ns delay constraint less
+      0.282ns CE_SET requirement (totaling 3.058ns) by 3.815ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452    SLICE_0.CLK to     SLICE_0.Q0 SLICE_0 (from RCLK_c)
+ROUTE         3   e 1.234     SLICE_0.Q0 to    SLICE_85.B0 FS_13
+CTOF_DEL    ---     0.495    SLICE_85.B0 to    SLICE_85.F0 SLICE_85
+ROUTE         5   e 1.234    SLICE_85.F0 to    SLICE_57.A1 n10
+CTOF_DEL    ---     0.495    SLICE_57.A1 to    SLICE_57.F1 SLICE_57
+ROUTE         2   e 1.234    SLICE_57.F1 to    SLICE_84.A0 n2367
+CTOF_DEL    ---     0.495    SLICE_84.A0 to    SLICE_84.F0 SLICE_84
+ROUTE         1   e 1.234    SLICE_84.F0 to    SLICE_57.CE RCLK_c_enable_15 (to RCLK_c)
+                  --------
+                    6.873   (28.2% logic, 71.8% route), 4 logic levels.
+
+Warning: 139.762MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+            113 items scored, 104 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 4.837ns (weighted slack = -9.674ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               9.577ns  (30.6% logic, 69.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.577ns physical path delay SLICE_101 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.307ns CE_SET requirement (totaling 4.740ns) by 4.837ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452  SLICE_101.CLK to   SLICE_101.Q1 SLICE_101 (from PHI2_c)
+ROUTE         1   e 1.234   SLICE_101.Q1 to   SLICE_100.C1 Bank_7
+CTOF_DEL    ---     0.495   SLICE_100.C1 to   SLICE_100.F1 SLICE_100
+ROUTE         1   e 1.234   SLICE_100.F1 to    SLICE_74.B1 n2277
+CTOF_DEL    ---     0.495    SLICE_74.B1 to    SLICE_74.F1 SLICE_74
+ROUTE         8   e 1.234    SLICE_74.F1 to    SLICE_91.B1 n26
+CTOF_DEL    ---     0.495    SLICE_91.B1 to    SLICE_91.F1 SLICE_91
+ROUTE         1   e 1.234    SLICE_91.F1 to    SLICE_88.D0 n2362
+CTOF_DEL    ---     0.495    SLICE_88.D0 to    SLICE_88.F0 SLICE_88
+ROUTE         3   e 0.480    SLICE_88.F0 to    SLICE_88.C1 C1Submitted_N_237
+CTOF_DEL    ---     0.495    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 1.234    SLICE_88.F1 to    SLICE_19.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    9.577   (30.6% logic, 69.4% route), 6 logic levels.
+
+Warning:  50.592MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 299.401000 MHz ; |  299.401 MHz|  139.762 MHz|   4 *
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |   99.079 MHz|   50.592 MHz|   6 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+2 preferences(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+n26                                     |       8|      78|     22.35%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 349  Score: 848079
+Cumulative negative slack: 584487
+
+Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:28 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_1200hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
+Device,speed:    LCMXO2-1200HC,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (0 errors)
    •             459 items scored, 0 timing errors detected.
+
+
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+            459 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.351ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.332ns  (40.1% logic, 59.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.332ns physical path delay SLICE_106 to SLICE_106 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
+
+ Physical Path Details:
+
+      Data path SLICE_106 to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133  SLICE_106.CLK to   SLICE_106.Q0 SLICE_106 (from RCLK_c)
+ROUTE         1   e 0.199   SLICE_106.Q0 to   SLICE_106.M1 n736 (to RCLK_c)
+                  --------
+                    0.332   (40.1% logic, 59.9% route), 1 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.447ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.434ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_15.CLK to    SLICE_15.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2   e 0.199    SLICE_15.Q0 to    SLICE_15.C0 C1Submitted
+CTOF_DEL    ---     0.101    SLICE_15.C0 to    SLICE_15.F0 SLICE_15
+ROUTE         1   e 0.001    SLICE_15.F0 to   SLICE_15.DI0 n1398 (to PHI2_c)
+                  --------
+                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 299.401000 MHz ; |     0.000 ns|     0.351 ns|   1  
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |     0.000 ns|     0.447 ns|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 349 (setup), 0 (hold)
+Score: 848079 (setup), 0 (hold)
+Cumulative negative slack: 584487 (584487+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html new file mode 100644 index 0000000..eab0fb8 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_twr.html @@ -0,0 +1,2244 @@ + +Lattice TRACE Report + + +
    Place & Route TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:40 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_1200hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
+Device,speed:    LCMXO2-1200HC,4
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (247 errors)
    • 
+                459 items scored, 247 timing errors detected.
+Warning: 174.216MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (88 errors)
    • 
+                113 items scored, 88 timing errors detected.
+Warning:  67.833MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+            459 items scored, 247 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 2.400ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               5.574ns  (43.6% logic, 56.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.574ns physical path delay SLICE_1 to SLICE_44 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.400ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C15C.CLK to      R7C15C.Q1 SLICE_1 (from RCLK_c)
+ROUTE         5     1.440      R7C15C.Q1 to      R8C15A.B0 FS_12
+CTOF_DEL    ---     0.495      R8C15A.B0 to      R8C15A.F0 SLICE_105
+ROUTE         1     0.626      R8C15A.F0 to      R8C15D.D1 n12
+CTOF_DEL    ---     0.495      R8C15D.D1 to      R8C15D.F1 SLICE_82
+ROUTE         3     0.640      R8C15D.F1 to      R8C16B.D1 n13_adj_6
+CTOF_DEL    ---     0.495      R8C16B.D1 to      R8C16B.F1 SLICE_44
+ROUTE         1     0.436      R8C16B.F1 to      R8C16B.C0 n1893
+CTOF_DEL    ---     0.495      R8C16B.C0 to      R8C16B.F0 SLICE_44
+ROUTE         1     0.000      R8C16B.F0 to     R8C16B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    5.574   (43.6% logic, 56.4% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C15C.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R8C16B.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.383ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        InitReady_394  (to RCLK_c +)
+
+   Delay:               5.441ns  (35.6% logic, 64.4% route), 4 logic levels.
+
+ Constraint Details:
+
+      5.441ns physical path delay SLICE_1 to SLICE_26 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 3.058ns) by 2.383ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C15C.CLK to      R7C15C.Q1 SLICE_1 (from RCLK_c)
+ROUTE         5     1.440      R7C15C.Q1 to      R8C15A.B0 FS_12
+CTOF_DEL    ---     0.495      R8C15A.B0 to      R8C15A.F0 SLICE_105
+ROUTE         1     0.626      R8C15A.F0 to      R8C15D.D1 n12
+CTOF_DEL    ---     0.495      R8C15D.D1 to      R8C15D.F1 SLICE_82
+ROUTE         3     0.453      R8C15D.F1 to      R8C15D.C0 n13_adj_6
+CTOF_DEL    ---     0.495      R8C15D.C0 to      R8C15D.F0 SLICE_82
+ROUTE         1     0.985      R8C15D.F0 to      R8C13D.CE RCLK_c_enable_28 (to RCLK_c)
+                  --------
+                    5.441   (35.6% logic, 64.4% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C15C.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R8C13D.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.217ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i16  (from RCLK_c +)
+   Destination:    FF         Data in        nUFMCS_415  (to RCLK_c +)
+
+   Delay:               5.391ns  (45.1% logic, 54.9% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.391ns physical path delay SLICE_9 to SLICE_70 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.217ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q1 SLICE_9 (from RCLK_c)
+ROUTE         3     1.017      R7C16A.Q1 to      R7C16D.B0 FS_16
+CTOF_DEL    ---     0.495      R7C16D.B0 to      R7C16D.F0 SLICE_85
+ROUTE         5     0.340      R7C16D.F0 to      R7C17A.D1 n10
+CTOF_DEL    ---     0.495      R7C17A.D1 to      R7C17A.F1 SLICE_76
+ROUTE         2     0.635      R7C17A.F1 to      R7C17D.D1 n2368
+CTOF_DEL    ---     0.495      R7C17D.D1 to      R7C17D.F1 SLICE_70
+ROUTE         1     0.967      R7C17D.F1 to      R7C17D.A0 n64
+CTOF_DEL    ---     0.495      R7C17D.A0 to      R7C17D.F0 SLICE_70
+ROUTE         1     0.000      R7C17D.F0 to     R7C17D.DI0 nUFMCS_N_199 (to RCLK_c)
+                  --------
+                    5.391   (45.1% logic, 54.9% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C17D.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.180ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        nUFMCS_415  (to RCLK_c +)
+
+   Delay:               5.354ns  (45.4% logic, 54.6% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.354ns physical path delay SLICE_9 to SLICE_70 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.180ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q0 SLICE_9 (from RCLK_c)
+ROUTE         3     0.980      R7C16A.Q0 to      R7C16D.A0 FS_15
+CTOF_DEL    ---     0.495      R7C16D.A0 to      R7C16D.F0 SLICE_85
+ROUTE         5     0.340      R7C16D.F0 to      R7C17A.D1 n10
+CTOF_DEL    ---     0.495      R7C17A.D1 to      R7C17A.F1 SLICE_76
+ROUTE         2     0.635      R7C17A.F1 to      R7C17D.D1 n2368
+CTOF_DEL    ---     0.495      R7C17D.D1 to      R7C17D.F1 SLICE_70
+ROUTE         1     0.967      R7C17D.F1 to      R7C17D.A0 n64
+CTOF_DEL    ---     0.495      R7C17D.A0 to      R7C17D.F0 SLICE_70
+ROUTE         1     0.000      R7C17D.F0 to     R7C17D.DI0 nUFMCS_N_199 (to RCLK_c)
+                  --------
+                    5.354   (45.4% logic, 54.6% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C17D.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.166ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i16  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               5.340ns  (45.5% logic, 54.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.340ns physical path delay SLICE_9 to SLICE_44 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.166ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q1 SLICE_9 (from RCLK_c)
+ROUTE         3     1.206      R7C16A.Q1 to      R8C15A.C0 FS_16
+CTOF_DEL    ---     0.495      R8C15A.C0 to      R8C15A.F0 SLICE_105
+ROUTE         1     0.626      R8C15A.F0 to      R8C15D.D1 n12
+CTOF_DEL    ---     0.495      R8C15D.D1 to      R8C15D.F1 SLICE_82
+ROUTE         3     0.640      R8C15D.F1 to      R8C16B.D1 n13_adj_6
+CTOF_DEL    ---     0.495      R8C16B.D1 to      R8C16B.F1 SLICE_44
+ROUTE         1     0.436      R8C16B.F1 to      R8C16B.C0 n1893
+CTOF_DEL    ---     0.495      R8C16B.C0 to      R8C16B.F0 SLICE_44
+ROUTE         1     0.000      R8C16B.F0 to     R8C16B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    5.340   (45.5% logic, 54.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R8C16B.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.158ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i16  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               5.332ns  (45.6% logic, 54.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.332ns physical path delay SLICE_9 to SLICE_44 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.158ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q1 SLICE_9 (from RCLK_c)
+ROUTE         3     1.017      R7C16A.Q1 to      R7C16D.B0 FS_16
+CTOF_DEL    ---     0.495      R7C16D.B0 to      R7C16D.F0 SLICE_85
+ROUTE         5     0.461      R7C16D.F0 to      R7C16D.C1 n10
+CTOF_DEL    ---     0.495      R7C16D.C1 to      R7C16D.F1 SLICE_85
+ROUTE         1     0.986      R7C16D.F1 to      R8C16B.A1 n2267
+CTOF_DEL    ---     0.495      R8C16B.A1 to      R8C16B.F1 SLICE_44
+ROUTE         1     0.436      R8C16B.F1 to      R8C16B.C0 n1893
+CTOF_DEL    ---     0.495      R8C16B.C0 to      R8C16B.F0 SLICE_44
+ROUTE         1     0.000      R8C16B.F0 to     R8C16B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    5.332   (45.6% logic, 54.4% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R8C16B.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.149ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i16  (from RCLK_c +)
+   Destination:    FF         Data in        InitReady_394  (to RCLK_c +)
+
+   Delay:               5.207ns  (37.2% logic, 62.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      5.207ns physical path delay SLICE_9 to SLICE_26 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 3.058ns) by 2.149ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q1 SLICE_9 (from RCLK_c)
+ROUTE         3     1.206      R7C16A.Q1 to      R8C15A.C0 FS_16
+CTOF_DEL    ---     0.495      R8C15A.C0 to      R8C15A.F0 SLICE_105
+ROUTE         1     0.626      R8C15A.F0 to      R8C15D.D1 n12
+CTOF_DEL    ---     0.495      R8C15D.D1 to      R8C15D.F1 SLICE_82
+ROUTE         3     0.453      R8C15D.F1 to      R8C15D.C0 n13_adj_6
+CTOF_DEL    ---     0.495      R8C15D.C0 to      R8C15D.F0 SLICE_82
+ROUTE         1     0.985      R8C15D.F0 to      R8C13D.CE RCLK_c_enable_28 (to RCLK_c)
+                  --------
+                    5.207   (37.2% logic, 62.8% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R8C13D.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.131ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i7  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               5.189ns  (37.3% logic, 62.7% route), 4 logic levels.
+
+ Constraint Details:
+
+      5.189ns physical path delay SLICE_2 to SLICE_57 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 3.058ns) by 2.131ns
+
+ Physical Path Details:
+
+      Data path SLICE_2 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C15A.CLK to      R7C15A.Q0 SLICE_2 (from RCLK_c)
+ROUTE         3     1.086      R7C15A.Q0 to      R8C14D.D0 FS_7
+CTOF_DEL    ---     0.495      R8C14D.D0 to      R8C14D.F0 SLICE_95
+ROUTE         1     0.747      R8C14D.F0 to      R8C14A.C0 n15
+CTOF_DEL    ---     0.495      R8C14A.C0 to      R8C14A.F0 SLICE_86
+ROUTE         1     0.766      R8C14A.F0 to      R8C16C.C0 n4_adj_7
+CTOF_DEL    ---     0.495      R8C16C.C0 to      R8C16C.F0 SLICE_84
+ROUTE         1     0.653      R8C16C.F0 to      R8C16A.CE RCLK_c_enable_15 (to RCLK_c)
+                  --------
+                    5.189   (37.3% logic, 62.7% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C15A.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R8C16A.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.121ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               5.295ns  (45.9% logic, 54.1% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.295ns physical path delay SLICE_9 to SLICE_44 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.121ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C16A.CLK to      R7C16A.Q0 SLICE_9 (from RCLK_c)
+ROUTE         3     0.980      R7C16A.Q0 to      R7C16D.A0 FS_15
+CTOF_DEL    ---     0.495      R7C16D.A0 to      R7C16D.F0 SLICE_85
+ROUTE         5     0.461      R7C16D.F0 to      R7C16D.C1 n10
+CTOF_DEL    ---     0.495      R7C16D.C1 to      R7C16D.F1 SLICE_85
+ROUTE         1     0.986      R7C16D.F1 to      R8C16B.A1 n2267
+CTOF_DEL    ---     0.495      R8C16B.A1 to      R8C16B.F1 SLICE_44
+ROUTE         1     0.436      R8C16B.F1 to      R8C16B.C0 n1893
+CTOF_DEL    ---     0.495      R8C16B.C0 to      R8C16B.F0 SLICE_44
+ROUTE         1     0.000      R8C16B.F0 to     R8C16B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    5.295   (45.9% logic, 54.1% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C16A.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R8C16B.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.087ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI_417  (to RCLK_c +)
+
+   Delay:               5.261ns  (46.2% logic, 53.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.261ns physical path delay SLICE_1 to SLICE_45 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.087ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_45:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R7C15C.CLK to      R7C15C.Q1 SLICE_1 (from RCLK_c)
+ROUTE         5     0.786      R7C15C.Q1 to      R8C15C.C1 FS_12
+CTOF_DEL    ---     0.495      R8C15C.C1 to      R8C15C.F1 SLICE_80
+ROUTE         3     0.640      R8C15C.F1 to      R8C14D.D1 n2375
+CTOF_DEL    ---     0.495      R8C14D.D1 to      R8C14D.F1 SLICE_95
+ROUTE         1     0.967      R8C14D.F1 to      R8C14C.A1 n7
+CTOF_DEL    ---     0.495      R8C14C.A1 to      R8C14C.F1 SLICE_45
+ROUTE         1     0.436      R8C14C.F1 to      R8C14C.C0 n2174
+CTOF_DEL    ---     0.495      R8C14C.C0 to      R8C14C.F0 SLICE_45
+ROUTE         1     0.000      R8C14C.F0 to     R8C14C.DI0 UFMSDI_N_231 (to RCLK_c)
+                  --------
+                    5.261   (46.2% logic, 53.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R7C15C.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_45:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     4.865       62.PADDI to     R8C14C.CLK RCLK_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning: 174.216MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+            113 items scored, 88 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 2.325ns (weighted slack = -4.650ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               7.065ns  (41.4% logic, 58.6% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.065ns physical path delay SLICE_101 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 2.325ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16C.CLK to      R9C16C.Q0 SLICE_101 (from PHI2_c)
+ROUTE         1     0.986      R9C16C.Q0 to      R9C14A.A0 Bank_6
+CTOF_DEL    ---     0.495      R9C14A.A0 to      R9C14A.F0 SLICE_68
+ROUTE         1     0.766      R9C14A.F0 to      R9C15B.C1 n2287
+CTOF_DEL    ---     0.495      R9C15B.C1 to      R9C15B.F1 SLICE_74
+ROUTE         8     0.662      R9C15B.F1 to      R9C14D.D1 n26
+CTOF_DEL    ---     0.495      R9C14D.D1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     0.445      R9C14C.F0 to      R9C14C.C1 C1Submitted_N_237
+CTOF_DEL    ---     0.495      R9C14C.C1 to      R9C14C.F1 SLICE_88
+ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    7.065   (41.4% logic, 58.6% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16C.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.287ns (weighted slack = -4.574ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i1  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               7.027ns  (41.7% logic, 58.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.027ns physical path delay SLICE_93 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 2.287ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16A.CLK to      R9C16A.Q1 SLICE_93 (from PHI2_c)
+ROUTE         1     0.744      R9C16A.Q1 to      R9C15C.C1 Bank_1
+CTOF_DEL    ---     0.495      R9C15C.C1 to      R9C15C.F1 SLICE_99
+ROUTE         2     0.635      R9C15C.F1 to      R9C15D.D1 n22
+CTOF_DEL    ---     0.495      R9C15D.D1 to      R9C15D.F1 SLICE_79
+ROUTE         7     0.997      R9C15D.F1 to      R9C14D.A1 n2369
+CTOF_DEL    ---     0.495      R9C14D.A1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     0.445      R9C14C.F0 to      R9C14C.C1 C1Submitted_N_237
+CTOF_DEL    ---     0.495      R9C14C.C1 to      R9C14C.F1 SLICE_88
+ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    7.027   (41.7% logic, 58.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16A.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.166ns (weighted slack = -4.332ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.906ns  (42.4% logic, 57.6% route), 6 logic levels.
+
+ Constraint Details:
+
+      6.906ns physical path delay SLICE_102 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 2.166ns
+
+ Physical Path Details:
+
+      Data path SLICE_102 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R8C15B.CLK to      R8C15B.Q0 SLICE_102 (from PHI2_c)
+ROUTE         1     0.623      R8C15B.Q0 to      R9C15C.D1 Bank_4
+CTOF_DEL    ---     0.495      R9C15C.D1 to      R9C15C.F1 SLICE_99
+ROUTE         2     0.635      R9C15C.F1 to      R9C15D.D1 n22
+CTOF_DEL    ---     0.495      R9C15D.D1 to      R9C15D.F1 SLICE_79
+ROUTE         7     0.997      R9C15D.F1 to      R9C14D.A1 n2369
+CTOF_DEL    ---     0.495      R9C14D.A1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     0.445      R9C14C.F0 to      R9C14C.C1 C1Submitted_N_237
+CTOF_DEL    ---     0.495      R9C14C.C1 to      R9C14C.F1 SLICE_88
+ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.906   (42.4% logic, 57.6% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_102:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R8C15B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.984ns (weighted slack = -3.968ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.724ns  (43.5% logic, 56.5% route), 6 logic levels.
+
+ Constraint Details:
+
+      6.724ns physical path delay SLICE_103 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 1.984ns
+
+ Physical Path Details:
+
+      Data path SLICE_103 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16D.CLK to      R9C16D.Q1 SLICE_103 (from PHI2_c)
+ROUTE         1     0.645      R9C16D.Q1 to      R9C14A.D0 Bank_3
+CTOF_DEL    ---     0.495      R9C14A.D0 to      R9C14A.F0 SLICE_68
+ROUTE         1     0.766      R9C14A.F0 to      R9C15B.C1 n2287
+CTOF_DEL    ---     0.495      R9C15B.C1 to      R9C15B.F1 SLICE_74
+ROUTE         8     0.662      R9C15B.F1 to      R9C14D.D1 n26
+CTOF_DEL    ---     0.495      R9C14D.D1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     0.445      R9C14C.F0 to      R9C14C.C1 C1Submitted_N_237
+CTOF_DEL    ---     0.495      R9C14C.C1 to      R9C14C.F1 SLICE_88
+ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.724   (43.5% logic, 56.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_103:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16D.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.874ns (weighted slack = -3.748ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.614ns  (44.3% logic, 55.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      6.614ns physical path delay SLICE_101 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 1.874ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16C.CLK to      R9C16C.Q1 SLICE_101 (from PHI2_c)
+ROUTE         1     0.986      R9C16C.Q1 to      R9C15A.A1 Bank_7
+CTOF_DEL    ---     0.495      R9C15A.A1 to      R9C15A.F1 SLICE_100
+ROUTE         1     0.315      R9C15A.F1 to      R9C15B.D1 n2277
+CTOF_DEL    ---     0.495      R9C15B.D1 to      R9C15B.F1 SLICE_74
+ROUTE         8     0.662      R9C15B.F1 to      R9C14D.D1 n26
+CTOF_DEL    ---     0.495      R9C14D.D1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     0.445      R9C14C.F0 to      R9C14C.C1 C1Submitted_N_237
+CTOF_DEL    ---     0.495      R9C14C.C1 to      R9C14C.F1 SLICE_88
+ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.614   (44.3% logic, 55.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16C.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.803ns (weighted slack = -3.606ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               6.565ns  (37.0% logic, 63.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.565ns physical path delay SLICE_101 to SLICE_10 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.285ns LSR_SET requirement (totaling 4.762ns) by 1.803ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16C.CLK to      R9C16C.Q0 SLICE_101 (from PHI2_c)
+ROUTE         1     0.986      R9C16C.Q0 to      R9C14A.A0 Bank_6
+CTOF_DEL    ---     0.495      R9C14A.A0 to      R9C14A.F0 SLICE_68
+ROUTE         1     0.766      R9C14A.F0 to      R9C15B.C1 n2287
+CTOF_DEL    ---     0.495      R9C15B.C1 to      R9C15B.F1 SLICE_74
+ROUTE         8     0.662      R9C15B.F1 to      R9C14D.D1 n26
+CTOF_DEL    ---     0.495      R9C14D.D1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     1.093      R9C14C.F0 to    R10C14B.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    6.565   (37.0% logic, 63.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16C.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to    R10C14B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.803ns (weighted slack = -3.606ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               6.565ns  (37.0% logic, 63.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.565ns physical path delay SLICE_101 to SLICE_15 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.285ns LSR_SET requirement (totaling 4.762ns) by 1.803ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16C.CLK to      R9C16C.Q0 SLICE_101 (from PHI2_c)
+ROUTE         1     0.986      R9C16C.Q0 to      R9C14A.A0 Bank_6
+CTOF_DEL    ---     0.495      R9C14A.A0 to      R9C14A.F0 SLICE_68
+ROUTE         1     0.766      R9C14A.F0 to      R9C15B.C1 n2287
+CTOF_DEL    ---     0.495      R9C15B.C1 to      R9C15B.F1 SLICE_74
+ROUTE         8     0.662      R9C15B.F1 to      R9C14D.D1 n26
+CTOF_DEL    ---     0.495      R9C14D.D1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     1.093      R9C14C.F0 to    R10C14C.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    6.565   (37.0% logic, 63.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16C.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to    R10C14C.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.765ns (weighted slack = -3.530ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i1  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               6.527ns  (37.3% logic, 62.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.527ns physical path delay SLICE_93 to SLICE_10 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.285ns LSR_SET requirement (totaling 4.762ns) by 1.765ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16A.CLK to      R9C16A.Q1 SLICE_93 (from PHI2_c)
+ROUTE         1     0.744      R9C16A.Q1 to      R9C15C.C1 Bank_1
+CTOF_DEL    ---     0.495      R9C15C.C1 to      R9C15C.F1 SLICE_99
+ROUTE         2     0.635      R9C15C.F1 to      R9C15D.D1 n22
+CTOF_DEL    ---     0.495      R9C15D.D1 to      R9C15D.F1 SLICE_79
+ROUTE         7     0.997      R9C15D.F1 to      R9C14D.A1 n2369
+CTOF_DEL    ---     0.495      R9C14D.A1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     1.093      R9C14C.F0 to    R10C14B.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    6.527   (37.3% logic, 62.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16A.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to    R10C14B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.765ns (weighted slack = -3.530ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i1  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               6.527ns  (37.3% logic, 62.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.527ns physical path delay SLICE_93 to SLICE_15 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.285ns LSR_SET requirement (totaling 4.762ns) by 1.765ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16A.CLK to      R9C16A.Q1 SLICE_93 (from PHI2_c)
+ROUTE         1     0.744      R9C16A.Q1 to      R9C15C.C1 Bank_1
+CTOF_DEL    ---     0.495      R9C15C.C1 to      R9C15C.F1 SLICE_99
+ROUTE         2     0.635      R9C15C.F1 to      R9C15D.D1 n22
+CTOF_DEL    ---     0.495      R9C15D.D1 to      R9C15D.F1 SLICE_79
+ROUTE         7     0.997      R9C15D.F1 to      R9C14D.A1 n2369
+CTOF_DEL    ---     0.495      R9C14D.A1 to      R9C14D.F1 SLICE_91
+ROUTE         1     0.626      R9C14D.F1 to      R9C14C.D0 n2362
+CTOF_DEL    ---     0.495      R9C14C.D0 to      R9C14C.F0 SLICE_88
+ROUTE         3     1.093      R9C14C.F0 to    R10C14C.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    6.527   (37.3% logic, 62.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16A.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to    R10C14C.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.750ns (weighted slack = -3.500ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.490ns  (37.5% logic, 62.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.490ns physical path delay SLICE_101 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 1.750ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R9C16C.CLK to      R9C16C.Q0 SLICE_101 (from PHI2_c)
+ROUTE         1     0.986      R9C16C.Q0 to      R9C14A.A0 Bank_6
+CTOF_DEL    ---     0.495      R9C14A.A0 to      R9C14A.F0 SLICE_68
+ROUTE         1     0.766      R9C14A.F0 to      R9C15B.C1 n2287
+CTOF_DEL    ---     0.495      R9C15B.C1 to      R9C15B.F1 SLICE_74
+ROUTE         8     0.688      R9C15B.F1 to     R10C15C.D0 n26
+CTOF_DEL    ---     0.495     R10C15C.D0 to     R10C15C.F0 SLICE_104
+ROUTE         2     0.965     R10C15C.F0 to      R9C14C.D1 n2363
+CTOF_DEL    ---     0.495      R9C14C.D1 to      R9C14C.F1 SLICE_88
+ROUTE         1     0.653      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.490   (37.5% logic, 62.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C16C.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.498        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    3.498   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning:  67.833MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 299.401000 MHz ; |  299.401 MHz|  174.216 MHz|   5 *
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |   99.079 MHz|   67.833 MHz|   6 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+2 preferences(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+n26                                     |       8|      64|     19.10%
+                                        |        |        |
+n1996                                   |       1|      49|     14.63%
+                                        |        |        |
+n1997                                   |       1|      46|     13.73%
+                                        |        |        |
+n1995                                   |       1|      45|     13.43%
+                                        |        |        |
+n1998                                   |       1|      38|     11.34%
+                                        |        |        |
+n1994                                   |       1|      37|     11.04%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 335  Score: 391939
+Cumulative negative slack: 304509
+
+Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:40 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_1200hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
+Device,speed:    LCMXO2-1200HC,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (0 errors)
    •             459 items scored, 0 timing errors detected.
+
+
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+            459 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_106 to SLICE_106 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_106 to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C13B.CLK to     R10C13B.Q0 SLICE_106 (from RCLK_c)
+ROUTE         1     0.152     R10C13B.Q0 to     R10C13B.M1 n736 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to    R10C13B.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to    R10C13B.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr_382  (from RCLK_c +)
+   Destination:    FF         Data in        CASr2_383  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_16 to SLICE_16 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_16 to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R7C12B.CLK to      R7C12B.Q0 SLICE_16 (from RCLK_c)
+ROUTE         1     0.152      R7C12B.Q0 to      R7C12B.M1 CASr (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R7C12B.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R7C12B.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i8  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i9  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_75 to SLICE_75 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C13D.CLK to     R10C13D.Q0 SLICE_75 (from RCLK_c)
+ROUTE         1     0.152     R10C13D.Q0 to     R10C13D.M1 n732 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to    R10C13D.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to    R10C13D.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_78 to SLICE_78 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_78 to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C12B.CLK to      R8C12B.Q0 SLICE_78 (from RCLK_c)
+ROUTE         1     0.152      R8C12B.Q0 to      R8C12B.M1 n728 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C12B.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_78:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C12B.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_81 to SLICE_81 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_81 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R9C12A.CLK to      R9C12A.Q0 SLICE_81 (from RCLK_c)
+ROUTE         1     0.152      R9C12A.Q0 to      R9C12A.M1 n726 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R9C12A.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R9C12A.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_84 to SLICE_84 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_84 to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C16C.CLK to      R8C16C.Q0 SLICE_84 (from RCLK_c)
+ROUTE         1     0.152      R8C16C.Q0 to      R8C16C.M1 n738 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C16C.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C16C.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_97 to SLICE_97 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C14A.CLK to     R10C14A.Q0 SLICE_97 (from RCLK_c)
+ROUTE         1     0.152     R10C14A.Q0 to     R10C14A.M1 n734 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to    R10C14A.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to    R10C14A.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr_379  (from RCLK_c +)
+   Destination:    FF         Data in        RASr2_380  (to RCLK_c +)
+
+   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.287ns physical path delay SLICE_30 to SLICE_30 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+      Data path SLICE_30 to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C13B.CLK to      R8C13B.Q0 SLICE_30 (from RCLK_c)
+ROUTE         2     0.154      R8C13B.Q0 to      R8C13B.M1 RASr (to RCLK_c)
+                  --------
+                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C13B.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C13B.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i1  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i2  (to RCLK_c +)
+
+   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.287ns physical path delay SLICE_98 to SLICE_84 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C16D.CLK to      R8C16D.Q1 SLICE_98 (from RCLK_c)
+ROUTE         4     0.154      R8C16D.Q1 to      R8C16C.M0 nRCAS_N_165 (to RCLK_c)
+                  --------
+                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C16D.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C16C.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
+
+   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.287ns physical path delay SLICE_98 to SLICE_98 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R8C16D.CLK to      R8C16D.Q0 SLICE_98 (from RCLK_c)
+ROUTE         4     0.154      R8C16D.Q0 to      R8C16D.M1 nRCS_N_139 (to RCLK_c)
+                  --------
+                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C16D.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.668       62.PADDI to     R8C16D.CLK RCLK_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C14C.CLK to     R10C14C.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2     0.132     R10C14C.Q0 to     R10C14C.A0 C1Submitted
+CTOF_DEL    ---     0.101     R10C14C.A0 to     R10C14C.F0 SLICE_15
+ROUTE         1     0.000     R10C14C.F0 to    R10C14C.DI0 n1398 (to PHI2_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to    R10C14C.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to    R10C14C.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.629ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_407  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               0.601ns  (38.9% logic, 61.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.601ns physical path delay SLICE_10 to SLICE_19 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.629ns
+
+ Physical Path Details:
+
+      Data path SLICE_10 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C14B.CLK to     R10C14B.Q0 SLICE_10 (from PHI2_c)
+ROUTE         1     0.224     R10C14B.Q0 to      R9C14C.B1 ADSubmitted
+CTOF_DEL    ---     0.101      R9C14C.B1 to      R9C14C.F1 SLICE_88
+ROUTE         1     0.143      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    0.601   (38.9% logic, 61.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to    R10C14B.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.715ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_408  (to PHI2_c -)
+
+   Delay:               0.687ns  (34.1% logic, 65.9% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.687ns physical path delay SLICE_19 to SLICE_50 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.715ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_50:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R9C14B.CLK to      R9C14B.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.310      R9C14B.Q0 to     R10C15B.B1 CmdEnable
+CTOF_DEL    ---     0.101     R10C15B.B1 to     R10C15B.F1 SLICE_83
+ROUTE         1     0.143     R10C15B.F1 to     R10C15D.CE PHI2_N_120_enable_3 (to PHI2_c)
+                  --------
+                    0.687   (34.1% logic, 65.9% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_50:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to    R10C15D.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.873ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
+                   FF                        CmdUFMCLK_413
+
+   Delay:               0.845ns  (39.6% logic, 60.4% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.845ns physical path delay SLICE_19 to SLICE_100 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.873ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R9C14B.CLK to      R9C14B.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.224      R9C14B.Q0 to     R10C15A.C0 CmdEnable
+CTOF_DEL    ---     0.101     R10C15A.C0 to     R10C15A.F0 SLICE_73
+ROUTE         2     0.138     R10C15A.F0 to     R10C15A.C1 n2204
+CTOF_DEL    ---     0.101     R10C15A.C1 to     R10C15A.F1 SLICE_73
+ROUTE         2     0.148     R10C15A.F1 to      R9C15A.CE PHI2_N_120_enable_8 (to PHI2_c)
+                  --------
+                    0.845   (39.6% logic, 60.4% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C15A.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.873ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:               0.845ns  (39.6% logic, 60.4% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.845ns physical path delay SLICE_19 to SLICE_99 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.873ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R9C14B.CLK to      R9C14B.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.224      R9C14B.Q0 to     R10C15A.C0 CmdEnable
+CTOF_DEL    ---     0.101     R10C15A.C0 to     R10C15A.F0 SLICE_73
+ROUTE         2     0.138     R10C15A.F0 to     R10C15A.C1 n2204
+CTOF_DEL    ---     0.101     R10C15A.C1 to     R10C15A.F1 SLICE_73
+ROUTE         2     0.148     R10C15A.F1 to      R9C15C.CE PHI2_N_120_enable_8 (to PHI2_c)
+                  --------
+                    0.845   (39.6% logic, 60.4% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C15C.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.252ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               1.224ns  (35.6% logic, 64.4% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.224ns physical path delay SLICE_15 to SLICE_19 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.252ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C14C.CLK to     R10C14C.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2     0.212     R10C14C.Q0 to     R10C14D.A1 C1Submitted
+CTOF_DEL    ---     0.101     R10C14D.A1 to     R10C14D.F1 SLICE_77
+ROUTE         1     0.222     R10C14D.F1 to     R10C14A.B1 n2210
+CTOF_DEL    ---     0.101     R10C14A.B1 to     R10C14A.F1 SLICE_97
+ROUTE         1     0.211     R10C14A.F1 to      R9C14C.A1 n7_adj_5
+CTOF_DEL    ---     0.101      R9C14C.A1 to      R9C14C.F1 SLICE_88
+ROUTE         1     0.143      R9C14C.F1 to      R9C14B.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    1.224   (35.6% logic, 64.4% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to    R10C14C.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.277ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_411  (to PHI2_c -)
+
+   Delay:               1.249ns  (34.9% logic, 65.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.249ns physical path delay SLICE_19 to SLICE_20 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.277ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R9C14B.CLK to      R9C14B.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.224      R9C14B.Q0 to     R10C15A.C0 CmdEnable
+CTOF_DEL    ---     0.101     R10C15A.C0 to     R10C15A.F0 SLICE_73
+ROUTE         2     0.225     R10C15A.F0 to      R9C15B.B0 n2204
+CTOF_DEL    ---     0.101      R9C15B.B0 to      R9C15B.F0 SLICE_74
+ROUTE         2     0.221      R9C15B.F0 to      R9C17A.D1 n2220
+CTOF_DEL    ---     0.101      R9C17A.D1 to      R9C17A.F1 SLICE_89
+ROUTE         1     0.143      R9C17A.F1 to      R9C17D.CE PHI2_N_120_enable_7 (to PHI2_c)
+                  --------
+                    1.249   (34.9% logic, 65.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C17D.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.277ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_410  (to PHI2_c -)
+
+   Delay:               1.249ns  (34.9% logic, 65.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.249ns physical path delay SLICE_19 to SLICE_24 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.277ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R9C14B.CLK to      R9C14B.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.224      R9C14B.Q0 to     R10C15A.C0 CmdEnable
+CTOF_DEL    ---     0.101     R10C15A.C0 to     R10C15A.F0 SLICE_73
+ROUTE         2     0.225     R10C15A.F0 to      R9C15B.B0 n2204
+CTOF_DEL    ---     0.101      R9C15B.B0 to      R9C15B.F0 SLICE_74
+ROUTE         2     0.221      R9C15B.F0 to      R9C17A.D0 n2220
+CTOF_DEL    ---     0.101      R9C17A.D0 to      R9C17A.F0 SLICE_89
+ROUTE         1     0.143      R9C17A.F0 to      R9C17C.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    1.249   (34.9% logic, 65.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C14B.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C17C.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 5.431ns (weighted slack = 10.862ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_408  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_385  (to PHI2_c +)
+
+   Delay:               0.371ns  (63.1% logic, 36.9% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.371ns physical path delay SLICE_50 to SLICE_33 meets
+     -0.013ns DIN_HLD and
+     -5.047ns delay constraint less
+      0.000ns skew requirement (totaling -5.060ns) by 5.431ns
+
+ Physical Path Details:
+
+      Data path SLICE_50 to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    R10C15D.CLK to     R10C15D.Q0 SLICE_50 (from PHI2_c)
+ROUTE         1     0.137     R10C15D.Q0 to     R10C16A.C0 XOR8MEG
+CTOF_DEL    ---     0.101     R10C16A.C0 to     R10C16A.F0 SLICE_33
+ROUTE         1     0.000     R10C16A.F0 to    R10C16A.DI0 RA11_N_184 (to PHI2_c)
+                  --------
+                    0.371   (63.1% logic, 36.9% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_50:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to    R10C15D.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to    R10C16A.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 5.992ns (weighted slack = 11.984ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
+                   FF                        CmdUFMCLK_413
+
+   Delay:               0.917ns  (47.5% logic, 52.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      0.917ns physical path delay SLICE_93 to SLICE_100 meets
+     -0.028ns CE_HLD and
+     -5.047ns delay constraint less
+      0.000ns skew requirement (totaling -5.075ns) by 5.992ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R9C16A.CLK to      R9C16A.Q0 SLICE_93 (from PHI2_c)
+ROUTE         1     0.138      R9C16A.Q0 to      R9C15A.C1 Bank_0
+CTOF_DEL    ---     0.101      R9C15A.C1 to      R9C15A.F1 SLICE_100
+ROUTE         1     0.053      R9C15A.F1 to      R9C15B.D1 n2277
+CTOF_DEL    ---     0.101      R9C15B.D1 to      R9C15B.F1 SLICE_74
+ROUTE         8     0.142      R9C15B.F1 to     R10C15A.D1 n26
+CTOF_DEL    ---     0.101     R10C15A.D1 to     R10C15A.F1 SLICE_73
+ROUTE         2     0.148     R10C15A.F1 to      R9C15A.CE PHI2_N_120_enable_8 (to PHI2_c)
+                  --------
+                    0.917   (47.5% logic, 52.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C16A.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.203        8.PADDI to     R9C15A.CLK PHI2_c
+                  --------
+                    1.203   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 299.401000 MHz ; |     0.000 ns|     0.304 ns|   1  
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |     0.000 ns|     0.379 ns|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 335 (setup), 0 (hold)
+Score: 391939 (setup), 0 (hold)
+Cumulative negative slack: 304509 (304509+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_drc.log b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_drc.log new file mode 100644 index 0000000..d48a448 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_drc.log @@ -0,0 +1,16 @@ +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 309 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO2_1200HC_impl1.ngd. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse.twr b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse.twr new file mode 100644 index 0000000..ccd5368 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse.twr @@ -0,0 +1,297 @@ +-------------------------------------------------------------------------------- +Lattice Synthesis Timing Report, Version +Tue Aug 15 05:03:26 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Design: RAM2GS +Constraint file: +Report level: verbose report, limited to 3 items per constraint +-------------------------------------------------------------------------------- + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c] + 122 items scored, 119 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 7.418ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i1 (from PHI2_c +) + Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -) + + Delay: 9.633ns (30.2% logic, 69.8% route), 6 logic levels. + + Constraint Details: + + 9.633ns data_path Bank_i1 to CmdEnable_405 violates + 2.500ns delay constraint less + 0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns + + Path Details: Bank_i1 to CmdEnable_405 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q Bank_i1 (from PHI2_c) +Route 1 e 0.941 Bank[1] +LUT4 --- 0.493 D to Z i8_4_lut +Route 2 e 1.141 n22 +LUT4 --- 0.493 B to Z i11_3_lut_rep_20 +Route 7 e 1.502 n2369 +LUT4 --- 0.493 A to Z i1_2_lut_rep_13_3_lut +Route 1 e 0.941 n2362 +LUT4 --- 0.493 D to Z i1_4_lut_adj_13 +Route 3 e 1.258 C1Submitted_N_237 +LUT4 --- 0.493 C to Z i34_4_lut +Route 1 e 0.941 PHI2_N_120_enable_1 + -------- + 9.633 (30.2% logic, 69.8% route), 6 logic levels. + + +Error: The following path violates requirements by 7.418ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i4 (from PHI2_c +) + Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -) + + Delay: 9.633ns (30.2% logic, 69.8% route), 6 logic levels. + + Constraint Details: + + 9.633ns data_path Bank_i4 to CmdEnable_405 violates + 2.500ns delay constraint less + 0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns + + Path Details: Bank_i4 to CmdEnable_405 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c) +Route 1 e 0.941 Bank[4] +LUT4 --- 0.493 C to Z i8_4_lut +Route 2 e 1.141 n22 +LUT4 --- 0.493 B to Z i11_3_lut_rep_20 +Route 7 e 1.502 n2369 +LUT4 --- 0.493 A to Z i1_2_lut_rep_13_3_lut +Route 1 e 0.941 n2362 +LUT4 --- 0.493 D to Z i1_4_lut_adj_13 +Route 3 e 1.258 C1Submitted_N_237 +LUT4 --- 0.493 C to Z i34_4_lut +Route 1 e 0.941 PHI2_N_120_enable_1 + -------- + 9.633 (30.2% logic, 69.8% route), 6 logic levels. + + +Error: The following path violates requirements by 7.256ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i3 (from PHI2_c +) + Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -) + + Delay: 9.471ns (30.7% logic, 69.3% route), 6 logic levels. + + Constraint Details: + + 9.471ns data_path Bank_i3 to CmdEnable_405 violates + 2.500ns delay constraint less + 0.285ns LCE_S requirement (totaling 2.215ns) by 7.256ns + + Path Details: Bank_i3 to CmdEnable_405 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q Bank_i3 (from PHI2_c) +Route 1 e 0.941 Bank[3] +LUT4 --- 0.493 B to Z i1989_2_lut +Route 1 e 0.941 n2287 +LUT4 --- 0.493 C to Z i12_4_lut +Route 8 e 1.540 n26 +LUT4 --- 0.493 B to Z i1_2_lut_rep_13_3_lut +Route 1 e 0.941 n2362 +LUT4 --- 0.493 D to Z i1_4_lut_adj_13 +Route 3 e 1.258 C1Submitted_N_237 +LUT4 --- 0.493 C to Z i34_4_lut +Route 1 e 0.941 PHI2_N_120_enable_1 + -------- + 9.471 (30.7% logic, 69.3% route), 6 logic levels. + +Warning: 9.918 ns is the maximum delay for this constraint. + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c] + 498 items scored, 186 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 3.319ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i13 (from RCLK_c +) + Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +) + + Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels. + + Constraint Details: + + 8.159ns data_path FS_610__i13 to nUFMCS_415 violates + 5.000ns delay constraint less + 0.160ns L_S requirement (totaling 4.840ns) by 3.319ns + + Path Details: FS_610__i13 to nUFMCS_415 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q FS_610__i13 (from RCLK_c) +Route 3 e 1.315 FS[13] +LUT4 --- 0.493 B to Z i3_4_lut_adj_7 +Route 5 e 1.405 n10 +LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut +Route 2 e 1.141 n2368 +LUT4 --- 0.493 B to Z i1_2_lut_4_lut +Route 1 e 0.941 n64 +LUT4 --- 0.493 B to Z i1448_4_lut +Route 1 e 0.941 nUFMCS_N_199 + -------- + 8.159 (29.6% logic, 70.4% route), 5 logic levels. + + +Error: The following path violates requirements by 3.319ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i15 (from RCLK_c +) + Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +) + + Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels. + + Constraint Details: + + 8.159ns data_path FS_610__i15 to nUFMCS_415 violates + 5.000ns delay constraint less + 0.160ns L_S requirement (totaling 4.840ns) by 3.319ns + + Path Details: FS_610__i15 to nUFMCS_415 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q FS_610__i15 (from RCLK_c) +Route 3 e 1.315 FS[15] +LUT4 --- 0.493 C to Z i3_4_lut_adj_7 +Route 5 e 1.405 n10 +LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut +Route 2 e 1.141 n2368 +LUT4 --- 0.493 B to Z i1_2_lut_4_lut +Route 1 e 0.941 n64 +LUT4 --- 0.493 B to Z i1448_4_lut +Route 1 e 0.941 nUFMCS_N_199 + -------- + 8.159 (29.6% logic, 70.4% route), 5 logic levels. + + +Error: The following path violates requirements by 3.319ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i16 (from RCLK_c +) + Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +) + + Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels. + + Constraint Details: + + 8.159ns data_path FS_610__i16 to nUFMCS_415 violates + 5.000ns delay constraint less + 0.160ns L_S requirement (totaling 4.840ns) by 3.319ns + + Path Details: FS_610__i16 to nUFMCS_415 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q FS_610__i16 (from RCLK_c) +Route 3 e 1.315 FS[16] +LUT4 --- 0.493 D to Z i3_4_lut_adj_7 +Route 5 e 1.405 n10 +LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut +Route 2 e 1.141 n2368 +LUT4 --- 0.493 B to Z i1_2_lut_4_lut +Route 1 e 0.941 n64 +LUT4 --- 0.493 B to Z i1448_4_lut +Route 1 e 0.941 nUFMCS_N_199 + -------- + 8.159 (29.6% logic, 70.4% route), 5 logic levels. + +Warning: 8.319 ns is the maximum delay for this constraint. + + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 5.000 ns| 19.836 ns| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 5.000 ns| 8.319 ns| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + +-------------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +-------------------------------------------------------------------------------- +n26 | 8| 84| 27.54% + | | | +n1997 | 1| 36| 11.80% + | | | +n1996 | 1| 35| 11.48% + | | | +n1995 | 1| 33| 10.82% + | | | +n10 | 5| 32| 10.49% + | | | +n1998 | 1| 32| 10.49% + | | | +-------------------------------------------------------------------------------- + + +Timing summary: +--------------- + +Timing errors: 305 Score: 1313492 + +Constraints cover 621 paths, 182 nets, and 471 connections (64.2% coverage) + + +Peak memory: 57921536 bytes, TRCE: 2363392 bytes, DLYMAN: 0 bytes +CPU_TIME_REPORT: 0 secs diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse_lsetwr.html new file mode 100644 index 0000000..8da9b01 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_lse_lsetwr.html @@ -0,0 +1,362 @@ + +Lattice Synthesis Timing Report + + +
    Lattice Synthesis Timing Report
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Tue Aug 15 05:03:26 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
+            122 items scored, 119 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 7.418ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i1  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
+
+   Delay:                   9.633ns  (30.2% logic, 69.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.633ns data_path Bank_i1 to CmdEnable_405 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
+
+ Path Details: Bank_i1 to CmdEnable_405
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i1 (from PHI2_c)
+Route         1   e 0.941                                  Bank[1]
+LUT4        ---     0.493              D to Z              i8_4_lut
+Route         2   e 1.141                                  n22
+LUT4        ---     0.493              B to Z              i11_3_lut_rep_20
+Route         7   e 1.502                                  n2369
+LUT4        ---     0.493              A to Z              i1_2_lut_rep_13_3_lut
+Route         1   e 0.941                                  n2362
+LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
+Route         3   e 1.258                                  C1Submitted_N_237
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_120_enable_1
+                  --------
+                    9.633  (30.2% logic, 69.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 7.418ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i4  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
+
+   Delay:                   9.633ns  (30.2% logic, 69.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.633ns data_path Bank_i4 to CmdEnable_405 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
+
+ Path Details: Bank_i4 to CmdEnable_405
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i4 (from PHI2_c)
+Route         1   e 0.941                                  Bank[4]
+LUT4        ---     0.493              C to Z              i8_4_lut
+Route         2   e 1.141                                  n22
+LUT4        ---     0.493              B to Z              i11_3_lut_rep_20
+Route         7   e 1.502                                  n2369
+LUT4        ---     0.493              A to Z              i1_2_lut_rep_13_3_lut
+Route         1   e 0.941                                  n2362
+LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
+Route         3   e 1.258                                  C1Submitted_N_237
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_120_enable_1
+                  --------
+                    9.633  (30.2% logic, 69.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 7.256ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
+
+   Delay:                   9.471ns  (30.7% logic, 69.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.471ns data_path Bank_i3 to CmdEnable_405 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 7.256ns
+
+ Path Details: Bank_i3 to CmdEnable_405
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 0.941                                  Bank[3]
+LUT4        ---     0.493              B to Z              i1989_2_lut
+Route         1   e 0.941                                  n2287
+LUT4        ---     0.493              C to Z              i12_4_lut
+Route         8   e 1.540                                  n26
+LUT4        ---     0.493              B to Z              i1_2_lut_rep_13_3_lut
+Route         1   e 0.941                                  n2362
+LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
+Route         3   e 1.258                                  C1Submitted_N_237
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_120_enable_1
+                  --------
+                    9.471  (30.7% logic, 69.3% route), 6 logic levels.
+
+Warning: 9.918 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            498 items scored, 186 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 3.319ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i13  (from RCLK_c +)
+   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
+
+   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.159ns data_path FS_610__i13 to nUFMCS_415 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
+
+ Path Details: FS_610__i13 to nUFMCS_415
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_610__i13 (from RCLK_c)
+Route         3   e 1.315                                  FS[13]
+LUT4        ---     0.493              B to Z              i3_4_lut_adj_7
+Route         5   e 1.405                                  n10
+LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
+Route         2   e 1.141                                  n2368
+LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
+Route         1   e 0.941                                  n64
+LUT4        ---     0.493              B to Z              i1448_4_lut
+Route         1   e 0.941                                  nUFMCS_N_199
+                  --------
+                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
+
+
+Error:  The following path violates requirements by 3.319ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i15  (from RCLK_c +)
+   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
+
+   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.159ns data_path FS_610__i15 to nUFMCS_415 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
+
+ Path Details: FS_610__i15 to nUFMCS_415
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_610__i15 (from RCLK_c)
+Route         3   e 1.315                                  FS[15]
+LUT4        ---     0.493              C to Z              i3_4_lut_adj_7
+Route         5   e 1.405                                  n10
+LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
+Route         2   e 1.141                                  n2368
+LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
+Route         1   e 0.941                                  n64
+LUT4        ---     0.493              B to Z              i1448_4_lut
+Route         1   e 0.941                                  nUFMCS_N_199
+                  --------
+                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
+
+
+Error:  The following path violates requirements by 3.319ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i16  (from RCLK_c +)
+   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
+
+   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.159ns data_path FS_610__i16 to nUFMCS_415 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
+
+ Path Details: FS_610__i16 to nUFMCS_415
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_610__i16 (from RCLK_c)
+Route         3   e 1.315                                  FS[16]
+LUT4        ---     0.493              D to Z              i3_4_lut_adj_7
+Route         5   e 1.405                                  n10
+LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
+Route         2   e 1.141                                  n2368
+LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
+Route         1   e 0.941                                  n64
+LUT4        ---     0.493              B to Z              i1448_4_lut
+Route         1   e 0.941                                  nUFMCS_N_199
+                  --------
+                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
+
+Warning: 8.319 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |     5.000 ns|    19.836 ns|     6 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|     8.319 ns|     5 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n26                                     |       8|      84|     27.54%
+                                        |        |        |
+n1997                                   |       1|      36|     11.80%
+                                        |        |        |
+n1996                                   |       1|      35|     11.48%
+                                        |        |        |
+n1995                                   |       1|      33|     10.82%
+                                        |        |        |
+n10                                     |       5|      32|     10.49%
+                                        |        |        |
+n1998                                   |       1|      32|     10.49%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 305  Score: 1313492
+
+Constraints cover  621 paths, 182 nets, and 471 connections (64.2% coverage)
+
+
+Peak memory: 57921536 bytes, TRCE: 2363392 bytes, DLYMAN: 0 bytes
+CPU_TIME_REPORT: 0 secs 
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2GS_prim.v b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_prim.v new file mode 100644 index 0000000..28a3dbb --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2GS_prim.v @@ -0,0 +1,802 @@ +// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.12.1.454 +// Netlist written on Tue Aug 15 05:03:26 2023 +// +// Verilog Description of module RAM2GS +// + +module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, + LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, + nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1[8:14]) + input PHI2; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + input [9:0]MAin; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + input [1:0]CROW; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + input [7:0]Din; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + output [7:0]Dout; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + input nCCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + input nCRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + input nFWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) + output LED; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) + output [1:0]RBA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + output [11:0]RA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + inout [7:0]RD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + output nRCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) + input RCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + output RCKE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) + output nRWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) + output nRRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) + output nRCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) + output RDQMH; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) + output RDQML; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) + output nUFMCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) + output UFMCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) + output UFMSDI; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) + input UFMSDO; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) + + wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + wire nCCAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + wire nCRAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + wire PHI2_N_120 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(38[6:13]) + wire nCRAS_c__inv /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + + wire GND_net, VCC_net, PHI2r, PHI2r2, PHI2r3, RASr, RASr2, + RASr3, CASr, CASr2, CASr3, FWEr, CBR, LEDEN, LED_c, + Din_c_7, Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, + Din_c_0; + wire [7:0]Bank; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(31[12:16]) + + wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, + MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, + nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, + nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, RA_0; + wire [9:0]RowA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(51[12:16]) + + wire RA_1_9, RA_1_8, RA_1_7, RA_1_6, RA_1_5, RA_1_4, RA_1_3, + RA_1_2, RA_1_1, RA_1_0, RDQML_c, RDQMH_c; + wire [7:0]WRD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(59[12:15]) + + wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted, + CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI, + CmdUFMCS, InitReady, Ready, n10; + wire [17:0]FS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15]) + + wire RA11_N_184, PHI2_N_120_enable_8, n2036, n1765, n1893, n7, + n917, n4, n2277, RCKE_N_132, nRowColSel_N_35, nRWE_N_182, + nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32, nRCS_N_146, + n15, n2260, nRCS_N_142, n2362, nRCS_N_141, nRCAS_N_166, + nRWE_N_178, n2180, nRCS_N_139, nRCAS_N_165, nRWE_N_177, nRWE_N_176, + n14, n6, n13, n1993, n2254, Ready_N_296, RCLK_c_enable_28, + nRCS_N_137, Ready_N_292, nRCS_N_136, nRRAS_N_156, nRCAS_N_161, + nRWE_N_171, n2220, RCKEEN_N_121, n15_adj_1, n2371, ADSubmitted_N_246, + CmdEnable_N_248, C1Submitted_N_237, PHI2_N_120_enable_3, n2174, + n6_adj_2, Cmdn8MEGEN_N_264, XOR8MEG_N_110, n2204, n1996, n6_adj_3, + RCLK_c_enable_10, n2191, n2208, n22, n8MEGEN_N_91, UFMCLK_N_224, + UFMSDI_N_231, n26, nUFMCS_N_199, n2055, PHI2_N_120_enable_2, + n1999, n2287, n726, n727, n728, n729, n730, n732, n733, + n734, n735, n736, n737, n738, n2267, n1398, n2183, n1995, + PHI2_N_120_enable_1, n1060, n1408, n2228, n2447, n1406, + PHI2_N_120_enable_6, n2225, n827, n2370, n1277, n15_adj_4, + Dout_c, n78, n79, n80, n81, n82, n83, n84, n85, n86, + n87, n88, n89, n90, n91, n92, n93, n94, n95, n2382, + RCLK_c_enable_15, n9, n2369, n7_adj_5, n13_adj_6, n2381, + n2210, n2380, n2227, n2368, PHI2_N_120_enable_7, n12, n1994, + RCLK_c_enable_27, n2367, n1407, n2379, n2378, n2377, n2366, + n2365, n2376, n1998, n2375, n4_adj_7, n2374, RCLK_c_enable_6, + Dout_0, Dout_1, n984, Dout_2, n8, Dout_3, Dout_4, n1314, + Dout_5, Dout_6, RCLK_c_enable_16, n2363, n13_adj_8, n2000, + n2373, RCLK_c_enable_5, n1992, n1997, n2372, n64; + + VHI i2 (.Z(VCC_net)); + INV i2046 (.A(PHI2_c), .Z(PHI2_N_120)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + FD1S3AX PHI2r2_377 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r2_377.GSR = "ENABLED"; + LUT4 nRCAS_I_43_4_lut (.A(nRCS_N_142), .B(RASr2), .C(nRowColSel_N_35), + .D(CBR), .Z(nRCAS_N_166)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(186[13] 231[7]) + defparam nRCAS_I_43_4_lut.init = 16'h3afa; + LUT4 nRCAS_I_0_452_3_lut_4_lut (.A(n2371), .B(nRCAS_N_165), .C(Ready), + .D(nRCAS_N_166), .Z(nRCAS_N_161)) /* synthesis lut_function=(A ((D)+!C)+!A (B ((D)+!C)+!B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRCAS_I_0_452_3_lut_4_lut.init = 16'hfe0e; + LUT4 nRWE_I_0_455_4_lut (.A(n1765), .B(nRWE_N_178), .C(Ready), .D(n2371), + .Z(nRWE_N_171)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRWE_I_0_455_4_lut.init = 16'hcfc5; + FD1S3AX PHI2r3_378 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r3_378.GSR = "ENABLED"; + FD1S3AX RASr_379 (.D(nCRAS_c__inv), .CK(RCLK_c), .Q(RASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr_379.GSR = "ENABLED"; + FD1S3AX RASr2_380 (.D(RASr), .CK(RCLK_c), .Q(RASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr2_380.GSR = "ENABLED"; + FD1S3AX RASr3_381 (.D(RASr2), .CK(RCLK_c), .Q(RASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr3_381.GSR = "ENABLED"; + FD1S3AX CASr_382 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr_382.GSR = "ENABLED"; + FD1S3AX CASr2_383 (.D(CASr), .CK(RCLK_c), .Q(CASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr2_383.GSR = "ENABLED"; + FD1S3AX CASr3_384 (.D(CASr2), .CK(RCLK_c), .Q(CASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr3_384.GSR = "ENABLED"; + FD1S3IX RA11_385 (.D(RA11_N_184), .CK(PHI2_c), .CD(n2380), .Q(RA_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam RA11_385.GSR = "ENABLED"; + CCU2D FS_610_add_4_15 (.A0(FS[13]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1998), + .COUT(n1999), .S0(n82), .S1(n81)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_15.INIT0 = 16'hfaaa; + defparam FS_610_add_4_15.INIT1 = 16'hfaaa; + defparam FS_610_add_4_15.INJECT1_0 = "NO"; + defparam FS_610_add_4_15.INJECT1_1 = "NO"; + FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i0.GSR = "ENABLED"; + FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i0.GSR = "ENABLED"; + FD1S3AX FWEr_389 (.D(n2373), .CK(nCRAS_c__inv), .Q(FWEr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam FWEr_389.GSR = "ENABLED"; + FD1S3AX CBR_390 (.D(nCCAS_N_3), .CK(nCRAS_c__inv), .Q(CBR)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam CBR_390.GSR = "ENABLED"; + FD1S3AX RCKE_395 (.D(RCKE_N_132), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(141[9] 144[5]) + defparam RCKE_395.GSR = "ENABLED"; + FD1P3AY nRCS_396 (.D(nRCS_N_136), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRCS_396.GSR = "ENABLED"; + LUT4 i1477_2_lut (.A(nRWE_N_177), .B(nRCAS_N_165), .Z(n1765)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1477_2_lut.init = 16'heeee; + FD1P3AX nRowColSel_402 (.D(n917), .SP(RCLK_c_enable_5), .CK(RCLK_c), + .Q(nRowColSel)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRowColSel_402.GSR = "ENABLED"; + CCU2D FS_610_add_4_13 (.A0(FS[11]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1997), + .COUT(n1998), .S0(n84), .S1(n83)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_13.INIT0 = 16'hfaaa; + defparam FS_610_add_4_13.INIT1 = 16'hfaaa; + defparam FS_610_add_4_13.INJECT1_0 = "NO"; + defparam FS_610_add_4_13.INJECT1_1 = "NO"; + LUT4 i2_2_lut (.A(InitReady), .B(Ready_N_296), .Z(n6_adj_3)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam i2_2_lut.init = 16'h8888; + FD1P3AX CmdEnable_405 (.D(CmdEnable_N_248), .SP(PHI2_N_120_enable_1), + .CK(PHI2_N_120), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdEnable_405.GSR = "ENABLED"; + LUT4 i4_4_lut (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n6_adj_2), + .Z(n2204)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; + defparam i4_4_lut.init = 16'h4000; + FD1P3IX ADSubmitted_407 (.D(ADSubmitted_N_246), .SP(PHI2_N_120_enable_2), + .CD(C1Submitted_N_237), .CK(PHI2_N_120), .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam ADSubmitted_407.GSR = "ENABLED"; + LUT4 i26_4_lut (.A(n2183), .B(n2191), .C(Din_c_5), .D(n2254), .Z(n15_adj_1)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ; + defparam i26_4_lut.init = 16'hc0ca; + LUT4 i1_2_lut_3_lut_4_lut (.A(n2369), .B(n26), .C(n2204), .D(nFWE_c), + .Z(n2220)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; + defparam i1_2_lut_3_lut_4_lut.init = 16'h0020; + FD1P3AY nRRAS_397 (.D(nRRAS_N_156), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRRAS_397.GSR = "ENABLED"; + LUT4 nRWE_I_50_1_lut (.A(nRWE_N_177), .Z(nRWE_N_176)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(255[14] 262[8]) + defparam nRWE_I_50_1_lut.init = 16'h5555; + BB Dout_pad_7__713 (.I(WRD[7]), .T(n984), .B(RD[7]), .O(Dout_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + FD1P3AY nRCAS_398 (.D(nRCAS_N_161), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRCAS_398.GSR = "ENABLED"; + FD1P3AY nRWE_399 (.D(nRWE_N_171), .SP(RCLK_c_enable_5), .CK(RCLK_c), + .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRWE_399.GSR = "ENABLED"; + FD1S3JX RA10_400 (.D(n2036), .CK(RCLK_c), .PD(nRWE_N_176), .Q(RA_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam RA10_400.GSR = "ENABLED"; + FD1P3AX RCKEEN_401 (.D(RCKEEN_N_121), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(RCKEEN)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam RCKEEN_401.GSR = "ENABLED"; + FD1S3AX FS_610__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i0.GSR = "ENABLED"; + FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_c__inv), .CD(n2380), .Q(RBA_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RBA__i1.GSR = "ENABLED"; + LUT4 i1_4_lut (.A(Din_c_5), .B(n2220), .C(Din_c_4), .D(Din_c_3), + .Z(PHI2_N_120_enable_6)) /* synthesis lut_function=(A (B (C (D)))+!A (B)) */ ; + defparam i1_4_lut.init = 16'hc444; + LUT4 i29_3_lut (.A(InitReady), .B(n15_adj_4), .C(Ready), .Z(RCKEEN_N_121)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam i29_3_lut.init = 16'hcaca; + LUT4 Cmdn8MEGEN_I_93_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_4), + .D(n1314), .Z(Cmdn8MEGEN_N_264)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(321[13] 335[7]) + defparam Cmdn8MEGEN_I_93_4_lut.init = 16'hcc5c; + LUT4 i1956_2_lut (.A(MAin_c_0), .B(Din_c_2), .Z(n2254)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1956_2_lut.init = 16'heeee; + FD1P3AX IS_FSM__i0 (.D(Ready_N_296), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(nRCS_N_139)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i0.GSR = "ENABLED"; + CCU2D FS_610_add_4_9 (.A0(FS[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1995), + .COUT(n1996), .S0(n88), .S1(n87)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_9.INIT0 = 16'hfaaa; + defparam FS_610_add_4_9.INIT1 = 16'hfaaa; + defparam FS_610_add_4_9.INJECT1_0 = "NO"; + defparam FS_610_add_4_9.INJECT1_1 = "NO"; + FD1S3JX C1Submitted_406 (.D(n1398), .CK(PHI2_N_120), .PD(C1Submitted_N_237), + .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam C1Submitted_406.GSR = "ENABLED"; + FD1P3AY nUFMCS_415 (.D(nUFMCS_N_199), .SP(RCLK_c_enable_10), .CK(RCLK_c), + .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam nUFMCS_415.GSR = "ENABLED"; + LUT4 i2_4_lut (.A(n2220), .B(Din_c_4), .C(Din_c_3), .D(Din_c_5), + .Z(PHI2_N_120_enable_7)) /* synthesis lut_function=(A (B (C+!(D)))) */ ; + defparam i2_4_lut.init = 16'h8088; + FD1S3AX S_FSM_i1 (.D(n2374), .CK(RCLK_c), .Q(nRowColSel_N_35)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i1.GSR = "ENABLED"; + CCU2D FS_610_add_4_7 (.A0(FS[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1994), + .COUT(n1995), .S0(n90), .S1(n89)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_7.INIT0 = 16'hfaaa; + defparam FS_610_add_4_7.INIT1 = 16'hfaaa; + defparam FS_610_add_4_7.INJECT1_0 = "NO"; + defparam FS_610_add_4_7.INJECT1_1 = "NO"; + LUT4 i1_2_lut (.A(Din_c_6), .B(Din_c_3), .Z(n2183)) /* synthesis lut_function=(!((B)+!A)) */ ; + defparam i1_2_lut.init = 16'h2222; + LUT4 i1_2_lut_rep_15_4_lut (.A(FS[10]), .B(FS[11]), .C(n2368), .D(InitReady), + .Z(RCLK_c_enable_16)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; + defparam i1_2_lut_rep_15_4_lut.init = 16'h0008; + CCU2D FS_610_add_4_3 (.A0(FS[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1992), + .COUT(n1993), .S0(n94), .S1(n93)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_3.INIT0 = 16'hfaaa; + defparam FS_610_add_4_3.INIT1 = 16'hfaaa; + defparam FS_610_add_4_3.INJECT1_0 = "NO"; + defparam FS_610_add_4_3.INJECT1_1 = "NO"; + LUT4 RA11_I_54_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_184)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(99[22:51]) + defparam RA11_I_54_3_lut.init = 16'hc6c6; + LUT4 i9_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(n9)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ; + defparam i9_2_lut_3_lut.init = 16'h1f1f; + LUT4 i1491_2_lut_rep_30 (.A(RCKE_c), .B(RASr2), .Z(n2379)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1491_2_lut_rep_30.init = 16'heeee; + LUT4 nRCS_I_31_3_lut_4_lut (.A(RCKE_c), .B(RASr2), .C(nRowColSel_N_35), + .D(nRCS_N_142), .Z(nRCS_N_141)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C+(D))))) */ ; + defparam nRCS_I_31_3_lut_4_lut.init = 16'h1f10; + FD1P3IX UFMCLK_416 (.D(UFMCLK_N_224), .SP(RCLK_c_enable_10), .CD(n2366), + .CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam UFMCLK_416.GSR = "ENABLED"; + LUT4 MAin_9__I_0_427_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), + .Z(RA_1_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i10_3_lut.init = 16'hcaca; + LUT4 i3_4_lut (.A(Din_c_2), .B(Din_c_3), .C(Din_c_6), .D(MAin_c_0), + .Z(n2191)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i3_4_lut.init = 16'h0800; + LUT4 i1_2_lut_rep_21_3_lut (.A(Din_c_7), .B(Din_c_1), .C(Din_c_0), + .Z(n2370)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i1_2_lut_rep_21_3_lut.init = 16'h2020; + LUT4 MAin_9__I_0_427_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), + .Z(RA_1_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i9_3_lut.init = 16'hcaca; + LUT4 MAin_9__I_0_427_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), + .Z(RA_1_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i8_3_lut.init = 16'hcaca; + LUT4 MAin_9__I_0_427_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), + .Z(RA_1_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i7_3_lut.init = 16'hcaca; + LUT4 MAin_9__I_0_427_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), + .Z(RA_1_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i6_3_lut.init = 16'hcaca; + CCU2D FS_610_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n1992), + .S1(n95)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_1.INIT0 = 16'hF000; + defparam FS_610_add_4_1.INIT1 = 16'h0555; + defparam FS_610_add_4_1.INJECT1_0 = "NO"; + defparam FS_610_add_4_1.INJECT1_1 = "NO"; + LUT4 MAin_9__I_0_427_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), + .Z(RA_1_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i5_3_lut.init = 16'hcaca; + FD1S3AX PHI2r_376 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r_376.GSR = "ENABLED"; + LUT4 i1962_4_lut (.A(Din_c_4), .B(Din_c_1), .C(n1314), .D(LEDEN), + .Z(n2260)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ; + defparam i1962_4_lut.init = 16'hfefa; + LUT4 i1423_2_lut (.A(RCKE_c), .B(RASr2), .Z(nRWE_N_182)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(168[14] 184[8]) + defparam i1423_2_lut.init = 16'hdddd; + LUT4 MAin_9__I_0_427_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), + .Z(RA_1_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i4_3_lut.init = 16'hcaca; + FD1S3IX S_FSM_i3 (.D(n1406), .CK(RCLK_c), .CD(n1407), .Q(nRowColSel_N_33)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i3.GSR = "ENABLED"; + FD1S3IX S_FSM_i4 (.D(n827), .CK(RCLK_c), .CD(n2374), .Q(nRowColSel_N_32)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i4.GSR = "ENABLED"; + LUT4 i1_2_lut_3_lut_4_lut_adj_1 (.A(Din_c_7), .B(Din_c_1), .C(Din_c_4), + .D(Din_c_0), .Z(n2208)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i1_2_lut_3_lut_4_lut_adj_1.init = 16'h0200; + LUT4 MAin_c_0_bdd_4_lut (.A(n2369), .B(n26), .C(nFWE_c), .D(MAin_c_1), + .Z(PHI2_N_120_enable_2)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; + defparam MAin_c_0_bdd_4_lut.init = 16'h0200; + FD1P3IX UFMSDI_417 (.D(UFMSDI_N_231), .SP(RCLK_c_enable_10), .CD(n2366), + .CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam UFMSDI_417.GSR = "ENABLED"; + LUT4 MAin_9__I_0_427_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), + .Z(RA_1_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i3_3_lut.init = 16'hcaca; + LUT4 MAin_9__I_0_427_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), + .Z(RA_1_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i2_3_lut.init = 16'hcaca; + LUT4 i1448_4_lut (.A(n13_adj_6), .B(n64), .C(CmdUFMCS), .D(InitReady), + .Z(nUFMCS_N_199)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (C+!(D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(345[12] 409[6]) + defparam i1448_4_lut.init = 16'h3fbb; + LUT4 i2_3_lut_rep_18_4_lut (.A(n10), .B(n2375), .C(FS[11]), .D(FS[10]), + .Z(n2367)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; + defparam i2_3_lut_rep_18_4_lut.init = 16'h1000; + LUT4 i3_4_lut_adj_2 (.A(nRCS_N_139), .B(InitReady), .C(nRowColSel_N_35), + .D(RASr2), .Z(nRCS_N_137)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; + defparam i3_4_lut_adj_2.init = 16'hbfff; + LUT4 MAin_9__I_0_427_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), + .Z(RA_1_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i1_3_lut.init = 16'hcaca; + LUT4 i1416_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(58[17:46]) + defparam i1416_2_lut.init = 16'hbbbb; + LUT4 i2001_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ; + defparam i2001_2_lut.init = 16'h7777; + LUT4 i2_3_lut_4_lut (.A(n2363), .B(MAin_c_1), .C(n2208), .D(n15_adj_1), + .Z(CmdEnable_N_248)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; + defparam i2_3_lut_4_lut.init = 16'h4000; + LUT4 i2005_3_lut_rep_17_4_lut (.A(n10), .B(n2375), .C(InitReady), + .D(FS[11]), .Z(n2366)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ; + defparam i2005_3_lut_rep_17_4_lut.init = 16'h0001; + FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i0.GSR = "ENABLED"; + LUT4 i1427_4_lut (.A(nRCS_N_146), .B(nRowColSel_N_34), .C(n2378), + .D(nRowColSel_N_33), .Z(nRCS_N_142)) /* synthesis lut_function=(A (B+(C (D)))+!A (B+(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(195[13] 231[7]) + defparam i1427_4_lut.init = 16'hfcdd; + LUT4 i3_3_lut_4_lut (.A(Din_c_7), .B(Din_c_1), .C(Din_c_6), .D(Din_c_4), + .Z(n8)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i3_3_lut_4_lut.init = 16'h0002; + LUT4 i1_2_lut_adj_3 (.A(FS[10]), .B(n13_adj_6), .Z(RCLK_c_enable_28)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_adj_3.init = 16'h8888; + LUT4 i1119_1_lut (.A(nRowColSel_N_35), .Z(n1408)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1119_1_lut.init = 16'h5555; + LUT4 nRCS_N_146_bdd_4_lut (.A(nRCS_N_146), .B(n1060), .C(nRWE_N_182), + .D(nRowColSel_N_35), .Z(nRWE_N_178)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ; + defparam nRCS_N_146_bdd_4_lut.init = 16'hf0dd; + LUT4 i11_3_lut_rep_20 (.A(MAin_c_2), .B(n22), .C(MAin_c_5), .Z(n2369)) /* synthesis lut_function=(A (B (C))) */ ; + defparam i11_3_lut_rep_20.init = 16'h8080; + LUT4 i13_2_lut_rep_16_4_lut (.A(MAin_c_2), .B(n22), .C(MAin_c_5), + .D(n26), .Z(n2365)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; + defparam i13_2_lut_rep_16_4_lut.init = 16'hff7f; + GSR GSR_INST (.GSR(VCC_net)); + LUT4 i1_4_lut_adj_4 (.A(n2180), .B(n2225), .C(n8), .D(n2382), .Z(ADSubmitted_N_246)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i1_4_lut_adj_4.init = 16'h2000; + LUT4 i6_4_lut (.A(FS[11]), .B(n12), .C(FS[14]), .D(FS[17]), .Z(n13_adj_6)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i6_4_lut.init = 16'h8000; + LUT4 i8_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]), + .Z(n22)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i8_4_lut.init = 16'h8000; + LUT4 i1_2_lut_3_lut_4_lut_adj_5 (.A(n2369), .B(n26), .C(MAin_c_0), + .D(MAin_c_1), .Z(n2225)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; + defparam i1_2_lut_3_lut_4_lut_adj_5.init = 16'hdfff; + LUT4 i5_4_lut (.A(FS[13]), .B(FS[12]), .C(FS[15]), .D(FS[16]), .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i5_4_lut.init = 16'h8000; + LUT4 i12_4_lut (.A(Bank[2]), .B(n2277), .C(n2287), .D(Bank[5]), + .Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; + defparam i12_4_lut.init = 16'hbfff; + LUT4 i2_3_lut_4_lut_adj_6 (.A(n2369), .B(n26), .C(MAin_c_0), .D(MAin_c_1), + .Z(n1277)) /* synthesis lut_function=((B+((D)+!C))+!A) */ ; + defparam i2_3_lut_4_lut_adj_6.init = 16'hffdf; + LUT4 i637_1_lut_rep_31 (.A(Ready), .Z(n2380)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i637_1_lut_rep_31.init = 16'h5555; + LUT4 i1573_4_lut (.A(n2367), .B(n2377), .C(InitReady), .D(n4_adj_7), + .Z(RCLK_c_enable_15)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15]) + defparam i1573_4_lut.init = 16'hcac0; + LUT4 i3_4_lut_adj_7 (.A(FS[17]), .B(FS[13]), .C(FS[15]), .D(FS[16]), + .Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i3_4_lut_adj_7.init = 16'hfffe; + LUT4 i786_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_34), .Z(n1060)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(195[13] 231[7]) + defparam i786_2_lut.init = 16'heeee; + LUT4 i1_4_lut_adj_8 (.A(FS[4]), .B(n15), .C(n13), .D(n14), .Z(n4_adj_7)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; + defparam i1_4_lut_adj_8.init = 16'h0002; + LUT4 i2_2_lut_3_lut_4_lut (.A(nRCS_N_139), .B(n2381), .C(Ready), .D(nRCAS_N_165), + .Z(n2036)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam i2_2_lut_3_lut_4_lut.init = 16'hfffb; + LUT4 i2_3_lut_4_lut_4_lut (.A(Ready), .B(n1060), .C(nRowColSel_N_32), + .D(nRowColSel_N_35), .Z(RCLK_c_enable_5)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i2_3_lut_4_lut_4_lut.init = 16'hfffd; + CCU2D FS_610_add_4_11 (.A0(FS[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1996), + .COUT(n1997), .S0(n86), .S1(n85)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_11.INIT0 = 16'hfaaa; + defparam FS_610_add_4_11.INIT1 = 16'hfaaa; + defparam FS_610_add_4_11.INJECT1_0 = "NO"; + defparam FS_610_add_4_11.INJECT1_1 = "NO"; + LUT4 i1603_3_lut (.A(n1893), .B(CmdUFMCLK), .C(InitReady), .Z(UFMCLK_N_224)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15]) + defparam i1603_3_lut.init = 16'hcaca; + LUT4 i1979_4_lut (.A(MAin_c_6), .B(MAin_c_4), .C(Bank[7]), .D(Bank[0]), + .Z(n2277)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i1979_4_lut.init = 16'h8000; + FD1P3AX IS_FSM__i15 (.D(n726), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(Ready_N_296)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i15.GSR = "ENABLED"; + LUT4 i771_2_lut_rep_23_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2372)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i771_2_lut_rep_23_2_lut.init = 16'hdddd; + LUT4 i6_4_lut_adj_9 (.A(FS[5]), .B(FS[7]), .C(FS[1]), .D(FS[2]), + .Z(n15)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i6_4_lut_adj_9.init = 16'hfffe; + LUT4 i1970_4_lut (.A(FS[4]), .B(n13_adj_6), .C(n2267), .D(FS[1]), + .Z(n1893)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15]) + defparam i1970_4_lut.init = 16'h3a0a; + LUT4 i1_2_lut_2_lut (.A(Ready), .B(nRowColSel_N_34), .Z(n6)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i1_2_lut_2_lut.init = 16'hdddd; + PFUMX i30 (.BLUT(n13_adj_8), .ALUT(n9), .C0(nRowColSel_N_35), .Z(n15_adj_4)); + FD1P3AX IS_FSM__i14 (.D(n727), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n726)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i14.GSR = "ENABLED"; + FD1P3AX IS_FSM__i13 (.D(n728), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n727)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i13.GSR = "ENABLED"; + LUT4 i1989_2_lut (.A(Bank[6]), .B(Bank[3]), .Z(n2287)) /* synthesis lut_function=(A (B)) */ ; + defparam i1989_2_lut.init = 16'h8888; + LUT4 i2_3_lut_rep_32 (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), + .Z(n2381)) /* synthesis lut_function=(A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20]) + defparam i2_3_lut_rep_32.init = 16'h8080; + LUT4 i1_2_lut_rep_22_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), + .D(nRCS_N_139), .Z(n2371)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20]) + defparam i1_2_lut_rep_22_4_lut.init = 16'hff7f; + FD1P3AX IS_FSM__i12 (.D(n729), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n728)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i12.GSR = "ENABLED"; + FD1P3AX XOR8MEG_408 (.D(XOR8MEG_N_110), .SP(PHI2_N_120_enable_3), .CK(PHI2_N_120), + .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam XOR8MEG_408.GSR = "ENABLED"; + FD1P3AX n8MEGEN_418 (.D(n8MEGEN_N_91), .SP(RCLK_c_enable_15), .CK(RCLK_c), + .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam n8MEGEN_418.GSR = "ENABLED"; + CCU2D FS_610_add_4_19 (.A0(FS[17]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2000), + .S0(n78)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_19.INIT0 = 16'hfaaa; + defparam FS_610_add_4_19.INIT1 = 16'h0000; + defparam FS_610_add_4_19.INJECT1_0 = "NO"; + defparam FS_610_add_4_19.INJECT1_1 = "NO"; + FD1P3AX LEDEN_419 (.D(n2447), .SP(RCLK_c_enable_16), .CK(RCLK_c), + .Q(LEDEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam LEDEN_419.GSR = "ENABLED"; + FD1P3AX Ready_404 (.D(n2447), .SP(Ready_N_292), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam Ready_404.GSR = "ENABLED"; + FD1P3AX CmdUFMCLK_413 (.D(Din_c_1), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), + .Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMCLK_413.GSR = "ENABLED"; + FD1P3AX CmdUFMSDI_414 (.D(Din_c_0), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), + .Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMSDI_414.GSR = "ENABLED"; + FD1P3AX Cmdn8MEGEN_410 (.D(Cmdn8MEGEN_N_264), .SP(PHI2_N_120_enable_6), + .CK(PHI2_N_120), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam Cmdn8MEGEN_410.GSR = "ENABLED"; + FD1P3AX CmdSubmitted_411 (.D(n2447), .SP(PHI2_N_120_enable_7), .CK(PHI2_N_120), + .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdSubmitted_411.GSR = "ENABLED"; + FD1P3AX CmdUFMCS_412 (.D(Din_c_2), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), + .Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMCS_412.GSR = "ENABLED"; + FD1P3AX IS_FSM__i11 (.D(n730), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n729)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i11.GSR = "ENABLED"; + LUT4 i2008_2_lut_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), + .D(Ready), .Z(RCLK_c_enable_27)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20]) + defparam i2008_2_lut_4_lut.init = 16'h0080; + LUT4 i1404_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), .Z(RCKE_N_132)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(15[12:17]) + defparam i1404_4_lut.init = 16'hcfc8; + LUT4 i1118_1_lut (.A(nRowColSel_N_34), .Z(n1407)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1118_1_lut.init = 16'h5555; + FD1P3AX IS_FSM__i10 (.D(nRWE_N_177), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n730)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i10.GSR = "ENABLED"; + LUT4 i1_2_lut_adj_10 (.A(RASr2), .B(nRowColSel_N_32), .Z(n1406)) /* synthesis lut_function=(!((B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam i1_2_lut_adj_10.init = 16'h2222; + LUT4 i1439_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_32), .Z(n827)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1439_2_lut.init = 16'heeee; + FD1P3AX IS_FSM__i9 (.D(n732), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(nRWE_N_177)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i9.GSR = "ENABLED"; + LUT4 i1432_4_lut (.A(FWEr), .B(n2372), .C(n1060), .D(n2376), .Z(n917)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i1432_4_lut.init = 16'h3032; + LUT4 i1_2_lut_rep_33 (.A(Din_c_0), .B(Din_c_2), .Z(n2382)) /* synthesis lut_function=(A (B)) */ ; + defparam i1_2_lut_rep_33.init = 16'h8888; + LUT4 i1_4_lut_4_lut (.A(CBR), .B(n2227), .C(FWEr), .D(nRowColSel_N_34), + .Z(n13_adj_8)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[27:31]) + defparam i1_4_lut_4_lut.init = 16'h5540; + LUT4 i4_2_lut (.A(FS[8]), .B(FS[0]), .Z(n13)) /* synthesis lut_function=(A+(B)) */ ; + defparam i4_2_lut.init = 16'heeee; + LUT4 i1589_4_lut (.A(n2174), .B(CmdUFMSDI), .C(InitReady), .D(n4), + .Z(UFMSDI_N_231)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15]) + defparam i1589_4_lut.init = 16'hcac0; + LUT4 i2_1_lut_rep_24 (.A(nFWE_c), .Z(n2373)) /* synthesis lut_function=(!(A)) */ ; + defparam i2_1_lut_rep_24.init = 16'h5555; + LUT4 i2_3_lut_4_lut_adj_11 (.A(Din_c_0), .B(Din_c_2), .C(n2260), .D(Din_c_3), + .Z(XOR8MEG_N_110)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; + defparam i2_3_lut_4_lut_adj_11.init = 16'h0008; + FD1P3AX IS_FSM__i8 (.D(n733), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n732)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i8.GSR = "ENABLED"; + FD1P3AX IS_FSM__i7 (.D(n734), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n733)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i7.GSR = "ENABLED"; + FD1P3AX IS_FSM__i6 (.D(n735), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n734)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i6.GSR = "ENABLED"; + FD1P3AX IS_FSM__i5 (.D(n736), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n735)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i5.GSR = "ENABLED"; + FD1P3AX IS_FSM__i4 (.D(n737), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n736)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i4.GSR = "ENABLED"; + FD1P3AX IS_FSM__i3 (.D(n738), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n737)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i3.GSR = "ENABLED"; + FD1P3AX IS_FSM__i2 (.D(nRCAS_N_165), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n738)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i2.GSR = "ENABLED"; + FD1P3AX IS_FSM__i1 (.D(nRCS_N_139), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(nRCAS_N_165)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i1.GSR = "ENABLED"; + FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_c__inv), .CD(n2380), .Q(RBA_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RBA__i2.GSR = "ENABLED"; + FD1S3AX FS_610__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i17.GSR = "ENABLED"; + FD1S3AX FS_610__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i16.GSR = "ENABLED"; + FD1S3AX FS_610__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i15.GSR = "ENABLED"; + FD1S3AX FS_610__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i14.GSR = "ENABLED"; + FD1S3AX FS_610__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i13.GSR = "ENABLED"; + FD1S3AX FS_610__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i12.GSR = "ENABLED"; + FD1S3AX FS_610__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i11.GSR = "ENABLED"; + FD1S3AX FS_610__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i10.GSR = "ENABLED"; + FD1S3AX FS_610__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i9.GSR = "ENABLED"; + FD1S3AX FS_610__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i8.GSR = "ENABLED"; + FD1S3AX FS_610__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i7.GSR = "ENABLED"; + FD1S3AX FS_610__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i6.GSR = "ENABLED"; + FD1S3AX FS_610__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i5.GSR = "ENABLED"; + FD1S3AX FS_610__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i4.GSR = "ENABLED"; + FD1S3AX FS_610__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i3.GSR = "ENABLED"; + FD1S3AX FS_610__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i2.GSR = "ENABLED"; + FD1S3AX FS_610__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i1.GSR = "ENABLED"; + FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i7.GSR = "ENABLED"; + FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i6.GSR = "ENABLED"; + FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i5.GSR = "ENABLED"; + FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i4.GSR = "ENABLED"; + FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i3.GSR = "ENABLED"; + FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i2.GSR = "ENABLED"; + FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i1.GSR = "ENABLED"; + FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_c__inv), .PD(n2380), .Q(RowA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i9.GSR = "ENABLED"; + FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i8.GSR = "ENABLED"; + FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i7.GSR = "ENABLED"; + FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i6.GSR = "ENABLED"; + FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_c__inv), .PD(n2380), .Q(RowA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i5.GSR = "ENABLED"; + FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i4.GSR = "ENABLED"; + FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i3.GSR = "ENABLED"; + FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i2.GSR = "ENABLED"; + FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i1.GSR = "ENABLED"; + FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i7.GSR = "ENABLED"; + LUT4 i2_3_lut_3_lut (.A(nFWE_c), .B(Din_c_5), .C(Din_c_3), .Z(n2180)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; + defparam i2_3_lut_3_lut.init = 16'h4040; + LUT4 i1_2_lut_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4), .Z(n6_adj_2)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) + defparam i1_2_lut_3_lut.init = 16'h1010; + LUT4 RASr2_I_0_1_lut_rep_25 (.A(RASr2), .Z(n2374)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46]) + defparam RASr2_I_0_1_lut_rep_25.init = 16'h5555; + LUT4 i1_4_lut_4_lut_adj_12 (.A(RASr2), .B(n6_adj_3), .C(nRowColSel_N_32), + .D(Ready), .Z(Ready_N_292)) /* synthesis lut_function=(A (D)+!A (B (C+(D))+!B (D))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46]) + defparam i1_4_lut_4_lut_adj_12.init = 16'hff40; + LUT4 i1_4_lut_adj_13 (.A(Din_c_2), .B(n2055), .C(MAin_c_0), .D(n2362), + .Z(C1Submitted_N_237)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; + defparam i1_4_lut_adj_13.init = 16'h0004; + FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i6.GSR = "ENABLED"; + FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i5.GSR = "ENABLED"; + FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i4.GSR = "ENABLED"; + FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i3.GSR = "ENABLED"; + FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i2.GSR = "ENABLED"; + FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i1.GSR = "ENABLED"; + CCU2D FS_610_add_4_5 (.A0(FS[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1993), + .COUT(n1994), .S0(n92), .S1(n91)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_5.INIT0 = 16'hfaaa; + defparam FS_610_add_4_5.INIT1 = 16'hfaaa; + defparam FS_610_add_4_5.INJECT1_0 = "NO"; + defparam FS_610_add_4_5.INJECT1_1 = "NO"; + BB Dout_pad_6__714 (.I(WRD[6]), .T(n984), .B(RD[6]), .O(Dout_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + LUT4 i2_3_lut_4_lut_adj_14 (.A(n2369), .B(n26), .C(n2180), .D(n2204), + .Z(PHI2_N_120_enable_8)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; + defparam i2_3_lut_4_lut_adj_14.init = 16'h2000; + BB Dout_pad_5__715 (.I(WRD[5]), .T(n984), .B(RD[5]), .O(Dout_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_4__716 (.I(WRD[4]), .T(n984), .B(RD[4]), .O(Dout_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_3__717 (.I(WRD[3]), .T(n984), .B(RD[3]), .O(Dout_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_2__718 (.I(WRD[2]), .T(n984), .B(RD[2]), .O(Dout_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + LUT4 i1_2_lut_3_lut_adj_15 (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), + .Z(n1314)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) + defparam i1_2_lut_3_lut_adj_15.init = 16'hfefe; + BB Dout_pad_1__719 (.I(WRD[1]), .T(n984), .B(RD[1]), .O(Dout_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_0__720 (.I(WRD[0]), .T(n984), .B(RD[0]), .O(Dout_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + OB Dout_pad_7 (.I(Dout_c), .O(Dout[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_6 (.I(Dout_0), .O(Dout[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_5 (.I(Dout_1), .O(Dout[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_4 (.I(Dout_2), .O(Dout[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_3 (.I(Dout_3), .O(Dout[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_2 (.I(Dout_4), .O(Dout[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_1 (.I(Dout_5), .O(Dout[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_0 (.I(Dout_6), .O(Dout[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB LED_pad (.I(LED_c), .O(LED)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) + OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + OB RA_pad_11 (.I(RA_c), .O(RA[11])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_10 (.I(RA_0), .O(RA[10])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_9 (.I(RA_1_9), .O(RA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_8 (.I(RA_1_8), .O(RA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_7 (.I(RA_1_7), .O(RA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_6 (.I(RA_1_6), .O(RA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_5 (.I(RA_1_5), .O(RA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_4 (.I(RA_1_4), .O(RA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_3 (.I(RA_1_3), .O(RA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_2 (.I(RA_1_2), .O(RA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_1 (.I(RA_1_1), .O(RA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_0 (.I(RA_1_0), .O(RA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB nRCS_pad (.I(nRCS_c), .O(nRCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) + OB RCKE_pad (.I(RCKE_c), .O(RCKE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) + OB nRWE_pad (.I(nRWE_c), .O(nRWE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) + OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) + OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) + OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) + OB RDQML_pad (.I(RDQML_c), .O(RDQML)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) + OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) + OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) + OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) + IB PHI2_pad (.I(PHI2), .O(PHI2_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + IB Din_pad_7 (.I(Din[7]), .O(Din_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_6 (.I(Din[6]), .O(Din_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_5 (.I(Din[5]), .O(Din_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_4 (.I(Din[4]), .O(Din_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_3 (.I(Din[3]), .O(Din_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_2 (.I(Din[2]), .O(Din_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_1 (.I(Din[1]), .O(Din_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_0 (.I(Din[0]), .O(Din_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + IB nFWE_pad (.I(nFWE), .O(nFWE_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) + IB RCLK_pad (.I(RCLK), .O(RCLK_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) + CCU2D FS_610_add_4_17 (.A0(FS[15]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1999), + .COUT(n2000), .S0(n80), .S1(n79)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_17.INIT0 = 16'hfaaa; + defparam FS_610_add_4_17.INIT1 = 16'hfaaa; + defparam FS_610_add_4_17.INJECT1_0 = "NO"; + defparam FS_610_add_4_17.INJECT1_1 = "NO"; + LUT4 i1_2_lut_rep_14_3_lut (.A(n2369), .B(n26), .C(nFWE_c), .Z(n2363)) /* synthesis lut_function=((B+(C))+!A) */ ; + defparam i1_2_lut_rep_14_3_lut.init = 16'hfdfd; + LUT4 i1_2_lut_rep_13_3_lut (.A(n2369), .B(n26), .C(MAin_c_1), .Z(n2362)) /* synthesis lut_function=((B+!(C))+!A) */ ; + defparam i1_2_lut_rep_13_3_lut.init = 16'hdfdf; + LUT4 i2010_3_lut_3_lut (.A(nCRAS_c), .B(LEDEN), .C(CBR), .Z(LED_c)) /* synthesis lut_function=(A+((C)+!B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[17:23]) + defparam i2010_3_lut_3_lut.init = 16'hfbfb; + LUT4 i5_3_lut (.A(FS[3]), .B(FS[9]), .C(FS[6]), .Z(n14)) /* synthesis lut_function=(A+(B+(C))) */ ; + defparam i5_3_lut.init = 16'hfefe; + LUT4 i4_4_lut_adj_16 (.A(nRowColSel_N_35), .B(nRowColSel_N_33), .C(nRowColSel_N_32), + .D(n6), .Z(RCLK_c_enable_6)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i4_4_lut_adj_16.init = 16'hfffe; + LUT4 i4_4_lut_adj_17 (.A(n7), .B(FS[8]), .C(FS[10]), .D(n10), .Z(n2174)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i4_4_lut_adj_17.init = 16'h0002; + LUT4 i34_4_lut (.A(n7_adj_5), .B(ADSubmitted), .C(C1Submitted_N_237), + .D(n2363), .Z(PHI2_N_120_enable_1)) /* synthesis lut_function=(A (B (C))+!A (B (C+!(D))+!B !(C+(D)))) */ ; + defparam i34_4_lut.init = 16'hc0c5; + LUT4 i13_3_lut (.A(MAin_c_0), .B(n2210), .C(MAin_c_1), .Z(n7_adj_5)) /* synthesis lut_function=(A (B (C))+!A (B+!(C))) */ ; + defparam i13_3_lut.init = 16'hc5c5; + LUT4 i1_2_lut_4_lut (.A(FS[11]), .B(n2368), .C(InitReady), .D(FS[10]), + .Z(n64)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i1_2_lut_4_lut.init = 16'hfffe; + LUT4 nRCS_N_137_I_0_4_lut (.A(nRCS_N_137), .B(n2379), .C(Ready), .D(nRowColSel_N_35), + .Z(nRRAS_N_156)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRCS_N_137_I_0_4_lut.init = 16'h3afa; + LUT4 i3_4_lut_adj_18 (.A(Din_c_5), .B(n2228), .C(n2183), .D(n2370), + .Z(n2055)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i3_4_lut_adj_18.init = 16'h1000; + LUT4 i1930_2_lut (.A(nFWE_c), .B(Din_c_4), .Z(n2228)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1930_2_lut.init = 16'heeee; + LUT4 i1110_2_lut_3_lut_4_lut (.A(nFWE_c), .B(n2365), .C(C1Submitted), + .D(MAin_c_1), .Z(n1398)) /* synthesis lut_function=(A (C)+!A (B (C)+!B !((D)+!C))) */ ; + defparam i1110_2_lut_3_lut_4_lut.init = 16'he0f0; + LUT4 i1_2_lut_adj_19 (.A(FS[11]), .B(FS[6]), .Z(n4)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_adj_19.init = 16'h8888; + LUT4 i2_4_lut_adj_20 (.A(n2375), .B(FS[7]), .C(FS[9]), .D(FS[5]), + .Z(n7)) /* synthesis lut_function=(!(A+(B (C)+!B !(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i2_4_lut_adj_20.init = 16'h1404; + LUT4 i1417_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n984)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1417_2_lut.init = 16'heeee; + LUT4 i2_4_lut_adj_21 (.A(n2228), .B(CmdEnable), .C(n1277), .D(n1314), + .Z(PHI2_N_120_enable_3)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; + defparam i2_4_lut_adj_21.init = 16'h0004; + LUT4 i3_4_lut_adj_22 (.A(Din_c_5), .B(n2191), .C(C1Submitted), .D(n2208), + .Z(n2210)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i3_4_lut_adj_22.init = 16'h0800; + LUT4 i1_2_lut_adj_23 (.A(nRowColSel_N_33), .B(CASr2), .Z(n2227)) /* synthesis lut_function=(A+!(B)) */ ; + defparam i1_2_lut_adj_23.init = 16'hbbbb; + FD1P3AX InitReady_394 (.D(n2447), .SP(RCLK_c_enable_28), .CK(RCLK_c), + .Q(InitReady)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(134[9] 138[5]) + defparam InitReady_394.GSR = "ENABLED"; + LUT4 nRCS_I_0_448_3_lut (.A(nRCS_N_137), .B(nRCS_N_141), .C(Ready), + .Z(nRCS_N_136)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRCS_I_0_448_3_lut.init = 16'hcaca; + LUT4 i1969_2_lut_3_lut_4_lut (.A(FS[12]), .B(FS[14]), .C(FS[11]), + .D(n10), .Z(n2267)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1969_2_lut_3_lut_4_lut.init = 16'hffef; + LUT4 i1_2_lut_rep_19_3_lut (.A(FS[12]), .B(FS[14]), .C(n10), .Z(n2368)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_rep_19_3_lut.init = 16'hfefe; + LUT4 i2_3_lut_4_lut_adj_24 (.A(CBR), .B(CASr3), .C(FWEr), .D(CASr2), + .Z(nRCS_N_146)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam i2_3_lut_4_lut_adj_24.init = 16'h1000; + LUT4 i3_2_lut_rep_26 (.A(FS[12]), .B(FS[14]), .Z(n2375)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i3_2_lut_rep_26.init = 16'heeee; + LUT4 i1_2_lut_rep_27 (.A(CBR), .B(CASr3), .Z(n2376)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam i1_2_lut_rep_27.init = 16'heeee; + LUT4 i2_3_lut_rep_28 (.A(PHI2r3), .B(PHI2r2), .C(CmdSubmitted), .Z(n2377)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) + defparam i2_3_lut_rep_28.init = 16'h2020; + INV i2044 (.A(nCRAS_c), .Z(nCRAS_c__inv)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + FD1S3IX S_FSM_i2 (.D(n1406), .CK(RCLK_c), .CD(n1408), .Q(nRowColSel_N_34)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i2.GSR = "ENABLED"; + INV i2045 (.A(nCCAS_c), .Z(nCCAS_N_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + VLO i1 (.Z(GND_net)); + TSALL TSALL_INST (.TSALL(GND_net)); + PUR PUR_INST (.PUR(VCC_net)); + defparam PUR_INST.RST_PULSE = 1; + LUT4 i1_2_lut_4_lut_adj_25 (.A(PHI2r3), .B(PHI2r2), .C(CmdSubmitted), + .D(InitReady), .Z(RCLK_c_enable_10)) /* synthesis lut_function=(!(A (B (D)+!B !(C+!(D)))+!A (D))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) + defparam i1_2_lut_4_lut_adj_25.init = 16'h20ff; + LUT4 i1_2_lut_rep_29 (.A(FWEr), .B(CBR), .Z(n2378)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1_2_lut_rep_29.init = 16'heeee; + LUT4 m1_lut (.Z(n2447)) /* synthesis lut_function=1, syn_instantiated=1 */ ; + defparam m1_lut.init = 16'hffff; + LUT4 n8MEGEN_I_14_3_lut_4_lut (.A(InitReady), .B(n2367), .C(UFMSDO_c), + .D(Cmdn8MEGEN), .Z(n8MEGEN_N_91)) /* synthesis lut_function=(A (D)+!A !(B (C)+!B !(D))) */ ; + defparam n8MEGEN_I_14_3_lut_4_lut.init = 16'hbf04; + +endmodule +// +// Verilog Description of module TSALL +// module not written out since it is a black-box. +// + +// +// Verilog Description of module PUR +// module not written out since it is a black-box. +// + diff --git a/CPLD/LCMXO2-1200HC/impl1/automake.log b/CPLD/LCMXO2-1200HC/impl1/automake.log new file mode 100644 index 0000000..bdf40a5 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/automake.log @@ -0,0 +1,1111 @@ + +synthesis -f "RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj" +synthesis: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:25 2023 + + +Command Line: synthesis -f RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml + + +Synthesis options: +The -a option is MachXO2. +The -s option is 4. +The -t option is TQFP100. +The -d option is LCMXO2-1200HC. +Using package TQFP100. +Using performance grade 4. + + +########################################################## + +### Lattice Family : MachXO2 + +### Device : LCMXO2-1200HC + +### Package : TQFP100 + +### Speed : 4 + +########################################################## + + + + +Optimization goal = Balanced +Top-level module name = RAM2GS. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added) +-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1 (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added) +Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v +NGD file = RAM2GS_LCMXO2_1200HC_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 +Compile design. +Compile Design Begin +Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 +Top module name (Verilog): RAM2GS + + + + +Last elaborated design is RAM2GS() +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Top-level module name = RAM2GS. + +original encoding -> new encoding (one-hot encoding) + + 0000 -> 0000000000000001 + + 0001 -> 0000000000000010 + + 0010 -> 0000000000000100 + + 0011 -> 0000000000001000 + + 0100 -> 0000000000010000 + + 0101 -> 0000000000100000 + + 0110 -> 0000000001000000 + + 0111 -> 0000000010000000 + + 1000 -> 0000000100000000 + + 1001 -> 0000001000000000 + + 1010 -> 0000010000000000 + + 1011 -> 0000100000000000 + + 1100 -> 0001000000000000 + + 1101 -> 0010000000000000 + + 1110 -> 0100000000000000 + + 1111 -> 1000000000000000 + + +original encoding -> new encoding (one-hot encoding) + + 00 -> 0001 + + 01 -> 0010 + + 10 -> 0100 + + 11 -> 1000 + + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. + +Applying 200.000000 MHz constraint to all clocks + + +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 309 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO2_1200HC_impl1.ngd. + +################### Begin Area Report (RAM2GS)###################### +Number of register bits => 102 of 1520 (6 % ) +BB => 8 +CCU2D => 10 +FD1P3AX => 29 +FD1P3AY => 5 +FD1P3IX => 3 +FD1S3AX => 47 +FD1S3IX => 14 +FD1S3JX => 4 +GSR => 1 +IB => 26 +INV => 3 +LUT4 => 122 +OB => 33 +PFUMX => 1 +################### End Area Report ################## + +################### Begin BlackBox Report ###################### +TSALL => 1 +################### End BlackBox Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 4 + Net : RCLK_c, loads : 62 + Net : PHI2_c, loads : 11 + Net : nCCAS_c, loads : 2 + Net : nCRAS_c, loads : 2 +Clock Enable Nets +Number of Clock Enables: 14 +Top 10 highest fanout Clock Enables: + Net : RCLK_c_enable_27, loads : 16 + Net : RCLK_c_enable_6, loads : 4 + Net : PHI2_N_120_enable_8, loads : 3 + Net : RCLK_c_enable_10, loads : 3 + Net : RCLK_c_enable_5, loads : 2 + Net : PHI2_N_120_enable_3, loads : 1 + Net : Ready_N_292, loads : 1 + Net : PHI2_N_120_enable_2, loads : 1 + Net : RCLK_c_enable_15, loads : 1 + Net : PHI2_N_120_enable_6, loads : 1 +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : RCLK_c_enable_27, loads : 16 + Net : InitReady, loads : 15 + Net : nCRAS_c__inv, loads : 15 + Net : RASr2, loads : 14 + Net : nRowColSel_N_35, loads : 13 + Net : n2380, loads : 13 + Net : nRowColSel, loads : 12 + Net : Ready, loads : 12 + Net : Din_c_4, loads : 10 + Net : MAin_c_1, loads : 10 +################### End Clock Report ################## + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 200.000 MHz| 50.413 MHz| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 200.000 MHz| 120.207 MHz| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + + +Peak Memory Usage: 55.238 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 0.891 secs +-------------------------------------------------------------- + +map -a "MachXO2" -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial "RAM2GS_LCMXO2_1200HC_impl1.ngd" -o "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -pr "RAM2GS_LCMXO2_1200HC_impl1.prf" -mp "RAM2GS_LCMXO2_1200HC_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.lpf" -c 0 +map: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + Process the file: RAM2GS_LCMXO2_1200HC_impl1.ngd + Picdevice="LCMXO2-1200HC" + + Pictype="TQFP100" + + Picspeed=4 + + Remove unused logic + + Do not produce over sized NCDs. + +Part used: LCMXO2-1200HCTQFP100, Performance used: 4. + +Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. + +Running general design DRC... + +Removing unused logic... + +Optimizing... + + + + +Design Summary: + Number of registers: 102 out of 1520 (7%) + PFU registers: 102 out of 1280 (8%) + PIO registers: 0 out of 240 (0%) + Number of SLICEs: 75 out of 640 (12%) + SLICEs as Logic/ROM: 75 out of 640 (12%) + SLICEs as RAM: 0 out of 480 (0%) + SLICEs as Carry: 10 out of 640 (2%) + Number of LUT4s: 143 out of 1280 (11%) + Number used as logic LUTs: 123 + Number used as distributed RAM: 0 + Number used as ripple logic: 20 + Number used as shift registers: 0 + Number of PIO sites used: 67 + 4(JTAG) out of 80 (89%) + Number of block RAMs: 0 out of 7 (0%) + Number of GSRs: 0 out of 1 (0%) + EFB used : No + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + POR : On + Bandgap : On + Number of Power Controller: 0 out of 1 (0%) + Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) + Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) + Number of DCCA: 0 out of 8 (0%) + Number of DCMA: 0 out of 2 (0%) + Number of PLLs: 0 out of 1 (0%) + Number of DQSDLLs: 0 out of 2 (0%) + Number of CLKDIVC: 0 out of 4 (0%) + Number of ECLKSYNCA: 0 out of 4 (0%) + Number of ECLKBRIDGECS: 0 out of 2 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. + Number of clocks: 4 + Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Number of Clock Enables: 14 + Net RCLK_c_enable_6: 4 loads, 4 LSLICEs + Net RCLK_c_enable_5: 2 loads, 2 LSLICEs + Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs + Net RCLK_c_enable_27: 8 loads, 8 LSLICEs + Net RCLK_c_enable_10: 3 loads, 3 LSLICEs + Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_16: 1 loads, 1 LSLICEs + Net RCLK_c_enable_28: 1 loads, 1 LSLICEs + Net RCLK_c_enable_15: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs + Net Ready_N_292: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs + Number of LSRs: 7 + Net RASr2: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net nRWE_N_177: 1 loads, 1 LSLICEs + Net C1Submitted_N_237: 2 loads, 2 LSLICEs + Net n2366: 2 loads, 2 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 18 loads + Net InitReady: 15 loads + Net RASr2: 15 loads + Net nRowColSel_N_35: 13 loads + Net nRowColSel: 12 loads + Net Din_c_4: 10 loads + Net MAin_c_1: 10 loads + Net Din_c_5: 9 loads + Net MAin_c_0: 9 loads + Net Din_c_0: 8 loads + + + Number of warnings: 0 + Number of errors: 0 + + + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 41 MB + +Dumping design to file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. + +ncd2vdb "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO2_1200HC_impl1_map.vdb" + +Loading device for application ncd2vdb from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. + +trce -f "RAM2GS_LCMXO2_1200HC_impl1.mt" -o "RAM2GS_LCMXO2_1200HC_impl1.tw1" "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" "RAM2GS_LCMXO2_1200HC_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:28 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd +Preference file: ram2gs_lcmxo2_1200hc_impl1.prf +Device,speed: LCMXO2-1200HC,4 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 349 Score: 848079 +Cumulative negative slack: 584487 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:28 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd +Preference file: ram2gs_lcmxo2_1200hc_impl1.prf +Device,speed: LCMXO2-1200HC,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 349 (setup), 0 (hold) +Score: 848079 (setup), 0 (hold) +Cumulative negative slack: 584487 (584487+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 48 MB + + +ldbanno "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -n Verilog -o "RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a Verilog netlist using the orca library type based on the RAM2GS_LCMXO2_1200HC_impl1_map design file. + + +Loading design for application ldbanno from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application ldbanno from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Converting design RAM2GS_LCMXO2_1200HC_impl1_map.ncd into .ldb format. +Writing Verilog netlist to file RAM2GS_LCMXO2_1200HC_impl1_mapvo.vo +Writing SDF timing to file RAM2GS_LCMXO2_1200HC_impl1_mapvo.sdf + +Total CPU Time: 1 secs +Total REAL Time: 2 secs +Peak Memory Usage: 41 MB + +ldbanno "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" -n VHDL -o "RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a VHDL netlist using the orca library type based on the RAM2GS_LCMXO2_1200HC_impl1_map design file. + + +Loading design for application ldbanno from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application ldbanno from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Converting design RAM2GS_LCMXO2_1200HC_impl1_map.ncd into .ldb format. +Writing VHDL netlist to file RAM2GS_LCMXO2_1200HC_impl1_mapvho.vho +Writing SDF timing to file RAM2GS_LCMXO2_1200HC_impl1_mapvho.sdf + +Total CPU Time: 1 secs +Total REAL Time: 0 secs +Peak Memory Usage: 40 MB + +mpartrce -p "RAM2GS_LCMXO2_1200HC_impl1.p2t" -f "RAM2GS_LCMXO2_1200HC_impl1.p3t" -tf "RAM2GS_LCMXO2_1200HC_impl1.pt" "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" "RAM2GS_LCMXO2_1200HC_impl1.ncd" + +---- MParTrce Tool ---- +Removing old design directory at request of -rem command line option to this program. +Running par. Please wait . . . + +Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd" +Tue Aug 15 05:03:31 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67+4(JTAG)/108 66% used + 67+4(JTAG)/80 89% bonded + + SLICE 75/640 11% used + + + +Number of Signals: 285 +Number of Connections: 674 + + +Pin Constraint Summary: + 66 out of 67 pins locked (98% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + + + + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + + +No signal is selected as Global Set/Reset. +. +Starting Placer Phase 0. +.......... +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +................... +Placer score = 143529. +Finished Placer Phase 1. REAL time: 4 secs + +Starting Placer Phase 2. +. +Placer score = 143450 +Finished Placer Phase 2. REAL time: 4 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 0 out of 8 (0%) + General PIO: 3 out of 108 (2%) + PLL : 0 out of 1 (0%) + DCM : 0 out of 2 (0%) + DCC : 0 out of 8 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 8 (25%) + SECONDARY: 1 out of 8 (12%) + +Edge Clocks: + No edge clock selected. + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 + 4(JTAG) out of 108 (65.7%) PIO sites used. + 67 + 4(JTAG) out of 80 (88.8%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+-----------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref | ++----------+----------------+------------+-----------+ +| 0 | 13 / 19 ( 68%) | 2.5V | - | +| 1 | 20 / 21 ( 95%) | 2.5V | - | +| 2 | 17 / 20 ( 85%) | 2.5V | - | +| 3 | 17 / 20 ( 85%) | 2.5V | - | ++----------+----------------+------------+-----------+ + +Total placer CPU time: 4 secs + +Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. + +0 connections routed; 674 unrouted. +Starting router resource preassignment + + + + + +Completed router resource preassignment. Real time: 7 secs + +Start NBR router at 05:03:38 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:38 08/15/23 + +Start NBR section for initial routing at 05:03:38 08/15/23 +Level 1, iteration 1 +2(0.00%) conflicts; 537(79.67%) untouched conns; 468417 (nbr) score; +Estimated worst slack/total negative slack: -5.186ns/-468.418ns; real time: 7 secs +Level 2, iteration 1 +11(0.01%) conflicts; 474(70.33%) untouched conns; 377050 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-377.051ns; real time: 8 secs +Level 3, iteration 1 +20(0.02%) conflicts; 254(37.69%) untouched conns; 373495 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-373.496ns; real time: 8 secs +Level 4, iteration 1 +11(0.01%) conflicts; 0(0.00%) untouched conn; 386254 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-386.255ns; real time: 8 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:39 08/15/23 +Level 1, iteration 1 +7(0.01%) conflicts; 4(0.59%) untouched conns; 379537 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-379.537ns; real time: 8 secs +Level 4, iteration 1 +9(0.01%) conflicts; 0(0.00%) untouched conn; 380799 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-380.800ns; real time: 8 secs +Level 4, iteration 2 +6(0.01%) conflicts; 0(0.00%) untouched conn; 390586 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-390.587ns; real time: 8 secs +Level 4, iteration 3 +6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs +Level 4, iteration 4 +6(0.01%) conflicts; 0(0.00%) untouched conn; 384718 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-384.719ns; real time: 8 secs +Level 4, iteration 5 +4(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs +Level 4, iteration 6 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393013 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.014ns; real time: 8 secs +Level 4, iteration 7 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs +Level 4, iteration 8 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393874 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.875ns; real time: 8 secs +Level 4, iteration 9 +2(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs +Level 4, iteration 10 +3(0.00%) conflicts; 0(0.00%) untouched conn; 409288 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-409.289ns; real time: 8 secs +Level 4, iteration 11 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs +Level 4, iteration 12 +3(0.00%) conflicts; 0(0.00%) untouched conn; 393035 (nbr) score; +Estimated worst slack/total negative slack: -4.364ns/-393.036ns; real time: 8 secs +Level 4, iteration 13 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs +Level 4, iteration 14 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404326 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.327ns; real time: 8 secs +Level 4, iteration 15 +2(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 16 +3(0.00%) conflicts; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 17 +2(0.00%) conflicts; 0(0.00%) untouched conn; 404668 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs +Level 4, iteration 18 +1(0.00%) conflict; 0(0.00%) untouched conn; 404668 (nbr) score; +Estimated worst slack/total negative slack: -4.574ns/-404.669ns; real time: 8 secs +Level 4, iteration 19 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 20 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 21 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 22 +1(0.00%) conflict; 0(0.00%) untouched conn; 411533 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.534ns; real time: 8 secs +Level 4, iteration 23 +1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs +Level 4, iteration 24 +1(0.00%) conflict; 0(0.00%) untouched conn; 411276 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.277ns; real time: 8 secs +Level 4, iteration 25 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:39 08/15/23 +Level 4, iteration 1 +1(0.00%) conflict; 0(0.00%) untouched conn; 405829 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-405.830ns; real time: 8 secs +Level 4, iteration 2 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for re-routing at 05:03:39 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 411952 (nbr) score; +Estimated worst slack/total negative slack: -4.650ns/-411.953ns; real time: 8 secs + +Start NBR section for post-routing at 05:03:39 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 254 (37.69%) + Estimated worst slack : -4.650ns + Timing score : 391939 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + + + +Total CPU time 7 secs +Total REAL time: 8 secs +Completely routed. +End of route. 674 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 391939 + +Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -4.650 +PAR_SUMMARY::Timing score> = 391.939 +PAR_SUMMARY::Worst slack> = 0.304 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 8 secs +Total REAL time to completion: 8 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Exiting par with exit code 0 +Exiting mpartrce with exit code 0 + +trce -f "RAM2GS_LCMXO2_1200HC_impl1.pt" -o "RAM2GS_LCMXO2_1200HC_impl1.twr" "RAM2GS_LCMXO2_1200HC_impl1.ncd" "RAM2GS_LCMXO2_1200HC_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:40 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Design file: ram2gs_lcmxo2_1200hc_impl1.ncd +Preference file: ram2gs_lcmxo2_1200hc_impl1.prf +Device,speed: LCMXO2-1200HC,4 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 335 Score: 391939 +Cumulative negative slack: 304509 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:40 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_1200HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf +Design file: ram2gs_lcmxo2_1200hc_impl1.ncd +Preference file: ram2gs_lcmxo2_1200hc_impl1.prf +Device,speed: LCMXO2-1200HC,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 335 (setup), 0 (hold) +Score: 391939 (setup), 0 (hold) +Cumulative negative slack: 304509 (304509+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 46 MB + + +iotiming "RAM2GS_LCMXO2_1200HC_impl1.ncd" "RAM2GS_LCMXO2_1200HC_impl1.prf" +I/O Timing Report: +: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application iotiming from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: 4 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: 5 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 6 +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: 6 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: M +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: M +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... +Done. + +tmcheck -par "RAM2GS_LCMXO2_1200HC_impl1.par" + +bitgen -f "RAM2GS_LCMXO2_1200HC_impl1.t2b" -w "RAM2GS_LCMXO2_1200HC_impl1.ncd" -jedec "RAM2GS_LCMXO2_1200HC_impl1.prf" + + +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + + +Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| RamCfg | Reset** | ++---------------------------------+---------------------------------+ +| MCCLK_FREQ | 2.08** | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| JTAG_PORT | ENABLE** | ++---------------------------------+---------------------------------+ +| SDM_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| SLAVE_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MASTER_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| I2C_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MUX_CONFIGURATION_PORTS | DISABLE** | ++---------------------------------+---------------------------------+ +| CONFIGURATION | CFG** | ++---------------------------------+---------------------------------+ +| COMPRESS_CONFIG | ON** | ++---------------------------------+---------------------------------+ +| MY_ASSP | OFF** | ++---------------------------------+---------------------------------+ +| ONE_TIME_PROGRAM | OFF** | ++---------------------------------+---------------------------------+ +| ENABLE_TRANSFR | DISABLE** | ++---------------------------------+---------------------------------+ +| SHAREDEBRINIT | DISABLE** | ++---------------------------------+---------------------------------+ +| BACKGROUND_RECONFIG | OFF** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... + +Bitstream Status: Final Version 1.95. + +Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed". + +=========== +UFM Summary. +=========== +UFM Size: 511 Pages (128*511 Bits). +UFM Utilization: General Purpose Flash Memory. + +Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510). +Initialized UFM Pages: 0 Page. + +Total CPU Time: 2 secs +Total REAL Time: 3 secs +Peak Memory Usage: 253 MB diff --git a/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html new file mode 100644 index 0000000..2f2bbe3 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html @@ -0,0 +1,9 @@ + 
    Setting log file to 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
+(VERI-1482) Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-411,10) (VERI-9000) elaborating module 'RAM2GS'
+Done: design load finished with (0) errors, and (0) warnings
+
+
    \ No newline at end of file diff --git a/CPLD/LCMXO2-1200HC/impl1/impl1.xcf b/CPLD/LCMXO2-1200HC/impl1/impl1.xcf new file mode 100644 index 0000000..9cdf76b --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/impl1.xcf @@ -0,0 +1,55 @@ + + + + + + JTAG + + + 1 + Lattice + MachXO2 + LCMXO2-1200HC + 0x012ba043 + All + LCMXO2-1200HC + + 8 + 11111111 + 1 + 0 + + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed + 08/15/23 05:01:25 + 0x680B + FLASH Erase,Program,Verify + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB + EzUSB-0 + \\?\usb#vid_1134&amp;pid_8001#5&amp;887acb0&amp;0&amp;13# + + TRST ABSENT; + ISPEN ABSENT; + + + diff --git a/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior b/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior new file mode 100644 index 0000000..c8edb74 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1.ior @@ -0,0 +1,139 @@ +Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 6 +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: M +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +// Design: RAM2GS +// Package: TQFP100 +// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd +// Version: Diamond (64-bit) 3.12.1.454 +// Written on Tue Aug 15 05:03:41 2023 +// M: Minimum Performance Grade +// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml + +I/O Timing Report (All units are in ns) + +Worst Case Results across Performance Grades (M, 6, 5, 4): + +// Input Setup and Hold Times + +Port Clock Edge Setup Performance_Grade Hold Performance_Grade +---------------------------------------------------------------------- +CROW[0] nCRAS F 0.891 4 0.676 4 +CROW[1] nCRAS F 0.281 4 1.216 4 +Din[0] PHI2 F 7.907 4 0.089 6 +Din[0] nCCAS F 1.465 4 0.158 4 +Din[1] PHI2 F 7.300 4 1.026 4 +Din[1] nCCAS F 1.035 4 0.527 4 +Din[2] PHI2 F 6.237 4 1.467 4 +Din[2] nCCAS F 1.719 4 -0.108 M +Din[3] PHI2 F 6.623 4 0.176 6 +Din[3] nCCAS F 0.339 4 0.916 4 +Din[4] PHI2 F 6.902 4 1.033 4 +Din[4] nCCAS F 0.687 4 0.951 4 +Din[5] PHI2 F 6.837 4 1.369 4 +Din[5] nCCAS F 2.810 4 -0.220 M +Din[6] PHI2 F 7.648 4 -0.050 M +Din[6] nCCAS F 1.281 4 0.266 4 +Din[7] PHI2 F 7.823 4 -0.159 M +Din[7] nCCAS F 1.810 4 -0.096 M +MAin[0] PHI2 F 6.751 4 -0.273 M +MAin[0] nCRAS F 1.765 4 -0.033 4 +MAin[1] PHI2 F 5.718 4 0.117 M +MAin[1] nCRAS F 1.814 4 -0.051 M +MAin[2] PHI2 F 5.759 4 -0.021 M +MAin[2] nCRAS F 1.323 4 0.309 4 +MAin[3] PHI2 F 6.165 4 -0.235 M +MAin[3] nCRAS F 0.694 4 0.836 4 +MAin[4] PHI2 F 5.236 4 -0.147 M +MAin[4] nCRAS F 0.730 4 0.835 4 +MAin[5] PHI2 F 6.024 4 0.135 M +MAin[5] nCRAS F 0.734 4 0.868 4 +MAin[6] PHI2 F 5.689 4 -0.277 M +MAin[6] nCRAS F 0.288 4 1.210 4 +MAin[7] PHI2 F 6.398 4 -0.307 M +MAin[7] nCRAS F 1.215 4 0.401 4 +MAin[8] nCRAS F 0.817 4 0.727 4 +MAin[9] nCRAS F 0.941 4 0.601 4 +PHI2 RCLK R 0.771 4 1.143 4 +UFMSDO RCLK R -0.238 M 2.305 4 +nCCAS RCLK R 1.651 4 0.388 4 +nCCAS nCRAS F 5.028 4 -0.828 M +nCRAS RCLK R 0.593 4 1.309 4 +nFWE PHI2 F 5.741 4 0.781 4 +nFWE nCRAS F 0.578 4 0.996 4 + + +// Clock to Output Delay + +Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade +------------------------------------------------------------------------ +LED RCLK R 14.758 4 4.129 M +LED nCRAS F 12.396 4 3.434 M +RA[0] RCLK R 13.780 4 3.894 M +RA[0] nCRAS F 11.795 4 3.277 M +RA[10] RCLK R 12.425 4 3.587 M +RA[11] PHI2 R 10.432 4 3.084 M +RA[1] RCLK R 15.081 4 4.198 M +RA[1] nCRAS F 12.364 4 3.447 M +RA[2] RCLK R 14.518 4 4.082 M +RA[2] nCRAS F 11.696 4 3.275 M +RA[3] RCLK R 13.789 4 3.897 M +RA[3] nCRAS F 12.223 4 3.392 M +RA[4] RCLK R 15.175 4 4.228 M +RA[4] nCRAS F 12.424 4 3.464 M +RA[5] RCLK R 13.789 4 3.897 M +RA[5] nCRAS F 12.359 4 3.437 M +RA[6] RCLK R 15.420 4 4.299 M +RA[6] nCRAS F 12.865 4 3.560 M +RA[7] RCLK R 14.672 4 4.127 M +RA[7] nCRAS F 12.253 4 3.386 M +RA[8] RCLK R 14.952 4 4.191 M +RA[8] nCRAS F 12.244 4 3.383 M +RA[9] RCLK R 14.092 4 3.978 M +RA[9] nCRAS F 13.164 4 3.653 M +RBA[0] nCRAS F 10.278 4 2.970 M +RBA[1] nCRAS F 10.474 4 3.030 M +RCKE RCLK R 12.407 4 3.610 M +RDQMH RCLK R 13.754 4 3.857 M +RDQML RCLK R 13.482 4 3.833 M +RD[0] nCCAS F 10.515 4 3.076 M +RD[1] nCCAS F 10.118 4 2.965 M +RD[2] nCCAS F 9.759 4 2.886 M +RD[3] nCCAS F 9.798 4 2.878 M +RD[4] nCCAS F 10.979 4 3.178 M +RD[5] nCCAS F 11.063 4 3.207 M +RD[6] nCCAS F 10.317 4 3.018 M +RD[7] nCCAS F 10.232 4 2.986 M +UFMCLK RCLK R 12.402 4 3.606 M +UFMSDI RCLK R 11.975 4 3.501 M +nRCAS RCLK R 12.350 4 3.564 M +nRCS RCLK R 11.923 4 3.459 M +nRRAS RCLK R 11.995 4 3.494 M +nRWE RCLK R 11.975 4 3.501 M +nUFMCS RCLK R 11.818 4 3.434 M +WARNING: you must also run trce with hold speed: 4 +WARNING: you must also run trce with hold speed: 6 +WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1_trce.asd b/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1_trce.asd new file mode 100644 index 0000000..0894708 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/ram2gs_lcmxo2_1200hc_impl1_trce.asd @@ -0,0 +1,13 @@ +[ActiveSupport TRCE] +; Setup Analysis +Fmax_0 = 174.216 MHz (299.401 MHz); +Fmax_1 = 67.833 MHz (99.079 MHz); +Failed = 2 (Total 2); +Clock_ports = 4; +Clock_nets = 4; +; Hold Analysis +Fmax_0 = 0.304 ns (0.000 ns); +Fmax_1 = 0.379 ns (0.000 ns); +Failed = 0 (Total 2); +Clock_ports = 4; +Clock_nets = 4; diff --git a/CPLD/LCMXO2-1200HC/impl1/synthesis.log b/CPLD/LCMXO2-1200HC/impl1/synthesis.log new file mode 100644 index 0000000..fee4113 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/synthesis.log @@ -0,0 +1,239 @@ +synthesis: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:25 2023 + + +Command Line: synthesis -f RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml + +Synthesis options: +The -a option is MachXO2. +The -s option is 4. +The -t option is TQFP100. +The -d option is LCMXO2-1200HC. +Using package TQFP100. +Using performance grade 4. + + +########################################################## + +### Lattice Family : MachXO2 + +### Device : LCMXO2-1200HC + +### Package : TQFP100 + +### Speed : 4 + +########################################################## + + + +INFO - synthesis: User-Selected Strategy Settings +Optimization goal = Balanced +Top-level module name = RAM2GS. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added) +-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1 (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added) +Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v +NGD file = RAM2GS_LCMXO2_1200HC_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 +Compile design. +Compile Design Begin +Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 +Top module name (Verilog): RAM2GS +INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209 +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Top-level module name = RAM2GS. +INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding +original encoding -> new encoding (one-hot encoding) + + 0000 -> 0000000000000001 + + 0001 -> 0000000000000010 + + 0010 -> 0000000000000100 + + 0011 -> 0000000000001000 + + 0100 -> 0000000000010000 + + 0101 -> 0000000000100000 + + 0110 -> 0000000001000000 + + 0111 -> 0000000010000000 + + 1000 -> 0000000100000000 + + 1001 -> 0000001000000000 + + 1010 -> 0000010000000000 + + 1011 -> 0000100000000000 + + 1100 -> 0001000000000000 + + 1101 -> 0010000000000000 + + 1110 -> 0100000000000000 + + 1111 -> 1000000000000000 + +INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding +original encoding -> new encoding (one-hot encoding) + + 00 -> 0001 + + 01 -> 0010 + + 10 -> 0100 + + 11 -> 1000 + + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. +WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored. +Applying 200.000000 MHz constraint to all clocks + +WARNING - synthesis: No user .sdc file. +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO2_1200HC_impl1.ngd. + +################### Begin Area Report (RAM2GS)###################### +Number of register bits => 102 of 1520 (6 % ) +BB => 8 +CCU2D => 10 +FD1P3AX => 29 +FD1P3AY => 5 +FD1P3IX => 3 +FD1S3AX => 47 +FD1S3IX => 14 +FD1S3JX => 4 +GSR => 1 +IB => 26 +INV => 3 +LUT4 => 122 +OB => 33 +PFUMX => 1 +################### End Area Report ################## + +################### Begin BlackBox Report ###################### +TSALL => 1 +################### End BlackBox Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 4 + Net : RCLK_c, loads : 62 + Net : PHI2_c, loads : 11 + Net : nCCAS_c, loads : 2 + Net : nCRAS_c, loads : 2 +Clock Enable Nets +Number of Clock Enables: 14 +Top 10 highest fanout Clock Enables: + Net : RCLK_c_enable_27, loads : 16 + Net : RCLK_c_enable_6, loads : 4 + Net : PHI2_N_120_enable_8, loads : 3 + Net : RCLK_c_enable_10, loads : 3 + Net : RCLK_c_enable_5, loads : 2 + Net : PHI2_N_120_enable_3, loads : 1 + Net : Ready_N_292, loads : 1 + Net : PHI2_N_120_enable_2, loads : 1 + Net : RCLK_c_enable_15, loads : 1 + Net : PHI2_N_120_enable_6, loads : 1 +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : RCLK_c_enable_27, loads : 16 + Net : InitReady, loads : 15 + Net : nCRAS_c__inv, loads : 15 + Net : RASr2, loads : 14 + Net : nRowColSel_N_35, loads : 13 + Net : n2380, loads : 13 + Net : nRowColSel, loads : 12 + Net : Ready, loads : 12 + Net : Din_c_4, loads : 10 + Net : MAin_c_1, loads : 10 +################### End Clock Report ################## + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 200.000 MHz| 50.413 MHz| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 200.000 MHz| 120.207 MHz| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + + +Peak Memory Usage: 55.238 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 0.891 secs +-------------------------------------------------------------- diff --git a/CPLD/LCMXO2-1200HC/impl1/synthesis_lse.html b/CPLD/LCMXO2-1200HC/impl1/synthesis_lse.html new file mode 100644 index 0000000..1a480d5 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/synthesis_lse.html @@ -0,0 +1,304 @@ + +Synthesis and Ngdbuild Report + + +
    Synthesis and Ngdbuild  Report
+synthesis:  version Diamond (64-bit) 3.12.1.454
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:25 2023
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO2_1200HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml 
+
+Synthesis options:
+The -a option is MachXO2.
+The -s option is 4.
+The -t option is TQFP100.
+The -d option is LCMXO2-1200HC.
+Using package TQFP100.
+Using performance grade 4.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO2
+
+### Device  : LCMXO2-1200HC
+
+### Package : TQFP100
+
+### Speed   : 4
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC/impl1 (searchpath added)
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC (searchpath added)
+Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
+NGD file = RAM2GS_LCMXO2_1200HC_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.44.
+Top-level module name = RAM2GS.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO2_1200HC_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 102 of 1520 (6 % )
+BB => 8
+CCU2D => 10
+FD1P3AX => 29
+FD1P3AY => 5
+FD1P3IX => 3
+FD1S3AX => 47
+FD1S3IX => 14
+FD1S3JX => 4
+GSR => 1
+IB => 26
+INV => 3
+LUT4 => 122
+OB => 33
+PFUMX => 1
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 4
+  Net : RCLK_c, loads : 62
+  Net : PHI2_c, loads : 11
+  Net : nCCAS_c, loads : 2
+  Net : nCRAS_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 14
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_27, loads : 16
+  Net : RCLK_c_enable_6, loads : 4
+  Net : PHI2_N_120_enable_8, loads : 3
+  Net : RCLK_c_enable_10, loads : 3
+  Net : RCLK_c_enable_5, loads : 2
+  Net : PHI2_N_120_enable_3, loads : 1
+  Net : Ready_N_292, loads : 1
+  Net : PHI2_N_120_enable_2, loads : 1
+  Net : RCLK_c_enable_15, loads : 1
+  Net : PHI2_N_120_enable_6, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : RCLK_c_enable_27, loads : 16
+  Net : InitReady, loads : 15
+  Net : nCRAS_c__inv, loads : 15
+  Net : RASr2, loads : 14
+  Net : nRowColSel_N_35, loads : 13
+  Net : n2380, loads : 13
+  Net : nRowColSel, loads : 12
+  Net : Ready, loads : 12
+  Net : Din_c_4, loads : 10
+  Net : MAin_c_1, loads : 10
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |  200.000 MHz|   50.413 MHz|     6 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|  120.207 MHz|     5 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 55.238  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.891  secs
+--------------------------------------------------------------
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-1200HC/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO2-1200HC/impl1/xxx_lse_cp_file_list new file mode 100644 index 0000000..1c1a02c --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/xxx_lse_cp_file_list @@ -0,0 +1,250 @@ +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v diff --git a/CPLD/LCMXO2-1200HC/impl1/xxx_lse_sign_file b/CPLD/LCMXO2-1200HC/impl1/xxx_lse_sign_file new file mode 100644 index 0000000..7e27975 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/xxx_lse_sign_file @@ -0,0 +1,250 @@ +LSE_CPS_ID_1 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" +LSE_CPS_ID_2 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_3 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:186[13] 231[7]" +LSE_CPS_ID_4 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_5 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_6 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_7 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_8 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_9 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_10 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_11 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_12 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_13 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_14 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_15 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_16 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_17 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_18 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_19 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:141[9] 144[5]" +LSE_CPS_ID_20 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_21 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_22 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_23 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_24 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_25 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_26 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_27 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:255[14] 262[8]" +LSE_CPS_ID_28 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_29 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_30 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_31 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_32 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_33 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_34 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_35 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_36 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:321[13] 335[7]" +LSE_CPS_ID_37 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_38 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_39 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_40 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_41 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_42 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_43 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_44 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:99[22:51]" +LSE_CPS_ID_45 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_46 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_47 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_48 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_49 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_50 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_51 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_52 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_53 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_54 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_55 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:168[14] 184[8]" +LSE_CPS_ID_56 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_57 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_58 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_59 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_60 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_61 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_62 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_63 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:345[12] 409[6]" +LSE_CPS_ID_64 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_65 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:58[17:46]" +LSE_CPS_ID_66 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_67 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:195[13] 231[7]" +LSE_CPS_ID_68 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_69 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_70 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_71 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_72 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_73 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_74 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_75 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:83[6:15]" +LSE_CPS_ID_76 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_77 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:195[13] 231[7]" +LSE_CPS_ID_78 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_79 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_80 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_81 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:83[6:15]" +LSE_CPS_ID_82 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_83 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_84 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:86[13:15]" +LSE_CPS_ID_85 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_86 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_87 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_88 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:233[8:20]" +LSE_CPS_ID_89 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:233[8:20]" +LSE_CPS_ID_90 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_91 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_92 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_93 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_94 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_95 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_96 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_97 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_98 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_99 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_100 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_101 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_102 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:233[8:20]" +LSE_CPS_ID_103 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:15[12:17]" +LSE_CPS_ID_104 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_105 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_106 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_107 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_108 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_109 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_110 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[27:31]" +LSE_CPS_ID_111 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:83[6:15]" +LSE_CPS_ID_112 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_113 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_114 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_115 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_116 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_117 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_118 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_119 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_120 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_121 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_122 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_123 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_124 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_125 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_126 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_127 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_128 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_129 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_130 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_131 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_132 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_133 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_134 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_135 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_136 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_137 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_138 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_139 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_140 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_141 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_142 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_143 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_144 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_145 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_146 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_147 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_148 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_149 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_150 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_151 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_152 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_153 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_154 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_155 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" +LSE_CPS_ID_156 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[40:46]" +LSE_CPS_ID_157 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[40:46]" +LSE_CPS_ID_158 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_159 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_160 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_161 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_162 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_163 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_164 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_165 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_166 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_167 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_168 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_169 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_170 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" +LSE_CPS_ID_171 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_172 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_173 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_174 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_175 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_176 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_177 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_178 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_179 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_180 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_181 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:22[9:12]" +LSE_CPS_ID_182 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" +LSE_CPS_ID_183 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" +LSE_CPS_ID_184 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_185 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_186 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_187 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_188 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_189 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_190 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_191 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_192 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_193 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_194 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_195 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_196 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[13:17]" +LSE_CPS_ID_197 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:45[13:17]" +LSE_CPS_ID_198 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[45:49]" +LSE_CPS_ID_199 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[23:28]" +LSE_CPS_ID_200 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[34:39]" +LSE_CPS_ID_201 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[16:21]" +LSE_CPS_ID_202 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[9:14]" +LSE_CPS_ID_203 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:63[13:19]" +LSE_CPS_ID_204 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:64[13:19]" +LSE_CPS_ID_205 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:65[13:19]" +LSE_CPS_ID_206 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" +LSE_CPS_ID_207 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_208 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_209 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_210 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_211 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_212 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_213 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_214 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_215 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_216 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_217 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" +LSE_CPS_ID_218 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" +LSE_CPS_ID_219 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_220 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_221 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_222 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_223 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_224 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_225 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_226 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_227 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" +LSE_CPS_ID_228 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" +LSE_CPS_ID_229 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:36[8:12]" +LSE_CPS_ID_230 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:41[8:12]" +LSE_CPS_ID_231 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:66[8:14]" +LSE_CPS_ID_232 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_233 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[17:23]" +LSE_CPS_ID_234 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_235 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_236 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_237 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_238 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_239 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:134[9] 138[5]" +LSE_CPS_ID_240 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_241 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_242 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_243 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_244 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_245 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_246 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" +LSE_CPS_ID_247 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" +LSE_CPS_ID_248 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_249 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" +LSE_CPS_ID_250 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" diff --git a/CPLD/LCMXO2-640HC/.run_manager.ini b/CPLD/LCMXO2-640HC/.run_manager.ini new file mode 100644 index 0000000..8c0aa7b --- /dev/null +++ b/CPLD/LCMXO2-640HC/.run_manager.ini @@ -0,0 +1,9 @@ +[Runmanager] +Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) +windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) + +[impl1%3CStrategy1%3E] +isChecked=false +isHidden=false +isExpanded=false diff --git a/CPLD/LCMXO2-640HC/.setting.ini b/CPLD/LCMXO2-640HC/.setting.ini new file mode 100644 index 0000000..713c9cf --- /dev/null +++ b/CPLD/LCMXO2-640HC/.setting.ini @@ -0,0 +1,4 @@ +[General] +Export.auto_tasks=Jedecgen +PAR.auto_tasks=PARTrace, IOTiming +Map.auto_tasks=MapTrace, MapVerilogSimFile, MapVHDLSimFile diff --git a/CPLD/LCMXO2-640HC/.spread_sheet.ini b/CPLD/LCMXO2-640HC/.spread_sheet.ini new file mode 100644 index 0000000..6c511f4 --- /dev/null +++ b/CPLD/LCMXO2-640HC/.spread_sheet.ini @@ -0,0 +1,3 @@ +[General] +COLUMN_POS_INFO_NAME_-1_0=Prioritize +COLUMN_POS_INFO_NAME_-1_1=PIO Register diff --git a/CPLD/LCMXO2-640HC/.spreadsheet_view.ini b/CPLD/LCMXO2-640HC/.spreadsheet_view.ini new file mode 100644 index 0000000..f26306f --- /dev/null +++ b/CPLD/LCMXO2-640HC/.spreadsheet_view.ini @@ -0,0 +1,76 @@ +[General] +pin_sort_type=0 +pin_sort_ascending=true +sig_sort_type=0 +sig_sort_ascending=true +active_Sheet=Port Assignments + +[Port%20Assignments] +Name="164,0" +Group%20By="84,1" +Pin="50,2" +BANK="62,3" +BANK_VCC="90,4" +VREF="60,5" +IO_TYPE="147,6" +PULLMODE="97,7" +DRIVE="67,8" +SLEWRATE="92,9" +CLAMP="71,10" +OPENDRAIN="97,11" +DIFFRESISTOR="114,12" +DIFFDRIVE="92,13" +HYSTERESIS="101,14" +Outload%20%28pF%29="103,15" +MaxSkew="87,16" +Clock%20Load%20Only="121,17" +SwitchingID="100,18" +Ground%20plane%20PCB%20noise%20%28mV%29="196,19" +Power%20plane%20PCB%20noise%20%28mV%29="190,20" +SSO%20Allowance%28%25%29="138,21" +sort_columns="Name,Ascending" + +[Pin%20Assignments] +Pin="90,0" +Pad%20Name="89,1" +Dual%20Function="158,2" +Polarity="77,3" +BANK="0,4" +BANK_VCC="90,5" +IO_TYPE="147,6" +Signal%20Name="123,7" +Signal%20Type="115,8" +sort_columns="Pin,Ascending" + +[Clock%20Resource] +Clock%20Type="100,ELLIPSIS" +Clock%20Name="100,ELLIPSIS" +Selection="100,ELLIPSIS" + +[Global%20Preferences] +Preference%20Name="231,ELLIPSIS" +Preference%20Value="236,ELLIPSIS" + +[Cell%20Mapping] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Din\Dout="100,ELLIPSIS" +PIO%20Register="100,ELLIPSIS" + +[Route%20Priority] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Prioritize="100,ELLIPSIS" + +[Timing%20Preferences] +Preference%20Name="129,ELLIPSIS" +Preference%20Value="105,ELLIPSIS" +Preference%20Unit="98,ELLIPSIS" + +[Group] +Group%20Type\Name="134,ELLIPSIS" +Value="39,ELLIPSIS" + +[Misc%20Preferences] +Preference%20Name="117,ELLIPSIS" +Preference%20Value="105,ELLIPSIS" diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ccl b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ccl new file mode 100644 index 0000000..dcf391b --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ccl @@ -0,0 +1 @@ +VERSION=20110520 diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf new file mode 100644 index 0000000..49c9e13 --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf new file mode 100644 index 0000000..63de512 --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf @@ -0,0 +1,68 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +LOCATE COMP "CROW[0]" SITE "10" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "RCLK" SITE "62" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "MAin[0]" SITE "14" ; +LOCATE COMP "MAin[1]" SITE "12" ; +LOCATE COMP "MAin[2]" SITE "13" ; +LOCATE COMP "MAin[3]" SITE "21" ; +LOCATE COMP "MAin[4]" SITE "20" ; +LOCATE COMP "MAin[5]" SITE "19" ; +LOCATE COMP "MAin[6]" SITE "24" ; +LOCATE COMP "MAin[7]" SITE "18" ; +LOCATE COMP "MAin[8]" SITE "25" ; +LOCATE COMP "MAin[9]" SITE "32" ; +LOCATE COMP "UFMSDO" SITE "27" ; +LOCATE COMP "nFWE" SITE "28" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "RA[1]" SITE "67" ; +LOCATE COMP "RA[2]" SITE "69" ; +LOCATE COMP "RA[3]" SITE "71" ; +LOCATE COMP "RA[4]" SITE "74" ; +LOCATE COMP "RA[5]" SITE "70" ; +LOCATE COMP "RA[6]" SITE "68" ; +LOCATE COMP "RA[7]" SITE "75" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[9]" SITE "63" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "UFMCLK" SITE "29" ; +LOCATE COMP "UFMSDI" SITE "30" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "nRCS" SITE "57" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[7]" SITE "43" ; diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty new file mode 100644 index 0000000..feec63c --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC1.sty @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html new file mode 100644 index 0000000..b1bb2c0 --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html @@ -0,0 +1,82 @@ + +Lattice TCL Log + + +
    pn230815045824
+#Start recording tcl command: 8/15/2023 04:58:13
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
+D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC
+RAM2GS_LCMXO2_1200HC
+#Start recording tcl command: 8/15/2023 04:58:24
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
+prj_project saveas -name "RAM2GS_LCMXO2_1200HC" -dir "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC"
+#Stop recording: 8/15/2023 04:58:24
+
+
+
+pn230815050055
+#Start recording tcl command: 8/15/2023 05:00:44
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
+#Stop recording: 8/15/2023 05:00:55
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815045824.tcr b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815045824.tcr new file mode 100644 index 0000000..a9d6771 --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815045824.tcr @@ -0,0 +1,9 @@ +#Start recording tcl command: 8/15/2023 04:58:13 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC +RAM2GS_LCMXO2_1200HC +#Start recording tcl command: 8/15/2023 04:58:24 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC +prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf" +prj_project saveas -name "RAM2GS_LCMXO2_1200HC" -dir "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-1200HC" +#Stop recording: 8/15/2023 04:58:24 diff --git a/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815050055.tcr b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815050055.tcr new file mode 100644 index 0000000..4ca6762 --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn230815050055.tcr @@ -0,0 +1,4 @@ +#Start recording tcl command: 8/15/2023 05:00:44 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC +prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf" +#Stop recording: 8/15/2023 05:00:55 diff --git a/CPLD/LCMXO2-640HC/hdlparser.log b/CPLD/LCMXO2-640HC/hdlparser.log new file mode 100644 index 0000000..fa8401f --- /dev/null +++ b/CPLD/LCMXO2-640HC/hdlparser.log @@ -0,0 +1,3 @@ +-- all messages logged in file hdlparser.log +-- Analyzing Verilog file 'C:/lscc/diamond/3.12/cae_library/synthesis/verilog/machxo2.v' (VERI-1482) +-- Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v' (VERI-1482) diff --git a/CPLD/LCMXO2-640HC/impl1/.build_status b/CPLD/LCMXO2-640HC/impl1/.build_status new file mode 100644 index 0000000..96c9059 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/.build_status @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb b/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb new file mode 100644 index 0000000..049dfbe Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb differ diff --git a/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_rtl.vdb b/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_rtl.vdb new file mode 100644 index 0000000..004500f Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_rtl.vdb differ diff --git a/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_tech.vdb b/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_tech.vdb new file mode 100644 index 0000000..936bc08 Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/.vdbs/RAM2GS_tech.vdb differ diff --git a/CPLD/LCMXO2-640HC/impl1/.vdbs/dbStat.txt b/CPLD/LCMXO2-640HC/impl1/.vdbs/dbStat.txt new file mode 100644 index 0000000..0a575a4 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/.vdbs/dbStat.txt @@ -0,0 +1 @@ +RAM2GS_rtl.vdb diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt new file mode 100644 index 0000000..4bf1035 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.alt @@ -0,0 +1,75 @@ +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Tue Aug 15 05:03:41 2023 * +NOTE DESIGN NAME: RAM2GS * +NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[7] : 43 : inout * +NOTE PINS RD[6] : 42 : inout * +NOTE PINS RD[5] : 41 : inout * +NOTE PINS RD[4] : 40 : inout * +NOTE PINS RD[3] : 39 : inout * +NOTE PINS RD[2] : 38 : inout * +NOTE PINS RD[1] : 37 : inout * +NOTE PINS RD[0] : 36 : inout * +NOTE PINS Dout[7] : 82 : out * +NOTE PINS Dout[6] : 78 : out * +NOTE PINS Dout[5] : 84 : out * +NOTE PINS Dout[4] : 83 : out * +NOTE PINS Dout[3] : 85 : out * +NOTE PINS Dout[2] : 87 : out * +NOTE PINS Dout[1] : 86 : out * +NOTE PINS Dout[0] : 76 : out * +NOTE PINS LED : 34 : out * +NOTE PINS RBA[1] : 60 : out * +NOTE PINS RBA[0] : 58 : out * +NOTE PINS RA[11] : 59 : out * +NOTE PINS RA[10] : 64 : out * +NOTE PINS RA[9] : 63 : out * +NOTE PINS RA[8] : 65 : out * +NOTE PINS RA[7] : 75 : out * +NOTE PINS RA[6] : 68 : out * +NOTE PINS RA[5] : 70 : out * +NOTE PINS RA[4] : 74 : out * +NOTE PINS RA[3] : 71 : out * +NOTE PINS RA[2] : 69 : out * +NOTE PINS RA[1] : 67 : out * +NOTE PINS RA[0] : 66 : out * +NOTE PINS nRCS : 57 : out * +NOTE PINS RCKE : 53 : out * +NOTE PINS nRWE : 49 : out * +NOTE PINS nRRAS : 54 : out * +NOTE PINS nRCAS : 52 : out * +NOTE PINS RDQMH : 51 : out * +NOTE PINS RDQML : 48 : out * +NOTE PINS nUFMCS : 77 : out * +NOTE PINS UFMCLK : 29 : out * +NOTE PINS UFMSDI : 30 : out * +NOTE PINS PHI2 : 8 : in * +NOTE PINS MAin[9] : 32 : in * +NOTE PINS MAin[8] : 25 : in * +NOTE PINS MAin[7] : 18 : in * +NOTE PINS MAin[6] : 24 : in * +NOTE PINS MAin[5] : 19 : in * +NOTE PINS MAin[4] : 20 : in * +NOTE PINS MAin[3] : 21 : in * +NOTE PINS MAin[2] : 13 : in * +NOTE PINS MAin[1] : 12 : in * +NOTE PINS MAin[0] : 14 : in * +NOTE PINS CROW[1] : 16 : in * +NOTE PINS CROW[0] : 10 : in * +NOTE PINS Din[7] : 1 : in * +NOTE PINS Din[6] : 2 : in * +NOTE PINS Din[5] : 98 : in * +NOTE PINS Din[4] : 99 : in * +NOTE PINS Din[3] : 97 : in * +NOTE PINS Din[2] : 88 : in * +NOTE PINS Din[1] : 96 : in * +NOTE PINS Din[0] : 3 : in * +NOTE PINS nCCAS : 9 : in * +NOTE PINS nCRAS : 17 : in * +NOTE PINS nFWE : 28 : in * +NOTE PINS RCLK : 62 : in * +NOTE PINS UFMSDO : 27 : in * +NOTE CONFIGURATION MODE: NONE * +NOTE COMPRESSION: on * diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep new file mode 100644 index 0000000..e4fda17 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.arearep @@ -0,0 +1,21 @@ +---------------------------------------------------------------------- +Report for cell RAM2GS.TECH +Register bits: 102 of 877 (11.631%) +I/O cells: 67 + Cell usage: + cell count Res Usage(%) + BB 8 100.0 + CCU2D 10 100.0 + FD1P3AX 29 100.0 + FD1P3AY 5 100.0 + FD1P3IX 3 100.0 + FD1S3AX 47 100.0 + FD1S3IX 14 100.0 + FD1S3JX 4 100.0 + GSR 1 100.0 + IB 26 100.0 + INV 3 100.0 + LUT4 122 100.0 + OB 33 100.0 + PFUMX 1 100.0 + TOTAL 306 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn new file mode 100644 index 0000000..e34c8b7 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.bgn @@ -0,0 +1,86 @@ +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:39 2023 + + +Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf + +Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| RamCfg | Reset** | ++---------------------------------+---------------------------------+ +| MCCLK_FREQ | 2.08** | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| JTAG_PORT | ENABLE** | ++---------------------------------+---------------------------------+ +| SDM_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| SLAVE_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MASTER_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| I2C_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MUX_CONFIGURATION_PORTS | DISABLE** | ++---------------------------------+---------------------------------+ +| CONFIGURATION | CFG** | ++---------------------------------+---------------------------------+ +| COMPRESS_CONFIG | ON** | ++---------------------------------+---------------------------------+ +| MY_ASSP | OFF** | ++---------------------------------+---------------------------------+ +| ONE_TIME_PROGRAM | OFF** | ++---------------------------------+---------------------------------+ +| ENABLE_TRANSFR | DISABLE** | ++---------------------------------+---------------------------------+ +| SHAREDEBRINIT | DISABLE** | ++---------------------------------+---------------------------------+ +| BACKGROUND_RECONFIG | OFF** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... + +Bitstream Status: Final Version 1.95. + +Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed". + +=========== +UFM Summary. +=========== +UFM Size: 191 Pages (128*191 Bits). +UFM Utilization: General Purpose Flash Memory. + +Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190). +Initialized UFM Pages: 0 Page. + +Total CPU Time: 1 secs +Total REAL Time: 2 secs +Peak Memory Usage: 245 MB diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd new file mode 100644 index 0000000..f841f90 Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd differ diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad new file mode 100644 index 0000000..0e66e0f --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad @@ -0,0 +1,281 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO2-640HC +Performance Grade: 4 +PACKAGE: TQFP100 +Package Status: Final Version 1.39 + +Tue Aug 15 05:03:32 2023 + +Pinout by Port Name: ++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | ++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ +| CROW[0] | 10/3 | LVCMOS25_IN | PL3D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| CROW[1] | 16/3 | LVCMOS25_IN | PL6A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[0] | 3/3 | LVCMOS25_IN | PL2C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[1] | 96/0 | LVCMOS25_IN | PT6D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[2] | 88/0 | LVCMOS25_IN | PT9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[3] | 97/0 | LVCMOS25_IN | PT6C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[4] | 99/0 | LVCMOS25_IN | PT6A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[5] | 98/0 | LVCMOS25_IN | PT6B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[6] | 2/3 | LVCMOS25_IN | PL2B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[7] | 1/3 | LVCMOS25_IN | PL2A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Dout[0] | 76/0 | LVCMOS25_OUT | PT11D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[1] | 86/0 | LVCMOS25_OUT | PT9C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[2] | 87/0 | LVCMOS25_OUT | PT9B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[3] | 85/0 | LVCMOS25_OUT | PT9D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[4] | 83/0 | LVCMOS25_OUT | PT10B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[5] | 84/0 | LVCMOS25_OUT | PT10A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[6] | 78/0 | LVCMOS25_OUT | PT11A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[7] | 82/0 | LVCMOS25_OUT | PT10C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| LED | 34/2 | LVCMOS25_OUT | PB6C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| MAin[0] | 14/3 | LVCMOS25_IN | PL5C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[1] | 12/3 | LVCMOS25_IN | PL5A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[2] | 13/3 | LVCMOS25_IN | PL5B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[3] | 21/3 | LVCMOS25_IN | PL7B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[4] | 20/3 | LVCMOS25_IN | PL7A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[5] | 19/3 | LVCMOS25_IN | PL6D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[6] | 24/3 | LVCMOS25_IN | PL7C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[7] | 18/3 | LVCMOS25_IN | PL6C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[8] | 25/3 | LVCMOS25_IN | PL7D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[9] | 32/2 | LVCMOS25_IN | PB6B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| PHI2 | 8/3 | LVCMOS25_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| RA[0] | 66/1 | LVCMOS25_OUT | PR3D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[10] | 64/1 | LVCMOS25_OUT | PR5B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[11] | 59/1 | LVCMOS25_OUT | PR6B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[1] | 67/1 | LVCMOS25_OUT | PR3C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[2] | 69/1 | LVCMOS25_OUT | PR3A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[3] | 71/1 | LVCMOS25_OUT | PR2C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[4] | 74/1 | LVCMOS25_OUT | PR2B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[5] | 70/1 | LVCMOS25_OUT | PR2D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[6] | 68/1 | LVCMOS25_OUT | PR3B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[7] | 75/1 | LVCMOS25_OUT | PR2A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[8] | 65/1 | LVCMOS25_OUT | PR5A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[9] | 63/1 | LVCMOS25_OUT | PR5C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RBA[0] | 58/1 | LVCMOS25_OUT | PR6C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RBA[1] | 60/1 | LVCMOS25_OUT | PR6A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RCKE | 53/1 | LVCMOS25_OUT | PR7B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RCLK | 62/1 | LVCMOS25_IN | PR5D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| RDQMH | 51/1 | LVCMOS25_OUT | PR7D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RDQML | 48/2 | LVCMOS25_OUT | PB14C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RD[0] | 36/2 | LVCMOS25_BIDI | PB10A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[1] | 37/2 | LVCMOS25_BIDI | PB10B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[2] | 38/2 | LVCMOS25_BIDI | PB10C | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[3] | 39/2 | LVCMOS25_BIDI | PB10D | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[4] | 40/2 | LVCMOS25_BIDI | PB12A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[5] | 41/2 | LVCMOS25_BIDI | PB12B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[6] | 42/2 | LVCMOS25_BIDI | PB12C | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[7] | 43/2 | LVCMOS25_BIDI | PB12D | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| UFMCLK | 29/2 | LVCMOS25_OUT | PB4C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| UFMSDI | 30/2 | LVCMOS25_OUT | PB4D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| UFMSDO | 27/2 | LVCMOS25_IN | PB4A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nCCAS | 9/3 | LVCMOS25_IN | PL3C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nCRAS | 17/3 | LVCMOS25_IN | PL6B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nFWE | 28/2 | LVCMOS25_IN | PB4B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nRCAS | 52/1 | LVCMOS25_OUT | PR7C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nRCS | 57/1 | LVCMOS25_OUT | PR6D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nRRAS | 54/1 | LVCMOS25_OUT | PR7A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nRWE | 49/2 | LVCMOS25_OUT | PB14D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nUFMCS | 77/0 | LVCMOS25_OUT | PT11C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | ++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 2.5V | +| 1 | 2.5V | +| 2 | 2.5V | +| 3 | 2.5V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| 1/3 | Din[7] | LOCATED | LVCMOS25_IN | PL2A | | | | +| 2/3 | Din[6] | LOCATED | LVCMOS25_IN | PL2B | | | | +| 3/3 | Din[0] | LOCATED | LVCMOS25_IN | PL2C | PCLKT3_2 | | | +| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | | +| 7/3 | unused, PULL:DOWN | | | PL3A | | | | +| 8/3 | PHI2 | LOCATED | LVCMOS25_IN | PL3B | | | | +| 9/3 | nCCAS | LOCATED | LVCMOS25_IN | PL3C | | | | +| 10/3 | CROW[0] | LOCATED | LVCMOS25_IN | PL3D | | | | +| 12/3 | MAin[1] | LOCATED | LVCMOS25_IN | PL5A | PCLKT3_1 | | | +| 13/3 | MAin[2] | LOCATED | LVCMOS25_IN | PL5B | PCLKC3_1 | | | +| 14/3 | MAin[0] | LOCATED | LVCMOS25_IN | PL5C | | | | +| 15/3 | unused, PULL:DOWN | | | PL5D | | | | +| 16/3 | CROW[1] | LOCATED | LVCMOS25_IN | PL6A | | | | +| 17/3 | nCRAS | LOCATED | LVCMOS25_IN | PL6B | | | | +| 18/3 | MAin[7] | LOCATED | LVCMOS25_IN | PL6C | | | | +| 19/3 | MAin[5] | LOCATED | LVCMOS25_IN | PL6D | | | | +| 20/3 | MAin[4] | LOCATED | LVCMOS25_IN | PL7A | PCLKT3_0 | | | +| 21/3 | MAin[3] | LOCATED | LVCMOS25_IN | PL7B | PCLKC3_0 | | | +| 24/3 | MAin[6] | LOCATED | LVCMOS25_IN | PL7C | | | | +| 25/3 | MAin[8] | LOCATED | LVCMOS25_IN | PL7D | | | | +| 27/2 | UFMSDO | LOCATED | LVCMOS25_IN | PB4A | CSSPIN | | | +| 28/2 | nFWE | LOCATED | LVCMOS25_IN | PB4B | | | | +| 29/2 | UFMCLK | LOCATED | LVCMOS25_OUT | PB4C | | | | +| 30/2 | UFMSDI | LOCATED | LVCMOS25_OUT | PB4D | | | | +| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | | +| 32/2 | MAin[9] | LOCATED | LVCMOS25_IN | PB6B | SO/SPISO | | | +| 34/2 | LED | LOCATED | LVCMOS25_OUT | PB6C | PCLKT2_0 | | | +| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | | +| 36/2 | RD[0] | LOCATED | LVCMOS25_BIDI | PB10A | | | | +| 37/2 | RD[1] | LOCATED | LVCMOS25_BIDI | PB10B | | | | +| 38/2 | RD[2] | LOCATED | LVCMOS25_BIDI | PB10C | PCLKT2_1 | | | +| 39/2 | RD[3] | LOCATED | LVCMOS25_BIDI | PB10D | PCLKC2_1 | | | +| 40/2 | RD[4] | LOCATED | LVCMOS25_BIDI | PB12A | | | | +| 41/2 | RD[5] | LOCATED | LVCMOS25_BIDI | PB12B | | | | +| 42/2 | RD[6] | LOCATED | LVCMOS25_BIDI | PB12C | | | | +| 43/2 | RD[7] | LOCATED | LVCMOS25_BIDI | PB12D | | | | +| 45/2 | unused, PULL:DOWN | | | PB14A | | | | +| 47/2 | unused, PULL:DOWN | | | PB14B | | | | +| 48/2 | RDQML | LOCATED | LVCMOS25_OUT | PB14C | SN | | | +| 49/2 | nRWE | LOCATED | LVCMOS25_OUT | PB14D | SI/SISPI | | | +| 51/1 | RDQMH | LOCATED | LVCMOS25_OUT | PR7D | | | | +| 52/1 | nRCAS | LOCATED | LVCMOS25_OUT | PR7C | | | | +| 53/1 | RCKE | LOCATED | LVCMOS25_OUT | PR7B | | | | +| 54/1 | nRRAS | LOCATED | LVCMOS25_OUT | PR7A | | | | +| 57/1 | nRCS | LOCATED | LVCMOS25_OUT | PR6D | | | | +| 58/1 | RBA[0] | LOCATED | LVCMOS25_OUT | PR6C | | | | +| 59/1 | RA[11] | LOCATED | LVCMOS25_OUT | PR6B | | | | +| 60/1 | RBA[1] | LOCATED | LVCMOS25_OUT | PR6A | | | | +| 62/1 | RCLK | LOCATED | LVCMOS25_IN | PR5D | PCLKC1_0 | | | +| 63/1 | RA[9] | LOCATED | LVCMOS25_OUT | PR5C | PCLKT1_0 | | | +| 64/1 | RA[10] | LOCATED | LVCMOS25_OUT | PR5B | | | | +| 65/1 | RA[8] | LOCATED | LVCMOS25_OUT | PR5A | | | | +| 66/1 | RA[0] | LOCATED | LVCMOS25_OUT | PR3D | | | | +| 67/1 | RA[1] | LOCATED | LVCMOS25_OUT | PR3C | | | | +| 68/1 | RA[6] | LOCATED | LVCMOS25_OUT | PR3B | | | | +| 69/1 | RA[2] | LOCATED | LVCMOS25_OUT | PR3A | | | | +| 70/1 | RA[5] | LOCATED | LVCMOS25_OUT | PR2D | | | | +| 71/1 | RA[3] | LOCATED | LVCMOS25_OUT | PR2C | | | | +| 74/1 | RA[4] | LOCATED | LVCMOS25_OUT | PR2B | | | | +| 75/1 | RA[7] | LOCATED | LVCMOS25_OUT | PR2A | | | | +| 76/0 | Dout[0] | LOCATED | LVCMOS25_OUT | PT11D | DONE | | | +| 77/0 | nUFMCS | | LVCMOS25_OUT | PT11C | INITN | | | +| 78/0 | Dout[6] | LOCATED | LVCMOS25_OUT | PT11A | | | | +| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | | +| 82/0 | Dout[7] | LOCATED | LVCMOS25_OUT | PT10C | JTAGENB | | | +| 83/0 | Dout[4] | LOCATED | LVCMOS25_OUT | PT10B | | | | +| 84/0 | Dout[5] | LOCATED | LVCMOS25_OUT | PT10A | | | | +| 85/0 | Dout[3] | LOCATED | LVCMOS25_OUT | PT9D | SDA/PCLKC0_0 | | | +| 86/0 | Dout[1] | LOCATED | LVCMOS25_OUT | PT9C | SCL/PCLKT0_0 | | | +| 87/0 | Dout[2] | LOCATED | LVCMOS25_OUT | PT9B | PCLKC0_1 | | | +| 88/0 | Din[2] | LOCATED | LVCMOS25_IN | PT9A | PCLKT0_1 | | | +| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | | +| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | | +| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | | +| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | | +| 96/0 | Din[1] | LOCATED | LVCMOS25_IN | PT6D | | | | +| 97/0 | Din[3] | LOCATED | LVCMOS25_IN | PT6C | | | | +| 98/0 | Din[5] | LOCATED | LVCMOS25_IN | PT6B | | | | +| 99/0 | Din[4] | LOCATED | LVCMOS25_IN | PT6A | | | | +| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ + +sysCONFIG Pins: ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | +| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | +| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | +| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | ++----------+--------------------+--------------------+----------+-------------+-------------------+ + +Dedicated sysCONFIG Pins: + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "10"; +LOCATE COMP "CROW[1]" SITE "16"; +LOCATE COMP "Din[0]" SITE "3"; +LOCATE COMP "Din[1]" SITE "96"; +LOCATE COMP "Din[2]" SITE "88"; +LOCATE COMP "Din[3]" SITE "97"; +LOCATE COMP "Din[4]" SITE "99"; +LOCATE COMP "Din[5]" SITE "98"; +LOCATE COMP "Din[6]" SITE "2"; +LOCATE COMP "Din[7]" SITE "1"; +LOCATE COMP "Dout[0]" SITE "76"; +LOCATE COMP "Dout[1]" SITE "86"; +LOCATE COMP "Dout[2]" SITE "87"; +LOCATE COMP "Dout[3]" SITE "85"; +LOCATE COMP "Dout[4]" SITE "83"; +LOCATE COMP "Dout[5]" SITE "84"; +LOCATE COMP "Dout[6]" SITE "78"; +LOCATE COMP "Dout[7]" SITE "82"; +LOCATE COMP "LED" SITE "34"; +LOCATE COMP "MAin[0]" SITE "14"; +LOCATE COMP "MAin[1]" SITE "12"; +LOCATE COMP "MAin[2]" SITE "13"; +LOCATE COMP "MAin[3]" SITE "21"; +LOCATE COMP "MAin[4]" SITE "20"; +LOCATE COMP "MAin[5]" SITE "19"; +LOCATE COMP "MAin[6]" SITE "24"; +LOCATE COMP "MAin[7]" SITE "18"; +LOCATE COMP "MAin[8]" SITE "25"; +LOCATE COMP "MAin[9]" SITE "32"; +LOCATE COMP "PHI2" SITE "8"; +LOCATE COMP "RA[0]" SITE "66"; +LOCATE COMP "RA[10]" SITE "64"; +LOCATE COMP "RA[11]" SITE "59"; +LOCATE COMP "RA[1]" SITE "67"; +LOCATE COMP "RA[2]" SITE "69"; +LOCATE COMP "RA[3]" SITE "71"; +LOCATE COMP "RA[4]" SITE "74"; +LOCATE COMP "RA[5]" SITE "70"; +LOCATE COMP "RA[6]" SITE "68"; +LOCATE COMP "RA[7]" SITE "75"; +LOCATE COMP "RA[8]" SITE "65"; +LOCATE COMP "RA[9]" SITE "63"; +LOCATE COMP "RBA[0]" SITE "58"; +LOCATE COMP "RBA[1]" SITE "60"; +LOCATE COMP "RCKE" SITE "53"; +LOCATE COMP "RCLK" SITE "62"; +LOCATE COMP "RDQMH" SITE "51"; +LOCATE COMP "RDQML" SITE "48"; +LOCATE COMP "RD[0]" SITE "36"; +LOCATE COMP "RD[1]" SITE "37"; +LOCATE COMP "RD[2]" SITE "38"; +LOCATE COMP "RD[3]" SITE "39"; +LOCATE COMP "RD[4]" SITE "40"; +LOCATE COMP "RD[5]" SITE "41"; +LOCATE COMP "RD[6]" SITE "42"; +LOCATE COMP "RD[7]" SITE "43"; +LOCATE COMP "UFMCLK" SITE "29"; +LOCATE COMP "UFMSDI" SITE "30"; +LOCATE COMP "UFMSDO" SITE "27"; +LOCATE COMP "nCCAS" SITE "9"; +LOCATE COMP "nCRAS" SITE "17"; +LOCATE COMP "nFWE" SITE "28"; +LOCATE COMP "nRCAS" SITE "52"; +LOCATE COMP "nRCS" SITE "57"; +LOCATE COMP "nRRAS" SITE "54"; +LOCATE COMP "nRWE" SITE "49"; +LOCATE COMP "nUFMCS" SITE "77"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:34 2023 + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par new file mode 100644 index 0000000..6c50535 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par @@ -0,0 +1,231 @@ + +Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd" +Tue Aug 15 05:03:28 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Preference file: RAM2GS_LCMXO2_640HC_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67+4(JTAG)/80 89% used + 67+4(JTAG)/79 90% bonded + + SLICE 75/320 23% used + + + +Number of Signals: 285 +Number of Connections: 674 +WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors. + +Pin Constraint Summary: + 66 out of 67 pins locked (98% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + +WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + +WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +No signal is selected as Global Set/Reset. +. +Starting Placer Phase 0. +............. +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +............... +Placer score = 121531. +Finished Placer Phase 1. REAL time: 4 secs + +Starting Placer Phase 2. +. +Placer score = 119079 +Finished Placer Phase 2. REAL time: 4 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 0 out of 8 (0%) + General PIO: 3 out of 80 (3%) + DCM : 0 out of 2 (0%) + DCC : 0 out of 8 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 8 (25%) + SECONDARY: 1 out of 8 (12%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 + 4(JTAG) out of 80 (88.8%) PIO sites used. + 67 + 4(JTAG) out of 79 (89.9%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+-----------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref | ++----------+----------------+------------+-----------+ +| 0 | 14 / 19 ( 73%) | 2.5V | - | +| 1 | 20 / 20 (100%) | 2.5V | - | +| 2 | 16 / 20 ( 80%) | 2.5V | - | +| 3 | 17 / 20 ( 85%) | 2.5V | - | ++----------+----------------+------------+-----------+ + +Total placer CPU time: 3 secs + +Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. + +0 connections routed; 674 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. +WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=6 clock_loads=4 + +Completed router resource preassignment. Real time: 7 secs + +Start NBR router at 05:03:35 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:35 08/15/23 + +Start NBR section for initial routing at 05:03:35 08/15/23 +Level 1, iteration 1 +2(0.00%) conflicts; 536(79.53%) untouched conns; 481988 (nbr) score; +Estimated worst slack/total negative slack: -4.914ns/-481.988ns; real time: 7 secs +Level 2, iteration 1 +7(0.02%) conflicts; 473(70.18%) untouched conns; 424953 (nbr) score; +Estimated worst slack/total negative slack: -4.988ns/-424.953ns; real time: 7 secs +Level 3, iteration 1 +12(0.03%) conflicts; 254(37.69%) untouched conns; 455640 (nbr) score; +Estimated worst slack/total negative slack: -5.118ns/-455.640ns; real time: 7 secs +Level 4, iteration 1 +6(0.01%) conflicts; 0(0.00%) untouched conn; 465237 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-465.237ns; real time: 7 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:35 08/15/23 +Level 4, iteration 1 +6(0.01%) conflicts; 0(0.00%) untouched conn; 461186 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.186ns; real time: 7 secs +Level 4, iteration 2 +3(0.01%) conflicts; 0(0.00%) untouched conn; 460933 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-460.933ns; real time: 7 secs +Level 4, iteration 3 +2(0.00%) conflicts; 0(0.00%) untouched conn; 461063 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs +Level 4, iteration 4 +1(0.00%) conflict; 0(0.00%) untouched conn; 461063 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs +Level 4, iteration 5 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:35 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for re-routing at 05:03:35 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for post-routing at 05:03:35 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 260 (38.58%) + Estimated worst slack : -5.122ns + Timing score : 452301 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=6 clock_loads=4 + +Total CPU time 7 secs +Total REAL time: 7 secs +Completely routed. +End of route. 674 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 452301 + +Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -5.122 +PAR_SUMMARY::Timing score> = 452.301 +PAR_SUMMARY::Worst slack> = 0.304 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 7 secs +Total REAL time to completion: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd new file mode 100644 index 0000000..cf7ea22 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1_par.asd @@ -0,0 +1,38 @@ +[ActiveSupport PAR] +; Global primary clocks +GLOBAL_PRIMARY_USED = 2; +; Global primary clock #0 +GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; +GLOBAL_PRIMARY_0_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_0_LOADNUM = 40; +; Global primary clock #1 +GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; +GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_1_LOADNUM = 13; +; # of global secondary clocks +GLOBAL_SECONDARY_USED = 1; +; Global secondary clock #0 +GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c; +GLOBAL_SECONDARY_0_DRIVERTYPE = PIO; +GLOBAL_SECONDARY_0_LOADNUM = 9; +GLOBAL_SECONDARY_0_SIGTYPE = CLK; +; I/O Bank 0 Usage +BANK_0_USED = 14; +BANK_0_AVAIL = 19; +BANK_0_VCCIO = 2.5V; +BANK_0_VREF1 = NA; +; I/O Bank 1 Usage +BANK_1_USED = 20; +BANK_1_AVAIL = 20; +BANK_1_VCCIO = 2.5V; +BANK_1_VREF1 = NA; +; I/O Bank 2 Usage +BANK_2_USED = 16; +BANK_2_AVAIL = 20; +BANK_2_VCCIO = 2.5V; +BANK_2_VREF1 = NA; +; I/O Bank 3 Usage +BANK_3_USED = 17; +BANK_3_AVAIL = 20; +BANK_3_VCCIO = 2.5V; +BANK_3_VREF1 = NA; diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par new file mode 100644 index 0000000..6a48b30 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par @@ -0,0 +1,28 @@ +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:28 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t +RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir +RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml + + +Preference file: RAM2GS_LCMXO2_640HC_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 -5.122 452301 0.304 0 07 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc new file mode 100644 index 0000000..ec074a2 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.drc @@ -0,0 +1 @@ +DRC detected 0 errors and 0 warnings. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed new file mode 100644 index 0000000..94c4dd3 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed @@ -0,0 +1,1435 @@ +* +NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.* +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* +NOTE All Rights Reserved.* +NOTE DATE CREATED: Tue Aug 15 05:03:40 2023* +NOTE DESIGN NAME: RAM2GS_LCMXO2_640HC_impl1.ncd* +NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100* +NOTE JEDEC FILE STATUS: Final Version 1.95* +NOTE PIN ASSIGNMENTS* +NOTE PINS RD[7] : 43 : inout* +NOTE PINS RD[6] : 42 : inout* +NOTE PINS RD[5] : 41 : inout* +NOTE PINS RD[4] : 40 : inout* +NOTE PINS RD[3] : 39 : inout* +NOTE PINS RD[2] : 38 : inout* +NOTE PINS RD[1] : 37 : inout* +NOTE PINS RD[0] : 36 : inout* +NOTE PINS Dout[7] : 82 : out* +NOTE PINS Dout[6] : 78 : out* +NOTE PINS Dout[5] : 84 : out* +NOTE PINS Dout[4] : 83 : out* +NOTE PINS Dout[3] : 85 : out* +NOTE PINS Dout[2] : 87 : out* +NOTE PINS Dout[1] : 86 : out* +NOTE PINS Dout[0] : 76 : out* +NOTE PINS LED : 34 : out* +NOTE PINS RBA[1] : 60 : out* +NOTE PINS RBA[0] : 58 : out* +NOTE PINS RA[11] : 59 : out* +NOTE PINS RA[10] : 64 : out* +NOTE PINS RA[9] : 63 : out* +NOTE PINS RA[8] : 65 : out* +NOTE PINS RA[7] : 75 : out* +NOTE PINS RA[6] : 68 : out* +NOTE PINS RA[5] : 70 : out* +NOTE PINS RA[4] : 74 : out* +NOTE PINS RA[3] : 71 : out* +NOTE PINS RA[2] : 69 : out* +NOTE PINS RA[1] : 67 : out* +NOTE PINS RA[0] : 66 : out* +NOTE PINS nRCS : 57 : out* +NOTE PINS RCKE : 53 : out* +NOTE PINS nRWE : 49 : out* +NOTE PINS nRRAS : 54 : out* +NOTE PINS nRCAS : 52 : out* +NOTE PINS RDQMH : 51 : out* +NOTE PINS RDQML : 48 : out* +NOTE PINS nUFMCS : 77 : out* +NOTE PINS UFMCLK : 29 : out* +NOTE PINS UFMSDI : 30 : out* +NOTE PINS PHI2 : 8 : in* +NOTE PINS MAin[9] : 32 : in* +NOTE PINS MAin[8] : 25 : in* +NOTE PINS MAin[7] : 18 : in* +NOTE PINS MAin[6] : 24 : in* +NOTE PINS MAin[5] : 19 : in* +NOTE PINS MAin[4] : 20 : in* +NOTE PINS MAin[3] : 21 : in* +NOTE PINS MAin[2] : 13 : in* +NOTE PINS MAin[1] : 12 : in* +NOTE PINS MAin[0] : 14 : in* +NOTE PINS CROW[1] : 16 : in* +NOTE PINS CROW[0] : 10 : in* +NOTE PINS Din[7] : 1 : in* +NOTE PINS Din[6] : 2 : in* +NOTE PINS Din[5] : 98 : in* +NOTE PINS Din[4] : 99 : in* +NOTE PINS Din[3] : 97 : in* +NOTE PINS Din[2] : 88 : in* +NOTE PINS Din[1] : 96 : in* +NOTE PINS Din[0] : 3 : in* +NOTE PINS nCCAS : 9 : in* +NOTE PINS nCRAS : 17 : in* +NOTE PINS nFWE : 28 : in* +NOTE PINS RCLK : 62 : in* +NOTE PINS UFMSDO : 27 : in* +QP100* +QF171904* +G0* +F0* +L000000 +11111111111111111011110110110011111111111111111100111011000000000000000000000000000000100000000000000000000000000000011000001001 +00110000000001010101000000101000010010001111111101000110000000000000000000000000101110001110000000000000110101110000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000010001000000000000000000000000100010000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000010010000000000000000000000000100100000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000100001000000000000000000000000000000000000001001001011010 +00001100100100010011100100100100010000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000 +00000000000010001001001100000010110100100101000000000000000010010000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000001001010000000010001110011001001000000000000001000001011100000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000100101100011000000010011000100101110001010001001100000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000010110100000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000010000100000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000001001110000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000010101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000010010100000000000101001000000000000000000000000000000000000000000000000000000000000000000000 +00000000101100000101011000000010110000000000100001000000100011000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000010000000000100010100111000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000001001110000100010000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000010001000000000000010100100000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000001001110000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000001011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000010010000000000000000000000000000000000000000000000000000000000000000000000000000000010 +01010000000000000010111000000100000000000000000001001010000000000000000000000000000000000000000000000000000000000000000000000000 +00000010001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000001000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000001000000000000000000000000000011100000010000000000001001010000000000000000000000000000000000000000000000000000000000000000 +00000000000000010001000000000000000000000001000100000000000000100011000000000000000000000000000000000000000000000000000000000000 +00000000000000000000001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000100101000000000000000010111110011100000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000101001000000000000000000000000000000000000000000000000000000000000 +00000100001100111000000000000000001000110000000000000000000000000000000000100110000000000000000000000000000000000000000000000000 +00000000001001010000000000000000001001010000000000000000000000000000100110100110000000000000000000000000000000000000000000000000 +00000000000000000000010010000000000000000000000000000000000000000000000000100100100100000000000000000000000000000000000000000000 +00000000000001001000000000100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +00110000000000000000010001100001000101001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000100001000000000000000000001001010000000000000000000000000000000000000110000011100000000000000000000000000000 +00000000000000100101000000000000000001001100000010011100000000001001000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000010011000000000000000000000000000000000000000000000001001000000000000000000 +00000000000000000000000000000000000000000000000001001110100011000000000000000000000000000000000000000000000000000000000000000010 +00011001110000000000000000000000000000000000000000000100001000000000000000000000000000000000000000000011000001110000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000001010110000001010010010001010011101001000010000000000100010000001000100000000000000000000000000000000000000000 +00000000000000000000000000000000000010101100000000000000000001001010010000100000010011100000100111000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000010011000000000000100001100111001010100000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000100011000000000000000000000000000000000000000000000000 +00000000001001110000010010000000000000000000000000000000000000001001010000000000000000000000000000010001100000000000000000000000 +00000000000110000011100000000000000100111000000000000000000000000000000000000000000000000000000001001110000000000000000000000000 +00000000000000000000000000000000100101010000100000000010101000000000000000000000000000000000000000000000100111010000100000000100 +10100000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000000000000000001000010000000000000 +00000000000000000000000000000000011000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000001000100100110000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000001011010111001000000000000000000000000000000000000000000000001011100000000000000000000000000 +00000000000000000000000000000000000000000010010000100011010010000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000001000101001010101111100101100011100010100001110100010010000000000001001010000000000000000100001000000000000000000 +10010100000000000000000000000000000000000000000000000000000000000100111010001010110110011001001111000011001110000110010001000100 +01100000000000000000000000100011000000000001001000000000001001100000000000000000000000000000000000000000000000000000010001011100 +01000110010010010011011010001001000101110000100010010111100010100010011101000111001110100111101010000000000000000000000000000000 +00001001100000000000000000000000000000000000000000000000000000000000000001010011000001000011000000011100000111000001000010100001 +00001000011010100000000000000000100000000000100110000000000001001000000000000000000000000000000000000000000000000000000000000010 +00100011000110001001000100010100111010010110001100000100101001100010100100111000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000100001100111000010011101001101011111101100000101011000110100001011011000000001001101000 +01010001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000010000101001111011 +00000100011001001101100011000110000101011100110001001111110100000100110000000000000000000000000000000000000110000111000000000000 +00000000000000000000000000000000000000000000001000010010011000100011001000111000001000010010010010010101000011000010100100000000 +00000000000000000000000000000000000110110000000000000000000000000000000000000000000000000000010000100001110001000100100100011100 +00010011110011001001001001000111001100011100100000000000100110000000000000000000000000000001010110000000001001001000010000000000 +00000000000000000000000000000000000000100000000111011001101001111011010100101111001000010011010010111110001101001101000010010010 +01101100100001110000001010010000100000000000000000000000000000000000000000000000000000000000000100111000000000000000000000000000 +00000011000110001001010010000100100001100011100101000011100010000100001000000000000000000000000000000000000011000011100000010001 +00000000000000000001000100000000000000000000000000000000010001001001110100011100010110110000001000110100001110000101010011010011 +00110100001000000110000001100100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +01001111010010101111100100010000110011101000101001101111000000100000001001101001101001110000011100100000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000010001100010110110010010011110110001001101110100000110001001001000111 +00000010001101011011000011000001100100010001001000010000100000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000001101000100001001001000010100110010010110111111000100101001010100001100111110001100010010010001101000011 +00111000000000000000000000000000010001010011100000000000000000000000000000000000000000000000000000000000000010011000001001000100 +10011100000011110001000100011100010000010001110001001000001100100010100111100110010011000010011000000000000000000000000000000000 +00100111000000000000000000000000000000000010001000000000000000000000100100110001100011000010101100100001001000011000110010011000 +01001111001010010111000010011100000000000000000000000000000011000011100000000000000100111000000000000000000000000001001110000000 +00001001110100011001100000011100001100100011000100101010011110000010010011001110000010100001110100000100010000011000100101001111 +00111010010100100001000000000000000000000000000000000000000000000010000100000000000000000000000000000000000000000000000100101010 +00001001010011000000111000011111000101010010100100001100111110010001000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000010001000100110000000101110100110100110010011001001001001001100001100110001100000011000100011001 +10101011010001000000000000000000000000000000000001100001110000000000011011000000100110000000000000000000000000000000000000001010 +01000000000010001111000100101011101100101010111000000100011000101000011010010011001010000100111000001001110000000000000000000000 +00000000000000000000010001000000000000000000000000000000000000000000000000000010011011010000010100011001001011011011101000001111 +10000001110010000010110001001000000000000000000000000000000000000000000001111000000000001001010000000000000000000000000000000000 +00000000000000011000101001100100100111100000011001000011100010010010101110001011100010001011000000111000010000000001000010000000 +00000000000000000000000000000000011110000001001000010001001010010000000000000000000000000000000000000000000000000110000001110010 +01101000110001000000010000101110010000001000100010001000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000001110111111111111101101010001101100110100110101000101000001111110111010100011111111010100000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011111010001010001101110000111111101111 +11001100110000111011001100111110111011110110010010001010100010010110100011111111001101110100100000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000010111110100010100011011000001101111111111000100011000011 +10101100110101010110110110010011111110111100001100011111101001101110000110010111000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000001101010101111110111001010001110001000101011101100110101010101010001010001001100 +11111101011000011100001111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +11000000111001001100001100111100000000110001101110010011000011001111000000001100000011101101110000110011110001000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000010010100100111000000000100101100011001011111000010010 +00010100101011010001001000111100100001100100100100000000000000000000000000010000000000000000000000000000000000000000000000000000 +00000011010000101001100000010001001001100100111110000101010011010100100010000110011010010101110001000100111100011010010101001001 +00001110010001011110000001100100010000000000000000000000000000010010000000000000000010000110011000000000000000000000000000000000 +00000000000001001000100110111001000000001010010100000001000110100110100001110100000100101001100000000100011100000010010100000000 +00000000000000000000001001010000000000000000000000000000000000000000000000000010001000000100000110000101001000111100000111011001 +00001100001101101100001000100001000100000110001000110000110011000011001000010101011010010100000000000000000000000000000100100000 +00000000000000000000000000000000000000000000000000010100110011100100000011100001001110000100100000110001010010011101001000110000 +11101010101000000110101100000001001000001001110000000000000000000000000000000000000000000000000000000000000000000000001000110000 +10001100000000100001110100000110011000010000101001100010110100010000100100001111100000010001100010000010011100000000000000000000 +00000000000000000000000000000000000000000000000000000010010100001001010000001011001000100110100010000100111001101101010100101000 +11001001001001101000101001110000010001011110000001000010000100110000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000100000010010010111110001001100010001100001100110001001011000001000011010100010011010000001001010001110000001 +10100110101001001000000000000000000000000000000000000000000000000000000000000000000000000000000001001110000000001000100110001100 +01011111011000110010001001000001011111010010100001111000001011010010011101100001111001000010010101000101010100111001010000010110 +01001101110011000100111000000010000000000000000000001000100000000000000000000000000000000000000000000000100010000000000100111010 +01101110010000001100000011010110110011000100111010011010011001000100100110100000100000101100011101010010011011000000010111000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000010011101001011001100110010000100110111001000 +01011001000111000111001001001000001101100010100111100100100000011100010000100110000000000000000000000000010000100000000000000000 +00000000000000000000000000000000000000000100010001100001100101100010010001011000101111011100101000010111010000010111010011010011 +11000110110001101010010010010110011010001010001010000010011110001010011000000001000010000000000000000000000000000000000000000000 +00000000000000000000000000000000000000100100010011101101010010110001000110011010011001110010010111100110011100101011001101101000 +10010011111000100101110010001110001011010001101010011001010100000110110000100000000010000000100010000000000000000000000000000000 +00000000000000000000000000000000000000000010011100010000000111011000010000011010001001001101100000011000100110101110100100100101 +10011011001001011001101101000001000000111001000000000000000100000000000000000000000000000000000000000000000000000000000000000000 +00000000000100011001001001000010000011100110000101101011100000101001101001111001001001100101110010010110001110011001110000001100 +01101000110000000100001000000000000000000000000000000000000000000000000000000000000000000000000001000100010011101000010011000100 +10100111110000101000001000101000111011101001000100011100001011010100101001101001010100010010111001001010000000000000000000000000 +00000000000010011000000000000000000000000000000000000000010000000000001000011110000001110010101011011001001111001000100101110000 +11001010101001011001001010010100010011000010101110010000010000110000011001001100110110000000100100000000000000000000000000000000 +10000100000000000000100011000000000000000000000000000000000000000010010100000100100010011000010011001000000100110010010100001100 +00101011000110001001110110101000110001000010000111110000100000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000010001101001011000000110010100111001001000100111101001011010011011001101011100100101001100100101100111000100 +10110011111000011001000111000110000000000000000000000000001001100000000000000000000000000000000000000000000000000000000000010011 +10011000100011001110100110100101001000111000010100000101111100110111000100001000111000010110001000101001110100010100000100000100 +11110011000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010010000010110010011011101000000 +01001111011001100000011010001011010010101111000000100100001100001100110010001001001100001100001010100101000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000100000010101010110110010010001000100111110100010110000101001100 +10010110001110010001110010000111101100010001101110000100100010010001110110000100101111001100000000000000000000000000000000000000 +00000001000000000000000000000000000000000000000000000001000000010001111000010101001011001001100010100000100011001001011001110100 +00110010101100100001001011011001101001010100000010011110010100000000000000000000000000000000000000000001000010000000000000000000 +00000000000000000000001000100001000011001101001110011100010001000011101001010101001010011010001011100001011100001010100110010001 +01000101101001001110110000110011010000000100110001001000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000101000001010111110101010011110001001010001001101100000011010000110100010011101100000011111111110001010000011000000111111 +11101001111101111111110111100111101111101111111011111100100000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000010010010100000101011011011100001111000100101000110000101001111111101100100101000010001111000000111010001101110000 +11111011111001111100001110011000010101101110000111110110110100000111101111101111001000010101000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000100100001000100101000100101110110011011100110011100001110101000110000110010110111 +11001100100001100011101000111110001011011100001000100101111111111111011110010101101100000011110100011000110101011101101110001011 +11010001000110000000000000000000000000000000000000000000000000000000000000000000000000000000000100001000110101010100110111111111 +11001000100110111101111111111111001000011111001100110000111001111111110111110111010000111111101111001110101000111100101001000001 +11101110110011001110101111100001110001011111111111101001100000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000010001000100001100111100011111100000000110001101011101000001000111111000101001100010001010001111110001000011000000 +11100100100011111100000000001000001001100010010000000000000000000000000000000000000000000000000000000000000000000000000000000100 +00000000000000100011011000011100100100011010100101000110100111000101010100000110010000100101010000100111100100000000000000000000 +00000000000000000000000000000000000000000000000000000010001100000100011100001100001100110000010000111010000100001010011000010000 +01101000010110110100000100000100011100001100011110010001000001001110000000000000000000100011000000000000000000000100110100110000 +00000000000000000000000000000000000000100101000100111000010011010011110101001001100111001000011100001001111000000100010101101010 +00110010000011010000100111100000010100110100101010010011000100100100110000000000000000010011000000000000010001100000000000000000 +00000000000000000000001001010000000001000110001100011001100001100011000100000100001100011001001111101000001100000001011110110100 +00010000010000001001100000000000000000000000000000000100110000000000000000001000100000000000000000000000000000000001100001100011 +00110100100010011110100000000100001110101001001011001001100011101110001010101000101010011000101100010010110010001010011110000000 +10010000100000100110000000000000000000000000100011000000000000000000000000001000000000000000001000110000000000000000000011001000 +10110100000101001111001111001000010010101000111110010000110010001011001000100100111100010010000111100000011001010100111100111100 +00111001001000000010001100100111000000000000000000000010011000000000000001000100000000000000000000000010010100000000000000000101 +01000011010000100100110010010101001001001110110100001000100111110001100001011100010011111100001001001111001101010010110010001010 +11000100110010001010011000101010000000000000000000000010101000000010101011000001110000000000000000000000000000000000000000000000 +00000011000100010101011100100100010010000000001111000000110100010110000111001001000110100010010011010000000010001011100010101110 +00000110000100001100100001010010010001000000000000000000000000000000000000000000000000001001100000000000000000000000000000100101 +00100011110110000101000011100010100111000001010110110010010101010011110010111001000011001010011011000101000100111000001010011101 +00111100010100110110001101000001001011101011000100011000000000000000000000000000000000000010010000000000000001000110000000000000 +00000000000000000110110010111010010011000011000000011001001001110000010100000110000001100101010110000110110011011001110001001011 +00110110100101010101010001010010101001101011100010000010011001000101000011101100000110000001100000000000000000000000000000000000 +01000100000010000000000000000000101011000000000000000000000010011001000111000000010111010010101100010001111000001010100100100010 +01001010010110011100010010011100110001001001011101100011010110110000101010100010001110000001010010000000000000000000000000000001 +10000011100000000000000100001000000000000000000000000000000000000000100000100110001000000100001000100100100011100001110100000111 +10100000100110110001000110001110011001110110000100110000010000110011110001101100010001010011000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000100011110000101001001100110101001010000010011001001101100010100100001100111110010 +01100101010100010001000011001010100001010110010010001001101001110100010100001000000000000000000000000000000000000000000000000000 +00000000000000000000000000000001101100000100011001110010000100111010000111100100000100110011010001100100111011101100000101010010 +01100111011000011010000101001101110000010011000110001000011001100100011000000000000000000000000000100110000000000000101001001011 +00000000000000000000000000000000000000000000100100100011110100100110011001000101110010000110010001010101110010111100100010010010 +01001111100010100110000110011101000001001011000011000000100001111000110101000111100001100100011110001000101001100000000000000000 +00000000000001010010000000000000000000000000000000000000000000000000010000110011110001110000000001011111100100100101011010001101 +01110010010110101100010000101001001001001000111100011010111000100001001011001011000001101100000001001000000000000000000000000000 +10001100000000000100010100111000000000000000000000000000000000001001100000010011100110011100001011001001101110001010110001010001 +00101110000101110011000001100010010100000110010000101000110110001001000011000110000000010001100000000000000000000000000000000011 +00000111000010001100000000000000000000000000000000010010000000000000100100011011000001000001001111001101001001001001101000101111 +01001011000101001101001110100001100001110100011001100001010110101001001001111011101110100000101110010011001000010000000000000000 +00000000000000000000000000001000011001110000000000000010101000000000000000000000000000100010000100100100000110100001001110001010 +01110010000110000110010001010011011010100111100001010011010100111110010000010011010011011000101000110100010001001001001101100010 +10001011010000100001100111000000000000000000000000000000010001000100110000000000000000000000000000000000000001000100000101110001 +10001001010001110001000111101001000100101100000010010110101101100010101110100011010000000100001001001100100001100011100011110000 +11010000000000000000000000000000000011000001110000000001001110000000000000000000000010001000000010001101010010001001110100100110 +00110011011110010000110100110001001101100001001100010100100011100001000010000010000101010110010100110001011011000001000010100011 +10000110011010010100000000000000000000000000000000000000000000010010100000000000000000000000010011100000100110000000111010000000 +10011010011110000111011010100111001000011001001011001010100011111110000010000010110111010101001001011110101000110100010010011110 +01111000110100101111100000010011110111110001000100101111000010011000100101001111000110000010001100000000000100011000000000000000 +01001100001000100100110000000000000000000000000000000000000010010010010101001010011000101001001101100101001100011111000001011001 +00010100100110001000111001000101000001011101101000010110001001010111010010011010100101000101110010010100100110000110010000000111 +01010000100010110011000100100110000000000000000001001010000010000110010000000000000001001010100011000000000000000000000000000000 +00000100010100000001100101001101110100101001100001100010000101001001100010001001100100100100111110001100001000101100001010100100 +10011011010000101000110110010010011010000100010011001000111100100101000000010010100000000000000000000000000000000100110000000000 +00000000000000000000000000000000000101000010100011100110010101011101000100001110000110011111100000110101001110011110000111000011 +11110011100110011010100011000100011000011110111111100101100110011111100001000011010001111110000010100010100001111101111111110111 +01001100000000000000000000000000000000000000000000000000000000000000000000000000000001001101010000110011111111100100011000111010 +11111111110111011100000010001111010111110110111000011001100111111111001101010110111111111000100011101110000111011111110010111001 +00110100110011011101001110111111001111110111101000100100101000111000100010001100000000000000000000000000000000000000000000000000 +00000000000000000000000000000111011000101100110100011111110010010000111011100001010001100011111110000110010100011111100001101110 +00011001110011010001100001110110100010011001000101101110000111111011101100101110111110111101101110000101101111111100110101010100 +00100101011111010001000110000000000000000000000000000000011110000000000000000000000000000000000000000000000000110001000100100011 +11111110010100100010000101110011111100110110111111101000011100111001111011111110101111011101111111101110100001101000100001101011 +10100010110110000111001111111111111001101011110111111100100010111110100010101100000000000000000000000000000000000000000000000000 +00000000000000000000000000001100000011100100100011111100000000100000011000011001111000101001100010011101101101100110100011100110 +00110111011011000111111000111001100001010111010000010110011010001110010000001000111111000000001100011000000000000000000000000000 +00000000010011000000000000000000000000000000000000000000001001011000100010001010011110000100000000000000000000100010100111010011 +00001000000000000000000000000000000000010010100001001110000000000000000000000000000000000000000001000110010001000110000001101100 +10011011010000100000100001100110000010000110011000001000011001100001100011100010010111010000011000010000000000000000000000000000 +01001000000000000010011000000000000000000000000000000000000000001010101001101010101001101001100010000001001111001100100110000100 +11000000100110000100110010011010001000100110010001111001000100000000000000000000000000000001000110000000000000000000000000000000 +00000000000000000000010001110000010000100100001010000010000101001000010000000000100000000010010010000001000000001101000001100001 +00000000000000000000000000000001001100000000000000000000000000000000000000000000000000100011000001100010100010101010011101001010 +01100101001100010111001000000001000000000001001000000000000000000000000000000000000000000000000000000000000000000000000000000100 +01100000000110010001011010000100000100001100110000100100100011100010100011000100001100110010000100100001100110100101000001001010 +00000000000000000000000000000000000000000000000000000000000000000000010011000000101010000001010100001001101000010010011010011010 +01101101000010010010100100110000001001101001100000000000000000000000000000000000000011000011110000000000000000000000000000000000 +00000000000000001001110001100100101000010010010000010000100001000000000010000000010010100010010100000000000000000000000000000000 +00000000000000000000000011010000010000000000000000000000000000000110001100000100100110000101010001100000000001000100000000000001 +00001010001100000000000000000000000000000000000000100100000000000000010001100000000000000000000000000001000110010000011100100000 +01110000001100110110010110101000000000000000100010000001000100000011100001001100000011000000000000000000000000000000000000000000 +00000000000000000000000000000000000000100111001000101001110110010010010001100000010110000010000000000000010100101010010100101010 +01110000000000000000000000000000001100001111000000000000000000001000100000000000000000000000000000000100000101011011100000101000 +00110001001010000101010110000000101010000100111000001001110010000110011100000000000000000000000000000000000000000000100110001000 +10000000000000000000000000000000000000000000100011010000001110000110001001111000100100111010101001000011001110100001000100111000 +10001000010001100000000000000000000000000000000000001000110001001110000000000000000000000000000000000000100111101001001001011110 +01000001011111001110100011010000011001010011001010001001000000010001000010011010000000010011000000000000000000000000000000000000 +00010011100000000000000000000000000000000000000000000000000001001010010001001110001000100110011011010000000010101100100010111001 +00000101011100000010011000000000000000000000000000000000000100100000000000000000000000000000000000000000001000010101001000010001 +01100010010110000101010101101001010110010001000100100000001111010000000000000100110110001001100000000000000000000000000000000000 +00100111010000000000000000000000000000000000000010001100000100111000001001101000111000001110011000100101000100011100010010011110 +00001100010100111000001011100001000100111101010001000100100111000001001010000000000000000000000000100000000001100001111000000000 +00000000000000000000000000000010011000000000101010001000011001011100010010110100000111000011011100100100011011000001001111001100 +10010110001110010101001100110000110010000110010001001100110000110000100110010011111010001000000000000000000000000000000000000000 +00001101010010000000000000000000000000000000000000000100001100010000001000101001110100000100111100000100010011100001000010011010 +00100100011010011001000100100011010011000100011001001100000000000000000000000000100010000000000000000000000000000000000000000000 +00000000000100010010011010011100010001101111000100101111100110010011110011011010000101101000010100110111000101010011100100100010 +01011001111000010100100010010110011100100001010010010011100000000000000000000000000000011000011110000000000001000100000000000000 +00000000000000000000000001000011000000010001000011000010101001111000011011001001101001110001110000010010000010001010001001001111 +01010100000010001001001110000010010100000000000000000000000000000000000000000100100010100100000000000000000000100011000000000000 +00010011110010101000001000000101101010011011000110001001110110001001010010101001101000101000111000011001010100110010001110001110 +01010100110000001000000100110000000000000100111000000000000000000000000000000000000000000000000000000000000000000000100000100010 +01000010110100110010100111100101001001011000100000010001110000110011010001110001011010010011000110110100010010011111010001001010 +01100011010001010011100100000100110000000000000100001000000000000010001000000000001001000011010001000111010000000000000000000000 +00010011000000000000000100010010011000110110101001001110111000100011000100011001000010011011000000110010010111101000000010010001 +00101100110001001000100101010010010011101001100000000000000000000000000001001110000000000000000000000000000000000000000000000000 +00000111110111100011000100011001101011011110100000010111010100001100110011111111000010010010100011111111001101001001110011111111 +11111100111001001011001111111111111100110100100111001111111111111100111001001011001111111100000011101001010100000101000000000000 +00000000000000000000000000000000000000000000000000000000000000000000011111000000001100010001110000111011001101011110100000100100 +11010011011010000001101110000101000011000011010011101100000011000011010011101100000101000100011011110011000011111111011001010000 +00000000000000000000000000000000000000000000000000000000000000000000000000000110010011100011000100011100001110011111100001001001 +10011001111111101101010101111101111111110000011011100000011000011010011101100000011000011010011101100000111111110010001101111111 +11000111111100110101000000000000000000000000000000000000000000000000000000000000000000000000000000000110010011100011110111011010 +11111111000011010001000101110111111011010011010100010010110000111001111111111111100110100000111001111111111111100111000001011001 +11111111111110011010000011100111111111111110011100000101100111111111111110010101101010000011111110011010110000000000000000000000 +00000000000000000000000000000000000000000000000000000000000011000000111001000000110001101110010010001111110001000010000001000111 +11100010011011010001000001111010011100100100011111100010011011010001000001111010011100100100011111100010011011010001000001111010 +00000100111001000110000000000000000000000000000000000000000001000000000000000000000000000000000000000001001101000101001110000000 +00000000000000000000000000000000000000000000000000000000010100110010100000000000000000000000000000000000000000000100001100100000 +00000000001001100000000000000000000000010001100000000000000000000000000000100100000000000010011000100010000000000000000000000000 +00000000000010001001001110000000000100111000000000000000001000000000010001000000000000100010100110000000000000000010011011100010 +00000000000000000000000000000000000000000000000000100111111000001000000000001000010100011000000000000000010000100000011101000000 +00000000001110010000000000000000000011000100101001100000000000000000000000000000000000000000000000000000000000000000100001100000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011100010010100000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101100000000000001000001 +00001000000000000000000000000000100011000000000000000000000110000111100000000000000000000000000000000000000000000000000010001000 +01000000000000000000000000000000000000000001000000000000000000000000000000000000000000001000000000000000000000000000001010010101 +00100000000010001101001100000010000100000010011000000000001000100000000000000000000000000000000000100100100001000000000000000000 +00000000000000000000000000000010011010010001001011000010000000000000000000110000001100010011100000000000000000000000000000000000 +00000000000000000000000000000000000000000100110010001100000010011101001001001010100100000000001001100001110010000010001100100010 +10101000100111000000000000000000000000000000000110000111100000000001000010000000000001000100000000000000000000000001000100100111 +00000100001000100010010011110101100001000000010001100100001001001010010000000100001001000011001110000000000000000000000000000000 +00000000000000000000000000000000000000000000000000001000011001110000100101001000010000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000010011000000000000000000000000000000000000000000000000000 +00010011100000000000000000000000000000000000000000000000100000000000000100000001001000000010101100000000101100000000000000000000 +00000000000000000001001000000000000000000000000000000000000000000000000010000100000010001100000000000000000000000000000000000000 +00000000000000000010011100000000000000000000000000000000000000000000100111000000000000000000000000000000000000000000000000000000 +00000000011000011110000000000000000000000000000000000000000000000000001000010000000000010011000000000000000000000000000000000000 +00000000000000000000000000000000000100111000000000000000000000000000000000000000000000000001001010000000000000000000000000000000 +00000000000000000000000000000000001000010000000000000000000000000000000000000000000000010010000010010000000000000000000000000000 +00000000000000000000001100001111000001000110101001000000000000000000000100011000000001000000000010011000000000100010010101100000 +00000000000000000000000000000000000000000000000000000000000001001000000000000000000000000010010000000000010010101101100100011101 +10000100100000000100101010011001000100000000000000000000001001100000000000011001001000000000000000000000000000000000000100101000 +00000000000000000000000000000010001000000000110000001111000110010001001110000000000000000000001000100000000000000000000000000000 +00000000001001000011010001000100110000000000000000000000110001100000000000000001001100000000001101000100011001000010000000000000 +00000000000000000000110010010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000001000010000000000000000000000010000100000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000100001000001100110010000000000000000001000010000011 +00110010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000010010110000100000000001001011000010000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000010011000000000000100110000000000001001100000000000000000000000000000 +00000001001100000000000000000000000000000000000000000000000000000000100111000000000001001110000000000010011100000000000000000000 +00010011100000000000100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000001011111100011000000000000010111111000110000000000 +00000000000000000000000000010000110001101001111001110000000000000000000000000000000000000000000010000100000000000000101111110001 +10000000000000101111110001100000000000000000000000001000011000110100111100111000000010000110001101001111001110000000000000000000 +00000000000000000000010011100000000000000000100111000000000000000000000000000000000000000000010111111000110001000001110000001100 +11100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000011000110100111100111000000 +00000001011111100011000100000111000000110011100000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011110001100100011001000110100111 +10001101001111000110100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000010010100000000000000011100010100000000101001001110111011111111111111111111111111111111 +11111111111111111111111111111111110000101000000000000000000000000000000000000000000000000000000000101010101001110010001000000000 +00000000000000000100000000000000000000000000000011111111111111111111111111111111111111111111111101011110000000000000000000000000 +11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 +* +NOTE END CONFIG DATA* +L41088 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +* +C5769* +NOTE FEATURE_ROW* +E0000000000000000000000000000000000000000000000000000000000000000 +0000010001100000* +NOTE User Electronic Signature Data* +UH00000000* +0994 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log new file mode 100644 index 0000000..d0353b8 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.log @@ -0,0 +1,4 @@ +---- MParTrce Tool Log File ---- + +==== Par Standard Out ==== +==== End of Par Standard Out ==== diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf new file mode 100644 index 0000000..2743d95 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf @@ -0,0 +1,4 @@ +#BLOCK ASYNCPATHS; +#BLOCK RESETPATHS; + +#FREQUENCY 200.000000 MHz; diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata new file mode 100644 index 0000000..83564a7 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata @@ -0,0 +1,6331 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp new file mode 100644 index 0000000..36bafd6 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp @@ -0,0 +1,336 @@ + + Lattice Mapping Report File for Design Module 'RAM2GS' + + +Design Information +------------------ + +Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial + RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr + RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf D:/One + Drive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_i + mpl1.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_ + LCMXO2_640HC.lpf -c 0 -gui -msgset + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml +Target Vendor: LATTICE +Target Device: LCMXO2-640HCTQFP100 +Target Performance: 4 +Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 +Mapped on: 08/15/23 05:03:24 + +Design Summary +-------------- + + Number of registers: 102 out of 877 (12%) + PFU registers: 102 out of 640 (16%) + PIO registers: 0 out of 237 (0%) + Number of SLICEs: 75 out of 320 (23%) + SLICEs as Logic/ROM: 75 out of 320 (23%) + SLICEs as RAM: 0 out of 240 (0%) + SLICEs as Carry: 10 out of 320 (3%) + Number of LUT4s: 143 out of 640 (22%) + Number used as logic LUTs: 123 + Number used as distributed RAM: 0 + Number used as ripple logic: 20 + Number used as shift registers: 0 + Number of PIO sites used: 67 + 4(JTAG) out of 79 (90%) + Number of block RAMs: 0 out of 2 (0%) + Number of GSRs: 0 out of 1 (0%) + EFB used : No + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + POR : On + Bandgap : On + Number of Power Controller: 0 out of 1 (0%) + Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) + Number of DCCA: 0 out of 8 (0%) + Number of DCMA: 0 out of 2 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of + distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and + ripple logic. + Number of clocks: 4 + Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Number of Clock Enables: 14 + Net RCLK_c_enable_6: 4 loads, 4 LSLICEs + Net RCLK_c_enable_5: 2 loads, 2 LSLICEs + + Page 1 + + + + +Design: RAM2GS Date: 08/15/23 05:03:24 + +Design Summary (cont) +--------------------- + Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs + Net RCLK_c_enable_27: 8 loads, 8 LSLICEs + Net RCLK_c_enable_10: 3 loads, 3 LSLICEs + Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_16: 1 loads, 1 LSLICEs + Net RCLK_c_enable_28: 1 loads, 1 LSLICEs + Net RCLK_c_enable_15: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs + Net Ready_N_292: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs + Number of LSRs: 7 + Net RASr2: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net nRWE_N_177: 1 loads, 1 LSLICEs + Net C1Submitted_N_237: 2 loads, 2 LSLICEs + Net n2366: 2 loads, 2 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 18 loads + Net InitReady: 15 loads + Net RASr2: 15 loads + Net nRowColSel_N_35: 13 loads + Net nRowColSel: 12 loads + Net Din_c_4: 10 loads + Net MAin_c_1: 10 loads + Net Din_c_5: 9 loads + Net MAin_c_0: 9 loads + Net Din_c_0: 8 loads + + + + + Number of warnings: 0 + Number of errors: 0 + + +Design Errors/Warnings +---------------------- + + No errors or warnings present. + +IO (PIO) Attributes +------------------- + ++---------------------+-----------+-----------+------------+ +| IO Name | Direction | Levelmode | IO | +| | | IO_TYPE | Register | ++---------------------+-----------+-----------+------------+ +| RD[7] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[6] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ + + Page 2 + + + + +Design: RAM2GS Date: 08/15/23 05:03:24 + +IO (PIO) Attributes (cont) +-------------------------- +| RD[5] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[4] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[3] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[2] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[1] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RD[0] | BIDIR | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[7] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[6] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[5] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[4] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[3] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[2] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[1] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Dout[0] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| LED | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RBA[1] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RBA[0] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[11] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[10] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[9] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[8] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[7] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[6] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[5] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[4] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[3] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[2] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RA[1] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ + + Page 3 + + + + +Design: RAM2GS Date: 08/15/23 05:03:24 + +IO (PIO) Attributes (cont) +-------------------------- +| RA[0] | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nRCS | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RCKE | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nRWE | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nRRAS | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nRCAS | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RDQMH | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RDQML | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nUFMCS | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| UFMCLK | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| UFMSDI | OUTPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| PHI2 | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[9] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[8] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[7] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[6] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[5] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[4] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[3] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[2] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[1] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| MAin[0] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| CROW[1] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| CROW[0] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[7] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[6] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[5] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[4] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ + + Page 4 + + + + +Design: RAM2GS Date: 08/15/23 05:03:24 + +IO (PIO) Attributes (cont) +-------------------------- +| Din[3] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[2] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[1] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| Din[0] | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nCCAS | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nCRAS | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| nFWE | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| RCLK | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ +| UFMSDO | INPUT | LVCMOS25 | | ++---------------------+-----------+-----------+------------+ + +Removed logic +------------- + +Block i2 undriven or does not drive anything - clipped. +Block GSR_INST undriven or does not drive anything - clipped. +Signal PHI2_N_120 was merged into signal PHI2_c +Signal n1407 was merged into signal nRowColSel_N_34 +Signal n2380 was merged into signal Ready +Signal n1408 was merged into signal nRowColSel_N_35 +Signal nRWE_N_176 was merged into signal nRWE_N_177 +Signal GND_net undriven or does not drive anything - clipped. +Signal VCC_net undriven or does not drive anything - clipped. +Signal FS_610_add_4_19/S1 undriven or does not drive anything - clipped. +Signal FS_610_add_4_19/CO undriven or does not drive anything - clipped. +Signal FS_610_add_4_1/S0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_1/CI undriven or does not drive anything - clipped. +Block i2046 was optimized away. +Block i1118_1_lut was optimized away. +Block i637_1_lut_rep_31 was optimized away. +Block i1119_1_lut was optimized away. +Block nRWE_I_50_1_lut was optimized away. +Block i1 was optimized away. + + + +Run Time and Memory Usage +------------------------- + + Total CPU Time: 0 secs + Total REAL Time: 0 secs + Peak Memory Usage: 35 MB + + + + + + + + Page 5 + + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. + Copyright (c) 1995 AT&T Corp. All rights reserved. + Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. + Copyright (c) 2001 Agere Systems All rights reserved. + Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights + reserved. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt new file mode 100644 index 0000000..2d70ad1 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mt @@ -0,0 +1,9 @@ +-v +1 + + +-gt + + +-mapchkpnt 0 +-sethld diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd new file mode 100644 index 0000000..f841f90 Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd differ diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ngd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ngd new file mode 100644 index 0000000..d2fd856 Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ngd differ diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p2t b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p2t new file mode 100644 index 0000000..16daf53 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p2t @@ -0,0 +1,9 @@ +-w +-l 5 +-i 6 +-n 1 +-t 1 +-s 1 +-c 0 +-e 0 +-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p3t b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p3t new file mode 100644 index 0000000..6ff5632 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.p3t @@ -0,0 +1,5 @@ +-rem +-distrce +-log "RAM2GS_LCMXO2_640HC_impl1.log" +-o "RAM2GS_LCMXO2_640HC_impl1.csv" +-pr "RAM2GS_LCMXO2_640HC_impl1.prf" diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pad b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pad new file mode 100644 index 0000000..0e66e0f --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pad @@ -0,0 +1,281 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO2-640HC +Performance Grade: 4 +PACKAGE: TQFP100 +Package Status: Final Version 1.39 + +Tue Aug 15 05:03:32 2023 + +Pinout by Port Name: ++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | ++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ +| CROW[0] | 10/3 | LVCMOS25_IN | PL3D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| CROW[1] | 16/3 | LVCMOS25_IN | PL6A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[0] | 3/3 | LVCMOS25_IN | PL2C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[1] | 96/0 | LVCMOS25_IN | PT6D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[2] | 88/0 | LVCMOS25_IN | PT9A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[3] | 97/0 | LVCMOS25_IN | PT6C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[4] | 99/0 | LVCMOS25_IN | PT6A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[5] | 98/0 | LVCMOS25_IN | PT6B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[6] | 2/3 | LVCMOS25_IN | PL2B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Din[7] | 1/3 | LVCMOS25_IN | PL2A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| Dout[0] | 76/0 | LVCMOS25_OUT | PT11D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[1] | 86/0 | LVCMOS25_OUT | PT9C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[2] | 87/0 | LVCMOS25_OUT | PT9B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[3] | 85/0 | LVCMOS25_OUT | PT9D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[4] | 83/0 | LVCMOS25_OUT | PT10B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[5] | 84/0 | LVCMOS25_OUT | PT10A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[6] | 78/0 | LVCMOS25_OUT | PT11A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| Dout[7] | 82/0 | LVCMOS25_OUT | PT10C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| LED | 34/2 | LVCMOS25_OUT | PB6C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| MAin[0] | 14/3 | LVCMOS25_IN | PL5C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[1] | 12/3 | LVCMOS25_IN | PL5A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[2] | 13/3 | LVCMOS25_IN | PL5B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[3] | 21/3 | LVCMOS25_IN | PL7B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[4] | 20/3 | LVCMOS25_IN | PL7A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[5] | 19/3 | LVCMOS25_IN | PL6D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[6] | 24/3 | LVCMOS25_IN | PL7C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[7] | 18/3 | LVCMOS25_IN | PL6C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[8] | 25/3 | LVCMOS25_IN | PL7D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| MAin[9] | 32/2 | LVCMOS25_IN | PB6B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| PHI2 | 8/3 | LVCMOS25_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| RA[0] | 66/1 | LVCMOS25_OUT | PR3D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[10] | 64/1 | LVCMOS25_OUT | PR5B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[11] | 59/1 | LVCMOS25_OUT | PR6B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[1] | 67/1 | LVCMOS25_OUT | PR3C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[2] | 69/1 | LVCMOS25_OUT | PR3A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[3] | 71/1 | LVCMOS25_OUT | PR2C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[4] | 74/1 | LVCMOS25_OUT | PR2B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[5] | 70/1 | LVCMOS25_OUT | PR2D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[6] | 68/1 | LVCMOS25_OUT | PR3B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[7] | 75/1 | LVCMOS25_OUT | PR2A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[8] | 65/1 | LVCMOS25_OUT | PR5A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RA[9] | 63/1 | LVCMOS25_OUT | PR5C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RBA[0] | 58/1 | LVCMOS25_OUT | PR6C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RBA[1] | 60/1 | LVCMOS25_OUT | PR6A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RCKE | 53/1 | LVCMOS25_OUT | PR7B | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RCLK | 62/1 | LVCMOS25_IN | PR5D | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| RDQMH | 51/1 | LVCMOS25_OUT | PR7D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RDQML | 48/2 | LVCMOS25_OUT | PB14C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| RD[0] | 36/2 | LVCMOS25_BIDI | PB10A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[1] | 37/2 | LVCMOS25_BIDI | PB10B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[2] | 38/2 | LVCMOS25_BIDI | PB10C | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[3] | 39/2 | LVCMOS25_BIDI | PB10D | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[4] | 40/2 | LVCMOS25_BIDI | PB12A | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[5] | 41/2 | LVCMOS25_BIDI | PB12B | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[6] | 42/2 | LVCMOS25_BIDI | PB12C | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[7] | 43/2 | LVCMOS25_BIDI | PB12D | | | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| UFMCLK | 29/2 | LVCMOS25_OUT | PB4C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| UFMSDI | 30/2 | LVCMOS25_OUT | PB4D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| UFMSDO | 27/2 | LVCMOS25_IN | PB4A | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nCCAS | 9/3 | LVCMOS25_IN | PL3C | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nCRAS | 17/3 | LVCMOS25_IN | PL6B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nFWE | 28/2 | LVCMOS25_IN | PB4B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL | +| nRCAS | 52/1 | LVCMOS25_OUT | PR7C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nRCS | 57/1 | LVCMOS25_OUT | PR6D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nRRAS | 54/1 | LVCMOS25_OUT | PR7A | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nRWE | 49/2 | LVCMOS25_OUT | PB14D | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | +| nUFMCS | 77/0 | LVCMOS25_OUT | PT11C | | | DRIVE:8mA PULL:DOWN SLEW:SLOW | ++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 2.5V | +| 1 | 2.5V | +| 2 | 2.5V | +| 3 | 2.5V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| 1/3 | Din[7] | LOCATED | LVCMOS25_IN | PL2A | | | | +| 2/3 | Din[6] | LOCATED | LVCMOS25_IN | PL2B | | | | +| 3/3 | Din[0] | LOCATED | LVCMOS25_IN | PL2C | PCLKT3_2 | | | +| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | | +| 7/3 | unused, PULL:DOWN | | | PL3A | | | | +| 8/3 | PHI2 | LOCATED | LVCMOS25_IN | PL3B | | | | +| 9/3 | nCCAS | LOCATED | LVCMOS25_IN | PL3C | | | | +| 10/3 | CROW[0] | LOCATED | LVCMOS25_IN | PL3D | | | | +| 12/3 | MAin[1] | LOCATED | LVCMOS25_IN | PL5A | PCLKT3_1 | | | +| 13/3 | MAin[2] | LOCATED | LVCMOS25_IN | PL5B | PCLKC3_1 | | | +| 14/3 | MAin[0] | LOCATED | LVCMOS25_IN | PL5C | | | | +| 15/3 | unused, PULL:DOWN | | | PL5D | | | | +| 16/3 | CROW[1] | LOCATED | LVCMOS25_IN | PL6A | | | | +| 17/3 | nCRAS | LOCATED | LVCMOS25_IN | PL6B | | | | +| 18/3 | MAin[7] | LOCATED | LVCMOS25_IN | PL6C | | | | +| 19/3 | MAin[5] | LOCATED | LVCMOS25_IN | PL6D | | | | +| 20/3 | MAin[4] | LOCATED | LVCMOS25_IN | PL7A | PCLKT3_0 | | | +| 21/3 | MAin[3] | LOCATED | LVCMOS25_IN | PL7B | PCLKC3_0 | | | +| 24/3 | MAin[6] | LOCATED | LVCMOS25_IN | PL7C | | | | +| 25/3 | MAin[8] | LOCATED | LVCMOS25_IN | PL7D | | | | +| 27/2 | UFMSDO | LOCATED | LVCMOS25_IN | PB4A | CSSPIN | | | +| 28/2 | nFWE | LOCATED | LVCMOS25_IN | PB4B | | | | +| 29/2 | UFMCLK | LOCATED | LVCMOS25_OUT | PB4C | | | | +| 30/2 | UFMSDI | LOCATED | LVCMOS25_OUT | PB4D | | | | +| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | | +| 32/2 | MAin[9] | LOCATED | LVCMOS25_IN | PB6B | SO/SPISO | | | +| 34/2 | LED | LOCATED | LVCMOS25_OUT | PB6C | PCLKT2_0 | | | +| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | | +| 36/2 | RD[0] | LOCATED | LVCMOS25_BIDI | PB10A | | | | +| 37/2 | RD[1] | LOCATED | LVCMOS25_BIDI | PB10B | | | | +| 38/2 | RD[2] | LOCATED | LVCMOS25_BIDI | PB10C | PCLKT2_1 | | | +| 39/2 | RD[3] | LOCATED | LVCMOS25_BIDI | PB10D | PCLKC2_1 | | | +| 40/2 | RD[4] | LOCATED | LVCMOS25_BIDI | PB12A | | | | +| 41/2 | RD[5] | LOCATED | LVCMOS25_BIDI | PB12B | | | | +| 42/2 | RD[6] | LOCATED | LVCMOS25_BIDI | PB12C | | | | +| 43/2 | RD[7] | LOCATED | LVCMOS25_BIDI | PB12D | | | | +| 45/2 | unused, PULL:DOWN | | | PB14A | | | | +| 47/2 | unused, PULL:DOWN | | | PB14B | | | | +| 48/2 | RDQML | LOCATED | LVCMOS25_OUT | PB14C | SN | | | +| 49/2 | nRWE | LOCATED | LVCMOS25_OUT | PB14D | SI/SISPI | | | +| 51/1 | RDQMH | LOCATED | LVCMOS25_OUT | PR7D | | | | +| 52/1 | nRCAS | LOCATED | LVCMOS25_OUT | PR7C | | | | +| 53/1 | RCKE | LOCATED | LVCMOS25_OUT | PR7B | | | | +| 54/1 | nRRAS | LOCATED | LVCMOS25_OUT | PR7A | | | | +| 57/1 | nRCS | LOCATED | LVCMOS25_OUT | PR6D | | | | +| 58/1 | RBA[0] | LOCATED | LVCMOS25_OUT | PR6C | | | | +| 59/1 | RA[11] | LOCATED | LVCMOS25_OUT | PR6B | | | | +| 60/1 | RBA[1] | LOCATED | LVCMOS25_OUT | PR6A | | | | +| 62/1 | RCLK | LOCATED | LVCMOS25_IN | PR5D | PCLKC1_0 | | | +| 63/1 | RA[9] | LOCATED | LVCMOS25_OUT | PR5C | PCLKT1_0 | | | +| 64/1 | RA[10] | LOCATED | LVCMOS25_OUT | PR5B | | | | +| 65/1 | RA[8] | LOCATED | LVCMOS25_OUT | PR5A | | | | +| 66/1 | RA[0] | LOCATED | LVCMOS25_OUT | PR3D | | | | +| 67/1 | RA[1] | LOCATED | LVCMOS25_OUT | PR3C | | | | +| 68/1 | RA[6] | LOCATED | LVCMOS25_OUT | PR3B | | | | +| 69/1 | RA[2] | LOCATED | LVCMOS25_OUT | PR3A | | | | +| 70/1 | RA[5] | LOCATED | LVCMOS25_OUT | PR2D | | | | +| 71/1 | RA[3] | LOCATED | LVCMOS25_OUT | PR2C | | | | +| 74/1 | RA[4] | LOCATED | LVCMOS25_OUT | PR2B | | | | +| 75/1 | RA[7] | LOCATED | LVCMOS25_OUT | PR2A | | | | +| 76/0 | Dout[0] | LOCATED | LVCMOS25_OUT | PT11D | DONE | | | +| 77/0 | nUFMCS | | LVCMOS25_OUT | PT11C | INITN | | | +| 78/0 | Dout[6] | LOCATED | LVCMOS25_OUT | PT11A | | | | +| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | | +| 82/0 | Dout[7] | LOCATED | LVCMOS25_OUT | PT10C | JTAGENB | | | +| 83/0 | Dout[4] | LOCATED | LVCMOS25_OUT | PT10B | | | | +| 84/0 | Dout[5] | LOCATED | LVCMOS25_OUT | PT10A | | | | +| 85/0 | Dout[3] | LOCATED | LVCMOS25_OUT | PT9D | SDA/PCLKC0_0 | | | +| 86/0 | Dout[1] | LOCATED | LVCMOS25_OUT | PT9C | SCL/PCLKT0_0 | | | +| 87/0 | Dout[2] | LOCATED | LVCMOS25_OUT | PT9B | PCLKC0_1 | | | +| 88/0 | Din[2] | LOCATED | LVCMOS25_IN | PT9A | PCLKT0_1 | | | +| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | | +| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | | +| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | | +| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | | +| 96/0 | Din[1] | LOCATED | LVCMOS25_IN | PT6D | | | | +| 97/0 | Din[3] | LOCATED | LVCMOS25_IN | PT6C | | | | +| 98/0 | Din[5] | LOCATED | LVCMOS25_IN | PT6B | | | | +| 99/0 | Din[4] | LOCATED | LVCMOS25_IN | PT6A | | | | +| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ + +sysCONFIG Pins: ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | +| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | +| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | +| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | ++----------+--------------------+--------------------+----------+-------------+-------------------+ + +Dedicated sysCONFIG Pins: + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "10"; +LOCATE COMP "CROW[1]" SITE "16"; +LOCATE COMP "Din[0]" SITE "3"; +LOCATE COMP "Din[1]" SITE "96"; +LOCATE COMP "Din[2]" SITE "88"; +LOCATE COMP "Din[3]" SITE "97"; +LOCATE COMP "Din[4]" SITE "99"; +LOCATE COMP "Din[5]" SITE "98"; +LOCATE COMP "Din[6]" SITE "2"; +LOCATE COMP "Din[7]" SITE "1"; +LOCATE COMP "Dout[0]" SITE "76"; +LOCATE COMP "Dout[1]" SITE "86"; +LOCATE COMP "Dout[2]" SITE "87"; +LOCATE COMP "Dout[3]" SITE "85"; +LOCATE COMP "Dout[4]" SITE "83"; +LOCATE COMP "Dout[5]" SITE "84"; +LOCATE COMP "Dout[6]" SITE "78"; +LOCATE COMP "Dout[7]" SITE "82"; +LOCATE COMP "LED" SITE "34"; +LOCATE COMP "MAin[0]" SITE "14"; +LOCATE COMP "MAin[1]" SITE "12"; +LOCATE COMP "MAin[2]" SITE "13"; +LOCATE COMP "MAin[3]" SITE "21"; +LOCATE COMP "MAin[4]" SITE "20"; +LOCATE COMP "MAin[5]" SITE "19"; +LOCATE COMP "MAin[6]" SITE "24"; +LOCATE COMP "MAin[7]" SITE "18"; +LOCATE COMP "MAin[8]" SITE "25"; +LOCATE COMP "MAin[9]" SITE "32"; +LOCATE COMP "PHI2" SITE "8"; +LOCATE COMP "RA[0]" SITE "66"; +LOCATE COMP "RA[10]" SITE "64"; +LOCATE COMP "RA[11]" SITE "59"; +LOCATE COMP "RA[1]" SITE "67"; +LOCATE COMP "RA[2]" SITE "69"; +LOCATE COMP "RA[3]" SITE "71"; +LOCATE COMP "RA[4]" SITE "74"; +LOCATE COMP "RA[5]" SITE "70"; +LOCATE COMP "RA[6]" SITE "68"; +LOCATE COMP "RA[7]" SITE "75"; +LOCATE COMP "RA[8]" SITE "65"; +LOCATE COMP "RA[9]" SITE "63"; +LOCATE COMP "RBA[0]" SITE "58"; +LOCATE COMP "RBA[1]" SITE "60"; +LOCATE COMP "RCKE" SITE "53"; +LOCATE COMP "RCLK" SITE "62"; +LOCATE COMP "RDQMH" SITE "51"; +LOCATE COMP "RDQML" SITE "48"; +LOCATE COMP "RD[0]" SITE "36"; +LOCATE COMP "RD[1]" SITE "37"; +LOCATE COMP "RD[2]" SITE "38"; +LOCATE COMP "RD[3]" SITE "39"; +LOCATE COMP "RD[4]" SITE "40"; +LOCATE COMP "RD[5]" SITE "41"; +LOCATE COMP "RD[6]" SITE "42"; +LOCATE COMP "RD[7]" SITE "43"; +LOCATE COMP "UFMCLK" SITE "29"; +LOCATE COMP "UFMSDI" SITE "30"; +LOCATE COMP "UFMSDO" SITE "27"; +LOCATE COMP "nCCAS" SITE "9"; +LOCATE COMP "nCRAS" SITE "17"; +LOCATE COMP "nFWE" SITE "28"; +LOCATE COMP "nRCAS" SITE "52"; +LOCATE COMP "nRCS" SITE "57"; +LOCATE COMP "nRRAS" SITE "54"; +LOCATE COMP "nRWE" SITE "49"; +LOCATE COMP "nUFMCS" SITE "77"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:34 2023 + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.par b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.par new file mode 100644 index 0000000..641fa59 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.par @@ -0,0 +1,259 @@ +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:28 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t +RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir +RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml + + +Preference file: RAM2GS_LCMXO2_640HC_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 -5.122 452301 0.304 0 07 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd" +Tue Aug 15 05:03:28 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Preference file: RAM2GS_LCMXO2_640HC_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67+4(JTAG)/80 89% used + 67+4(JTAG)/79 90% bonded + + SLICE 75/320 23% used + + + +Number of Signals: 285 +Number of Connections: 674 +WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors. + +Pin Constraint Summary: + 66 out of 67 pins locked (98% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + +WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + +WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. +No signal is selected as Global Set/Reset. +. +Starting Placer Phase 0. +............. +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +............... +Placer score = 121531. +Finished Placer Phase 1. REAL time: 4 secs + +Starting Placer Phase 2. +. +Placer score = 119079 +Finished Placer Phase 2. REAL time: 4 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 0 out of 8 (0%) + General PIO: 3 out of 80 (3%) + DCM : 0 out of 2 (0%) + DCC : 0 out of 8 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 8 (25%) + SECONDARY: 1 out of 8 (12%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 + 4(JTAG) out of 80 (88.8%) PIO sites used. + 67 + 4(JTAG) out of 79 (89.9%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+-----------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref | ++----------+----------------+------------+-----------+ +| 0 | 14 / 19 ( 73%) | 2.5V | - | +| 1 | 20 / 20 (100%) | 2.5V | - | +| 2 | 16 / 20 ( 80%) | 2.5V | - | +| 3 | 17 / 20 ( 85%) | 2.5V | - | ++----------+----------------+------------+-----------+ + +Total placer CPU time: 3 secs + +Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. + +0 connections routed; 674 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. +WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=6 clock_loads=4 + +Completed router resource preassignment. Real time: 7 secs + +Start NBR router at 05:03:35 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:35 08/15/23 + +Start NBR section for initial routing at 05:03:35 08/15/23 +Level 1, iteration 1 +2(0.00%) conflicts; 536(79.53%) untouched conns; 481988 (nbr) score; +Estimated worst slack/total negative slack: -4.914ns/-481.988ns; real time: 7 secs +Level 2, iteration 1 +7(0.02%) conflicts; 473(70.18%) untouched conns; 424953 (nbr) score; +Estimated worst slack/total negative slack: -4.988ns/-424.953ns; real time: 7 secs +Level 3, iteration 1 +12(0.03%) conflicts; 254(37.69%) untouched conns; 455640 (nbr) score; +Estimated worst slack/total negative slack: -5.118ns/-455.640ns; real time: 7 secs +Level 4, iteration 1 +6(0.01%) conflicts; 0(0.00%) untouched conn; 465237 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-465.237ns; real time: 7 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:35 08/15/23 +Level 4, iteration 1 +6(0.01%) conflicts; 0(0.00%) untouched conn; 461186 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.186ns; real time: 7 secs +Level 4, iteration 2 +3(0.01%) conflicts; 0(0.00%) untouched conn; 460933 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-460.933ns; real time: 7 secs +Level 4, iteration 3 +2(0.00%) conflicts; 0(0.00%) untouched conn; 461063 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs +Level 4, iteration 4 +1(0.00%) conflict; 0(0.00%) untouched conn; 461063 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs +Level 4, iteration 5 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:35 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for re-routing at 05:03:35 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for post-routing at 05:03:35 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 260 (38.58%) + Estimated worst slack : -5.122ns + Timing score : 452301 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=6 clock_loads=4 + +Total CPU time 7 secs +Total REAL time: 7 secs +Completely routed. +End of route. 674 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 452301 + +Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -5.122 +PAR_SUMMARY::Timing score> = 452.301 +PAR_SUMMARY::Worst slack> = 0.304 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 7 secs +Total REAL time to completion: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf new file mode 100644 index 0000000..ccdc34a --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf @@ -0,0 +1,80 @@ +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:24 2023 + +SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "RD[7]" SITE "43" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[9]" SITE "63" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[7]" SITE "75" ; +LOCATE COMP "RA[6]" SITE "68" ; +LOCATE COMP "RA[5]" SITE "70" ; +LOCATE COMP "RA[4]" SITE "74" ; +LOCATE COMP "RA[3]" SITE "71" ; +LOCATE COMP "RA[2]" SITE "69" ; +LOCATE COMP "RA[1]" SITE "67" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "nRCS" SITE "57" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "UFMCLK" SITE "29" ; +LOCATE COMP "UFMSDI" SITE "30" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "MAin[9]" SITE "32" ; +LOCATE COMP "MAin[8]" SITE "25" ; +LOCATE COMP "MAin[7]" SITE "18" ; +LOCATE COMP "MAin[6]" SITE "24" ; +LOCATE COMP "MAin[5]" SITE "19" ; +LOCATE COMP "MAin[4]" SITE "20" ; +LOCATE COMP "MAin[3]" SITE "21" ; +LOCATE COMP "MAin[2]" SITE "13" ; +LOCATE COMP "MAin[1]" SITE "12" ; +LOCATE COMP "MAin[0]" SITE "14" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "CROW[0]" SITE "10" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "nFWE" SITE "28" ; +LOCATE COMP "RCLK" SITE "62" ; +LOCATE COMP "UFMSDO" SITE "27" ; +SCHEMATIC END ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +COMMERCIAL ; + +// No timing preferences found. TRCE invokes auto-generation of timing preferences +// Section Autogen +FREQUENCY NET "RCLK_c" 299.401 MHz ; +FREQUENCY NET "PHI2_c" 99.079 MHz ; +// End Section Autogen diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pt b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pt new file mode 100644 index 0000000..e5e32de --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pt @@ -0,0 +1,10 @@ +-v +10 + + + + +-gt +-sethld +-sp 4 +-sphld m diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b new file mode 100644 index 0000000..a0ffb20 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.t2b @@ -0,0 +1,5 @@ + + +-g RamCfg:Reset + +-path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC" diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 new file mode 100644 index 0000000..4d39d68 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1 @@ -0,0 +1,349 @@ + +Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:25 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd +Preference file: ram2gs_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,4 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + 459 items scored, 245 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 3.815ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i13 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 6.873ns (28.2% logic, 71.8% route), 4 logic levels. + + Constraint Details: + + 6.873ns physical path delay SLICE_0 to SLICE_57 exceeds + 3.340ns delay constraint less + 0.282ns CE_SET requirement (totaling 3.058ns) by 3.815ns + + Physical Path Details: + + Data path SLICE_0 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 SLICE_0.CLK to SLICE_0.Q0 SLICE_0 (from RCLK_c) +ROUTE 3 e 1.234 SLICE_0.Q0 to SLICE_85.B0 FS_13 +CTOF_DEL --- 0.495 SLICE_85.B0 to SLICE_85.F0 SLICE_85 +ROUTE 5 e 1.234 SLICE_85.F0 to SLICE_57.A1 n10 +CTOF_DEL --- 0.495 SLICE_57.A1 to SLICE_57.F1 SLICE_57 +ROUTE 2 e 1.234 SLICE_57.F1 to SLICE_84.A0 n2367 +CTOF_DEL --- 0.495 SLICE_84.A0 to SLICE_84.F0 SLICE_84 +ROUTE 1 e 1.234 SLICE_84.F0 to SLICE_57.CE RCLK_c_enable_15 (to RCLK_c) + -------- + 6.873 (28.2% logic, 71.8% route), 4 logic levels. + +Warning: 139.762MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + 113 items scored, 104 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 4.837ns (weighted slack = -9.674ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels. + + Constraint Details: + + 9.577ns physical path delay SLICE_101 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.307ns CE_SET requirement (totaling 4.740ns) by 4.837ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 SLICE_101.CLK to SLICE_101.Q1 SLICE_101 (from PHI2_c) +ROUTE 1 e 1.234 SLICE_101.Q1 to SLICE_100.C1 Bank_7 +CTOF_DEL --- 0.495 SLICE_100.C1 to SLICE_100.F1 SLICE_100 +ROUTE 1 e 1.234 SLICE_100.F1 to SLICE_74.B1 n2277 +CTOF_DEL --- 0.495 SLICE_74.B1 to SLICE_74.F1 SLICE_74 +ROUTE 8 e 1.234 SLICE_74.F1 to SLICE_91.B1 n26 +CTOF_DEL --- 0.495 SLICE_91.B1 to SLICE_91.F1 SLICE_91 +ROUTE 1 e 1.234 SLICE_91.F1 to SLICE_88.D0 n2362 +CTOF_DEL --- 0.495 SLICE_88.D0 to SLICE_88.F0 SLICE_88 +ROUTE 3 e 0.480 SLICE_88.F0 to SLICE_88.C1 C1Submitted_N_237 +CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88 +ROUTE 1 e 1.234 SLICE_88.F1 to SLICE_19.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 9.577 (30.6% logic, 69.4% route), 6 logic levels. + +Warning: 50.592MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 299.401 MHz| 139.762 MHz| 4 * + | | | +FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 99.079 MHz| 50.592 MHz| 6 * + | | | +---------------------------------------------------------------------------- + + +2 preferences(marked by "*" above) not met. + +---------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +---------------------------------------------------------------------------- +n26 | 8| 78| 22.35% + | | | +---------------------------------------------------------------------------- + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 349 Score: 848079 +Cumulative negative slack: 584487 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:25 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd +Preference file: ram2gs_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + 459 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.351ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i4 (from RCLK_c +) + Destination: FF Data in IS_FSM__i5 (to RCLK_c +) + + Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels. + + Constraint Details: + + 0.332ns physical path delay SLICE_106 to SLICE_106 meets + -0.019ns M_HLD and + 0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns + + Physical Path Details: + + Data path SLICE_106 to SLICE_106: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 SLICE_106.CLK to SLICE_106.Q0 SLICE_106 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_106.Q0 to SLICE_106.M1 n736 (to RCLK_c) + -------- + 0.332 (40.1% logic, 59.9% route), 1 logic levels. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + 113 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.447ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels. + + Constraint Details: + + 0.434ns physical path delay SLICE_15 to SLICE_15 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns + + Physical Path Details: + + Data path SLICE_15 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 SLICE_15.CLK to SLICE_15.Q0 SLICE_15 (from PHI2_c) +ROUTE 2 e 0.199 SLICE_15.Q0 to SLICE_15.C0 C1Submitted +CTOF_DEL --- 0.101 SLICE_15.C0 to SLICE_15.F0 SLICE_15 +ROUTE 1 e 0.001 SLICE_15.F0 to SLICE_15.DI0 n1398 (to PHI2_c) + -------- + 0.434 (53.9% logic, 46.1% route), 2 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 0.000 ns| 0.351 ns| 1 + | | | +FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 0.000 ns| 0.447 ns| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 349 (setup), 0 (hold) +Score: 848079 (setup), 0 (hold) +Cumulative negative slack: 584487 (584487+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr new file mode 100644 index 0000000..813d789 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr @@ -0,0 +1,2164 @@ + +Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:36 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Design file: ram2gs_lcmxo2_640hc_impl1.ncd +Preference file: ram2gs_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,4 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + 459 items scored, 264 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 2.902ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in UFMSDI_417 (to RCLK_c +) + + Delay: 6.076ns (40.0% logic, 60.0% route), 5 logic levels. + + Constraint Details: + + 6.076ns physical path delay SLICE_1 to SLICE_45 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.902ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_45: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C8C.CLK to R6C8C.Q1 SLICE_1 (from RCLK_c) +ROUTE 5 0.984 R6C8C.Q1 to R4C8D.D1 FS_12 +CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 SLICE_80 +ROUTE 3 1.598 R4C8D.F1 to R4C7B.C1 n2375 +CTOF_DEL --- 0.495 R4C7B.C1 to R4C7B.F1 SLICE_95 +ROUTE 1 0.436 R4C7B.F1 to R4C7A.C1 n7 +CTOF_DEL --- 0.495 R4C7A.C1 to R4C7A.F1 SLICE_45 +ROUTE 1 0.626 R4C7A.F1 to R4C7A.D0 n2174 +CTOF_DEL --- 0.495 R4C7A.D0 to R4C7A.F0 SLICE_45 +ROUTE 1 0.000 R4C7A.F0 to R4C7A.DI0 UFMSDI_N_231 (to RCLK_c) + -------- + 6.076 (40.0% logic, 60.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C8C.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_45: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C7A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.710ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i14 (from RCLK_c +) + Destination: FF Data in UFMSDI_417 (to RCLK_c +) + + Delay: 5.884ns (41.3% logic, 58.7% route), 5 logic levels. + + Constraint Details: + + 5.884ns physical path delay SLICE_0 to SLICE_45 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.710ns + + Physical Path Details: + + Data path SLICE_0 to SLICE_45: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C8D.CLK to R6C8D.Q1 SLICE_0 (from RCLK_c) +ROUTE 5 0.792 R6C8D.Q1 to R4C8D.C1 FS_14 +CTOF_DEL --- 0.495 R4C8D.C1 to R4C8D.F1 SLICE_80 +ROUTE 3 1.598 R4C8D.F1 to R4C7B.C1 n2375 +CTOF_DEL --- 0.495 R4C7B.C1 to R4C7B.F1 SLICE_95 +ROUTE 1 0.436 R4C7B.F1 to R4C7A.C1 n7 +CTOF_DEL --- 0.495 R4C7A.C1 to R4C7A.F1 SLICE_45 +ROUTE 1 0.626 R4C7A.F1 to R4C7A.D0 n2174 +CTOF_DEL --- 0.495 R4C7A.D0 to R4C7A.F0 SLICE_45 +ROUTE 1 0.000 R4C7A.F0 to R4C7A.DI0 UFMSDI_N_231 (to RCLK_c) + -------- + 5.884 (41.3% logic, 58.7% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C8D.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_45: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C7A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.665ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CASr2_383 (from RCLK_c +) + Destination: FF Data in nRCS_396 (to RCLK_c +) + + Delay: 5.839ns (41.7% logic, 58.3% route), 5 logic levels. + + Constraint Details: + + 5.839ns physical path delay SLICE_16 to SLICE_61 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.665ns + + Physical Path Details: + + Data path SLICE_16 to SLICE_61: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C9B.CLK to R4C9B.Q1 SLICE_16 (from RCLK_c) +ROUTE 3 1.000 R4C9B.Q1 to R6C9D.A0 CASr2 +CTOF_DEL --- 0.495 R6C9D.A0 to R6C9D.F0 SLICE_96 +ROUTE 2 0.976 R6C9D.F0 to R6C9C.A0 nRCS_N_146 +CTOF_DEL --- 0.495 R6C9C.A0 to R6C9C.F0 SLICE_81 +ROUTE 2 0.995 R6C9C.F0 to R6C11D.A1 nRCS_N_142 +CTOF_DEL --- 0.495 R6C11D.A1 to R6C11D.F1 SLICE_61 +ROUTE 1 0.436 R6C11D.F1 to R6C11D.C0 nRCS_N_141 +CTOF_DEL --- 0.495 R6C11D.C0 to R6C11D.F0 SLICE_61 +ROUTE 1 0.000 R6C11D.F0 to R6C11D.DI0 nRCS_N_136 (to RCLK_c) + -------- + 5.839 (41.7% logic, 58.3% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_16: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C9B.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_61: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C11D.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.621ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 5.679ns (34.1% logic, 65.9% route), 4 logic levels. + + Constraint Details: + + 5.679ns physical path delay SLICE_9 to SLICE_57 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.282ns CE_SET requirement (totaling 3.058ns) by 2.621ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C9A.CLK to R6C9A.Q0 SLICE_9 (from RCLK_c) +ROUTE 3 1.320 R6C9A.Q0 to R4C8A.A0 FS_15 +CTOF_DEL --- 0.495 R4C8A.A0 to R4C8A.F0 SLICE_85 +ROUTE 5 0.793 R4C8A.F0 to R4C8B.C1 n10 +CTOF_DEL --- 0.495 R4C8B.C1 to R4C8B.F1 SLICE_57 +ROUTE 2 0.976 R4C8B.F1 to R4C8C.A0 n2367 +CTOF_DEL --- 0.495 R4C8C.A0 to R4C8C.F0 SLICE_84 +ROUTE 1 0.653 R4C8C.F0 to R4C8B.CE RCLK_c_enable_15 (to RCLK_c) + -------- + 5.679 (34.1% logic, 65.9% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C9A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C8B.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.513ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 5.571ns (34.8% logic, 65.2% route), 4 logic levels. + + Constraint Details: + + 5.571ns physical path delay SLICE_1 to SLICE_57 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.282ns CE_SET requirement (totaling 3.058ns) by 2.513ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C8C.CLK to R6C8C.Q1 SLICE_1 (from RCLK_c) +ROUTE 5 0.984 R6C8C.Q1 to R4C8D.D1 FS_12 +CTOF_DEL --- 0.495 R4C8D.D1 to R4C8D.F1 SLICE_80 +ROUTE 3 1.021 R4C8D.F1 to R4C8B.B1 n2375 +CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_57 +ROUTE 2 0.976 R4C8B.F1 to R4C8C.A0 n2367 +CTOF_DEL --- 0.495 R4C8C.A0 to R4C8C.F0 SLICE_84 +ROUTE 1 0.653 R4C8C.F0 to R4C8B.CE RCLK_c_enable_15 (to RCLK_c) + -------- + 5.571 (34.8% logic, 65.2% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C8C.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C8B.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.487ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i3 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 5.545ns (34.9% logic, 65.1% route), 4 logic levels. + + Constraint Details: + + 5.545ns physical path delay SLICE_8 to SLICE_57 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.282ns CE_SET requirement (totaling 3.058ns) by 2.487ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_57: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C7C.CLK to R6C7C.Q0 SLICE_8 (from RCLK_c) +ROUTE 2 1.306 R6C7C.Q0 to R4C7D.A1 FS_3 +CTOF_DEL --- 0.495 R4C7D.A1 to R4C7D.F1 SLICE_86 +ROUTE 1 1.004 R4C7D.F1 to R4C7D.B0 n14 +CTOF_DEL --- 0.495 R4C7D.B0 to R4C7D.F0 SLICE_86 +ROUTE 1 0.645 R4C7D.F0 to R4C8C.D0 n4_adj_7 +CTOF_DEL --- 0.495 R4C8C.D0 to R4C8C.F0 SLICE_84 +ROUTE 1 0.653 R4C8C.F0 to R4C8B.CE RCLK_c_enable_15 (to RCLK_c) + -------- + 5.545 (34.9% logic, 65.1% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C7C.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_57: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C8B.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.479ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in nUFMCS_415 (to RCLK_c +) + + Delay: 5.653ns (43.0% logic, 57.0% route), 5 logic levels. + + Constraint Details: + + 5.653ns physical path delay SLICE_9 to SLICE_70 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.479ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_70: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C9A.CLK to R6C9A.Q0 SLICE_9 (from RCLK_c) +ROUTE 3 1.320 R6C9A.Q0 to R4C8A.A0 FS_15 +CTOF_DEL --- 0.495 R4C8A.A0 to R4C8A.F0 SLICE_85 +ROUTE 5 0.640 R4C8A.F0 to R4C9D.D1 n10 +CTOF_DEL --- 0.495 R4C9D.D1 to R4C9D.F1 SLICE_76 +ROUTE 2 0.635 R4C9D.F1 to R4C9A.D1 n2368 +CTOF_DEL --- 0.495 R4C9A.D1 to R4C9A.F1 SLICE_70 +ROUTE 1 0.626 R4C9A.F1 to R4C9A.D0 n64 +CTOF_DEL --- 0.495 R4C9A.D0 to R4C9A.F0 SLICE_70 +ROUTE 1 0.000 R4C9A.F0 to R4C9A.DI0 nUFMCS_N_199 (to RCLK_c) + -------- + 5.653 (43.0% logic, 57.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C9A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_70: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C9A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.452ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 5.626ns (43.2% logic, 56.8% route), 5 logic levels. + + Constraint Details: + + 5.626ns physical path delay SLICE_9 to SLICE_44 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.452ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C9A.CLK to R6C9A.Q0 SLICE_9 (from RCLK_c) +ROUTE 3 1.320 R6C9A.Q0 to R4C8A.A0 FS_15 +CTOF_DEL --- 0.495 R4C8A.A0 to R4C8A.F0 SLICE_85 +ROUTE 5 0.672 R4C8A.F0 to R4C8A.D1 n10 +CTOF_DEL --- 0.495 R4C8A.D1 to R4C8A.F1 SLICE_85 +ROUTE 1 0.766 R4C8A.F1 to R4C6B.C1 n2267 +CTOF_DEL --- 0.495 R4C6B.C1 to R4C6B.F1 SLICE_44 +ROUTE 1 0.436 R4C6B.F1 to R4C6B.C0 n1893 +CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 SLICE_44 +ROUTE 1 0.000 R4C6B.F0 to R4C6B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 5.626 (43.2% logic, 56.8% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C9A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C6B.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.438ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CASr3_384 (from RCLK_c +) + Destination: FF Data in nRCS_396 (to RCLK_c +) + + Delay: 5.612ns (43.3% logic, 56.7% route), 5 logic levels. + + Constraint Details: + + 5.612ns physical path delay SLICE_5 to SLICE_61 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.438ns + + Physical Path Details: + + Data path SLICE_5 to SLICE_61: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C7A.CLK to R6C7A.Q0 SLICE_5 (from RCLK_c) +ROUTE 2 0.773 R6C7A.Q0 to R6C9D.C0 CASr3 +CTOF_DEL --- 0.495 R6C9D.C0 to R6C9D.F0 SLICE_96 +ROUTE 2 0.976 R6C9D.F0 to R6C9C.A0 nRCS_N_146 +CTOF_DEL --- 0.495 R6C9C.A0 to R6C9C.F0 SLICE_81 +ROUTE 2 0.995 R6C9C.F0 to R6C11D.A1 nRCS_N_142 +CTOF_DEL --- 0.495 R6C11D.A1 to R6C11D.F1 SLICE_61 +ROUTE 1 0.436 R6C11D.F1 to R6C11D.C0 nRCS_N_141 +CTOF_DEL --- 0.495 R6C11D.C0 to R6C11D.F0 SLICE_61 +ROUTE 1 0.000 R6C11D.F0 to R6C11D.DI0 nRCS_N_136 (to RCLK_c) + -------- + 5.612 (43.3% logic, 56.7% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_5: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C7A.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_61: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C11D.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.423ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i13 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 5.597ns (43.5% logic, 56.5% route), 5 logic levels. + + Constraint Details: + + 5.597ns physical path delay SLICE_0 to SLICE_44 exceeds + 3.340ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 3.174ns) by 2.423ns + + Physical Path Details: + + Data path SLICE_0 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R6C8D.CLK to R6C8D.Q0 SLICE_0 (from RCLK_c) +ROUTE 3 1.433 R6C8D.Q0 to R6C6C.B0 FS_13 +CTOF_DEL --- 0.495 R6C6C.B0 to R6C6C.F0 SLICE_105 +ROUTE 1 0.315 R6C6C.F0 to R6C6A.D1 n12 +CTOF_DEL --- 0.495 R6C6A.D1 to R6C6A.F1 SLICE_82 +ROUTE 3 0.981 R6C6A.F1 to R4C6B.D1 n13_adj_6 +CTOF_DEL --- 0.495 R4C6B.D1 to R4C6B.F1 SLICE_44 +ROUTE 1 0.436 R4C6B.F1 to R4C6B.C0 n1893 +CTOF_DEL --- 0.495 R4C6B.C0 to R4C6B.F0 SLICE_44 +ROUTE 1 0.000 R4C6B.F0 to R4C6B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 5.597 (43.5% logic, 56.5% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R6C8D.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 3.070 62.PADDI to R4C6B.CLK RCLK_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + +Warning: 160.205MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + 113 items scored, 85 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 2.561ns (weighted slack = -5.122ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i3 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 7.301ns (40.1% logic, 59.9% route), 6 logic levels. + + Constraint Details: + + 7.301ns physical path delay SLICE_103 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 2.561ns + + Physical Path Details: + + Data path SLICE_103 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q1 SLICE_103 (from PHI2_c) +ROUTE 1 1.023 R5C9B.Q1 to R5C7A.B0 Bank_3 +CTOF_DEL --- 0.495 R5C7A.B0 to R5C7A.F0 SLICE_68 +ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 +CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 +ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 +CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 +ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 7.301 (40.1% logic, 59.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_103: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.184ns (weighted slack = -4.368ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i3 (from PHI2_c +) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 6.946ns (35.0% logic, 65.0% route), 5 logic levels. + + Constraint Details: + + 6.946ns physical path delay SLICE_103 to SLICE_10 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.285ns LSR_SET requirement (totaling 4.762ns) by 2.184ns + + Physical Path Details: + + Data path SLICE_103 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q1 SLICE_103 (from PHI2_c) +ROUTE 1 1.023 R5C9B.Q1 to R5C7A.B0 Bank_3 +CTOF_DEL --- 0.495 R5C7A.B0 to R5C7A.F0 SLICE_68 +ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 +CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 +ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 +CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 1.428 R5C9A.F0 to R3C8A.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 6.946 (35.0% logic, 65.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_103: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R3C8A.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.184ns (weighted slack = -4.368ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i3 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 6.946ns (35.0% logic, 65.0% route), 5 logic levels. + + Constraint Details: + + 6.946ns physical path delay SLICE_103 to SLICE_15 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.285ns LSR_SET requirement (totaling 4.762ns) by 2.184ns + + Physical Path Details: + + Data path SLICE_103 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R5C9B.CLK to R5C9B.Q1 SLICE_103 (from PHI2_c) +ROUTE 1 1.023 R5C9B.Q1 to R5C7A.B0 Bank_3 +CTOF_DEL --- 0.495 R5C7A.B0 to R5C7A.F0 SLICE_68 +ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 +CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 +ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 +CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 1.428 R5C9A.F0 to R3C8B.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 6.946 (35.0% logic, 65.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_103: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9B.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R3C8B.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.161ns (weighted slack = -4.322ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.901ns (42.4% logic, 57.6% route), 6 logic levels. + + Constraint Details: + + 6.901ns physical path delay SLICE_101 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 2.161ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q0 SLICE_101 (from PHI2_c) +ROUTE 1 0.623 R4C7C.Q0 to R5C7A.D0 Bank_6 +CTOF_DEL --- 0.495 R5C7A.D0 to R5C7A.F0 SLICE_68 +ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 +CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 +ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 +CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 +ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.901 (42.4% logic, 57.6% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R4C7C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.092ns (weighted slack = -4.184ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.832ns (42.8% logic, 57.2% route), 6 logic levels. + + Constraint Details: + + 6.832ns physical path delay SLICE_101 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 2.092ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q1 SLICE_101 (from PHI2_c) +ROUTE 1 0.744 R4C7C.Q1 to R5C7B.C1 Bank_7 +CTOF_DEL --- 0.495 R5C7B.C1 to R5C7B.F1 SLICE_100 +ROUTE 1 0.436 R5C7B.F1 to R5C7D.C1 n2277 +CTOF_DEL --- 0.495 R5C7D.C1 to R5C7D.F1 SLICE_74 +ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 +CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 +ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.832 (42.8% logic, 57.2% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R4C7C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 2.081ns (weighted slack = -4.162ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i4 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.821ns (42.9% logic, 57.1% route), 6 logic levels. + + Constraint Details: + + 6.821ns physical path delay SLICE_102 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 2.081ns + + Physical Path Details: + + Data path SLICE_102 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R5C6A.CLK to R5C6A.Q0 SLICE_102 (from PHI2_c) +ROUTE 1 0.766 R5C6A.Q0 to R5C8D.C1 Bank_4 +CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 SLICE_99 +ROUTE 2 0.635 R5C8D.F1 to R5C8B.D1 n22 +CTOF_DEL --- 0.495 R5C8B.D1 to R5C8B.F1 SLICE_79 +ROUTE 7 0.461 R5C8B.F1 to R5C8A.C1 n2369 +CTOF_DEL --- 0.495 R5C8A.C1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 +ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.821 (42.9% logic, 57.1% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_102: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C6A.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.971ns (weighted slack = -3.942ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.711ns (43.6% logic, 56.4% route), 6 logic levels. + + Constraint Details: + + 6.711ns physical path delay SLICE_93 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 1.971ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R5C8C.CLK to R5C8C.Q0 SLICE_93 (from PHI2_c) +ROUTE 1 0.623 R5C8C.Q0 to R5C7B.D1 Bank_0 +CTOF_DEL --- 0.495 R5C7B.D1 to R5C7B.F1 SLICE_100 +ROUTE 1 0.436 R5C7B.F1 to R5C7D.C1 n2277 +CTOF_DEL --- 0.495 R5C7D.C1 to R5C7D.F1 SLICE_74 +ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 +CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 +ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.711 (43.6% logic, 56.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C8C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.941ns (weighted slack = -3.882ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i1 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 6.681ns (43.8% logic, 56.2% route), 6 logic levels. + + Constraint Details: + + 6.681ns physical path delay SLICE_93 to SLICE_19 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.307ns CE_SET requirement (totaling 4.740ns) by 1.941ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R5C8C.CLK to R5C8C.Q1 SLICE_93 (from PHI2_c) +ROUTE 1 0.626 R5C8C.Q1 to R5C8D.D1 Bank_1 +CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 SLICE_99 +ROUTE 2 0.635 R5C8D.F1 to R5C8B.D1 n22 +CTOF_DEL --- 0.495 R5C8B.D1 to R5C8B.F1 SLICE_79 +ROUTE 7 0.461 R5C8B.F1 to R5C8A.C1 n2369 +CTOF_DEL --- 0.495 R5C8A.C1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 0.635 R5C9A.F0 to R5C9A.D1 C1Submitted_N_237 +CTOF_DEL --- 0.495 R5C9A.D1 to R5C9A.F1 SLICE_88 +ROUTE 1 0.653 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 6.681 (43.8% logic, 56.2% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C8C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R5C9D.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.784ns (weighted slack = -3.568ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 6.546ns (37.2% logic, 62.8% route), 5 logic levels. + + Constraint Details: + + 6.546ns physical path delay SLICE_101 to SLICE_10 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.784ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q0 SLICE_101 (from PHI2_c) +ROUTE 1 0.623 R4C7C.Q0 to R5C7A.D0 Bank_6 +CTOF_DEL --- 0.495 R5C7A.D0 to R5C7A.F0 SLICE_68 +ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 +CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 +ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 +CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 1.428 R5C9A.F0 to R3C8A.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 6.546 (37.2% logic, 62.8% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R4C7C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R3C8A.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 1.784ns (weighted slack = -3.568ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 6.546ns (37.2% logic, 62.8% route), 5 logic levels. + + Constraint Details: + + 6.546ns physical path delay SLICE_101 to SLICE_15 exceeds + 5.047ns delay constraint less + 0.000ns skew and + 0.285ns LSR_SET requirement (totaling 4.762ns) by 1.784ns + + Physical Path Details: + + Data path SLICE_101 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C7C.CLK to R4C7C.Q0 SLICE_101 (from PHI2_c) +ROUTE 1 0.623 R4C7C.Q0 to R5C7A.D0 Bank_6 +CTOF_DEL --- 0.495 R5C7A.D0 to R5C7A.F0 SLICE_68 +ROUTE 1 0.626 R5C7A.F0 to R5C7D.D1 n2287 +CTOF_DEL --- 0.495 R5C7D.D1 to R5C7D.F1 SLICE_74 +ROUTE 8 0.693 R5C7D.F1 to R5C8A.D1 n26 +CTOF_DEL --- 0.495 R5C8A.D1 to R5C8A.F1 SLICE_91 +ROUTE 1 0.744 R5C8A.F1 to R5C9A.C0 n2362 +CTOF_DEL --- 0.495 R5C9A.C0 to R5C9A.F0 SLICE_88 +ROUTE 3 1.428 R5C9A.F0 to R3C8B.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 6.546 (37.2% logic, 62.8% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_101: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R4C7C.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.539 8.PADDI to R3C8B.CLK PHI2_c + -------- + 3.539 (0.0% logic, 100.0% route), 0 logic levels. + +Warning: 65.729MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 299.401 MHz| 160.205 MHz| 5 * + | | | +FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 99.079 MHz| 65.729 MHz| 6 * + | | | +---------------------------------------------------------------------------- + + +2 preferences(marked by "*" above) not met. + +---------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +---------------------------------------------------------------------------- +n26 | 8| 63| 18.05% + | | | +n1996 | 1| 49| 14.04% + | | | +n1997 | 1| 46| 13.18% + | | | +n1995 | 1| 45| 12.89% + | | | +n1998 | 1| 38| 10.89% + | | | +n1994 | 1| 37| 10.60% + | | | +---------------------------------------------------------------------------- + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 349 Score: 452301 +Cumulative negative slack: 370485 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:36 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Design file: ram2gs_lcmxo2_640hc_impl1.ncd +Preference file: ram2gs_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + 459 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i4 (from RCLK_c +) + Destination: FF Data in IS_FSM__i5 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_106 to SLICE_106 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_106 to SLICE_106: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C8D.CLK to R3C8D.Q0 SLICE_106 (from RCLK_c) +ROUTE 1 0.152 R3C8D.Q0 to R3C8D.M1 n736 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_106: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R3C8D.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_106: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R3C8D.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CASr_382 (from RCLK_c +) + Destination: FF Data in CASr2_383 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_16 to SLICE_16 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_16 to SLICE_16: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C9B.CLK to R4C9B.Q0 SLICE_16 (from RCLK_c) +ROUTE 1 0.152 R4C9B.Q0 to R4C9B.M1 CASr (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_16: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R4C9B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_16: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R4C9B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i8 (from RCLK_c +) + Destination: FF Data in IS_FSM__i9 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_75 to SLICE_75 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_75 to SLICE_75: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C9D.CLK to R3C9D.Q0 SLICE_75 (from RCLK_c) +ROUTE 1 0.152 R3C9D.Q0 to R3C9D.M1 n732 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R3C9D.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R3C9D.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i10 (from RCLK_c +) + Destination: FF Data in IS_FSM__i11 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_79 to SLICE_79 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_79 to SLICE_79: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C8B.CLK to R5C8B.Q0 SLICE_79 (from RCLK_c) +ROUTE 1 0.152 R5C8B.Q0 to R5C8B.M1 n730 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_79: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R5C8B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_79: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R5C8B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i14 (from RCLK_c +) + Destination: FF Data in IS_FSM__i15 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_81 to SLICE_81 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_81 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C9C.CLK to R6C9C.Q0 SLICE_81 (from RCLK_c) +ROUTE 1 0.152 R6C9C.Q0 to R6C9C.M1 n726 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R6C9C.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R6C9C.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i7 (from RCLK_c +) + Destination: FF Data in IS_FSM__i8 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_97 to SLICE_75 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_97 to SLICE_75: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q1 SLICE_97 (from RCLK_c) +ROUTE 1 0.152 R3C9A.Q1 to R3C9D.M0 n733 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_97: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R3C9A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_75: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R3C9D.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.304ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i6 (from RCLK_c +) + Destination: FF Data in IS_FSM__i7 (to RCLK_c +) + + Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. + + Constraint Details: + + 0.285ns physical path delay SLICE_97 to SLICE_97 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.304ns + + Physical Path Details: + + Data path SLICE_97 to SLICE_97: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C9A.CLK to R3C9A.Q0 SLICE_97 (from RCLK_c) +ROUTE 1 0.152 R3C9A.Q0 to R3C9A.M1 n734 (to RCLK_c) + -------- + 0.285 (46.7% logic, 53.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_97: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R3C9A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_97: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R3C9A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.306ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr_379 (from RCLK_c +) + Destination: FF Data in RASr2_380 (to RCLK_c +) + + Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. + + Constraint Details: + + 0.287ns physical path delay SLICE_30 to SLICE_30 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.306ns + + Physical Path Details: + + Data path SLICE_30 to SLICE_30: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C10B.CLK to R5C10B.Q0 SLICE_30 (from RCLK_c) +ROUTE 2 0.154 R5C10B.Q0 to R5C10B.M1 RASr (to RCLK_c) + -------- + 0.287 (46.3% logic, 53.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_30: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R5C10B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_30: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R5C10B.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.306ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q PHI2r2_377 (from RCLK_c +) + Destination: FF Data in PHI2r3_378 (to RCLK_c +) + + Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. + + Constraint Details: + + 0.287ns physical path delay SLICE_36 to SLICE_69 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.306ns + + Physical Path Details: + + Data path SLICE_36 to SLICE_69: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C10A.CLK to R4C10A.Q1 SLICE_36 (from RCLK_c) +ROUTE 3 0.154 R4C10A.Q1 to R4C10C.M1 PHI2r2 (to RCLK_c) + -------- + 0.287 (46.3% logic, 53.7% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_36: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R4C10A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_69: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R4C10C.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.307ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i0 (from RCLK_c +) + Destination: FF Data in IS_FSM__i1 (to RCLK_c +) + + Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels. + + Constraint Details: + + 0.288ns physical path delay SLICE_98 to SLICE_98 meets + -0.019ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.307ns + + Physical Path Details: + + Data path SLICE_98 to SLICE_98: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C11A.CLK to R6C11A.Q0 SLICE_98 (from RCLK_c) +ROUTE 4 0.155 R6C11A.Q0 to R6C11A.M1 nRCS_N_139 (to RCLK_c) + -------- + 0.288 (46.2% logic, 53.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_98: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R6C11A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_98: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.059 62.PADDI to R6C11A.CLK RCLK_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + 113 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_15 to SLICE_15 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_15 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C8B.CLK to R3C8B.Q0 SLICE_15 (from PHI2_c) +ROUTE 2 0.132 R3C8B.Q0 to R3C8B.A0 C1Submitted +CTOF_DEL --- 0.101 R3C8B.A0 to R3C8B.F0 SLICE_15 +ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 n1398 (to PHI2_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.851ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in XOR8MEG_408 (to PHI2_c -) + + Delay: 0.823ns (28.4% logic, 71.6% route), 2 logic levels. + + Constraint Details: + + 0.823ns physical path delay SLICE_19 to SLICE_50 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.851ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_50: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.332 R5C9D.Q0 to R5C6B.D1 CmdEnable +CTOF_DEL --- 0.101 R5C6B.D1 to R5C6B.F1 SLICE_83 +ROUTE 1 0.257 R5C6B.F1 to R4C6A.CE PHI2_N_120_enable_3 (to PHI2_c) + -------- + 0.823 (28.4% logic, 71.6% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_50: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R4C6A.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.906ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_407 (from PHI2_c -) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 0.878ns (26.7% logic, 73.3% route), 2 logic levels. + + Constraint Details: + + 0.878ns physical path delay SLICE_10 to SLICE_19 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.906ns + + Physical Path Details: + + Data path SLICE_10 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C8A.CLK to R3C8A.Q0 SLICE_10 (from PHI2_c) +ROUTE 1 0.501 R3C8A.Q0 to R5C9A.B1 ADSubmitted +CTOF_DEL --- 0.101 R5C9A.B1 to R5C9A.F1 SLICE_88 +ROUTE 1 0.143 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 0.878 (26.7% logic, 73.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_10: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R3C8A.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.937ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 0.909ns (48.0% logic, 52.0% route), 4 logic levels. + + Constraint Details: + + 0.909ns physical path delay SLICE_15 to SLICE_19 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 0.937ns + + Physical Path Details: + + Data path SLICE_15 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R3C8B.CLK to R3C8B.Q0 SLICE_15 (from PHI2_c) +ROUTE 2 0.136 R3C8B.Q0 to R3C9B.D1 C1Submitted +CTOF_DEL --- 0.101 R3C9B.D1 to R3C9B.F1 SLICE_77 +ROUTE 1 0.056 R3C9B.F1 to R3C9A.C1 n2210 +CTOF_DEL --- 0.101 R3C9A.C1 to R3C9A.F1 SLICE_97 +ROUTE 1 0.138 R3C9A.F1 to R5C9A.C1 n7_adj_5 +CTOF_DEL --- 0.101 R5C9A.C1 to R5C9A.F1 SLICE_88 +ROUTE 1 0.143 R5C9A.F1 to R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 0.909 (48.0% logic, 52.0% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.059ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) + FF CmdUFMCLK_413 + + Delay: 1.031ns (32.5% logic, 67.5% route), 3 logic levels. + + Constraint Details: + + 1.031ns physical path delay SLICE_19 to SLICE_100 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 1.059ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.224 R5C9D.Q0 to R5C6D.C0 CmdEnable +CTOF_DEL --- 0.101 R5C6D.C0 to R5C6D.F0 SLICE_73 +ROUTE 2 0.212 R5C6D.F0 to R5C6D.A1 n2204 +CTOF_DEL --- 0.101 R5C6D.A1 to R5C6D.F1 SLICE_73 +ROUTE 2 0.260 R5C6D.F1 to R5C7B.CE PHI2_N_120_enable_8 (to PHI2_c) + -------- + 1.031 (32.5% logic, 67.5% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C7B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.059ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) + + Delay: 1.031ns (32.5% logic, 67.5% route), 3 logic levels. + + Constraint Details: + + 1.031ns physical path delay SLICE_19 to SLICE_99 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 1.059ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.224 R5C9D.Q0 to R5C6D.C0 CmdEnable +CTOF_DEL --- 0.101 R5C6D.C0 to R5C6D.F0 SLICE_73 +ROUTE 2 0.212 R5C6D.F0 to R5C6D.A1 n2204 +CTOF_DEL --- 0.101 R5C6D.A1 to R5C6D.F1 SLICE_73 +ROUTE 2 0.260 R5C6D.F1 to R5C8D.CE PHI2_N_120_enable_8 (to PHI2_c) + -------- + 1.031 (32.5% logic, 67.5% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C8D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.106ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdSubmitted_411 (to PHI2_c -) + + Delay: 1.078ns (40.4% logic, 59.6% route), 4 logic levels. + + Constraint Details: + + 1.078ns physical path delay SLICE_19 to SLICE_20 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 1.106ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.224 R5C9D.Q0 to R5C6D.C0 CmdEnable +CTOF_DEL --- 0.101 R5C6D.C0 to R5C6D.F0 SLICE_73 +ROUTE 2 0.137 R5C6D.F0 to R5C7D.D0 n2204 +CTOF_DEL --- 0.101 R5C7D.D0 to R5C7D.F0 SLICE_74 +ROUTE 2 0.138 R5C7D.F0 to R3C7C.D1 n2220 +CTOF_DEL --- 0.101 R3C7C.D1 to R3C7C.F1 SLICE_89 +ROUTE 1 0.143 R3C7C.F1 to R3C7D.CE PHI2_N_120_enable_7 (to PHI2_c) + -------- + 1.078 (40.4% logic, 59.6% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_20: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R3C7D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.106ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in Cmdn8MEGEN_410 (to PHI2_c -) + + Delay: 1.078ns (40.4% logic, 59.6% route), 4 logic levels. + + Constraint Details: + + 1.078ns physical path delay SLICE_19 to SLICE_24 meets + -0.028ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.028ns) by 1.106ns + + Physical Path Details: + + Data path SLICE_19 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q0 SLICE_19 (from PHI2_c) +ROUTE 2 0.224 R5C9D.Q0 to R5C6D.C0 CmdEnable +CTOF_DEL --- 0.101 R5C6D.C0 to R5C6D.F0 SLICE_73 +ROUTE 2 0.137 R5C6D.F0 to R5C7D.D0 n2204 +CTOF_DEL --- 0.101 R5C7D.D0 to R5C7D.F0 SLICE_74 +ROUTE 2 0.138 R5C7D.F0 to R3C7C.D0 n2220 +CTOF_DEL --- 0.101 R3C7C.D0 to R3C7C.F0 SLICE_89 +ROUTE 1 0.143 R3C7C.F0 to R3C7B.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 1.078 (40.4% logic, 59.6% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C9D.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_24: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R3C7B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 5.504ns (weighted slack = 11.008ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q XOR8MEG_408 (from PHI2_c -) + Destination: FF Data in RA11_385 (to PHI2_c +) + + Delay: 0.444ns (52.7% logic, 47.3% route), 2 logic levels. + + Constraint Details: + + 0.444ns physical path delay SLICE_50 to SLICE_33 meets + -0.013ns DIN_HLD and + -5.047ns delay constraint less + 0.000ns skew requirement (totaling -5.060ns) by 5.504ns + + Physical Path Details: + + Data path SLICE_50 to SLICE_33: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C6A.CLK to R4C6A.Q0 SLICE_50 (from PHI2_c) +ROUTE 1 0.210 R4C6A.Q0 to R4C6C.A0 XOR8MEG +CTOF_DEL --- 0.101 R4C6C.A0 to R4C6C.F0 SLICE_33 +ROUTE 1 0.000 R4C6C.F0 to R4C6C.DI0 RA11_N_184 (to PHI2_c) + -------- + 0.444 (52.7% logic, 47.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_50: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R4C6A.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_33: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R4C6C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 5.899ns (weighted slack = 11.798ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i1 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.839ns (52.0% logic, 48.0% route), 4 logic levels. + + Constraint Details: + + 0.839ns physical path delay SLICE_93 to SLICE_15 meets + -0.013ns DIN_HLD and + -5.047ns delay constraint less + 0.000ns skew requirement (totaling -5.060ns) by 5.899ns + + Physical Path Details: + + Data path SLICE_93 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C8C.CLK to R5C8C.Q1 SLICE_93 (from PHI2_c) +ROUTE 1 0.133 R5C8C.Q1 to R5C8D.D1 Bank_1 +CTOF_DEL --- 0.101 R5C8D.D1 to R5C8D.F1 SLICE_99 +ROUTE 2 0.214 R5C8D.F1 to R3C8B.A1 n22 +CTOF_DEL --- 0.101 R3C8B.A1 to R3C8B.F1 SLICE_15 +ROUTE 1 0.056 R3C8B.F1 to R3C8B.C0 n2365 +CTOF_DEL --- 0.101 R3C8B.C0 to R3C8B.F0 SLICE_15 +ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 n1398 (to PHI2_c) + -------- + 0.839 (52.0% logic, 48.0% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R5C8C.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 1.240 8.PADDI to R3C8B.CLK PHI2_c + -------- + 1.240 (0.0% logic, 100.0% route), 0 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 299.401000 MHz ; | 0.000 ns| 0.304 ns| 1 + | | | +FREQUENCY NET "PHI2_c" 99.079000 MHz ; | 0.000 ns| 0.379 ns| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 6 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 349 (setup), 0 (hold) +Score: 452301 (setup), 0 (hold) +Cumulative negative slack: 370485 (370485+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html new file mode 100644 index 0000000..7144090 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_bgn.html @@ -0,0 +1,152 @@ + +Bitgen Report + + +
    BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:00:22 2023
+
+
+Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
+ 
+===========
+UFM Summary.
+===========
+UFM Size:        191 Pages (128*191 Bits).
+UFM Utilization: General Purpose Flash Memory.
+ 
+Available General Purpose Flash Memory:  191 Pages (Page 0 to Page 190).
+Initialized UFM Pages:                     0 Page.
+ 
+Total CPU Time: 1 secs 
+Total REAL Time: 2 secs 
+Peak Memory Usage: 245 MB
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html new file mode 100644 index 0000000..85916f1 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html @@ -0,0 +1,204 @@ + +I/O Timing Report + + +
    I/O Timing Report
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 6
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
+// Version: Diamond (64-bit) 3.12.1.454
+// Written on Tue Aug 15 05:03:37 2023
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 6, 5, 4):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F     0.993      4       0.541     4
+CROW[1] nCRAS F     0.293      4       1.148     4
+Din[0]  PHI2  F     4.804      4       1.483     4
+Din[0]  nCCAS F     1.539      4      -0.150     M
+Din[1]  PHI2  F     4.733      4       0.702     4
+Din[1]  nCCAS F     1.638      4      -0.177     M
+Din[2]  PHI2  F     4.046      4       1.702     4
+Din[2]  nCCAS F     1.651      4      -0.121     M
+Din[3]  PHI2  F     4.770      4       1.575     4
+Din[3]  nCCAS F     1.973      4      -0.207     M
+Din[4]  PHI2  F     5.656      4       0.720     4
+Din[4]  nCCAS F     1.606      4      -0.156     M
+Din[5]  PHI2  F     4.165      4       1.131     4
+Din[5]  nCCAS F     0.618      4       0.435     4
+Din[6]  PHI2  F     5.309      4       1.478     4
+Din[6]  nCCAS F     1.331      4      -0.053     M
+Din[7]  PHI2  F     5.874      4       1.774     4
+Din[7]  nCCAS F     2.023      4      -0.205     M
+MAin[0] PHI2  F     5.149      4       0.137     M
+MAin[0] nCRAS F    -0.022      M       1.415     4
+MAin[1] PHI2  F     4.216      4       1.539     4
+MAin[1] nCRAS F     1.716      4      -0.018     M
+MAin[2] PHI2  F     3.754      4       0.553     4
+MAin[2] nCRAS F    -0.164      M       1.715     4
+MAin[3] PHI2  F     5.957      4      -0.100     M
+MAin[3] nCRAS F     0.033      4       1.356     4
+MAin[4] PHI2  F     5.652      4      -0.180     M
+MAin[4] nCRAS F    -0.173      M       1.726     4
+MAin[5] PHI2  F     4.938      4       0.693     6
+MAin[5] nCRAS F     0.005      4       1.395     4
+MAin[6] PHI2  F     5.535      4      -0.147     M
+MAin[6] nCRAS F     0.012      4       1.387     4
+MAin[7] PHI2  F     5.951      4      -0.083     M
+MAin[7] nCRAS F     0.858      4       0.664     4
+MAin[8] nCRAS F     0.526      4       0.915     4
+MAin[9] nCRAS F     0.038      4       1.342     4
+PHI2    RCLK  R     2.772      4      -0.342     M
+UFMSDO  RCLK  R     0.780      4       0.632     4
+nCCAS   RCLK  R     0.557      4       0.872     4
+nCCAS   nCRAS F     2.108      4      -0.053     M
+nCRAS   RCLK  R     2.536      4      -0.169     M
+nFWE    PHI2  F     5.830      4       0.629     4
+nFWE    nCRAS F     1.386      4       0.176     4
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R    11.611         4        3.288          M
+LED    nCRAS F    12.009         4        3.367          M
+RA[0]  RCLK  R    12.268         4        3.492          M
+RA[0]  nCRAS F    11.741         4        3.284          M
+RA[10] RCLK  R    10.004         4        2.964          M
+RA[11] PHI2  R    10.669         4        3.160          M
+RA[1]  RCLK  R    12.975         4        3.665          M
+RA[1]  nCRAS F    11.918         4        3.321          M
+RA[2]  RCLK  R    12.531         4        3.533          M
+RA[2]  nCRAS F    11.755         4        3.277          M
+RA[3]  RCLK  R    11.851         4        3.375          M
+RA[3]  nCRAS F    12.624         4        3.513          M
+RA[4]  RCLK  R    13.380         4        3.775          M
+RA[4]  nCRAS F    12.857         4        3.569          M
+RA[5]  RCLK  R    12.767         4        3.632          M
+RA[5]  nCRAS F    12.469         4        3.456          M
+RA[6]  RCLK  R    12.163         4        3.468          M
+RA[6]  nCRAS F    12.141         4        3.394          M
+RA[7]  RCLK  R    11.990         4        3.375          M
+RA[7]  nCRAS F    12.172         4        3.381          M
+RA[8]  RCLK  R    11.712         4        3.314          M
+RA[8]  nCRAS F    12.431         4        3.457          M
+RA[9]  RCLK  R    11.412         4        3.233          M
+RA[9]  nCRAS F    12.128         4        3.377          M
+RBA[0] nCRAS F    10.844         4        3.124          M
+RBA[1] nCRAS F    10.216         4        2.967          M
+RCKE   RCLK  R    10.964         4        3.209          M
+RDQMH  RCLK  R    12.109         4        3.426          M
+RDQML  RCLK  R    10.974         4        3.140          M
+RD[0]  nCCAS F     8.747         4        2.603          M
+RD[1]  nCCAS F     8.747         4        2.603          M
+RD[2]  nCCAS F     8.737         4        2.605          M
+RD[3]  nCCAS F     9.239         4        2.740          M
+RD[4]  nCCAS F     9.283         4        2.726          M
+RD[5]  nCCAS F     9.355         4        2.761          M
+RD[6]  nCCAS F     9.106         4        2.681          M
+RD[7]  nCCAS F     9.181         4        2.711          M
+UFMCLK RCLK  R    10.078         4        3.002          M
+UFMSDI RCLK  R    10.108         4        2.996          M
+nRCAS  RCLK  R    10.525         4        3.100          M
+nRCS   RCLK  R    10.119         4        2.984          M
+nRRAS  RCLK  R    10.200         4        3.024          M
+nRWE   RCLK  R     9.984         4        2.972          M
+nUFMCS RCLK  R    10.165         4        3.020          M
+WARNING: you must also run trce with hold speed: 4
+WARNING: you must also run trce with hold speed: 6
+WARNING: you must also run trce with setup speed: M
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj new file mode 100644 index 0000000..c4e5990 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj @@ -0,0 +1,41 @@ +-a "MachXO2" +-d LCMXO2-640HC +-t TQFP100 +-s 4 +-frequency 200 +-optimization_goal Balanced +-bram_utilization 100 +-ramstyle Auto +-romstyle auto +-dsp_utilization 100 +-use_dsp 1 +-use_carry_chain 1 +-carry_chain_length 0 +-force_gsr Auto +-resource_sharing 1 +-propagate_constants 1 +-remove_duplicate_regs 1 +-mux_style Auto +-max_fanout 1000 +-fsm_encoding_style Auto +-twr_paths 3 +-fix_gated_clocks 1 +-loop_limit 1950 + + + +-use_io_insertion 1 +-resolve_mixed_drivers 0 +-use_io_reg auto + + +-lpf 1 +-p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC" +-ver "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v" +-top RAM2GS + + +-p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC" + +-ngd "RAM2GS_LCMXO2_640HC_impl1.ngd" + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd new file mode 100644 index 0000000..bcf1f47 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.asd @@ -0,0 +1,15 @@ +[ActiveSupport MAP] +Device = LCMXO2-640HC; +Package = TQFP100; +Performance = 4; +LUTS_avail = 640; +LUTS_used = 143; +FF_avail = 719; +FF_used = 102; +INPUT_LVCMOS25 = 26; +OUTPUT_LVCMOS25 = 33; +BIDI_LVCMOS25 = 8; +IO_avail = 79; +IO_used = 67; +EBR_avail = 2; +EBR_used = 0; diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam new file mode 100644 index 0000000..5798330 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam @@ -0,0 +1,88 @@ +[ START MERGED ] +n2380 Ready +PHI2_N_120 PHI2_c +nRWE_N_176 nRWE_N_177 +n1407 nRowColSel_N_34 +n1408 nRowColSel_N_35 +[ END MERGED ] +[ START CLIPPED ] +GND_net +VCC_net +FS_610_add_4_19/S1 +FS_610_add_4_19/CO +FS_610_add_4_1/S0 +FS_610_add_4_1/CI +[ END CLIPPED ] +[ START DESIGN PREFS ] +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:24 2023 + +SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "RD[7]" SITE "43" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "Dout[7]" SITE "82" ; +LOCATE COMP "Dout[6]" SITE "78" ; +LOCATE COMP "Dout[5]" SITE "84" ; +LOCATE COMP "Dout[4]" SITE "83" ; +LOCATE COMP "Dout[3]" SITE "85" ; +LOCATE COMP "Dout[2]" SITE "87" ; +LOCATE COMP "Dout[1]" SITE "86" ; +LOCATE COMP "Dout[0]" SITE "76" ; +LOCATE COMP "LED" SITE "34" ; +LOCATE COMP "RBA[1]" SITE "60" ; +LOCATE COMP "RBA[0]" SITE "58" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[9]" SITE "63" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[7]" SITE "75" ; +LOCATE COMP "RA[6]" SITE "68" ; +LOCATE COMP "RA[5]" SITE "70" ; +LOCATE COMP "RA[4]" SITE "74" ; +LOCATE COMP "RA[3]" SITE "71" ; +LOCATE COMP "RA[2]" SITE "69" ; +LOCATE COMP "RA[1]" SITE "67" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "nRCS" SITE "57" ; +LOCATE COMP "RCKE" SITE "53" ; +LOCATE COMP "nRWE" SITE "49" ; +LOCATE COMP "nRRAS" SITE "54" ; +LOCATE COMP "nRCAS" SITE "52" ; +LOCATE COMP "RDQMH" SITE "51" ; +LOCATE COMP "RDQML" SITE "48" ; +LOCATE COMP "UFMCLK" SITE "29" ; +LOCATE COMP "UFMSDI" SITE "30" ; +LOCATE COMP "PHI2" SITE "8" ; +LOCATE COMP "MAin[9]" SITE "32" ; +LOCATE COMP "MAin[8]" SITE "25" ; +LOCATE COMP "MAin[7]" SITE "18" ; +LOCATE COMP "MAin[6]" SITE "24" ; +LOCATE COMP "MAin[5]" SITE "19" ; +LOCATE COMP "MAin[4]" SITE "20" ; +LOCATE COMP "MAin[3]" SITE "21" ; +LOCATE COMP "MAin[2]" SITE "13" ; +LOCATE COMP "MAin[1]" SITE "12" ; +LOCATE COMP "MAin[0]" SITE "14" ; +LOCATE COMP "CROW[1]" SITE "16" ; +LOCATE COMP "CROW[0]" SITE "10" ; +LOCATE COMP "Din[7]" SITE "1" ; +LOCATE COMP "Din[6]" SITE "2" ; +LOCATE COMP "Din[5]" SITE "98" ; +LOCATE COMP "Din[4]" SITE "99" ; +LOCATE COMP "Din[3]" SITE "97" ; +LOCATE COMP "Din[2]" SITE "88" ; +LOCATE COMP "Din[1]" SITE "96" ; +LOCATE COMP "Din[0]" SITE "3" ; +LOCATE COMP "nCCAS" SITE "9" ; +LOCATE COMP "nCRAS" SITE "17" ; +LOCATE COMP "nFWE" SITE "28" ; +LOCATE COMP "RCLK" SITE "62" ; +LOCATE COMP "UFMSDO" SITE "27" ; +SCHEMATIC END ; +[ END DESIGN PREFS ] diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr new file mode 100644 index 0000000..a9cd083 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.hrr @@ -0,0 +1,10 @@ +--------------------------------------------------- +Report for cell RAM2GS + Instance path: RAM2GS + Cell usage: + cell count Res Usage(%) + SLIC 75.00 100.0 + LUT4 123.00 100.0 + IOBUF 67 100.0 + PFUREG 102 100.0 + RIPPLE 10 100.0 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd new file mode 100644 index 0000000..3b0a349 Binary files /dev/null and b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd differ diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvho.sdf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvho.sdf new file mode 100644 index 0000000..2bb7626 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvho.sdf @@ -0,0 +1,3176 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Tue Aug 15 05:03:27 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7I) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9I) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_10") + (INSTANCE SLICE_10I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_15") + (INSTANCE SLICE_15I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_16") + (INSTANCE SLICE_16I) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_20") + (INSTANCE SLICE_20I) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_24") + (INSTANCE SLICE_24I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_25") + (INSTANCE SLICE_25I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_26") + (INSTANCE SLICE_26I) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_27") + (INSTANCE SLICE_27I) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_30") + (INSTANCE SLICE_30I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_33") + (INSTANCE SLICE_33I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_35") + (INSTANCE SLICE_35I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_36") + (INSTANCE SLICE_36I) + (DELAY + (ABSOLUTE + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_37") + (INSTANCE SLICE_37I) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_45") + (INSTANCE SLICE_45I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_50") + (INSTANCE SLICE_50I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_57") + (INSTANCE SLICE_57I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_59") + (INSTANCE SLICE_59I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_61") + (INSTANCE SLICE_61I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_62") + (INSTANCE SLICE_62I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_64") + (INSTANCE SLICE_64I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_65") + (INSTANCE SLICE_65I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_66") + (INSTANCE SLICE_66I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_67") + (INSTANCE SLICE_67I) + (DELAY + (ABSOLUTE + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_68") + (INSTANCE SLICE_68I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_69") + (INSTANCE SLICE_69I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_70") + (INSTANCE SLICE_70I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "i30_SLICE_71") + (INSTANCE i30_SLICE_71I) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (457:589:721)(457:589:721)) + (IOPATH B1 OFX0 (457:589:721)(457:589:721)) + (IOPATH A1 OFX0 (457:589:721)(457:589:721)) + (IOPATH D0 OFX0 (457:589:721)(457:589:721)) + (IOPATH C0 OFX0 (457:589:721)(457:589:721)) + (IOPATH B0 OFX0 (457:589:721)(457:589:721)) + (IOPATH A0 OFX0 (457:589:721)(457:589:721)) + (IOPATH M0 OFX0 (322:349:376)(322:349:376)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_72") + (INSTANCE SLICE_72I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_73") + (INSTANCE SLICE_73I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_74") + (INSTANCE SLICE_74I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_75") + (INSTANCE SLICE_75I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_76") + (INSTANCE SLICE_76I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_80") + (INSTANCE SLICE_80I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_81") + (INSTANCE SLICE_81I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_84") + (INSTANCE SLICE_84I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_85") + (INSTANCE SLICE_85I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_102") + (INSTANCE SLICE_102I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_103") + (INSTANCE SLICE_103I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_104") + (INSTANCE SLICE_104I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_105") + (INSTANCE SLICE_105I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_106") + (INSTANCE SLICE_106I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_7_B") + (INSTANCE RD_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD7 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD7 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD7) (3330:3330:3330)) + (WIDTH (negedge RD7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_6_B") + (INSTANCE RD_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD6 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD6 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD6) (3330:3330:3330)) + (WIDTH (negedge RD6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_5_B") + (INSTANCE RD_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD5 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD5 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD5) (3330:3330:3330)) + (WIDTH (negedge RD5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_4_B") + (INSTANCE RD_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD4 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD4 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD4) (3330:3330:3330)) + (WIDTH (negedge RD4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_3_B") + (INSTANCE RD_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD3 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD3 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD3) (3330:3330:3330)) + (WIDTH (negedge RD3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_2_B") + (INSTANCE RD_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD2 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD2 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD2) (3330:3330:3330)) + (WIDTH (negedge RD2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_1_B") + (INSTANCE RD_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD1 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD1 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD1) (3330:3330:3330)) + (WIDTH (negedge RD1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_0_B") + (INSTANCE RD_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD0 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD0 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD0) (3330:3330:3330)) + (WIDTH (negedge RD0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Dout_7_B") + (INSTANCE Dout_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout7 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_6_B") + (INSTANCE Dout_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout6 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_5_B") + (INSTANCE Dout_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout5 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_4_B") + (INSTANCE Dout_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout4 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_3_B") + (INSTANCE Dout_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout3 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_2_B") + (INSTANCE Dout_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout2 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1_B") + (INSTANCE Dout_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0_B") + (INSTANCE Dout_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "LEDB") + (INSTANCE LEDI) + (DELAY + (ABSOLUTE + (IOPATH PADDO LEDS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_B") + (INSTANCE RBA_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_0_B") + (INSTANCE RBA_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_11_B") + (INSTANCE RA_11_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA11 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_10_B") + (INSTANCE RA_10_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA10 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_9_B") + (INSTANCE RA_9_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA9 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_8_B") + (INSTANCE RA_8_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA8 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_7_B") + (INSTANCE RA_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA7 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_6_B") + (INSTANCE RA_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA6 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_5_B") + (INSTANCE RA_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA5 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_4_B") + (INSTANCE RA_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA4 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_3_B") + (INSTANCE RA_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA3 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_2_B") + (INSTANCE RA_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA2 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_1_B") + (INSTANCE RA_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_0_B") + (INSTANCE RA_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRCSB") + (INSTANCE nRCSI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCSS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RCKEB") + (INSTANCE RCKEI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RCKES (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRWEB") + (INSTANCE nRWEI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRWES (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRRASB") + (INSTANCE nRRASI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRRASS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRCASB") + (INSTANCE nRCASI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCASS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMHB") + (INSTANCE RDQMHI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMHS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMLB") + (INSTANCE RDQMLI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMLS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nUFMCSB") + (INSTANCE nUFMCSI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nUFMCSS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "UFMCLKB") + (INSTANCE UFMCLKI) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMCLKS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "UFMSDIB") + (INSTANCE UFMSDII) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMSDIS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "PHI2B") + (INSTANCE PHI2I) + (DELAY + (ABSOLUTE + (IOPATH PHI2S PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI2S) (3330:3330:3330)) + (WIDTH (negedge PHI2S) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_9_B") + (INSTANCE MAin_9_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (3330:3330:3330)) + (WIDTH (negedge MAin9) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_8_B") + (INSTANCE MAin_8_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (3330:3330:3330)) + (WIDTH (negedge MAin8) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_7_B") + (INSTANCE MAin_7_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (3330:3330:3330)) + (WIDTH (negedge MAin7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_6_B") + (INSTANCE MAin_6_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (3330:3330:3330)) + (WIDTH (negedge MAin6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_5_B") + (INSTANCE MAin_5_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (3330:3330:3330)) + (WIDTH (negedge MAin5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_4_B") + (INSTANCE MAin_4_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (3330:3330:3330)) + (WIDTH (negedge MAin4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_3_B") + (INSTANCE MAin_3_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (3330:3330:3330)) + (WIDTH (negedge MAin3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_2_B") + (INSTANCE MAin_2_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (3330:3330:3330)) + (WIDTH (negedge MAin2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_1_B") + (INSTANCE MAin_1_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (3330:3330:3330)) + (WIDTH (negedge MAin1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_0_B") + (INSTANCE MAin_0_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (3330:3330:3330)) + (WIDTH (negedge MAin0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "CROW_1_B") + (INSTANCE CROW_1_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (3330:3330:3330)) + (WIDTH (negedge CROW1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "CROW_0_B") + (INSTANCE CROW_0_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (3330:3330:3330)) + (WIDTH (negedge CROW0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_7_B") + (INSTANCE Din_7_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (3330:3330:3330)) + (WIDTH (negedge Din7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_6_B") + (INSTANCE Din_6_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (3330:3330:3330)) + (WIDTH (negedge Din6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_5_B") + (INSTANCE Din_5_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (3330:3330:3330)) + (WIDTH (negedge Din5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_4_B") + (INSTANCE Din_4_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (3330:3330:3330)) + (WIDTH (negedge Din4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_3_B") + (INSTANCE Din_3_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (3330:3330:3330)) + (WIDTH (negedge Din3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_2_B") + (INSTANCE Din_2_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (3330:3330:3330)) + (WIDTH (negedge Din2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_1_B") + (INSTANCE Din_1_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (3330:3330:3330)) + (WIDTH (negedge Din1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_0_B") + (INSTANCE Din_0_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (3330:3330:3330)) + (WIDTH (negedge Din0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nCCASB") + (INSTANCE nCCASI) + (DELAY + (ABSOLUTE + (IOPATH nCCASS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCCASS) (3330:3330:3330)) + (WIDTH (negedge nCCASS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nCRASB") + (INSTANCE nCRASI) + (DELAY + (ABSOLUTE + (IOPATH nCRASS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCRASS) (3330:3330:3330)) + (WIDTH (negedge nCRASS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nFWEB") + (INSTANCE nFWEI) + (DELAY + (ABSOLUTE + (IOPATH nFWES PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nFWES) (3330:3330:3330)) + (WIDTH (negedge nFWES) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RCLKB") + (INSTANCE RCLKI) + (DELAY + (ABSOLUTE + (IOPATH RCLKS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RCLKS) (3330:3330:3330)) + (WIDTH (negedge RCLKS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "UFMSDOB") + (INSTANCE UFMSDOI) + (DELAY + (ABSOLUTE + (IOPATH UFMSDOS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge UFMSDOS) (3330:3330:3330)) + (WIDTH (negedge UFMSDOS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_76I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_80I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_82I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_85I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_0I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_85I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_105I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/F1 SLICE_0I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/F0 SLICE_0I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_9I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_16I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_26I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_27I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_30I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_32I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_35I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_36I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_37I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_44I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_45I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_57I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_59I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_61I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_62I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_64I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_65I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_66I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_67I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_68I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_69I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_70I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_75I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_78I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_79I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_81I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_84I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_86I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_97I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_98I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_106I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/FCO SLICE_0I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/FCO SLICE_9I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_1I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_76I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_80I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_85I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_105I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_57I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_70I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_76I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_80I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_82I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_85I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_105I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/F1 SLICE_1I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/F0 SLICE_1I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/FCO SLICE_1I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_45I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_68I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_95I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_95I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/F1 SLICE_2I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/F0 SLICE_2I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/FCO SLICE_2I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/FCO SLICE_6I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_86I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_105I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_95I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_95I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/F1 SLICE_3I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/F0 SLICE_3I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/FCO SLICE_3I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_95I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_44I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_95I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/F1 SLICE_4I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/F0 SLICE_4I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/FCO SLICE_4I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/FCO SLICE_8I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_68I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/F1 SLICE_5I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/Q1 SLICE_5I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/Q1 SLICE_66I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/Q1 SLICE_96I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_96I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_96I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_45I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_57I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_70I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_76I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_82I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_86I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_95I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/F1 SLICE_6I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/F0 SLICE_6I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_82I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_85I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/F0 SLICE_7I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/FCO SLICE_7I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_44I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_86I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_86I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/F1 SLICE_8I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/F0 SLICE_8I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q1 SLICE_9I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q1 SLICE_85I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q1 SLICE_105I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 SLICE_9I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 SLICE_85I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 SLICE_105I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/F1 SLICE_9I/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/F0 SLICE_9I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_10I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_24I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_33I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_50I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_89I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_89I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_89I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_90I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_102I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_106I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_10I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_24I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_33I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_33I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_75I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_77I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_88I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_101I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_10I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_50I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_90I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_90I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_90I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_93I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_100I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_10I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_24I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_33I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_88I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_90I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_90I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_101I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106I/F1 SLICE_10I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10I/F1 SLICE_10I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F0 SLICE_10I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_10I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_73I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10I/F0 SLICE_10I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F0 SLICE_10I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F0 SLICE_10I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F0 SLICE_15I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F0 SLICE_88I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_10I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_15I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_19I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_20I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_24I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_33I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_50I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_86I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_93I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_99I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_100I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_101I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_102I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_103I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10I/Q0 SLICE_88I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_15I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_73I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_74I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_79I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_83I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_91I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_91I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_104I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_15I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_79I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_82I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_101I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F1 SLICE_15I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F1 SLICE_79I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_15I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_79I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_91I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_103I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_15I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_19I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_73I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_74I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_79I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_83I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_91I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_91I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_97I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_102I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15I/Q0 SLICE_15I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15I/Q0 SLICE_77I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15I/F1 SLICE_15I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_15I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_25I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_25I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_74I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_79I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_104I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_104I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_106I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15I/F0 SLICE_15I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_16I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_88I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_89I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_90I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_92I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_104I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/F0 SLICE_16I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/F0 SLICE_25I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16I/Q0 SLICE_16I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/F0 SLICE_19I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_19I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_24I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_25I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_75I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_77I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_89I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_89I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_89I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_102I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F0 SLICE_19I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F0 SLICE_77I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F0 SLICE_19I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F0 SLICE_75I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F1 SLICE_19I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F1 SLICE_19I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F1 SLICE_77I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F0 SLICE_19I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F0 SLICE_88I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F0 SLICE_19I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F1 SLICE_19I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/Q0 SLICE_73I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/Q0 SLICE_83I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20I/F0 SLICE_20I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/F1 SLICE_20I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20I/Q0 SLICE_35I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20I/Q0 SLICE_84I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/F1 SLICE_24I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/F1 SLICE_50I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/F1 SLICE_83I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/Q0 SLICE_24I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/Q0 SLICE_33I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_24I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_50I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_90I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_90I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_90I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_93I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_99I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_106I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/F0 SLICE_24I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/F0 SLICE_24I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24I/Q0 SLICE_57I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_25I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_50I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_75I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_77I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_89I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_89I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_92I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_103I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F0 SLICE_25I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_25I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_30I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_30I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_74I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_76I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_82I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_87I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_91I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_104I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_65I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 i30_SLICE_71I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 i30_SLICE_71I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_81I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_96I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 SLICE_30I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 SLICE_59I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 i30_SLICE_71I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 i30_SLICE_71I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 SLICE_81I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 SLICE_96I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q1 SLICE_96I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/F0 SLICE_26I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F0 SLICE_26I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_32I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_35I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_35I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_44I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_45I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_57I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_62I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_70I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_70I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_72I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_76I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_80I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_84I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_92I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_92I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27I/F0 SLICE_27I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F0 SLICE_27I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27I/Q0 SLICE_30I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27I/Q0 SLICE_50I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/F0 SLICE_30I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q0 SLICE_30I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q0 SLICE_36I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/F1 LEDI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_32I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_36I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_59I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_61I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_62I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_66I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_67I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_69I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_69I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 i30_SLICE_71I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_72I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_78I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_86I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_92I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30I/Q1 SLICE_92I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_32I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_59I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_61I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_62I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_62I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_68I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 i30_SLICE_71I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_78I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_87I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_92I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_92I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_94I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_94I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_32I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_59I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_64I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_84I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_32I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_33I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_35I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_59I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_61I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_62I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_64I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_72I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_74I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_76I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_82I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_87I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_87I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_91I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_92I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_94I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_94I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/Q0 SLICE_104I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/F1 SLICE_32I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_32I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_62I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_92I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_98I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/F0 SLICE_32I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/Q1 SLICE_32I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/Q1 SLICE_64I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/Q1 SLICE_79I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/Q0 RA_10_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50I/Q0 SLICE_33I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33I/F0 SLICE_33I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33I/Q0 RA_11_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33I/F1 SLICE_73I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q1 SLICE_35I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q1 SLICE_69I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q1 SLICE_84I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q1 SLICE_35I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q1 SLICE_84I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT i30_SLICE_71I/OFX0 SLICE_35I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F0 SLICE_35I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F1 SLICE_35I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F1 SLICE_59I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F1 SLICE_61I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F1 SLICE_62I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q0 SLICE_36I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F1 SLICE_44I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F1 SLICE_45I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F1 SLICE_70I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/Q1 SLICE_36I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/F0 SLICE_36I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/Q0 SLICE_36I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_61I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_69I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_78I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 RCKEI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37I/F0 SLICE_37I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_72I/F1 SLICE_37I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F1 SLICE_44I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F1 SLICE_44I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F1 SLICE_70I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F1 SLICE_82I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/Q0 SLICE_44I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F1 SLICE_44I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F0 SLICE_44I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F0 SLICE_44I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F0 SLICE_45I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/Q0 UFMCLKI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_45I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_57I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_76I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_80I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_85I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/F1 SLICE_45I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 SLICE_45I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/Q0 SLICE_45I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45I/F1 SLICE_45I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45I/F0 SLICE_45I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45I/Q0 UFMSDII/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50I/F1 SLICE_50I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_50I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_77I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_88I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_92I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_97I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_100I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_103I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_106I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50I/F0 SLICE_50I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F1 SLICE_50I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_57I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_80I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_95I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDOI/PADDI SLICE_57I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/F1 SLICE_57I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/F1 SLICE_84I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57I/F0 SLICE_57I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/F0 SLICE_57I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F0 SLICE_59I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F0 SLICE_61I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59I/F1 SLICE_59I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F0 SLICE_59I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F0 SLICE_64I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59I/F0 SLICE_59I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59I/Q0 nRCASI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/F1 SLICE_61I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62I/F1 SLICE_61I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62I/F1 SLICE_62I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/F0 SLICE_61I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/Q0 nRCSI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F1 SLICE_62I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62I/F0 SLICE_62I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62I/Q0 nRRASI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F1 SLICE_64I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/F1 SLICE_64I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/F0 SLICE_64I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F0 SLICE_64I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F0 SLICE_65I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 nRWEI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_65I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_67I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 i30_SLICE_71I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_81I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_87I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_65I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_66I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_66I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_81I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_87I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F1 SLICE_65I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F1 SLICE_65I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F1 SLICE_78I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F1 SLICE_94I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F1 SLICE_65I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F0 SLICE_65I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_93I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_93I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_98I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_98I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_99I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_100I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_101I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_101I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_102I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_102I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_103I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_103I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_66I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_67I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_72I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_87I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_94I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F0 SLICE_66I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F1 i30_SLICE_71I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/F0 SLICE_67I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/F0 SLICE_68I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/Q1 SLICE_68I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/Q0 SLICE_68I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F0 SLICE_74I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F1 SLICE_86I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F0 SLICE_69I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F1 SLICE_70I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F1 SLICE_76I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/Q1 SLICE_70I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70I/F1 SLICE_70I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70I/F0 SLICE_70I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70I/Q0 nUFMCSI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_72I/F0 SLICE_72I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q1 SLICE_72I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q1 SLICE_98I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73I/F0 SLICE_73I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73I/F0 SLICE_74I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_73I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_74I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_79I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_83I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_91I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_91I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_104I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_73I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_74I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_77I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_83I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_88I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_91I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_97I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_97I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_101I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73I/F1 SLICE_99I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73I/F1 SLICE_100I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/Q1 SLICE_74I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F1 SLICE_74I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/Q0 SLICE_74I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F0 SLICE_89I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F0 SLICE_89I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_101I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q1 SLICE_102I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F0 SLICE_75I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106I/F0 SLICE_75I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106I/F0 SLICE_83I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/Q0 SLICE_75I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/Q1 SLICE_75I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_75I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_78I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_79I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_81I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_84I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_97I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_98I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 SLICE_106I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F1 SLICE_88I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_76I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_93I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_93I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_98I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_8_I/PADDI SLICE_76I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_8_I/PADDI SLICE_98I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q0 SLICE_98I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q1 SLICE_93I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F1 SLICE_97I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F0 SLICE_78I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F0 SLICE_78I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F0 SLICE_81I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/Q0 SLICE_78I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q1 SLICE_78I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/Q1 SLICE_81I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q0 SLICE_79I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F1 SLICE_81I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q0 SLICE_81I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F0 SLICE_82I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_82I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_100I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_102I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/Q0 SLICE_102I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/Q1 SLICE_101I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F0 SLICE_83I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F0 SLICE_84I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/F1 SLICE_84I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/Q0 SLICE_84I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/Q1 SLICE_106I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F1 SLICE_86I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/F0 SLICE_86I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F0 SLICE_87I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW_1_I/PADDI SLICE_87I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW_0_I/PADDI SLICE_87I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 RBA_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 RBA_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/F1 SLICE_88I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F1 SLICE_88I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/Q0 RD_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/Q1 RD_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/Q0 RD_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/Q1 RD_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/Q0 RD_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/Q1 RD_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_91I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_99I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_103I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q0 SLICE_103I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q1 SLICE_103I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/Q0 RD_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/Q1 RD_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/F0 RA_9_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/Q0 SLICE_100I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/F1 RDQMLI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/Q1 SLICE_99I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/Q0 SLICE_97I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106I/Q1 SLICE_97I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/F0 RA_8_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/F1 RDQMHI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/Q0 SLICE_99I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_99I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_99I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_104I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/Q1 SLICE_99I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F0 RA_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/Q1 SLICE_100I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_100I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_100I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_104I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/Q0 SLICE_100I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F0 RA_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/F0 RA_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/F1 RA_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/F0 RA_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/F1 RA_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/F0 RA_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/F1 RA_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_7_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_6_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_5_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_4_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_3_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_2_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_1_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 RD_0_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106I/Q0 SLICE_106I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT RD_7_I/PADDI Dout_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_6_I/PADDI Dout_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_5_I/PADDI Dout_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_4_I/PADDI Dout_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_3_I/PADDI Dout_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_2_I/PADDI Dout_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_1_I/PADDI Dout_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_0_I/PADDI Dout_0_I/PADDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvho.vho b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvho.vho new file mode 100644 index 0000000..f5718ec --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvho.vho @@ -0,0 +1,26387 @@ + +-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +-- ldbanno -n VHDL -o RAM2GS_LCMXO2_640HC_impl1_mapvho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd +-- Netlist created on Tue Aug 15 05:03:24 2023 +-- Netlist written on Tue Aug 15 05:03:27 2023 +-- Design is for device LCMXO2-640HC +-- Design is for package TQFP100 +-- Design is for performance grade 4 + +-- entity vmuxregsre + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE; + + end vmuxregsre; + + architecture Structure of vmuxregsre is + begin + INST01: FL1P3DX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity vcc + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vcc is + port (PWR1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE; + + end vcc; + + architecture Structure of vcc is + begin + INST1: VHI + port map (Z=>PWR1); + end Structure; + +-- entity gnd + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity gnd is + port (PWR0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE; + + end gnd; + + architecture Structure of gnd is + begin + INST1: VLO + port map (Z=>PWR0); + end Structure; + +-- entity ccu2B0 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu2B0 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu2B0 : ENTITY IS TRUE; + + end ccu2B0; + + architecture Structure of ccu2B0 is + begin + inst1: CCU2D + generic map (INIT0 => X"faaa", INIT1 => X"faaa", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_0 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_0 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_0"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE; + + end SLICE_0; + + architecture Structure of SLICE_0 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i14: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i13: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_15: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_1 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_1 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_1"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE; + + end SLICE_1; + + architecture Structure of SLICE_1 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i12: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i11: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_13: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_2 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_2 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_2"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE; + + end SLICE_2; + + architecture Structure of SLICE_2 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i8: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i7: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_9: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_3 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_3 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_3"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE; + + end SLICE_3; + + architecture Structure of SLICE_3 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i6: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i5: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_7: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_4 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_4 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_4"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE; + + end SLICE_4; + + architecture Structure of SLICE_4 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i2: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i1: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_3: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity ccu20001 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu20001 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE; + + end ccu20001; + + architecture Structure of ccu20001 is + begin + inst1: CCU2D + generic map (INIT0 => X"F000", INIT1 => X"0555", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_5 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_5 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_5"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; DI1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE; + + end SLICE_5; + + architecture Structure of SLICE_5 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20001 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i0: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CASr3_384: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_1: ccu20001 + port map (A0=>GNDI, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>open, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, DI1_dly, M0_dly, CLK_dly, Q0_out, F1_out, + Q1_out, FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_6 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_6 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_6"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE; + + end SLICE_6; + + architecture Structure of SLICE_6 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i10: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i9: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_11: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity ccu20002 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity ccu20002 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20002 : ENTITY IS TRUE; + + end ccu20002; + + architecture Structure of ccu20002 is + begin + inst1: CCU2D + generic map (INIT0 => X"faaa", INIT1 => X"0000", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT=>CO1); + end Structure; + +-- entity SLICE_7 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_7 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_7"; + + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE; + + end SLICE_7; + + architecture Structure of SLICE_7 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20002 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i17: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_add_4_19: ccu20002 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>GNDI, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>open, + CO1=>open); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A0_ipd, DI0_dly, CLK_dly, FCI_ipd, F0_out, Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_8 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_8 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_8"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE; + + end SLICE_8; + + architecture Structure of SLICE_8 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i4: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i3: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_5: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_9 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_9 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_9"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI1_CLK : VitalDelayType := 0 ns; + tsetup_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE; + + end SLICE_9; + + architecture Structure of SLICE_9 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI1_ipd : std_logic := 'X'; + signal DI1_dly : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B0 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO1: out Std_logic); + end component; + begin + FS_610_i16: vmuxregsre + port map (D0=>VCCI, D1=>DI1_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i15: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_17: ccu2B0 + port map (A0=>A0_ipd, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_ipd, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_ipd, S0=>F0_out, S1=>F1_out, + CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI1_ipd, DI1, tipd_DI1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI1_dly, DI1_ipd, tisd_DI1_CLK); + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_ipd, A0_ipd, DI1_dly, DI0_dly, CLK_dly, + FCI_ipd, F0_out, Q0_out, F1_out, Q1_out, FCO_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI1_CLK : x01 := '0'; + VARIABLE DI1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI1_dly, + TestSignalName => "DI1", + TestDelay => tisd_DI1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI1_CLK_noedge_posedge, + SetupLow => tsetup_DI1_CLK_noedge_posedge, + HoldHigh => thold_DI1_CLK_noedge_posedge, + HoldLow => thold_DI1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI1_CLK_TimingDatash, + Violation => tviol_DI1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_ipd'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut4 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut4 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE; + + end lut4; + + architecture Structure of lut4 is + begin + INST10: ROM16X1A + generic map (initval => X"0002") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40003 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40003 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40003 : ENTITY IS TRUE; + + end lut40003; + + architecture Structure of lut40003 is + begin + INST10: ROM16X1A + generic map (initval => X"2000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0004 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre0004 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0004 : ENTITY IS TRUE; + + end vmuxregsre0004; + + architecture Structure of vmuxregsre0004 is + begin + INST01: FL1P3IY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity inverter + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity inverter is + port (I: in Std_logic; Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE; + + end inverter; + + architecture Structure of inverter is + begin + INST1: INV + port map (A=>I, Z=>Z); + end Structure; + +-- entity SLICE_10 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_10 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_10"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_10 : ENTITY IS TRUE; + + end SLICE_10; + + architecture Structure of SLICE_10 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40003 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + begin + i3_3_lut_4_lut: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut_adj_4: lut40003 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + ADSubmitted_407: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40005 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40005 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE; + + end lut40005; + + architecture Structure of lut40005 is + begin + INST10: ROM16X1A + generic map (initval => X"FF7F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40006 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40006 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40006 : ENTITY IS TRUE; + + end lut40006; + + architecture Structure of lut40006 is + begin + INST10: ROM16X1A + generic map (initval => X"E0F0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0007 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre0007 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0007 : ENTITY IS TRUE; + + end vmuxregsre0007; + + architecture Structure of vmuxregsre0007 is + begin + INST01: FL1P3JY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); + end Structure; + +-- entity SLICE_15 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_15 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_15"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_15 : ENTITY IS TRUE; + + end SLICE_15; + + architecture Structure of SLICE_15 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40006 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0007 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + begin + i13_2_lut_rep_16_4_lut: lut40005 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1110_2_lut_3_lut_4_lut: lut40006 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + C1Submitted_406: vmuxregsre0007 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40008 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40008 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE; + + end lut40008; + + architecture Structure of lut40008 is + begin + INST10: ROM16X1A + generic map (initval => X"5555") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_16 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_16 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_16"; + + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_16 : ENTITY IS TRUE; + + end SLICE_16; + + architecture Structure of SLICE_16 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2045: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CASr2_383: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CASr_382: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A0_ipd, DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40009 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40009 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE; + + end lut40009; + + architecture Structure of lut40009 is + begin + INST10: ROM16X1A + generic map (initval => X"C0CA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40010 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40010 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE; + + end lut40010; + + architecture Structure of lut40010 is + begin + INST10: ROM16X1A + generic map (initval => X"4000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_19 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_19 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_19"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE; + + end SLICE_19; + + architecture Structure of SLICE_19 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i26_4_lut: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_3_lut_4_lut: lut40010 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdEnable_405: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40011 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40011 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE; + + end lut40011; + + architecture Structure of lut40011 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_20 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_20 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_20"; + + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_20 : ENTITY IS TRUE; + + end SLICE_20; + + architecture Structure of SLICE_20 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2447_001_BUF1_BUF1: lut40011 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdSubmitted_411: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40012 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40012 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE; + + end lut40012; + + architecture Structure of lut40012 is + begin + INST10: ROM16X1A + generic map (initval => X"FEFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40013 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40013 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE; + + end lut40013; + + architecture Structure of lut40013 is + begin + INST10: ROM16X1A + generic map (initval => X"CC5C") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_24 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_24 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_24"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_24 : ENTITY IS TRUE; + + end SLICE_24; + + architecture Structure of SLICE_24 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut_adj_15: lut40012 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Cmdn8MEGEN_I_93_4_lut: lut40013 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Cmdn8MEGEN_410: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40014 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40014 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE; + + end lut40014; + + architecture Structure of lut40014 is + begin + INST10: ROM16X1A + generic map (initval => X"4040") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_25 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_25 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_25"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE; + + end SLICE_25; + + architecture Structure of SLICE_25 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_3_lut: lut40014 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_1_lut_rep_24: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + CBR_390: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + FWEr_389: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_26 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_26 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_26"; + + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE; + + end SLICE_26; + + architecture Structure of SLICE_26 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2447_000_BUF1_BUF1: lut40011 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + InitReady_394: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_27 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_27 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_27"; + + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_27 : ENTITY IS TRUE; + + end SLICE_27; + + architecture Structure of SLICE_27 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + m1_lut: lut40011 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + LEDEN_419: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40015 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40015 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE; + + end lut40015; + + architecture Structure of lut40015 is + begin + INST10: ROM16X1A + generic map (initval => X"FBFB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_30 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_30 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_30"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_30 : ENTITY IS TRUE; + + end SLICE_30; + + architecture Structure of SLICE_30 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2010_3_lut_3_lut: lut40015 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2044: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + RASr2_380: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + RASr_379: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, + CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40016 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40016 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE; + + end lut40016; + + architecture Structure of lut40016 is + begin + INST10: ROM16X1A + generic map (initval => X"8080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40017 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40017 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE; + + end lut40017; + + architecture Structure of lut40017 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_32 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_32 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_32"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE; + + end SLICE_32; + + architecture Structure of SLICE_32 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0007 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40017 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_rep_32: lut40016 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_2_lut_3_lut_4_lut: lut40017 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RA10_400: vmuxregsre0007 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40018 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40018 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE; + + end lut40018; + + architecture Structure of lut40018 is + begin + INST10: ROM16X1A + generic map (initval => X"1010") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40019 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40019 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE; + + end lut40019; + + architecture Structure of lut40019 is + begin + INST10: ROM16X1A + generic map (initval => X"C6C6") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_33 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_33 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_33"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_33 : ENTITY IS TRUE; + + end SLICE_33; + + architecture Structure of SLICE_33 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RA11_I_54_3_lut: lut40019 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RA11_385: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40020 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40020 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE; + + end lut40020; + + architecture Structure of lut40020 is + begin + INST10: ROM16X1A + generic map (initval => X"20FF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40021 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40021 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE; + + end lut40021; + + architecture Structure of lut40021 is + begin + INST10: ROM16X1A + generic map (initval => X"CACA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_35 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_35 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_35"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE; + + end SLICE_35; + + architecture Structure of SLICE_35 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40020 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_4_lut_adj_25: lut40020 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i29_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKEEN_401: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40022 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40022 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE; + + end lut40022; + + architecture Structure of lut40022 is + begin + INST10: ROM16X1A + generic map (initval => X"CFC8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_36 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_36 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_36"; + + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE; + + end SLICE_36; + + architecture Structure of SLICE_36 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40022 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1404_4_lut: lut40022 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + PHI2r2_377: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKE_395: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D0_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, M1_dly, + CLK_dly, F0_out, Q0_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_37 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_37 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_37"; + + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_37 : ENTITY IS TRUE; + + end SLICE_37; + + architecture Structure of SLICE_37 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2447_002_BUF1_BUF1: lut40011 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Ready_404: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40023 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40023 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE; + + end lut40023; + + architecture Structure of lut40023 is + begin + INST10: ROM16X1A + generic map (initval => X"3A0A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_44 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_44 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_44"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE; + + end SLICE_44; + + architecture Structure of SLICE_44 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40023 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1970_4_lut: lut40023 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1603_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + UFMCLK_416: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40024 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40024 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE; + + end lut40024; + + architecture Structure of lut40024 is + begin + INST10: ROM16X1A + generic map (initval => X"CAC0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_45 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_45 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_45"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_45 : ENTITY IS TRUE; + + end SLICE_45; + + architecture Structure of SLICE_45 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i4_4_lut_adj_17: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1589_4_lut: lut40024 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + UFMSDI_417: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40025 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40025 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE; + + end lut40025; + + architecture Structure of lut40025 is + begin + INST10: ROM16X1A + generic map (initval => X"FEFA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40026 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40026 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE; + + end lut40026; + + architecture Structure of lut40026 is + begin + INST10: ROM16X1A + generic map (initval => X"0008") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_50 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_50 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_50"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_50 : ENTITY IS TRUE; + + end SLICE_50; + + architecture Structure of SLICE_50 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40025 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1962_4_lut: lut40025 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_3_lut_4_lut_adj_11: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + XOR8MEG_408: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40027 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40027 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE; + + end lut40027; + + architecture Structure of lut40027 is + begin + INST10: ROM16X1A + generic map (initval => X"1000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40028 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40028 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE; + + end lut40028; + + architecture Structure of lut40028 is + begin + INST10: ROM16X1A + generic map (initval => X"BF04") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_57 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_57 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_57"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_57 : ENTITY IS TRUE; + + end SLICE_57; + + architecture Structure of SLICE_57 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_rep_18_4_lut: lut40027 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + n8MEGEN_I_14_3_lut_4_lut: lut40028 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + n8MEGEN_418: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40029 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40029 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE; + + end lut40029; + + architecture Structure of lut40029 is + begin + INST10: ROM16X1A + generic map (initval => X"3AFA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40030 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40030 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40030 : ENTITY IS TRUE; + + end lut40030; + + architecture Structure of lut40030 is + begin + INST10: ROM16X1A + generic map (initval => X"FE0E") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0031 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity vmuxregsre0031 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0031 : ENTITY IS TRUE; + + end vmuxregsre0031; + + architecture Structure of vmuxregsre0031 is + begin + INST01: FL1P3BX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); + end Structure; + +-- entity SLICE_59 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_59 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_59"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_59 : ENTITY IS TRUE; + + end SLICE_59; + + architecture Structure of SLICE_59 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40030 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + begin + nRCAS_I_43_4_lut: lut40029 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCAS_I_0_452_3_lut_4_lut: lut40030 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRCAS_398: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40032 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40032 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE; + + end lut40032; + + architecture Structure of lut40032 is + begin + INST10: ROM16X1A + generic map (initval => X"1F10") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_61 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_61 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_61"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE; + + end SLICE_61; + + architecture Structure of SLICE_61 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40032 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRCS_I_31_3_lut_4_lut: lut40032 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCS_I_0_448_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRCS_396: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40033 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40033 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE; + + end lut40033; + + architecture Structure of lut40033 is + begin + INST10: ROM16X1A + generic map (initval => X"BFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_62 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_62 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_62"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_62 : ENTITY IS TRUE; + + end SLICE_62; + + architecture Structure of SLICE_62 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_4_lut_adj_2: lut40033 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRCS_N_137_I_0_4_lut: lut40029 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRRAS_397: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40034 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40034 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE; + + end lut40034; + + architecture Structure of lut40034 is + begin + INST10: ROM16X1A + generic map (initval => X"EEEE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40035 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40035 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE; + + end lut40035; + + architecture Structure of lut40035 is + begin + INST10: ROM16X1A + generic map (initval => X"CFC5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_64 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_64 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_64"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE; + + end SLICE_64; + + architecture Structure of SLICE_64 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40035 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1477_2_lut: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRWE_I_0_455_4_lut: lut40035 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRWE_399: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40036 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40036 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE; + + end lut40036; + + architecture Structure of lut40036 is + begin + INST10: ROM16X1A + generic map (initval => X"3032") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_65 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_65 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_65"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE; + + end SLICE_65; + + architecture Structure of SLICE_65 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40036 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i786_2_lut: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1432_4_lut: lut40036 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRowColSel_402: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40037 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40037 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE; + + end lut40037; + + architecture Structure of lut40037 is + begin + INST10: ROM16X1A + generic map (initval => X"BBBB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_66 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_66 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_66"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE; + + end SLICE_66; + + architecture Structure of SLICE_66 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_23: lut40037 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1439_2_lut: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + S_FSM_i4: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, DI0_dly, LSR_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40038 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40038 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE; + + end lut40038; + + architecture Structure of lut40038 is + begin + INST10: ROM16X1A + generic map (initval => X"2222") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_67 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_67 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_67"; + + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE; + + end SLICE_67; + + architecture Structure of SLICE_67 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_10: lut40038 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_FSM_i3: vmuxregsre0004 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B0_ipd, A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, + Q0_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40039 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40039 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE; + + end lut40039; + + architecture Structure of lut40039 is + begin + INST10: ROM16X1A + generic map (initval => X"8888") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_68 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_68 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_68"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE; + + end SLICE_68; + + architecture Structure of SLICE_68 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i4_2_lut: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1989_2_lut: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + S_FSM_i2: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, LSR_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_69 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_69 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_69"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE; + + end SLICE_69; + + architecture Structure of SLICE_69 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1491_2_lut_rep_30: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RASr2_I_0_1_lut_rep_25: lut40008 + port map (A=>A0_ipd, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + PHI2r3_378: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + S_FSM_i1: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, A0_ipd, DI0_dly, M1_dly, CLK_dly, + F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40040 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40040 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE; + + end lut40040; + + architecture Structure of lut40040 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40041 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40041 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE; + + end lut40041; + + architecture Structure of lut40041 is + begin + INST10: ROM16X1A + generic map (initval => X"3FBB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_70 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_70 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_70"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_70 : ENTITY IS TRUE; + + end SLICE_70; + + architecture Structure of SLICE_70 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0031 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40041 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_4_lut: lut40040 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1448_4_lut: lut40041 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nUFMCS_415: vmuxregsre0031 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40042 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40042 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE; + + end lut40042; + + architecture Structure of lut40042 is + begin + INST10: ROM16X1A + generic map (initval => X"1F1F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40043 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40043 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE; + + end lut40043; + + architecture Structure of lut40043 is + begin + INST10: ROM16X1A + generic map (initval => X"5540") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity selmux2 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity selmux2 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE; + + end selmux2; + + architecture Structure of selmux2 is + begin + INST1: MUX21 + port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z); + end Structure; + +-- entity i30_SLICE_71 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity i30_SLICE_71 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "i30_SLICE_71"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF i30_SLICE_71 : ENTITY IS TRUE; + + end i30_SLICE_71; + + architecture Structure of i30_SLICE_71 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal i30_SLICE_71_i30_SLICE_71_K1_H1: Std_logic; + signal i30_SLICE_71_i30_GATE_H0: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40043 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + begin + i30_SLICE_71_K1: lut40042 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, + Z=>i30_SLICE_71_i30_SLICE_71_K1_H1); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i30_GATE: lut40043 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>i30_SLICE_71_i30_GATE_H0); + i30_SLICE_71_K0K1MUX: selmux2 + port map (D0=>i30_SLICE_71_i30_GATE_H0, + D1=>i30_SLICE_71_i30_SLICE_71_K1_H1, SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40044 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40044 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE; + + end lut40044; + + architecture Structure of lut40044 is + begin + INST10: ROM16X1A + generic map (initval => X"FF40") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_72 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_72 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_72"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_72 : ENTITY IS TRUE; + + end SLICE_72; + + architecture Structure of SLICE_72 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40044 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_4_lut_4_lut_adj_12: lut40044 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_2_lut: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_73 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_73 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_73"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_73 : ENTITY IS TRUE; + + end SLICE_73; + + architecture Structure of SLICE_73 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40003 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_4_lut_adj_14: lut40003 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i4_4_lut: lut40010 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40045 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40045 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE; + + end lut40045; + + architecture Structure of lut40045 is + begin + INST10: ROM16X1A + generic map (initval => X"0020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_74 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_74 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_74"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE; + + end SLICE_74; + + architecture Structure of SLICE_74 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40045 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i12_4_lut: lut40033 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_3_lut_4_lut: lut40045 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i1: vmuxregsre0004 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i0: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_75 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_75 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_75"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE; + + end SLICE_75; + + architecture Structure of SLICE_75 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_4_lut_adj_18: lut40027 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut: lut40038 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i9: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i8: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_76 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_76 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_76"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE; + + end SLICE_76; + + architecture Structure of SLICE_76 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0007 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_19_3_lut: lut40012 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_rep_15_4_lut: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i9: vmuxregsre0007 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i8: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40046 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40046 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE; + + end lut40046; + + architecture Structure of lut40046 is + begin + INST10: ROM16X1A + generic map (initval => X"0800") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_77 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_77 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_77"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE; + + end SLICE_77; + + architecture Structure of SLICE_77 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40046 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_4_lut_adj_22: lut40046 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut: lut40046 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40047 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40047 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE; + + end lut40047; + + architecture Structure of lut40047 is + begin + INST10: ROM16X1A + generic map (initval => X"F0DD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40048 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40048 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE; + + end lut40048; + + architecture Structure of lut40048 is + begin + INST10: ROM16X1A + generic map (initval => X"DDDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_78 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_78 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_78"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE; + + end SLICE_78; + + architecture Structure of SLICE_78 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40047 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + nRCS_N_146_bdd_4_lut: lut40047 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1423_2_lut: lut40048 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i13: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i12: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40049 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40049 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE; + + end lut40049; + + architecture Structure of lut40049 is + begin + INST10: ROM16X1A + generic map (initval => X"0200") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_79 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_79 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_79"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE; + + end SLICE_79; + + architecture Structure of SLICE_79 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40049 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i11_3_lut_rep_20: lut40016 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_c_0_bdd_4_lut: lut40049 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i11: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i10: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40050 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40050 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE; + + end lut40050; + + architecture Structure of lut40050 is + begin + INST10: ROM16X1A + generic map (initval => X"0001") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_80 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_80 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_80"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE; + + end SLICE_80; + + architecture Structure of SLICE_80 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40050 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_2_lut_rep_26: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2005_3_lut_rep_17_4_lut: lut40050 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40051 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40051 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE; + + end lut40051; + + architecture Structure of lut40051 is + begin + INST10: ROM16X1A + generic map (initval => X"FCDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_81 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_81 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_81"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE; + + end SLICE_81; + + architecture Structure of SLICE_81 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40051 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_29: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1427_4_lut: lut40051 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i15: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i14: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40052 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40052 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE; + + end lut40052; + + architecture Structure of lut40052 is + begin + INST10: ROM16X1A + generic map (initval => X"8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_82 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_82 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_82"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE; + + end SLICE_82; + + architecture Structure of SLICE_82 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0007 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i6_4_lut: lut40052 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_adj_3: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowA_i5: vmuxregsre0007 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i4: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40053 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40053 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE; + + end lut40053; + + architecture Structure of lut40053 is + begin + INST10: ROM16X1A + generic map (initval => X"0004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40054 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40054 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE; + + end lut40054; + + architecture Structure of lut40054 is + begin + INST10: ROM16X1A + generic map (initval => X"FFDF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_83 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_83 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_83"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE; + + end SLICE_83; + + architecture Structure of SLICE_83 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40053 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40054 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_4_lut_adj_21: lut40053 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_3_lut_4_lut_adj_6: lut40054 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40055 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40055 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE; + + end lut40055; + + architecture Structure of lut40055 is + begin + INST10: ROM16X1A + generic map (initval => X"2020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_84 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_84 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_84"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE; + + end SLICE_84; + + architecture Structure of SLICE_84 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40055 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_rep_28: lut40055 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1573_4_lut: lut40024 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40056 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40056 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE; + + end lut40056; + + architecture Structure of lut40056 is + begin + INST10: ROM16X1A + generic map (initval => X"FFEF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_85 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_85 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_85"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE; + + end SLICE_85; + + architecture Structure of SLICE_85 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40056 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1969_2_lut_3_lut_4_lut: lut40056 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut_adj_7: lut40040 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_86 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_86 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_86"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE; + + end SLICE_86; + + architecture Structure of SLICE_86 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i5_3_lut: lut40012 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_4_lut_adj_8: lut4 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RASr3_381: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + PHI2r_376: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_87 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_87 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_87"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE; + + end SLICE_87; + + architecture Structure of SLICE_87 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i4_4_lut_adj_16: lut40040 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_2_lut: lut40048 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RBA_i2: vmuxregsre0004 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RBA_i1: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40057 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40057 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE; + + end lut40057; + + architecture Structure of lut40057 is + begin + INST10: ROM16X1A + generic map (initval => X"C0C5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_88 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_88 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_88"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE; + + end SLICE_88; + + architecture Structure of SLICE_88 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40053 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40057 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i34_4_lut: lut40057 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut_adj_13: lut40053 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + WRD_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40058 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40058 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE; + + end lut40058; + + architecture Structure of lut40058 is + begin + INST10: ROM16X1A + generic map (initval => X"8088") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40059 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40059 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE; + + end lut40059; + + architecture Structure of lut40059 is + begin + INST10: ROM16X1A + generic map (initval => X"C444") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_89 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_89 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_89"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE; + + end SLICE_89; + + architecture Structure of SLICE_89 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40058 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40059 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_4_lut: lut40058 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut: lut40059 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + WRD_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_90 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_90 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_90"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE; + + end SLICE_90; + + architecture Structure of SLICE_90 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40049 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40055 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut_4_lut_adj_1: lut40049 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_rep_21_3_lut: lut40055 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + WRD_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40060 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40060 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE; + + end lut40060; + + architecture Structure of lut40060 is + begin + INST10: ROM16X1A + generic map (initval => X"DFDF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40061 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40061 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE; + + end lut40061; + + architecture Structure of lut40061 is + begin + INST10: ROM16X1A + generic map (initval => X"DFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_91 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_91 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_91"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE; + + end SLICE_91; + + architecture Structure of SLICE_91 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40060 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_13_3_lut: lut40060 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_3_lut_4_lut_adj_5: lut40061 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i3: vmuxregsre0004 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i2: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40062 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40062 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE; + + end lut40062; + + architecture Structure of lut40062 is + begin + INST10: ROM16X1A + generic map (initval => X"0080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_92 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_92 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_92"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE; + + end SLICE_92; + + architecture Structure of SLICE_92 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40062 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2008_2_lut_4_lut: lut40062 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_rep_22_4_lut: lut40005 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + WRD_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40063 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40063 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE; + + end lut40063; + + architecture Structure of lut40063 is + begin + INST10: ROM16X1A + generic map (initval => X"7777") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_93 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_93 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_93"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE; + + end SLICE_93; + + architecture Structure of SLICE_93 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40063 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2001_2_lut: lut40063 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i10_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40064 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40064 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE; + + end lut40064; + + architecture Structure of lut40064 is + begin + INST10: ROM16X1A + generic map (initval => X"FFFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_94 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_94 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_94"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE; + + end SLICE_94; + + architecture Structure of SLICE_94 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40064 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i771_2_lut_rep_23_2_lut: lut40048 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_4_lut_4_lut: lut40064 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40065 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40065 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE; + + end lut40065; + + architecture Structure of lut40065 is + begin + INST10: ROM16X1A + generic map (initval => X"1404") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_95 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_95 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_95"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_95 : ENTITY IS TRUE; + + end SLICE_95; + + architecture Structure of SLICE_95 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40065 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_4_lut_adj_20: lut40065 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i6_4_lut_adj_9: lut40040 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_96 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_96 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_96"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_96 : ENTITY IS TRUE; + + end SLICE_96; + + architecture Structure of SLICE_96 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_27: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_4_lut_adj_24: lut40027 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40066 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40066 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE; + + end lut40066; + + architecture Structure of lut40066 is + begin + INST10: ROM16X1A + generic map (initval => X"C5C5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_97 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_97 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_97"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_97 : ENTITY IS TRUE; + + end SLICE_97; + + architecture Structure of SLICE_97 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40066 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i13_3_lut: lut40066 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1956_2_lut: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + IS_FSM_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_98 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_98 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_98"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_98 : ENTITY IS TRUE; + + end SLICE_98; + + architecture Structure of SLICE_98 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1416_2_lut: lut40037 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i9_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + IS_FSM_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_99 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_99 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_99"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_99 : ENTITY IS TRUE; + + end SLICE_99; + + architecture Structure of SLICE_99 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i8_4_lut: lut40052 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + MAin_9_I_0_427_i8_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdUFMSDI_414: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_100 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_100 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_100"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_100 : ENTITY IS TRUE; + + end SLICE_100; + + architecture Structure of SLICE_100 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1979_4_lut: lut40052 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + MAin_9_I_0_427_i7_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + CmdUFMCS_412: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + CmdUFMCLK_413: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_101 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_101 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_101"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_101 : ENTITY IS TRUE; + + end SLICE_101; + + architecture Structure of SLICE_101 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i1_3_lut: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i6_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_102 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_102 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_102"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_102 : ENTITY IS TRUE; + + end SLICE_102; + + architecture Structure of SLICE_102 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i2_3_lut: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i5_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_103 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_103 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_103"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_103 : ENTITY IS TRUE; + + end SLICE_103; + + architecture Structure of SLICE_103 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i3_3_lut: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i4_3_lut: lut40021 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40067 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity lut40067 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE; + + end lut40067; + + architecture Structure of lut40067 is + begin + INST10: ROM16X1A + generic map (initval => X"FDFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_104 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_104 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_104"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_LSR : VitalDelayType := 0 ns; + tpw_LSR_posedge : VitalDelayType := 0 ns; + tpw_LSR_negedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_104 : ENTITY IS TRUE; + + end SLICE_104; + + architecture Structure of SLICE_104 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0004 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40067 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1417_2_lut: lut40034 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_rep_14_3_lut: lut40067 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RowA_i7: vmuxregsre0004 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i6: vmuxregsre0004 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_LSR : x01 := '0'; + VARIABLE periodcheckinfo_LSR : VitalPeriodDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => LSR_ipd, + TestSignalName => "LSR", + Period => tperiod_LSR, + PulseWidthHigh => tpw_LSR_posedge, + PulseWidthLow => tpw_LSR_negedge, + PeriodData => periodcheckinfo_LSR, + Violation => tviol_LSR_LSR, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_105 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_105 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_105"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_105 : ENTITY IS TRUE; + + end SLICE_105; + + architecture Structure of SLICE_105 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_19: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i5_4_lut: lut40052 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_106 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity SLICE_106 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_106"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_106 : ENTITY IS TRUE; + + end SLICE_106; + + architecture Structure of SLICE_106 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_33: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1930_2_lut: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + IS_FSM_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M1_dly, M0_dly, + CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf is + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf : ENTITY IS TRUE; + + end xo2iobuf; + + architecture Structure of xo2iobuf is + begin + INST1: IBPD + port map (I=>PADI, O=>Z); + INST2: OBZPD + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity RD_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_7_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD7 : VitalDelayType := 0 ns; + tpw_RD7_posedge : VitalDelayType := 0 ns; + tpw_RD7_negedge : VitalDelayType := 0 ns; + tpd_RD7_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD7: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE; + + end RD_7_B; + + architecture Structure of RD_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD7_ipd : std_logic := 'X'; + signal RD7_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_7_713: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, + PADI=>RD7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD7_ipd, RD7, tipd_RD7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD7_zd : std_logic := 'X'; + VARIABLE RD7_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD7_RD7 : x01 := '0'; + VARIABLE periodcheckinfo_RD7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD7_ipd, + TestSignalName => "RD7", + Period => tperiod_RD7, + PulseWidthHigh => tpw_RD7_posedge, + PulseWidthLow => tpw_RD7_negedge, + PeriodData => periodcheckinfo_RD7, + Violation => tviol_RD7_RD7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD7_zd := RD7_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD7_ipd'last_event, + PathDelay => tpd_RD7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD7, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD7, + PathCondition => TRUE)), + GlitchData => RD7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_6_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD6 : VitalDelayType := 0 ns; + tpw_RD6_posedge : VitalDelayType := 0 ns; + tpw_RD6_negedge : VitalDelayType := 0 ns; + tpd_RD6_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD6: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE; + + end RD_6_B; + + architecture Structure of RD_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD6_ipd : std_logic := 'X'; + signal RD6_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_6_714: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, + PADI=>RD6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD6_ipd, RD6, tipd_RD6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD6_zd : std_logic := 'X'; + VARIABLE RD6_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD6_RD6 : x01 := '0'; + VARIABLE periodcheckinfo_RD6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD6_ipd, + TestSignalName => "RD6", + Period => tperiod_RD6, + PulseWidthHigh => tpw_RD6_posedge, + PulseWidthLow => tpw_RD6_negedge, + PeriodData => periodcheckinfo_RD6, + Violation => tviol_RD6_RD6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD6_zd := RD6_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD6_ipd'last_event, + PathDelay => tpd_RD6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD6, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD6, + PathCondition => TRUE)), + GlitchData => RD6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_5_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD5 : VitalDelayType := 0 ns; + tpw_RD5_posedge : VitalDelayType := 0 ns; + tpw_RD5_negedge : VitalDelayType := 0 ns; + tpd_RD5_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD5: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE; + + end RD_5_B; + + architecture Structure of RD_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD5_ipd : std_logic := 'X'; + signal RD5_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_5_715: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, + PADI=>RD5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD5_ipd, RD5, tipd_RD5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD5_zd : std_logic := 'X'; + VARIABLE RD5_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD5_RD5 : x01 := '0'; + VARIABLE periodcheckinfo_RD5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD5_ipd, + TestSignalName => "RD5", + Period => tperiod_RD5, + PulseWidthHigh => tpw_RD5_posedge, + PulseWidthLow => tpw_RD5_negedge, + PeriodData => periodcheckinfo_RD5, + Violation => tviol_RD5_RD5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD5_zd := RD5_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD5_ipd'last_event, + PathDelay => tpd_RD5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD5, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD5, + PathCondition => TRUE)), + GlitchData => RD5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_4_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD4 : VitalDelayType := 0 ns; + tpw_RD4_posedge : VitalDelayType := 0 ns; + tpw_RD4_negedge : VitalDelayType := 0 ns; + tpd_RD4_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD4: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE; + + end RD_4_B; + + architecture Structure of RD_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD4_ipd : std_logic := 'X'; + signal RD4_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_4_716: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, + PADI=>RD4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD4_ipd, RD4, tipd_RD4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD4_zd : std_logic := 'X'; + VARIABLE RD4_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD4_RD4 : x01 := '0'; + VARIABLE periodcheckinfo_RD4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD4_ipd, + TestSignalName => "RD4", + Period => tperiod_RD4, + PulseWidthHigh => tpw_RD4_posedge, + PulseWidthLow => tpw_RD4_negedge, + PeriodData => periodcheckinfo_RD4, + Violation => tviol_RD4_RD4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD4_zd := RD4_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD4_ipd'last_event, + PathDelay => tpd_RD4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD4, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD4, + PathCondition => TRUE)), + GlitchData => RD4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_3_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD3 : VitalDelayType := 0 ns; + tpw_RD3_posedge : VitalDelayType := 0 ns; + tpw_RD3_negedge : VitalDelayType := 0 ns; + tpd_RD3_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD3: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE; + + end RD_3_B; + + architecture Structure of RD_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD3_ipd : std_logic := 'X'; + signal RD3_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_3_717: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, + PADI=>RD3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD3_ipd, RD3, tipd_RD3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD3_zd : std_logic := 'X'; + VARIABLE RD3_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD3_RD3 : x01 := '0'; + VARIABLE periodcheckinfo_RD3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD3_ipd, + TestSignalName => "RD3", + Period => tperiod_RD3, + PulseWidthHigh => tpw_RD3_posedge, + PulseWidthLow => tpw_RD3_negedge, + PeriodData => periodcheckinfo_RD3, + Violation => tviol_RD3_RD3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD3_zd := RD3_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD3_ipd'last_event, + PathDelay => tpd_RD3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD3, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD3, + PathCondition => TRUE)), + GlitchData => RD3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_2_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD2 : VitalDelayType := 0 ns; + tpw_RD2_posedge : VitalDelayType := 0 ns; + tpw_RD2_negedge : VitalDelayType := 0 ns; + tpd_RD2_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD2: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE; + + end RD_2_B; + + architecture Structure of RD_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD2_ipd : std_logic := 'X'; + signal RD2_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_2_718: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, + PADI=>RD2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD2_ipd, RD2, tipd_RD2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD2_zd : std_logic := 'X'; + VARIABLE RD2_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD2_RD2 : x01 := '0'; + VARIABLE periodcheckinfo_RD2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD2_ipd, + TestSignalName => "RD2", + Period => tperiod_RD2, + PulseWidthHigh => tpw_RD2_posedge, + PulseWidthLow => tpw_RD2_negedge, + PeriodData => periodcheckinfo_RD2, + Violation => tviol_RD2_RD2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD2_zd := RD2_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD2_ipd'last_event, + PathDelay => tpd_RD2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD2, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD2, + PathCondition => TRUE)), + GlitchData => RD2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_1_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD1 : VitalDelayType := 0 ns; + tpw_RD1_posedge : VitalDelayType := 0 ns; + tpw_RD1_negedge : VitalDelayType := 0 ns; + tpd_RD1_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD1: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE; + + end RD_1_B; + + architecture Structure of RD_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD1_ipd : std_logic := 'X'; + signal RD1_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_1_719: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, + PADI=>RD1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD1_ipd, RD1, tipd_RD1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD1_zd : std_logic := 'X'; + VARIABLE RD1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD1_RD1 : x01 := '0'; + VARIABLE periodcheckinfo_RD1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD1_ipd, + TestSignalName => "RD1", + Period => tperiod_RD1, + PulseWidthHigh => tpw_RD1_posedge, + PulseWidthLow => tpw_RD1_negedge, + PeriodData => periodcheckinfo_RD1, + Violation => tviol_RD1_RD1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD1_zd := RD1_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD1_ipd'last_event, + PathDelay => tpd_RD1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD1, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD1, + PathCondition => TRUE)), + GlitchData => RD1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RD_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_0_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD0 : VitalDelayType := 0 ns; + tpw_RD0_posedge : VitalDelayType := 0 ns; + tpw_RD0_negedge : VitalDelayType := 0 ns; + tpd_RD0_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD0: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE; + + end RD_0_B; + + architecture Structure of RD_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD0_ipd : std_logic := 'X'; + signal RD0_out : std_logic := 'Z'; + + component xo2iobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_0_720: xo2iobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, + PADI=>RD0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD0_ipd, RD0, tipd_RD0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD0_zd : std_logic := 'X'; + VARIABLE RD0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD0_RD0 : x01 := '0'; + VARIABLE periodcheckinfo_RD0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD0_ipd, + TestSignalName => "RD0", + Period => tperiod_RD0, + PulseWidthHigh => tpw_RD0_posedge, + PulseWidthLow => tpw_RD0_negedge, + PeriodData => periodcheckinfo_RD0, + Violation => tviol_RD0_RD0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD0_zd := RD0_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD0_ipd'last_event, + PathDelay => tpd_RD0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD0, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD0, + PathCondition => TRUE)), + GlitchData => RD0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0068 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0068 is + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0068 : ENTITY IS TRUE; + + end xo2iobuf0068; + + architecture Structure of xo2iobuf0068 is + begin + INST5: OBZPD + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity Dout_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout7 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE; + + end Dout_7_B; + + architecture Structure of Dout_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout7_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_7: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout7_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout7_out) + VARIABLE Dout7_zd : std_logic := 'X'; + VARIABLE Dout7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout7_zd := Dout7_out; + + VitalPathDelay01 ( + OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout7, + PathCondition => TRUE)), + GlitchData => Dout7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout6 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE; + + end Dout_6_B; + + architecture Structure of Dout_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout6_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_6: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout6_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout6_out) + VARIABLE Dout6_zd : std_logic := 'X'; + VARIABLE Dout6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout6_zd := Dout6_out; + + VitalPathDelay01 ( + OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout6, + PathCondition => TRUE)), + GlitchData => Dout6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout5 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE; + + end Dout_5_B; + + architecture Structure of Dout_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout5_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_5: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout5_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout5_out) + VARIABLE Dout5_zd : std_logic := 'X'; + VARIABLE Dout5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout5_zd := Dout5_out; + + VitalPathDelay01 ( + OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout5, + PathCondition => TRUE)), + GlitchData => Dout5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout4 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE; + + end Dout_4_B; + + architecture Structure of Dout_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout4_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_4: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout4_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout4_out) + VARIABLE Dout4_zd : std_logic := 'X'; + VARIABLE Dout4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout4_zd := Dout4_out; + + VitalPathDelay01 ( + OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout4, + PathCondition => TRUE)), + GlitchData => Dout4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout3 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE; + + end Dout_3_B; + + architecture Structure of Dout_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout3_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_3: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout3_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout3_out) + VARIABLE Dout3_zd : std_logic := 'X'; + VARIABLE Dout3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout3_zd := Dout3_out; + + VitalPathDelay01 ( + OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout3, + PathCondition => TRUE)), + GlitchData => Dout3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout2 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE; + + end Dout_2_B; + + architecture Structure of Dout_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout2_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_2: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout2_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout2_out) + VARIABLE Dout2_zd : std_logic := 'X'; + VARIABLE Dout2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout2_zd := Dout2_out; + + VitalPathDelay01 ( + OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout2, + PathCondition => TRUE)), + GlitchData => Dout2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE; + + end Dout_1_B; + + architecture Structure of Dout_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_1: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout1_out) + VARIABLE Dout1_zd : std_logic := 'X'; + VARIABLE Dout1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout1_zd := Dout1_out; + + VitalPathDelay01 ( + OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout1, + PathCondition => TRUE)), + GlitchData => Dout1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Dout_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; Dout0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE; + + end Dout_0_B; + + architecture Structure of Dout_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_0: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout0_out) + VARIABLE Dout0_zd : std_logic := 'X'; + VARIABLE Dout0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout0_zd := Dout0_out; + + VitalPathDelay01 ( + OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout0, + PathCondition => TRUE)), + GlitchData => Dout0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity LEDB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity LEDB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "LEDB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_LEDS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; LEDS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE; + + end LEDB; + + architecture Structure of LEDB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal LEDS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + LED_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>LEDS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, LEDS_out) + VARIABLE LEDS_zd : std_logic := 'X'; + VARIABLE LEDS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + LEDS_zd := LEDS_out; + + VitalPathDelay01 ( + OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_LEDS, + PathCondition => TRUE)), + GlitchData => LEDS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RBA1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RBA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE; + + end RBA_1_B; + + architecture Structure of RBA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RBA1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_1: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RBA1_out) + VARIABLE RBA1_zd : std_logic := 'X'; + VARIABLE RBA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA1_zd := RBA1_out; + + VitalPathDelay01 ( + OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RBA1, + PathCondition => TRUE)), + GlitchData => RBA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RBA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RBA0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RBA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE; + + end RBA_0_B; + + architecture Structure of RBA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RBA0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_0: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RBA0_out) + VARIABLE RBA0_zd : std_logic := 'X'; + VARIABLE RBA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA0_zd := RBA0_out; + + VitalPathDelay01 ( + OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RBA0, + PathCondition => TRUE)), + GlitchData => RBA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_11_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_11_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_11_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA11 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA11: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE; + + end RA_11_B; + + architecture Structure of RA_11_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA11_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_11: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA11_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA11_out) + VARIABLE RA11_zd : std_logic := 'X'; + VARIABLE RA11_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA11_zd := RA11_out; + + VitalPathDelay01 ( + OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA11, + PathCondition => TRUE)), + GlitchData => RA11_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_10_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_10_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_10_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA10 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA10: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE; + + end RA_10_B; + + architecture Structure of RA_10_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA10_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_10: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA10_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA10_out) + VARIABLE RA10_zd : std_logic := 'X'; + VARIABLE RA10_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA10_zd := RA10_out; + + VitalPathDelay01 ( + OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA10, + PathCondition => TRUE)), + GlitchData => RA10_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_9_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_9_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA9 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA9: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE; + + end RA_9_B; + + architecture Structure of RA_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA9_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_9: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA9_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA9_out) + VARIABLE RA9_zd : std_logic := 'X'; + VARIABLE RA9_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA9_zd := RA9_out; + + VitalPathDelay01 ( + OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA9, + PathCondition => TRUE)), + GlitchData => RA9_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_8_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_8_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA8 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA8: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE; + + end RA_8_B; + + architecture Structure of RA_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA8_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_8: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA8_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA8_out) + VARIABLE RA8_zd : std_logic := 'X'; + VARIABLE RA8_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA8_zd := RA8_out; + + VitalPathDelay01 ( + OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA8, + PathCondition => TRUE)), + GlitchData => RA8_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA7 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE; + + end RA_7_B; + + architecture Structure of RA_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA7_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_7: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA7_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA7_out) + VARIABLE RA7_zd : std_logic := 'X'; + VARIABLE RA7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA7_zd := RA7_out; + + VitalPathDelay01 ( + OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA7, + PathCondition => TRUE)), + GlitchData => RA7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA6 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE; + + end RA_6_B; + + architecture Structure of RA_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA6_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_6: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA6_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA6_out) + VARIABLE RA6_zd : std_logic := 'X'; + VARIABLE RA6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA6_zd := RA6_out; + + VitalPathDelay01 ( + OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA6, + PathCondition => TRUE)), + GlitchData => RA6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA5 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE; + + end RA_5_B; + + architecture Structure of RA_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA5_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_5: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA5_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA5_out) + VARIABLE RA5_zd : std_logic := 'X'; + VARIABLE RA5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA5_zd := RA5_out; + + VitalPathDelay01 ( + OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA5, + PathCondition => TRUE)), + GlitchData => RA5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA4 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE; + + end RA_4_B; + + architecture Structure of RA_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA4_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_4: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA4_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA4_out) + VARIABLE RA4_zd : std_logic := 'X'; + VARIABLE RA4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA4_zd := RA4_out; + + VitalPathDelay01 ( + OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA4, + PathCondition => TRUE)), + GlitchData => RA4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA3 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE; + + end RA_3_B; + + architecture Structure of RA_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA3_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_3: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA3_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA3_out) + VARIABLE RA3_zd : std_logic := 'X'; + VARIABLE RA3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA3_zd := RA3_out; + + VitalPathDelay01 ( + OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA3, + PathCondition => TRUE)), + GlitchData => RA3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA2 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE; + + end RA_2_B; + + architecture Structure of RA_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA2_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_2: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA2_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA2_out) + VARIABLE RA2_zd : std_logic := 'X'; + VARIABLE RA2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA2_zd := RA2_out; + + VitalPathDelay01 ( + OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA2, + PathCondition => TRUE)), + GlitchData => RA2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA1 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE; + + end RA_1_B; + + architecture Structure of RA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_1: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA1_out) + VARIABLE RA1_zd : std_logic := 'X'; + VARIABLE RA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA1_zd := RA1_out; + + VitalPathDelay01 ( + OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA1, + PathCondition => TRUE)), + GlitchData => RA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE; + + end RA_0_B; + + architecture Structure of RA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_0: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA0_out) + VARIABLE RA0_zd : std_logic := 'X'; + VARIABLE RA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA0_zd := RA0_out; + + VitalPathDelay01 ( + OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA0, + PathCondition => TRUE)), + GlitchData => RA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCSB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCSB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRCSS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nRCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE; + + end nRCSB; + + architecture Structure of nRCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRCSS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCS_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCSS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out) + VARIABLE nRCSS_zd : std_logic := 'X'; + VARIABLE nRCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCSS_zd := nRCSS_out; + + VitalPathDelay01 ( + OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRCSS, + PathCondition => TRUE)), + GlitchData => nRCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCKEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RCKEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCKEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RCKES : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RCKES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE; + + end RCKEB; + + architecture Structure of RCKEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RCKES_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RCKE_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RCKES_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RCKES_out) + VARIABLE RCKES_zd : std_logic := 'X'; + VARIABLE RCKES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RCKES_zd := RCKES_out; + + VitalPathDelay01 ( + OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RCKES, + PathCondition => TRUE)), + GlitchData => RCKES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRWEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRWEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRWES : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nRWES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE; + + end nRWEB; + + architecture Structure of nRWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRWES_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRWE_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRWES_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRWES_out) + VARIABLE nRWES_zd : std_logic := 'X'; + VARIABLE nRWES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRWES_zd := nRWES_out; + + VitalPathDelay01 ( + OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRWES, + PathCondition => TRUE)), + GlitchData => nRWES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRRASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRRASB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRRASS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nRRASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE; + + end nRRASB; + + architecture Structure of nRRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRRASS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRRAS_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRRASS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out) + VARIABLE nRRASS_zd : std_logic := 'X'; + VARIABLE nRRASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRRASS_zd := nRRASS_out; + + VitalPathDelay01 ( + OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRRASS, + PathCondition => TRUE)), + GlitchData => nRRASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nRCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCASB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRCASS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nRCASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE; + + end nRCASB; + + architecture Structure of nRCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRCASS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCAS_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCASS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out) + VARIABLE nRCASS_zd : std_logic := 'X'; + VARIABLE nRCASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCASS_zd := nRCASS_out; + + VitalPathDelay01 ( + OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRCASS, + PathCondition => TRUE)), + GlitchData => nRCASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMHB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RDQMHB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMHB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMHS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE; + + end RDQMHB; + + architecture Structure of RDQMHB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMHS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQMH_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMHS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out) + VARIABLE RDQMHS_zd : std_logic := 'X'; + VARIABLE RDQMHS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMHS_zd := RDQMHS_out; + + VitalPathDelay01 ( + OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMHS, + PathCondition => TRUE)), + GlitchData => RDQMHS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMLB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RDQMLB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMLB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMLS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE; + + end RDQMLB; + + architecture Structure of RDQMLB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMLS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQML_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMLS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out) + VARIABLE RDQMLS_zd : std_logic := 'X'; + VARIABLE RDQMLS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMLS_zd := RDQMLS_out; + + VitalPathDelay01 ( + OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMLS, + PathCondition => TRUE)), + GlitchData => RDQMLS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nUFMCSB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nUFMCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nUFMCSB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nUFMCSS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE; + + end nUFMCSB; + + architecture Structure of nUFMCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nUFMCSS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nUFMCS_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nUFMCSS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out) + VARIABLE nUFMCSS_zd : std_logic := 'X'; + VARIABLE nUFMCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nUFMCSS_zd := nUFMCSS_out; + + VitalPathDelay01 ( + OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nUFMCSS, + PathCondition => TRUE)), + GlitchData => nUFMCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMCLKB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMCLKB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_UFMCLKS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE; + + end UFMCLKB; + + architecture Structure of UFMCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal UFMCLKS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMCLK_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMCLKS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out) + VARIABLE UFMCLKS_zd : std_logic := 'X'; + VARIABLE UFMCLKS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMCLKS_zd := UFMCLKS_out; + + VitalPathDelay01 ( + OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_UFMCLKS, + PathCondition => TRUE)), + GlitchData => UFMCLKS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDIB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMSDIB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDIB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_UFMSDIS : VitalDelayType01 := (0 ns, 0 ns)); + + port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE; + + end UFMSDIB; + + architecture Structure of UFMSDIB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal UFMSDIS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component xo2iobuf0068 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMSDI_pad: xo2iobuf0068 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMSDIS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out) + VARIABLE UFMSDIS_zd : std_logic := 'X'; + VARIABLE UFMSDIS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMSDIS_zd := UFMSDIS_out; + + VitalPathDelay01 ( + OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_UFMSDIS, + PathCondition => TRUE)), + GlitchData => UFMSDIS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity xo2iobuf0069 + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity xo2iobuf0069 is + port (Z: out Std_logic; PAD: in Std_logic); + + ATTRIBUTE Vital_Level0 OF xo2iobuf0069 : ENTITY IS TRUE; + + end xo2iobuf0069; + + architecture Structure of xo2iobuf0069 is + begin + INST1: IBPD + port map (I=>PAD, O=>Z); + end Structure; + +-- entity PHI2B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity PHI2B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "PHI2B"; + + tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns); + tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_PHI2S : VitalDelayType := 0 ns; + tpw_PHI2S_posedge : VitalDelayType := 0 ns; + tpw_PHI2S_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; PHI2S: in Std_logic); + + ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE; + + end PHI2B; + + architecture Structure of PHI2B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PHI2S_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + PHI2_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>PHI2S_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_PHI2S_PHI2S : x01 := '0'; + VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => PHI2S_ipd, + TestSignalName => "PHI2S", + Period => tperiod_PHI2S, + PulseWidthHigh => tpw_PHI2S_posedge, + PulseWidthLow => tpw_PHI2S_negedge, + PeriodData => periodcheckinfo_PHI2S, + Violation => tviol_PHI2S_PHI2S, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event, + PathDelay => tpd_PHI2S_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_9_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_9_B"; + + tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin9 : VitalDelayType := 0 ns; + tpw_MAin9_posedge : VitalDelayType := 0 ns; + tpw_MAin9_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin9: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE; + + end MAin_9_B; + + architecture Structure of MAin_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin9_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_9: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin9_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin9_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin9_MAin9 : x01 := '0'; + VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin9_ipd, + TestSignalName => "MAin9", + Period => tperiod_MAin9, + PulseWidthHigh => tpw_MAin9_posedge, + PulseWidthLow => tpw_MAin9_negedge, + PeriodData => periodcheckinfo_MAin9, + Violation => tviol_MAin9_MAin9, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin9_ipd'last_event, + PathDelay => tpd_MAin9_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_8_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_8_B"; + + tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin8 : VitalDelayType := 0 ns; + tpw_MAin8_posedge : VitalDelayType := 0 ns; + tpw_MAin8_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin8: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE; + + end MAin_8_B; + + architecture Structure of MAin_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin8_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_8: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin8_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin8_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin8_MAin8 : x01 := '0'; + VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin8_ipd, + TestSignalName => "MAin8", + Period => tperiod_MAin8, + PulseWidthHigh => tpw_MAin8_posedge, + PulseWidthLow => tpw_MAin8_negedge, + PeriodData => periodcheckinfo_MAin8, + Violation => tviol_MAin8_MAin8, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin8_ipd'last_event, + PathDelay => tpd_MAin8_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_7_B"; + + tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin7 : VitalDelayType := 0 ns; + tpw_MAin7_posedge : VitalDelayType := 0 ns; + tpw_MAin7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE; + + end MAin_7_B; + + architecture Structure of MAin_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin7_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_7: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin7_MAin7 : x01 := '0'; + VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin7_ipd, + TestSignalName => "MAin7", + Period => tperiod_MAin7, + PulseWidthHigh => tpw_MAin7_posedge, + PulseWidthLow => tpw_MAin7_negedge, + PeriodData => periodcheckinfo_MAin7, + Violation => tviol_MAin7_MAin7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin7_ipd'last_event, + PathDelay => tpd_MAin7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_6_B"; + + tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin6 : VitalDelayType := 0 ns; + tpw_MAin6_posedge : VitalDelayType := 0 ns; + tpw_MAin6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE; + + end MAin_6_B; + + architecture Structure of MAin_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin6_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_6: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin6_MAin6 : x01 := '0'; + VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin6_ipd, + TestSignalName => "MAin6", + Period => tperiod_MAin6, + PulseWidthHigh => tpw_MAin6_posedge, + PulseWidthLow => tpw_MAin6_negedge, + PeriodData => periodcheckinfo_MAin6, + Violation => tviol_MAin6_MAin6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin6_ipd'last_event, + PathDelay => tpd_MAin6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_5_B"; + + tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin5 : VitalDelayType := 0 ns; + tpw_MAin5_posedge : VitalDelayType := 0 ns; + tpw_MAin5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE; + + end MAin_5_B; + + architecture Structure of MAin_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin5_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_5: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin5_MAin5 : x01 := '0'; + VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin5_ipd, + TestSignalName => "MAin5", + Period => tperiod_MAin5, + PulseWidthHigh => tpw_MAin5_posedge, + PulseWidthLow => tpw_MAin5_negedge, + PeriodData => periodcheckinfo_MAin5, + Violation => tviol_MAin5_MAin5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin5_ipd'last_event, + PathDelay => tpd_MAin5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_4_B"; + + tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin4 : VitalDelayType := 0 ns; + tpw_MAin4_posedge : VitalDelayType := 0 ns; + tpw_MAin4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE; + + end MAin_4_B; + + architecture Structure of MAin_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin4_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_4: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin4_MAin4 : x01 := '0'; + VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin4_ipd, + TestSignalName => "MAin4", + Period => tperiod_MAin4, + PulseWidthHigh => tpw_MAin4_posedge, + PulseWidthLow => tpw_MAin4_negedge, + PeriodData => periodcheckinfo_MAin4, + Violation => tviol_MAin4_MAin4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin4_ipd'last_event, + PathDelay => tpd_MAin4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_3_B"; + + tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin3 : VitalDelayType := 0 ns; + tpw_MAin3_posedge : VitalDelayType := 0 ns; + tpw_MAin3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE; + + end MAin_3_B; + + architecture Structure of MAin_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin3_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_3: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin3_MAin3 : x01 := '0'; + VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin3_ipd, + TestSignalName => "MAin3", + Period => tperiod_MAin3, + PulseWidthHigh => tpw_MAin3_posedge, + PulseWidthLow => tpw_MAin3_negedge, + PeriodData => periodcheckinfo_MAin3, + Violation => tviol_MAin3_MAin3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin3_ipd'last_event, + PathDelay => tpd_MAin3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_2_B"; + + tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin2 : VitalDelayType := 0 ns; + tpw_MAin2_posedge : VitalDelayType := 0 ns; + tpw_MAin2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE; + + end MAin_2_B; + + architecture Structure of MAin_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin2_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_2: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin2_MAin2 : x01 := '0'; + VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin2_ipd, + TestSignalName => "MAin2", + Period => tperiod_MAin2, + PulseWidthHigh => tpw_MAin2_posedge, + PulseWidthLow => tpw_MAin2_negedge, + PeriodData => periodcheckinfo_MAin2, + Violation => tviol_MAin2_MAin2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin2_ipd'last_event, + PathDelay => tpd_MAin2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_1_B"; + + tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin1 : VitalDelayType := 0 ns; + tpw_MAin1_posedge : VitalDelayType := 0 ns; + tpw_MAin1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE; + + end MAin_1_B; + + architecture Structure of MAin_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin1_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_1: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin1_MAin1 : x01 := '0'; + VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin1_ipd, + TestSignalName => "MAin1", + Period => tperiod_MAin1, + PulseWidthHigh => tpw_MAin1_posedge, + PulseWidthLow => tpw_MAin1_negedge, + PeriodData => periodcheckinfo_MAin1, + Violation => tviol_MAin1_MAin1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin1_ipd'last_event, + PathDelay => tpd_MAin1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity MAin_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_0_B"; + + tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin0 : VitalDelayType := 0 ns; + tpw_MAin0_posedge : VitalDelayType := 0 ns; + tpw_MAin0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE; + + end MAin_0_B; + + architecture Structure of MAin_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin0_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_0: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>MAin0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin0_MAin0 : x01 := '0'; + VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin0_ipd, + TestSignalName => "MAin0", + Period => tperiod_MAin0, + PulseWidthHigh => tpw_MAin0_posedge, + PulseWidthLow => tpw_MAin0_negedge, + PeriodData => periodcheckinfo_MAin0, + Violation => tviol_MAin0_MAin0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin0_ipd'last_event, + PathDelay => tpd_MAin0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity CROW_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_1_B"; + + tipd_CROW1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW1 : VitalDelayType := 0 ns; + tpw_CROW1_posedge : VitalDelayType := 0 ns; + tpw_CROW1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE; + + end CROW_1_B; + + architecture Structure of CROW_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW1_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_1: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>CROW1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW1_CROW1 : x01 := '0'; + VARIABLE periodcheckinfo_CROW1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW1_ipd, + TestSignalName => "CROW1", + Period => tperiod_CROW1, + PulseWidthHigh => tpw_CROW1_posedge, + PulseWidthLow => tpw_CROW1_negedge, + PeriodData => periodcheckinfo_CROW1, + Violation => tviol_CROW1_CROW1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW1_ipd'last_event, + PathDelay => tpd_CROW1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity CROW_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_0_B"; + + tipd_CROW0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW0 : VitalDelayType := 0 ns; + tpw_CROW0_posedge : VitalDelayType := 0 ns; + tpw_CROW0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE; + + end CROW_0_B; + + architecture Structure of CROW_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW0_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_0: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>CROW0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW0_CROW0 : x01 := '0'; + VARIABLE periodcheckinfo_CROW0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW0_ipd, + TestSignalName => "CROW0", + Period => tperiod_CROW0, + PulseWidthHigh => tpw_CROW0_posedge, + PulseWidthLow => tpw_CROW0_negedge, + PeriodData => periodcheckinfo_CROW0, + Violation => tviol_CROW0_CROW0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW0_ipd'last_event, + PathDelay => tpd_CROW0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_7_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_7_B"; + + tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din7 : VitalDelayType := 0 ns; + tpw_Din7_posedge : VitalDelayType := 0 ns; + tpw_Din7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE; + + end Din_7_B; + + architecture Structure of Din_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din7_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_7: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din7_ipd, Din7, tipd_Din7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din7_Din7 : x01 := '0'; + VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din7_ipd, + TestSignalName => "Din7", + Period => tperiod_Din7, + PulseWidthHigh => tpw_Din7_posedge, + PulseWidthLow => tpw_Din7_negedge, + PeriodData => periodcheckinfo_Din7, + Violation => tviol_Din7_Din7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din7_ipd'last_event, + PathDelay => tpd_Din7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_6_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_6_B"; + + tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din6 : VitalDelayType := 0 ns; + tpw_Din6_posedge : VitalDelayType := 0 ns; + tpw_Din6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE; + + end Din_6_B; + + architecture Structure of Din_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din6_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_6: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din6_ipd, Din6, tipd_Din6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din6_Din6 : x01 := '0'; + VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din6_ipd, + TestSignalName => "Din6", + Period => tperiod_Din6, + PulseWidthHigh => tpw_Din6_posedge, + PulseWidthLow => tpw_Din6_negedge, + PeriodData => periodcheckinfo_Din6, + Violation => tviol_Din6_Din6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din6_ipd'last_event, + PathDelay => tpd_Din6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_5_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_5_B"; + + tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din5 : VitalDelayType := 0 ns; + tpw_Din5_posedge : VitalDelayType := 0 ns; + tpw_Din5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE; + + end Din_5_B; + + architecture Structure of Din_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din5_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_5: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din5_ipd, Din5, tipd_Din5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din5_Din5 : x01 := '0'; + VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din5_ipd, + TestSignalName => "Din5", + Period => tperiod_Din5, + PulseWidthHigh => tpw_Din5_posedge, + PulseWidthLow => tpw_Din5_negedge, + PeriodData => periodcheckinfo_Din5, + Violation => tviol_Din5_Din5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din5_ipd'last_event, + PathDelay => tpd_Din5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_4_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_4_B"; + + tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din4 : VitalDelayType := 0 ns; + tpw_Din4_posedge : VitalDelayType := 0 ns; + tpw_Din4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE; + + end Din_4_B; + + architecture Structure of Din_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din4_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_4: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din4_ipd, Din4, tipd_Din4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din4_Din4 : x01 := '0'; + VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din4_ipd, + TestSignalName => "Din4", + Period => tperiod_Din4, + PulseWidthHigh => tpw_Din4_posedge, + PulseWidthLow => tpw_Din4_negedge, + PeriodData => periodcheckinfo_Din4, + Violation => tviol_Din4_Din4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din4_ipd'last_event, + PathDelay => tpd_Din4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_3_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_3_B"; + + tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din3 : VitalDelayType := 0 ns; + tpw_Din3_posedge : VitalDelayType := 0 ns; + tpw_Din3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE; + + end Din_3_B; + + architecture Structure of Din_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din3_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_3: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din3_ipd, Din3, tipd_Din3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din3_Din3 : x01 := '0'; + VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din3_ipd, + TestSignalName => "Din3", + Period => tperiod_Din3, + PulseWidthHigh => tpw_Din3_posedge, + PulseWidthLow => tpw_Din3_negedge, + PeriodData => periodcheckinfo_Din3, + Violation => tviol_Din3_Din3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din3_ipd'last_event, + PathDelay => tpd_Din3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_2_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_2_B"; + + tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din2 : VitalDelayType := 0 ns; + tpw_Din2_posedge : VitalDelayType := 0 ns; + tpw_Din2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE; + + end Din_2_B; + + architecture Structure of Din_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din2_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_2: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din2_ipd, Din2, tipd_Din2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din2_Din2 : x01 := '0'; + VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din2_ipd, + TestSignalName => "Din2", + Period => tperiod_Din2, + PulseWidthHigh => tpw_Din2_posedge, + PulseWidthLow => tpw_Din2_negedge, + PeriodData => periodcheckinfo_Din2, + Violation => tviol_Din2_Din2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din2_ipd'last_event, + PathDelay => tpd_Din2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_1_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_1_B"; + + tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din1 : VitalDelayType := 0 ns; + tpw_Din1_posedge : VitalDelayType := 0 ns; + tpw_Din1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE; + + end Din_1_B; + + architecture Structure of Din_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din1_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_1: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din1_ipd, Din1, tipd_Din1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din1_Din1 : x01 := '0'; + VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din1_ipd, + TestSignalName => "Din1", + Period => tperiod_Din1, + PulseWidthHigh => tpw_Din1_posedge, + PulseWidthLow => tpw_Din1_negedge, + PeriodData => periodcheckinfo_Din1, + Violation => tviol_Din1_Din1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din1_ipd'last_event, + PathDelay => tpd_Din1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_0_B + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity Din_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_0_B"; + + tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din0 : VitalDelayType := 0 ns; + tpw_Din0_posedge : VitalDelayType := 0 ns; + tpw_Din0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE; + + end Din_0_B; + + architecture Structure of Din_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din0_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_0: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>Din0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din0_ipd, Din0, tipd_Din0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din0_Din0 : x01 := '0'; + VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din0_ipd, + TestSignalName => "Din0", + Period => tperiod_Din0, + PulseWidthHigh => tpw_Din0_posedge, + PulseWidthLow => tpw_Din0_negedge, + PeriodData => periodcheckinfo_Din0, + Violation => tviol_Din0_Din0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din0_ipd'last_event, + PathDelay => tpd_Din0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCCASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nCCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCCASB"; + + tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCCASS : VitalDelayType := 0 ns; + tpw_nCCASS_posedge : VitalDelayType := 0 ns; + tpw_nCCASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCCASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE; + + end nCCASB; + + architecture Structure of nCCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCCASS_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCCAS_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>nCCASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCCASS_nCCASS : x01 := '0'; + VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCCASS_ipd, + TestSignalName => "nCCASS", + Period => tperiod_nCCASS, + PulseWidthHigh => tpw_nCCASS_posedge, + PulseWidthLow => tpw_nCCASS_negedge, + PeriodData => periodcheckinfo_nCCASS, + Violation => tviol_nCCASS_nCCASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event, + PathDelay => tpd_nCCASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCRASB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nCRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCRASB"; + + tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCRASS : VitalDelayType := 0 ns; + tpw_nCRASS_posedge : VitalDelayType := 0 ns; + tpw_nCRASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCRASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE; + + end nCRASB; + + architecture Structure of nCRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCRASS_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCRAS_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>nCRASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCRASS_nCRASS : x01 := '0'; + VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCRASS_ipd, + TestSignalName => "nCRASS", + Period => tperiod_nCRASS, + PulseWidthHigh => tpw_nCRASS_posedge, + PulseWidthLow => tpw_nCRASS_negedge, + PeriodData => periodcheckinfo_nCRASS, + Violation => tviol_nCRASS_nCRASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event, + PathDelay => tpd_nCRASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nFWEB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity nFWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nFWEB"; + + tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns); + tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nFWES : VitalDelayType := 0 ns; + tpw_nFWES_posedge : VitalDelayType := 0 ns; + tpw_nFWES_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nFWES: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE; + + end nFWEB; + + architecture Structure of nFWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nFWES_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nFWE_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>nFWES_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nFWES_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nFWES_nFWES : x01 := '0'; + VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nFWES_ipd, + TestSignalName => "nFWES", + Period => tperiod_nFWES, + PulseWidthHigh => tpw_nFWES_posedge, + PulseWidthLow => tpw_nFWES_negedge, + PeriodData => periodcheckinfo_nFWES, + Violation => tviol_nFWES_nFWES, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nFWES_ipd'last_event, + PathDelay => tpd_nFWES_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCLKB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCLKB"; + + tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns); + tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RCLKS : VitalDelayType := 0 ns; + tpw_RCLKS_posedge : VitalDelayType := 0 ns; + tpw_RCLKS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; RCLKS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE; + + end RCLKB; + + architecture Structure of RCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal RCLKS_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + RCLK_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>RCLKS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RCLKS_RCLKS : x01 := '0'; + VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RCLKS_ipd, + TestSignalName => "RCLKS", + Period => tperiod_RCLKS, + PulseWidthHigh => tpw_RCLKS_posedge, + PulseWidthLow => tpw_RCLKS_negedge, + PeriodData => periodcheckinfo_RCLKS, + Violation => tviol_RCLKS_RCLKS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event, + PathDelay => tpd_RCLKS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDOB + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity UFMSDOB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDOB"; + + tipd_UFMSDOS : VitalDelayType01 := (0 ns, 0 ns); + tpd_UFMSDOS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_UFMSDOS : VitalDelayType := 0 ns; + tpw_UFMSDOS_posedge : VitalDelayType := 0 ns; + tpw_UFMSDOS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE; + + end UFMSDOB; + + architecture Structure of UFMSDOB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal UFMSDOS_ipd : std_logic := 'X'; + + component xo2iobuf0069 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + UFMSDO_pad: xo2iobuf0069 + port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_UFMSDOS_UFMSDOS : x01 := '0'; + VARIABLE periodcheckinfo_UFMSDOS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => UFMSDOS_ipd, + TestSignalName => "UFMSDOS", + Period => tperiod_UFMSDOS, + PulseWidthHigh => tpw_UFMSDOS_posedge, + PulseWidthLow => tpw_UFMSDOS_negedge, + PeriodData => periodcheckinfo_UFMSDOS, + Violation => tviol_UFMSDOS_UFMSDOS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => UFMSDOS_ipd'last_event, + PathDelay => tpd_UFMSDOS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RAM2GS + library IEEE, vital2000, MACHXO2; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO2.COMPONENTS.ALL; + + entity RAM2GS is + port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); + CROW: in Std_logic_vector (1 downto 0); + Din: in Std_logic_vector (7 downto 0); + Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; + nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; + RBA: out Std_logic_vector (1 downto 0); + RA: out Std_logic_vector (11 downto 0); + RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; + RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; + nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; + RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; + UFMSDI: out Std_logic; UFMSDO: in Std_logic); + + + + end RAM2GS; + + architecture Structure of RAM2GS is + signal FS_14: Std_logic; + signal FS_13: Std_logic; + signal n81: Std_logic; + signal n82: Std_logic; + signal RCLK_c: Std_logic; + signal n1998: Std_logic; + signal n1999: Std_logic; + signal FS_12: Std_logic; + signal FS_11: Std_logic; + signal n83: Std_logic; + signal n84: Std_logic; + signal n1997: Std_logic; + signal FS_8: Std_logic; + signal FS_7: Std_logic; + signal n87: Std_logic; + signal n88: Std_logic; + signal n1995: Std_logic; + signal n1996: Std_logic; + signal FS_6: Std_logic; + signal FS_5: Std_logic; + signal n89: Std_logic; + signal n90: Std_logic; + signal n1994: Std_logic; + signal FS_2: Std_logic; + signal FS_1: Std_logic; + signal n93: Std_logic; + signal n94: Std_logic; + signal n1992: Std_logic; + signal n1993: Std_logic; + signal FS_0: Std_logic; + signal n95: Std_logic; + signal CASr2: Std_logic; + signal CASr3: Std_logic; + signal FS_10: Std_logic; + signal FS_9: Std_logic; + signal n85: Std_logic; + signal n86: Std_logic; + signal FS_17: Std_logic; + signal n78: Std_logic; + signal n2000: Std_logic; + signal FS_4: Std_logic; + signal FS_3: Std_logic; + signal n91: Std_logic; + signal n92: Std_logic; + signal FS_16: Std_logic; + signal FS_15: Std_logic; + signal n79: Std_logic; + signal n80: Std_logic; + signal Din_c_4: Std_logic; + signal Din_c_6: Std_logic; + signal Din_c_1: Std_logic; + signal Din_c_7: Std_logic; + signal n2382: Std_logic; + signal n8: Std_logic; + signal n2225: Std_logic; + signal n2180: Std_logic; + signal ADSubmitted_N_246: Std_logic; + signal PHI2_N_120_enable_2: Std_logic; + signal C1Submitted_N_237: Std_logic; + signal PHI2_c: Std_logic; + signal ADSubmitted: Std_logic; + signal n26: Std_logic; + signal MAin_c_5: Std_logic; + signal n22: Std_logic; + signal MAin_c_2: Std_logic; + signal MAin_c_1: Std_logic; + signal C1Submitted: Std_logic; + signal n2365: Std_logic; + signal nFWE_c: Std_logic; + signal n1398: Std_logic; + signal nCCAS_c: Std_logic; + signal nCCAS_N_3: Std_logic; + signal CASr: Std_logic; + signal n2254: Std_logic; + signal Din_c_5: Std_logic; + signal n2191: Std_logic; + signal n2183: Std_logic; + signal n15_adj_1: Std_logic; + signal n2208: Std_logic; + signal n2363: Std_logic; + signal CmdEnable_N_248: Std_logic; + signal PHI2_N_120_enable_1: Std_logic; + signal CmdEnable: Std_logic; + signal n2447_001_BUF1: Std_logic; + signal PHI2_N_120_enable_7: Std_logic; + signal CmdSubmitted: Std_logic; + signal n1314: Std_logic; + signal n8MEGEN: Std_logic; + signal Din_c_0: Std_logic; + signal Cmdn8MEGEN_N_264: Std_logic; + signal PHI2_N_120_enable_6: Std_logic; + signal Cmdn8MEGEN: Std_logic; + signal Din_c_3: Std_logic; + signal n2373: Std_logic; + signal nCRAS_c: Std_logic; + signal FWEr: Std_logic; + signal CBR: Std_logic; + signal n2447_000_BUF1: Std_logic; + signal RCLK_c_enable_28: Std_logic; + signal InitReady: Std_logic; + signal n2447: Std_logic; + signal RCLK_c_enable_16: Std_logic; + signal LEDEN: Std_logic; + signal nCRAS_c_inv: Std_logic; + signal RASr: Std_logic; + signal LED_c: Std_logic; + signal RASr2: Std_logic; + signal nRowColSel_N_35: Std_logic; + signal nRCAS_N_165: Std_logic; + signal Ready: Std_logic; + signal n2381: Std_logic; + signal nRCS_N_139: Std_logic; + signal n2036: Std_logic; + signal nRWE_N_177: Std_logic; + signal RA_0S: Std_logic; + signal XOR8MEG: Std_logic; + signal RA11_N_184: Std_logic; + signal RA_c: Std_logic; + signal n6_adj_2: Std_logic; + signal PHI2r2: Std_logic; + signal PHI2r3: Std_logic; + signal n15_adj_4: Std_logic; + signal RCKEEN_N_121: Std_logic; + signal RCLK_c_enable_6: Std_logic; + signal RCKEEN: Std_logic; + signal RCLK_c_enable_10: Std_logic; + signal RASr3: Std_logic; + signal RCKE_N_132: Std_logic; + signal PHI2r: Std_logic; + signal RCKE_c: Std_logic; + signal n2447_002_BUF1: Std_logic; + signal Ready_N_292: Std_logic; + signal n2267: Std_logic; + signal n13_adj_6: Std_logic; + signal CmdUFMCLK: Std_logic; + signal n1893: Std_logic; + signal UFMCLK_N_224: Std_logic; + signal n2366: Std_logic; + signal UFMCLK_c: Std_logic; + signal n10: Std_logic; + signal n7: Std_logic; + signal n4: Std_logic; + signal CmdUFMSDI: Std_logic; + signal n2174: Std_logic; + signal UFMSDI_N_231: Std_logic; + signal UFMSDI_c: Std_logic; + signal n2260: Std_logic; + signal Din_c_2: Std_logic; + signal XOR8MEG_N_110: Std_logic; + signal PHI2_N_120_enable_3: Std_logic; + signal n2375: Std_logic; + signal UFMSDO_c: Std_logic; + signal n2367: Std_logic; + signal n8MEGEN_N_91: Std_logic; + signal RCLK_c_enable_15: Std_logic; + signal nRCS_N_142: Std_logic; + signal nRCAS_N_166: Std_logic; + signal n2371: Std_logic; + signal nRCAS_N_161: Std_logic; + signal nRCAS_c: Std_logic; + signal nRCS_N_141: Std_logic; + signal nRCS_N_137: Std_logic; + signal nRCS_N_136: Std_logic; + signal nRCS_c: Std_logic; + signal n2379: Std_logic; + signal nRRAS_N_156: Std_logic; + signal nRRAS_c: Std_logic; + signal nRWE_N_178: Std_logic; + signal n1765: Std_logic; + signal nRWE_N_171: Std_logic; + signal RCLK_c_enable_5: Std_logic; + signal nRWE_c: Std_logic; + signal nRowColSel_N_34: Std_logic; + signal nRowColSel_N_33: Std_logic; + signal n2376: Std_logic; + signal n1060: Std_logic; + signal n2372: Std_logic; + signal n917: Std_logic; + signal nRowColSel: Std_logic; + signal nRowColSel_N_32: Std_logic; + signal n827: Std_logic; + signal n2227: Std_logic; + signal n1406: Std_logic; + signal Bank_3: Std_logic; + signal Bank_6: Std_logic; + signal n2287: Std_logic; + signal n13: Std_logic; + signal n2374: Std_logic; + signal n2368: Std_logic; + signal CmdUFMCS: Std_logic; + signal n64: Std_logic; + signal nUFMCS_N_199: Std_logic; + signal nUFMCS_c: Std_logic; + signal n6_adj_3: Std_logic; + signal Ready_N_296: Std_logic; + signal n2204: Std_logic; + signal n2369: Std_logic; + signal MAin_c_0: Std_logic; + signal PHI2_N_120_enable_8: Std_logic; + signal Bank_5: Std_logic; + signal n2277: Std_logic; + signal Bank_2: Std_logic; + signal n2220: Std_logic; + signal RowA_0: Std_logic; + signal RowA_1: Std_logic; + signal n2370: Std_logic; + signal n2228: Std_logic; + signal n732: Std_logic; + signal n733: Std_logic; + signal RCLK_c_enable_27: Std_logic; + signal n2055: Std_logic; + signal MAin_c_9: Std_logic; + signal MAin_c_8: Std_logic; + signal RowA_8: Std_logic; + signal RowA_9: Std_logic; + signal n2210: Std_logic; + signal nRWE_N_182: Std_logic; + signal nRCS_N_146: Std_logic; + signal n728: Std_logic; + signal n729: Std_logic; + signal n727: Std_logic; + signal n730: Std_logic; + signal n2378: Std_logic; + signal n726: Std_logic; + signal n12: Std_logic; + signal MAin_c_4: Std_logic; + signal RowA_4: Std_logic; + signal RowA_5: Std_logic; + signal n1277: Std_logic; + signal n4_adj_7: Std_logic; + signal n2377: Std_logic; + signal n738: Std_logic; + signal n737: Std_logic; + signal n14: Std_logic; + signal n15: Std_logic; + signal n6: Std_logic; + signal CROW_c_1: Std_logic; + signal CROW_c_0: Std_logic; + signal RBA_c_0: Std_logic; + signal RBA_c_1: Std_logic; + signal n7_adj_5: Std_logic; + signal n2362: Std_logic; + signal WRD_6: Std_logic; + signal WRD_7: Std_logic; + signal WRD_4: Std_logic; + signal WRD_5: Std_logic; + signal WRD_0: Std_logic; + signal WRD_1: Std_logic; + signal MAin_c_3: Std_logic; + signal RowA_2: Std_logic; + signal RowA_3: Std_logic; + signal WRD_2: Std_logic; + signal WRD_3: Std_logic; + signal RA_1_9: Std_logic; + signal Bank_0: Std_logic; + signal RDQML_c: Std_logic; + signal Bank_1: Std_logic; + signal n734: Std_logic; + signal n735: Std_logic; + signal RA_1_8: Std_logic; + signal RDQMH_c: Std_logic; + signal Bank_4: Std_logic; + signal MAin_c_7: Std_logic; + signal RowA_7: Std_logic; + signal RA_1_7: Std_logic; + signal Bank_7: Std_logic; + signal MAin_c_6: Std_logic; + signal RowA_6: Std_logic; + signal RA_1_6: Std_logic; + signal RA_1_5: Std_logic; + signal RA_1_0: Std_logic; + signal RA_1_4: Std_logic; + signal RA_1_1: Std_logic; + signal RA_1_3: Std_logic; + signal RA_1_2: Std_logic; + signal n984: Std_logic; + signal n736: Std_logic; + signal Dout_c: Std_logic; + signal Dout_0S: Std_logic; + signal Dout_1S: Std_logic; + signal Dout_2S: Std_logic; + signal Dout_3S: Std_logic; + signal Dout_4S: Std_logic; + signal Dout_5S: Std_logic; + signal Dout_6S: Std_logic; + signal VCCI: Std_logic; + component SLICE_0 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_1 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_2 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_3 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_4 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_5 + port (A1: in Std_logic; DI1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_6 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_7 + port (A0: in Std_logic; DI0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_8 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_9 + port (A1: in Std_logic; A0: in Std_logic; DI1: in Std_logic; + DI0: in Std_logic; CLK: in Std_logic; FCI: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_10 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_15 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_16 + port (A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_19 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_20 + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_24 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_25 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_26 + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_27 + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_30 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_32 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_33 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_35 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_36 + port (D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M1: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_37 + port (DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_44 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_45 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_50 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_57 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_59 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_61 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_62 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_64 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_65 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_66 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_67 + port (B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic); + end component; + component SLICE_68 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_69 + port (B1: in Std_logic; A1: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_70 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component i30_SLICE_71 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + end component; + component SLICE_72 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_73 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_74 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_75 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_76 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_77 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_78 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_79 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_80 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_81 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_82 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_83 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_84 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_85 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_86 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_87 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_88 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_89 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_90 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_91 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_92 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_93 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_94 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_95 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; F0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_96 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_97 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_98 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_99 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_100 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_101 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_102 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_103 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_104 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_105 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_106 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component RD_7_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD7: inout Std_logic); + end component; + component RD_6_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD6: inout Std_logic); + end component; + component RD_5_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD5: inout Std_logic); + end component; + component RD_4_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD4: inout Std_logic); + end component; + component RD_3_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD3: inout Std_logic); + end component; + component RD_2_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD2: inout Std_logic); + end component; + component RD_1_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD1: inout Std_logic); + end component; + component RD_0_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD0: inout Std_logic); + end component; + component Dout_7_B + port (PADDO: in Std_logic; Dout7: out Std_logic); + end component; + component Dout_6_B + port (PADDO: in Std_logic; Dout6: out Std_logic); + end component; + component Dout_5_B + port (PADDO: in Std_logic; Dout5: out Std_logic); + end component; + component Dout_4_B + port (PADDO: in Std_logic; Dout4: out Std_logic); + end component; + component Dout_3_B + port (PADDO: in Std_logic; Dout3: out Std_logic); + end component; + component Dout_2_B + port (PADDO: in Std_logic; Dout2: out Std_logic); + end component; + component Dout_1_B + port (PADDO: in Std_logic; Dout1: out Std_logic); + end component; + component Dout_0_B + port (PADDO: in Std_logic; Dout0: out Std_logic); + end component; + component LEDB + port (PADDO: in Std_logic; LEDS: out Std_logic); + end component; + component RBA_1_B + port (PADDO: in Std_logic; RBA1: out Std_logic); + end component; + component RBA_0_B + port (PADDO: in Std_logic; RBA0: out Std_logic); + end component; + component RA_11_B + port (PADDO: in Std_logic; RA11: out Std_logic); + end component; + component RA_10_B + port (PADDO: in Std_logic; RA10: out Std_logic); + end component; + component RA_9_B + port (PADDO: in Std_logic; RA9: out Std_logic); + end component; + component RA_8_B + port (PADDO: in Std_logic; RA8: out Std_logic); + end component; + component RA_7_B + port (PADDO: in Std_logic; RA7: out Std_logic); + end component; + component RA_6_B + port (PADDO: in Std_logic; RA6: out Std_logic); + end component; + component RA_5_B + port (PADDO: in Std_logic; RA5: out Std_logic); + end component; + component RA_4_B + port (PADDO: in Std_logic; RA4: out Std_logic); + end component; + component RA_3_B + port (PADDO: in Std_logic; RA3: out Std_logic); + end component; + component RA_2_B + port (PADDO: in Std_logic; RA2: out Std_logic); + end component; + component RA_1_B + port (PADDO: in Std_logic; RA1: out Std_logic); + end component; + component RA_0_B + port (PADDO: in Std_logic; RA0: out Std_logic); + end component; + component nRCSB + port (PADDO: in Std_logic; nRCSS: out Std_logic); + end component; + component RCKEB + port (PADDO: in Std_logic; RCKES: out Std_logic); + end component; + component nRWEB + port (PADDO: in Std_logic; nRWES: out Std_logic); + end component; + component nRRASB + port (PADDO: in Std_logic; nRRASS: out Std_logic); + end component; + component nRCASB + port (PADDO: in Std_logic; nRCASS: out Std_logic); + end component; + component RDQMHB + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + end component; + component RDQMLB + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + end component; + component nUFMCSB + port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + end component; + component UFMCLKB + port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + end component; + component UFMSDIB + port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + end component; + component PHI2B + port (PADDI: out Std_logic; PHI2S: in Std_logic); + end component; + component MAin_9_B + port (PADDI: out Std_logic; MAin9: in Std_logic); + end component; + component MAin_8_B + port (PADDI: out Std_logic; MAin8: in Std_logic); + end component; + component MAin_7_B + port (PADDI: out Std_logic; MAin7: in Std_logic); + end component; + component MAin_6_B + port (PADDI: out Std_logic; MAin6: in Std_logic); + end component; + component MAin_5_B + port (PADDI: out Std_logic; MAin5: in Std_logic); + end component; + component MAin_4_B + port (PADDI: out Std_logic; MAin4: in Std_logic); + end component; + component MAin_3_B + port (PADDI: out Std_logic; MAin3: in Std_logic); + end component; + component MAin_2_B + port (PADDI: out Std_logic; MAin2: in Std_logic); + end component; + component MAin_1_B + port (PADDI: out Std_logic; MAin1: in Std_logic); + end component; + component MAin_0_B + port (PADDI: out Std_logic; MAin0: in Std_logic); + end component; + component CROW_1_B + port (PADDI: out Std_logic; CROW1: in Std_logic); + end component; + component CROW_0_B + port (PADDI: out Std_logic; CROW0: in Std_logic); + end component; + component Din_7_B + port (PADDI: out Std_logic; Din7: in Std_logic); + end component; + component Din_6_B + port (PADDI: out Std_logic; Din6: in Std_logic); + end component; + component Din_5_B + port (PADDI: out Std_logic; Din5: in Std_logic); + end component; + component Din_4_B + port (PADDI: out Std_logic; Din4: in Std_logic); + end component; + component Din_3_B + port (PADDI: out Std_logic; Din3: in Std_logic); + end component; + component Din_2_B + port (PADDI: out Std_logic; Din2: in Std_logic); + end component; + component Din_1_B + port (PADDI: out Std_logic; Din1: in Std_logic); + end component; + component Din_0_B + port (PADDI: out Std_logic; Din0: in Std_logic); + end component; + component nCCASB + port (PADDI: out Std_logic; nCCASS: in Std_logic); + end component; + component nCRASB + port (PADDI: out Std_logic; nCRASS: in Std_logic); + end component; + component nFWEB + port (PADDI: out Std_logic; nFWES: in Std_logic); + end component; + component RCLKB + port (PADDI: out Std_logic; RCLKS: in Std_logic); + end component; + component UFMSDOB + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + end component; + begin + SLICE_0I: SLICE_0 + port map (A1=>FS_14, A0=>FS_13, DI1=>n81, DI0=>n82, CLK=>RCLK_c, + FCI=>n1998, F0=>n82, Q0=>FS_13, F1=>n81, Q1=>FS_14, FCO=>n1999); + SLICE_1I: SLICE_1 + port map (A1=>FS_12, A0=>FS_11, DI1=>n83, DI0=>n84, CLK=>RCLK_c, + FCI=>n1997, F0=>n84, Q0=>FS_11, F1=>n83, Q1=>FS_12, FCO=>n1998); + SLICE_2I: SLICE_2 + port map (A1=>FS_8, A0=>FS_7, DI1=>n87, DI0=>n88, CLK=>RCLK_c, + FCI=>n1995, F0=>n88, Q0=>FS_7, F1=>n87, Q1=>FS_8, FCO=>n1996); + SLICE_3I: SLICE_3 + port map (A1=>FS_6, A0=>FS_5, DI1=>n89, DI0=>n90, CLK=>RCLK_c, + FCI=>n1994, F0=>n90, Q0=>FS_5, F1=>n89, Q1=>FS_6, FCO=>n1995); + SLICE_4I: SLICE_4 + port map (A1=>FS_2, A0=>FS_1, DI1=>n93, DI0=>n94, CLK=>RCLK_c, + FCI=>n1992, F0=>n94, Q0=>FS_1, F1=>n93, Q1=>FS_2, FCO=>n1993); + SLICE_5I: SLICE_5 + port map (A1=>FS_0, DI1=>n95, M0=>CASr2, CLK=>RCLK_c, Q0=>CASr3, F1=>n95, + Q1=>FS_0, FCO=>n1992); + SLICE_6I: SLICE_6 + port map (A1=>FS_10, A0=>FS_9, DI1=>n85, DI0=>n86, CLK=>RCLK_c, + FCI=>n1996, F0=>n86, Q0=>FS_9, F1=>n85, Q1=>FS_10, FCO=>n1997); + SLICE_7I: SLICE_7 + port map (A0=>FS_17, DI0=>n78, CLK=>RCLK_c, FCI=>n2000, F0=>n78, + Q0=>FS_17); + SLICE_8I: SLICE_8 + port map (A1=>FS_4, A0=>FS_3, DI1=>n91, DI0=>n92, CLK=>RCLK_c, + FCI=>n1993, F0=>n92, Q0=>FS_3, F1=>n91, Q1=>FS_4, FCO=>n1994); + SLICE_9I: SLICE_9 + port map (A1=>FS_16, A0=>FS_15, DI1=>n79, DI0=>n80, CLK=>RCLK_c, + FCI=>n1999, F0=>n80, Q0=>FS_15, F1=>n79, Q1=>FS_16, FCO=>n2000); + SLICE_10I: SLICE_10 + port map (D1=>Din_c_4, C1=>Din_c_6, B1=>Din_c_1, A1=>Din_c_7, D0=>n2382, + C0=>n8, B0=>n2225, A0=>n2180, DI0=>ADSubmitted_N_246, + CE=>PHI2_N_120_enable_2, LSR=>C1Submitted_N_237, CLK=>PHI2_c, + F0=>ADSubmitted_N_246, Q0=>ADSubmitted, F1=>n8); + SLICE_15I: SLICE_15 + port map (D1=>n26, C1=>MAin_c_5, B1=>n22, A1=>MAin_c_2, D0=>MAin_c_1, + C0=>C1Submitted, B0=>n2365, A0=>nFWE_c, DI0=>n1398, + LSR=>C1Submitted_N_237, CLK=>PHI2_c, F0=>n1398, + Q0=>C1Submitted, F1=>n2365); + SLICE_16I: SLICE_16 + port map (A0=>nCCAS_c, DI0=>nCCAS_N_3, M1=>CASr, CLK=>RCLK_c, + F0=>nCCAS_N_3, Q0=>CASr, Q1=>CASr2); + SLICE_19I: SLICE_19 + port map (D1=>n2254, C1=>Din_c_5, B1=>n2191, A1=>n2183, D0=>n15_adj_1, + C0=>n2208, B0=>MAin_c_1, A0=>n2363, DI0=>CmdEnable_N_248, + CE=>PHI2_N_120_enable_1, CLK=>PHI2_c, F0=>CmdEnable_N_248, + Q0=>CmdEnable, F1=>n15_adj_1); + SLICE_20I: SLICE_20 + port map (DI0=>n2447_001_BUF1, CE=>PHI2_N_120_enable_7, CLK=>PHI2_c, + F0=>n2447_001_BUF1, Q0=>CmdSubmitted); + SLICE_24I: SLICE_24 + port map (C1=>Din_c_5, B1=>Din_c_7, A1=>Din_c_6, D0=>n1314, C0=>Din_c_4, + B0=>n8MEGEN, A0=>Din_c_0, DI0=>Cmdn8MEGEN_N_264, + CE=>PHI2_N_120_enable_6, CLK=>PHI2_c, F0=>Cmdn8MEGEN_N_264, + Q0=>Cmdn8MEGEN, F1=>n1314); + SLICE_25I: SLICE_25 + port map (C1=>Din_c_3, B1=>Din_c_5, A1=>nFWE_c, A0=>nFWE_c, DI0=>n2373, + M1=>nCCAS_N_3, CLK=>nCRAS_c, F0=>n2373, Q0=>FWEr, F1=>n2180, + Q1=>CBR); + SLICE_26I: SLICE_26 + port map (DI0=>n2447_000_BUF1, CE=>RCLK_c_enable_28, CLK=>RCLK_c, + F0=>n2447_000_BUF1, Q0=>InitReady); + SLICE_27I: SLICE_27 + port map (DI0=>n2447, CE=>RCLK_c_enable_16, CLK=>RCLK_c, F0=>n2447, + Q0=>LEDEN); + SLICE_30I: SLICE_30 + port map (C1=>CBR, B1=>LEDEN, A1=>nCRAS_c, A0=>nCRAS_c, DI0=>nCRAS_c_inv, + M1=>RASr, CLK=>RCLK_c, F0=>nCRAS_c_inv, Q0=>RASr, F1=>LED_c, + Q1=>RASr2); + SLICE_32I: SLICE_32 + port map (C1=>nRowColSel_N_35, B1=>InitReady, A1=>RASr2, D0=>nRCAS_N_165, + C0=>Ready, B0=>n2381, A0=>nRCS_N_139, DI0=>n2036, + LSR=>nRWE_N_177, CLK=>RCLK_c, F0=>n2036, Q0=>RA_0S, F1=>n2381); + SLICE_33I: SLICE_33 + port map (C1=>Din_c_4, B1=>Din_c_7, A1=>Din_c_6, C0=>n8MEGEN, + B0=>XOR8MEG, A0=>Din_c_6, DI0=>RA11_N_184, LSR=>Ready, + CLK=>PHI2_c, F0=>RA11_N_184, Q0=>RA_c, F1=>n6_adj_2); + SLICE_35I: SLICE_35 + port map (D1=>InitReady, C1=>CmdSubmitted, B1=>PHI2r2, A1=>PHI2r3, + C0=>Ready, B0=>n15_adj_4, A0=>InitReady, DI0=>RCKEEN_N_121, + CE=>RCLK_c_enable_6, CLK=>RCLK_c, F0=>RCKEEN_N_121, Q0=>RCKEEN, + F1=>RCLK_c_enable_10); + SLICE_36I: SLICE_36 + port map (D0=>RASr3, C0=>RASr2, B0=>RCKEEN, A0=>RASr, DI0=>RCKE_N_132, + M1=>PHI2r, CLK=>RCLK_c, F0=>RCKE_N_132, Q0=>RCKE_c, Q1=>PHI2r2); + SLICE_37I: SLICE_37 + port map (DI0=>n2447_002_BUF1, CE=>Ready_N_292, CLK=>RCLK_c, + F0=>n2447_002_BUF1, Q0=>Ready); + SLICE_44I: SLICE_44 + port map (D1=>FS_1, C1=>n2267, B1=>n13_adj_6, A1=>FS_4, C0=>InitReady, + B0=>CmdUFMCLK, A0=>n1893, DI0=>UFMCLK_N_224, + CE=>RCLK_c_enable_10, LSR=>n2366, CLK=>RCLK_c, + F0=>UFMCLK_N_224, Q0=>UFMCLK_c, F1=>n1893); + SLICE_45I: SLICE_45 + port map (D1=>n10, C1=>FS_10, B1=>FS_8, A1=>n7, D0=>n4, C0=>InitReady, + B0=>CmdUFMSDI, A0=>n2174, DI0=>UFMSDI_N_231, + CE=>RCLK_c_enable_10, LSR=>n2366, CLK=>RCLK_c, + F0=>UFMSDI_N_231, Q0=>UFMSDI_c, F1=>n2174); + SLICE_50I: SLICE_50 + port map (D1=>LEDEN, C1=>n1314, B1=>Din_c_1, A1=>Din_c_4, D0=>Din_c_3, + C0=>n2260, B0=>Din_c_2, A0=>Din_c_0, DI0=>XOR8MEG_N_110, + CE=>PHI2_N_120_enable_3, CLK=>PHI2_c, F0=>XOR8MEG_N_110, + Q0=>XOR8MEG, F1=>n2260); + SLICE_57I: SLICE_57 + port map (D1=>FS_10, C1=>FS_11, B1=>n2375, A1=>n10, D0=>Cmdn8MEGEN, + C0=>UFMSDO_c, B0=>n2367, A0=>InitReady, DI0=>n8MEGEN_N_91, + CE=>RCLK_c_enable_15, CLK=>RCLK_c, F0=>n8MEGEN_N_91, + Q0=>n8MEGEN, F1=>n2367); + SLICE_59I: SLICE_59 + port map (D1=>CBR, C1=>nRowColSel_N_35, B1=>RASr2, A1=>nRCS_N_142, + D0=>nRCAS_N_166, C0=>Ready, B0=>nRCAS_N_165, A0=>n2371, + DI0=>nRCAS_N_161, CE=>RCLK_c_enable_6, CLK=>RCLK_c, + F0=>nRCAS_N_161, Q0=>nRCAS_c, F1=>nRCAS_N_166); + SLICE_61I: SLICE_61 + port map (D1=>nRCS_N_142, C1=>nRowColSel_N_35, B1=>RASr2, A1=>RCKE_c, + C0=>Ready, B0=>nRCS_N_141, A0=>nRCS_N_137, DI0=>nRCS_N_136, + CE=>RCLK_c_enable_6, CLK=>RCLK_c, F0=>nRCS_N_136, Q0=>nRCS_c, + F1=>nRCS_N_141); + SLICE_62I: SLICE_62 + port map (D1=>RASr2, C1=>nRowColSel_N_35, B1=>InitReady, A1=>nRCS_N_139, + D0=>nRowColSel_N_35, C0=>Ready, B0=>n2379, A0=>nRCS_N_137, + DI0=>nRRAS_N_156, CE=>RCLK_c_enable_6, CLK=>RCLK_c, + F0=>nRRAS_N_156, Q0=>nRRAS_c, F1=>nRCS_N_137); + SLICE_64I: SLICE_64 + port map (B1=>nRCAS_N_165, A1=>nRWE_N_177, D0=>n2371, C0=>Ready, + B0=>nRWE_N_178, A0=>n1765, DI0=>nRWE_N_171, + CE=>RCLK_c_enable_5, CLK=>RCLK_c, F0=>nRWE_N_171, Q0=>nRWE_c, + F1=>n1765); + SLICE_65I: SLICE_65 + port map (B1=>nRowColSel_N_34, A1=>nRowColSel_N_33, D0=>n2376, C0=>n1060, + B0=>n2372, A0=>FWEr, DI0=>n917, CE=>RCLK_c_enable_5, + CLK=>RCLK_c, F0=>n917, Q0=>nRowColSel, F1=>n1060); + SLICE_66I: SLICE_66 + port map (B1=>CASr2, A1=>nRowColSel_N_33, B0=>nRowColSel_N_32, + A0=>nRowColSel_N_33, DI0=>n827, LSR=>RASr2, CLK=>RCLK_c, + F0=>n827, Q0=>nRowColSel_N_32, F1=>n2227); + SLICE_67I: SLICE_67 + port map (B0=>nRowColSel_N_32, A0=>RASr2, DI0=>n1406, + LSR=>nRowColSel_N_34, CLK=>RCLK_c, F0=>n1406, + Q0=>nRowColSel_N_33); + SLICE_68I: SLICE_68 + port map (B1=>FS_0, A1=>FS_8, B0=>Bank_3, A0=>Bank_6, M0=>n1406, + LSR=>nRowColSel_N_35, CLK=>RCLK_c, F0=>n2287, + Q0=>nRowColSel_N_34, F1=>n13); + SLICE_69I: SLICE_69 + port map (B1=>RASr2, A1=>RCKE_c, A0=>RASr2, DI0=>n2374, M1=>PHI2r2, + CLK=>RCLK_c, F0=>n2374, Q0=>nRowColSel_N_35, F1=>n2379, + Q1=>PHI2r3); + SLICE_70I: SLICE_70 + port map (D1=>FS_10, C1=>InitReady, B1=>n2368, A1=>FS_11, D0=>InitReady, + C0=>CmdUFMCS, B0=>n64, A0=>n13_adj_6, DI0=>nUFMCS_N_199, + CE=>RCLK_c_enable_10, CLK=>RCLK_c, F0=>nUFMCS_N_199, + Q0=>nUFMCS_c, F1=>n64); + i30_SLICE_71I: i30_SLICE_71 + port map (C1=>RASr2, B1=>FWEr, A1=>CBR, D0=>nRowColSel_N_34, C0=>FWEr, + B0=>n2227, A0=>CBR, M0=>nRowColSel_N_35, OFX0=>n15_adj_4); + SLICE_72I: SLICE_72 + port map (D1=>Ready, C1=>nRowColSel_N_32, B1=>n6_adj_3, A1=>RASr2, + B0=>Ready_N_296, A0=>InitReady, F0=>n6_adj_3, F1=>Ready_N_292); + SLICE_73I: SLICE_73 + port map (D1=>n2204, C1=>n2180, B1=>n26, A1=>n2369, D0=>n6_adj_2, + C0=>CmdEnable, B0=>MAin_c_0, A0=>MAin_c_1, F0=>n2204, + F1=>PHI2_N_120_enable_8); + SLICE_74I: SLICE_74 + port map (D1=>Bank_5, C1=>n2287, B1=>n2277, A1=>Bank_2, D0=>nFWE_c, + C0=>n2204, B0=>n26, A0=>n2369, M1=>MAin_c_1, M0=>MAin_c_0, + LSR=>Ready, CLK=>nCRAS_c, F0=>n2220, Q0=>RowA_0, F1=>n26, + Q1=>RowA_1); + SLICE_75I: SLICE_75 + port map (D1=>n2370, C1=>n2183, B1=>n2228, A1=>Din_c_5, B0=>Din_c_3, + A0=>Din_c_6, M1=>n732, M0=>n733, CE=>RCLK_c_enable_27, + CLK=>RCLK_c, F0=>n2183, Q0=>n732, F1=>n2055, Q1=>nRWE_N_177); + SLICE_76I: SLICE_76 + port map (C1=>n10, B1=>FS_14, A1=>FS_12, D0=>InitReady, C0=>n2368, + B0=>FS_11, A0=>FS_10, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready, + CLK=>nCRAS_c, F0=>RCLK_c_enable_16, Q0=>RowA_8, F1=>n2368, + Q1=>RowA_9); + SLICE_77I: SLICE_77 + port map (D1=>n2208, C1=>C1Submitted, B1=>n2191, A1=>Din_c_5, + D0=>MAin_c_0, C0=>Din_c_6, B0=>Din_c_3, A0=>Din_c_2, F0=>n2191, + F1=>n2210); + SLICE_78I: SLICE_78 + port map (D1=>nRowColSel_N_35, C1=>nRWE_N_182, B1=>n1060, A1=>nRCS_N_146, + B0=>RASr2, A0=>RCKE_c, M1=>n728, M0=>n729, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>nRWE_N_182, Q0=>n728, + F1=>nRWE_N_178, Q1=>n727); + SLICE_79I: SLICE_79 + port map (C1=>MAin_c_5, B1=>n22, A1=>MAin_c_2, D0=>MAin_c_1, C0=>nFWE_c, + B0=>n26, A0=>n2369, M1=>n730, M0=>nRWE_N_177, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>PHI2_N_120_enable_2, + Q0=>n730, F1=>n2369, Q1=>n729); + SLICE_80I: SLICE_80 + port map (B1=>FS_14, A1=>FS_12, D0=>FS_11, C0=>InitReady, B0=>n2375, + A0=>n10, F0=>n2366, F1=>n2375); + SLICE_81I: SLICE_81 + port map (B1=>CBR, A1=>FWEr, D0=>nRowColSel_N_33, C0=>n2378, + B0=>nRowColSel_N_34, A0=>nRCS_N_146, M1=>n726, M0=>n727, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>nRCS_N_142, Q0=>n726, + F1=>n2378, Q1=>Ready_N_296); + SLICE_82I: SLICE_82 + port map (D1=>FS_17, C1=>FS_14, B1=>n12, A1=>FS_11, B0=>n13_adj_6, + A0=>FS_10, M1=>MAin_c_5, M0=>MAin_c_4, LSR=>Ready, + CLK=>nCRAS_c, F0=>RCLK_c_enable_28, Q0=>RowA_4, F1=>n13_adj_6, + Q1=>RowA_5); + SLICE_83I: SLICE_83 + port map (D1=>n1314, C1=>n1277, B1=>CmdEnable, A1=>n2228, D0=>MAin_c_1, + C0=>MAin_c_0, B0=>n26, A0=>n2369, F0=>n1277, + F1=>PHI2_N_120_enable_3); + SLICE_84I: SLICE_84 + port map (C1=>CmdSubmitted, B1=>PHI2r2, A1=>PHI2r3, D0=>n4_adj_7, + C0=>InitReady, B0=>n2377, A0=>n2367, M1=>n738, M0=>nRCAS_N_165, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>RCLK_c_enable_15, + Q0=>n738, F1=>n2377, Q1=>n737); + SLICE_85I: SLICE_85 + port map (D1=>n10, C1=>FS_11, B1=>FS_14, A1=>FS_12, D0=>FS_16, C0=>FS_15, + B0=>FS_13, A0=>FS_17, F0=>n10, F1=>n2267); + SLICE_86I: SLICE_86 + port map (C1=>FS_6, B1=>FS_9, A1=>FS_3, D0=>n14, C0=>n13, B0=>n15, + A0=>FS_4, M1=>RASr2, M0=>PHI2_c, CLK=>RCLK_c, F0=>n4_adj_7, + Q0=>PHI2r, F1=>n14, Q1=>RASr3); + SLICE_87I: SLICE_87 + port map (D1=>n6, C1=>nRowColSel_N_32, B1=>nRowColSel_N_33, + A1=>nRowColSel_N_35, B0=>nRowColSel_N_34, A0=>Ready, + M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready, CLK=>nCRAS_c, F0=>n6, + Q0=>RBA_c_0, F1=>RCLK_c_enable_6, Q1=>RBA_c_1); + SLICE_88I: SLICE_88 + port map (D1=>n2363, C1=>C1Submitted_N_237, B1=>ADSubmitted, + A1=>n7_adj_5, D0=>n2362, C0=>MAin_c_0, B0=>n2055, A0=>Din_c_2, + M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, F0=>C1Submitted_N_237, + Q0=>WRD_6, F1=>PHI2_N_120_enable_1, Q1=>WRD_7); + SLICE_89I: SLICE_89 + port map (D1=>Din_c_5, C1=>Din_c_3, B1=>Din_c_4, A1=>n2220, D0=>Din_c_3, + C0=>Din_c_4, B0=>n2220, A0=>Din_c_5, M1=>Din_c_5, M0=>Din_c_4, + CLK=>nCCAS_c, F0=>PHI2_N_120_enable_6, Q0=>WRD_4, + F1=>PHI2_N_120_enable_7, Q1=>WRD_5); + SLICE_90I: SLICE_90 + port map (D1=>Din_c_0, C1=>Din_c_4, B1=>Din_c_1, A1=>Din_c_7, + C0=>Din_c_0, B0=>Din_c_1, A0=>Din_c_7, M1=>Din_c_1, + M0=>Din_c_0, CLK=>nCCAS_c, F0=>n2370, Q0=>WRD_0, F1=>n2208, + Q1=>WRD_1); + SLICE_91I: SLICE_91 + port map (C1=>MAin_c_1, B1=>n26, A1=>n2369, D0=>MAin_c_1, C0=>MAin_c_0, + B0=>n26, A0=>n2369, M1=>MAin_c_3, M0=>MAin_c_2, LSR=>Ready, + CLK=>nCRAS_c, F0=>n2225, Q0=>RowA_2, F1=>n2362, Q1=>RowA_3); + SLICE_92I: SLICE_92 + port map (D1=>Ready, C1=>nRowColSel_N_35, B1=>InitReady, A1=>RASr2, + D0=>nRCS_N_139, C0=>nRowColSel_N_35, B0=>InitReady, A0=>RASr2, + M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, F0=>n2371, Q0=>WRD_2, + F1=>RCLK_c_enable_27, Q1=>WRD_3); + SLICE_93I: SLICE_93 + port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>MAin_c_9, + A0=>RowA_9, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, F0=>RA_1_9, + Q0=>Bank_0, F1=>RDQML_c, Q1=>Bank_1); + SLICE_94I: SLICE_94 + port map (B1=>nRowColSel_N_35, A1=>Ready, D0=>nRowColSel_N_35, + C0=>nRowColSel_N_32, B0=>n1060, A0=>Ready, F0=>RCLK_c_enable_5, + F1=>n2372); + SLICE_95I: SLICE_95 + port map (D1=>FS_5, C1=>FS_9, B1=>FS_7, A1=>n2375, D0=>FS_2, C0=>FS_1, + B0=>FS_7, A0=>FS_5, F0=>n15, F1=>n7); + SLICE_96I: SLICE_96 + port map (B1=>CASr3, A1=>CBR, D0=>CASr2, C0=>FWEr, B0=>CASr3, A0=>CBR, + F0=>nRCS_N_146, F1=>n2376); + SLICE_97I: SLICE_97 + port map (C1=>MAin_c_1, B1=>n2210, A1=>MAin_c_0, B0=>Din_c_2, + A0=>MAin_c_0, M1=>n734, M0=>n735, CE=>RCLK_c_enable_27, + CLK=>RCLK_c, F0=>n2254, Q0=>n734, F1=>n7_adj_5, Q1=>n733); + SLICE_98I: SLICE_98 + port map (B1=>nRowColSel, A1=>MAin_c_9, C0=>nRowColSel, B0=>MAin_c_8, + A0=>RowA_8, M1=>nRCS_N_139, M0=>Ready_N_296, + CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>RA_1_8, Q0=>nRCS_N_139, + F1=>RDQMH_c, Q1=>nRCAS_N_165); + SLICE_99I: SLICE_99 + port map (D1=>Bank_1, C1=>Bank_4, B1=>MAin_c_3, A1=>MAin_c_7, + C0=>nRowColSel, B0=>MAin_c_7, A0=>RowA_7, M0=>Din_c_0, + CE=>PHI2_N_120_enable_8, CLK=>PHI2_c, F0=>RA_1_7, + Q0=>CmdUFMSDI, F1=>n22); + SLICE_100I: SLICE_100 + port map (D1=>Bank_0, C1=>Bank_7, B1=>MAin_c_4, A1=>MAin_c_6, + C0=>nRowColSel, B0=>MAin_c_6, A0=>RowA_6, M1=>Din_c_2, + M0=>Din_c_1, CE=>PHI2_N_120_enable_8, CLK=>PHI2_c, F0=>RA_1_6, + Q0=>CmdUFMCLK, F1=>n2277, Q1=>CmdUFMCS); + SLICE_101I: SLICE_101 + port map (C1=>nRowColSel, B1=>MAin_c_0, A1=>RowA_0, C0=>nRowColSel, + B0=>MAin_c_5, A0=>RowA_5, M1=>Din_c_7, M0=>Din_c_6, + CLK=>PHI2_c, F0=>RA_1_5, Q0=>Bank_6, F1=>RA_1_0, Q1=>Bank_7); + SLICE_102I: SLICE_102 + port map (C1=>nRowColSel, B1=>MAin_c_1, A1=>RowA_1, C0=>nRowColSel, + B0=>MAin_c_4, A0=>RowA_4, M1=>Din_c_5, M0=>Din_c_4, + CLK=>PHI2_c, F0=>RA_1_4, Q0=>Bank_4, F1=>RA_1_1, Q1=>Bank_5); + SLICE_103I: SLICE_103 + port map (C1=>nRowColSel, B1=>MAin_c_2, A1=>RowA_2, C0=>nRowColSel, + B0=>MAin_c_3, A0=>RowA_3, M1=>Din_c_3, M0=>Din_c_2, + CLK=>PHI2_c, F0=>RA_1_3, Q0=>Bank_2, F1=>RA_1_2, Q1=>Bank_3); + SLICE_104I: SLICE_104 + port map (B1=>nFWE_c, A1=>nCCAS_c, C0=>nFWE_c, B0=>n26, A0=>n2369, + M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready, CLK=>nCRAS_c, + F0=>n2363, Q0=>RowA_6, F1=>n984, Q1=>RowA_7); + SLICE_105I: SLICE_105 + port map (B1=>FS_6, A1=>FS_11, D0=>FS_16, C0=>FS_15, B0=>FS_12, + A0=>FS_13, F0=>n12, F1=>n4); + SLICE_106I: SLICE_106 + port map (B1=>Din_c_2, A1=>Din_c_0, B0=>Din_c_4, A0=>nFWE_c, M1=>n736, + M0=>n737, CE=>RCLK_c_enable_27, CLK=>RCLK_c, F0=>n2228, + Q0=>n736, F1=>n2382, Q1=>n735); + RD_7_I: RD_7_B + port map (PADDI=>Dout_c, PADDT=>n984, PADDO=>WRD_7, RD7=>RD(7)); + RD_6_I: RD_6_B + port map (PADDI=>Dout_0S, PADDT=>n984, PADDO=>WRD_6, RD6=>RD(6)); + RD_5_I: RD_5_B + port map (PADDI=>Dout_1S, PADDT=>n984, PADDO=>WRD_5, RD5=>RD(5)); + RD_4_I: RD_4_B + port map (PADDI=>Dout_2S, PADDT=>n984, PADDO=>WRD_4, RD4=>RD(4)); + RD_3_I: RD_3_B + port map (PADDI=>Dout_3S, PADDT=>n984, PADDO=>WRD_3, RD3=>RD(3)); + RD_2_I: RD_2_B + port map (PADDI=>Dout_4S, PADDT=>n984, PADDO=>WRD_2, RD2=>RD(2)); + RD_1_I: RD_1_B + port map (PADDI=>Dout_5S, PADDT=>n984, PADDO=>WRD_1, RD1=>RD(1)); + RD_0_I: RD_0_B + port map (PADDI=>Dout_6S, PADDT=>n984, PADDO=>WRD_0, RD0=>RD(0)); + Dout_7_I: Dout_7_B + port map (PADDO=>Dout_c, Dout7=>Dout(7)); + Dout_6_I: Dout_6_B + port map (PADDO=>Dout_0S, Dout6=>Dout(6)); + Dout_5_I: Dout_5_B + port map (PADDO=>Dout_1S, Dout5=>Dout(5)); + Dout_4_I: Dout_4_B + port map (PADDO=>Dout_2S, Dout4=>Dout(4)); + Dout_3_I: Dout_3_B + port map (PADDO=>Dout_3S, Dout3=>Dout(3)); + Dout_2_I: Dout_2_B + port map (PADDO=>Dout_4S, Dout2=>Dout(2)); + Dout_1_I: Dout_1_B + port map (PADDO=>Dout_5S, Dout1=>Dout(1)); + Dout_0_I: Dout_0_B + port map (PADDO=>Dout_6S, Dout0=>Dout(0)); + LEDI: LEDB + port map (PADDO=>LED_c, LEDS=>LED); + RBA_1_I: RBA_1_B + port map (PADDO=>RBA_c_1, RBA1=>RBA(1)); + RBA_0_I: RBA_0_B + port map (PADDO=>RBA_c_0, RBA0=>RBA(0)); + RA_11_I: RA_11_B + port map (PADDO=>RA_c, RA11=>RA(11)); + RA_10_I: RA_10_B + port map (PADDO=>RA_0S, RA10=>RA(10)); + RA_9_I: RA_9_B + port map (PADDO=>RA_1_9, RA9=>RA(9)); + RA_8_I: RA_8_B + port map (PADDO=>RA_1_8, RA8=>RA(8)); + RA_7_I: RA_7_B + port map (PADDO=>RA_1_7, RA7=>RA(7)); + RA_6_I: RA_6_B + port map (PADDO=>RA_1_6, RA6=>RA(6)); + RA_5_I: RA_5_B + port map (PADDO=>RA_1_5, RA5=>RA(5)); + RA_4_I: RA_4_B + port map (PADDO=>RA_1_4, RA4=>RA(4)); + RA_3_I: RA_3_B + port map (PADDO=>RA_1_3, RA3=>RA(3)); + RA_2_I: RA_2_B + port map (PADDO=>RA_1_2, RA2=>RA(2)); + RA_1_I: RA_1_B + port map (PADDO=>RA_1_1, RA1=>RA(1)); + RA_0_I: RA_0_B + port map (PADDO=>RA_1_0, RA0=>RA(0)); + nRCSI: nRCSB + port map (PADDO=>nRCS_c, nRCSS=>nRCS); + RCKEI: RCKEB + port map (PADDO=>RCKE_c, RCKES=>RCKE); + nRWEI: nRWEB + port map (PADDO=>nRWE_c, nRWES=>nRWE); + nRRASI: nRRASB + port map (PADDO=>nRRAS_c, nRRASS=>nRRAS); + nRCASI: nRCASB + port map (PADDO=>nRCAS_c, nRCASS=>nRCAS); + RDQMHI: RDQMHB + port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH); + RDQMLI: RDQMLB + port map (PADDO=>RDQML_c, RDQMLS=>RDQML); + nUFMCSI: nUFMCSB + port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS); + UFMCLKI: UFMCLKB + port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK); + UFMSDII: UFMSDIB + port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI); + PHI2I: PHI2B + port map (PADDI=>PHI2_c, PHI2S=>PHI2); + MAin_9_I: MAin_9_B + port map (PADDI=>MAin_c_9, MAin9=>MAin(9)); + MAin_8_I: MAin_8_B + port map (PADDI=>MAin_c_8, MAin8=>MAin(8)); + MAin_7_I: MAin_7_B + port map (PADDI=>MAin_c_7, MAin7=>MAin(7)); + MAin_6_I: MAin_6_B + port map (PADDI=>MAin_c_6, MAin6=>MAin(6)); + MAin_5_I: MAin_5_B + port map (PADDI=>MAin_c_5, MAin5=>MAin(5)); + MAin_4_I: MAin_4_B + port map (PADDI=>MAin_c_4, MAin4=>MAin(4)); + MAin_3_I: MAin_3_B + port map (PADDI=>MAin_c_3, MAin3=>MAin(3)); + MAin_2_I: MAin_2_B + port map (PADDI=>MAin_c_2, MAin2=>MAin(2)); + MAin_1_I: MAin_1_B + port map (PADDI=>MAin_c_1, MAin1=>MAin(1)); + MAin_0_I: MAin_0_B + port map (PADDI=>MAin_c_0, MAin0=>MAin(0)); + CROW_1_I: CROW_1_B + port map (PADDI=>CROW_c_1, CROW1=>CROW(1)); + CROW_0_I: CROW_0_B + port map (PADDI=>CROW_c_0, CROW0=>CROW(0)); + Din_7_I: Din_7_B + port map (PADDI=>Din_c_7, Din7=>Din(7)); + Din_6_I: Din_6_B + port map (PADDI=>Din_c_6, Din6=>Din(6)); + Din_5_I: Din_5_B + port map (PADDI=>Din_c_5, Din5=>Din(5)); + Din_4_I: Din_4_B + port map (PADDI=>Din_c_4, Din4=>Din(4)); + Din_3_I: Din_3_B + port map (PADDI=>Din_c_3, Din3=>Din(3)); + Din_2_I: Din_2_B + port map (PADDI=>Din_c_2, Din2=>Din(2)); + Din_1_I: Din_1_B + port map (PADDI=>Din_c_1, Din1=>Din(1)); + Din_0_I: Din_0_B + port map (PADDI=>Din_c_0, Din0=>Din(0)); + nCCASI: nCCASB + port map (PADDI=>nCCAS_c, nCCASS=>nCCAS); + nCRASI: nCRASB + port map (PADDI=>nCRAS_c, nCRASS=>nCRAS); + nFWEI: nFWEB + port map (PADDI=>nFWE_c, nFWES=>nFWE); + RCLKI: RCLKB + port map (PADDI=>RCLK_c, RCLKS=>RCLK); + UFMSDOI: UFMSDOB + port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO); + VHI_INST: VHI + port map (Z=>VCCI); + PUR_INST: PUR + port map (PUR=>VCCI); + GSR_INST: GSR + port map (GSR=>VCCI); + end Structure; + + + + library IEEE, vital2000, MACHXO2; + configuration Structure_CON of RAM2GS is + for Structure + end for; + end Structure_CON; + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf new file mode 100644 index 0000000..76a02d9 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf @@ -0,0 +1,3176 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Tue Aug 15 05:03:26 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_10") + (INSTANCE SLICE_10) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_15") + (INSTANCE SLICE_15) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_16") + (INSTANCE SLICE_16) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_20") + (INSTANCE SLICE_20) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_24") + (INSTANCE SLICE_24) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_25") + (INSTANCE SLICE_25) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_26") + (INSTANCE SLICE_26) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_27") + (INSTANCE SLICE_27) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_30") + (INSTANCE SLICE_30) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_33") + (INSTANCE SLICE_33) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_35") + (INSTANCE SLICE_35) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_36") + (INSTANCE SLICE_36) + (DELAY + (ABSOLUTE + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_37") + (INSTANCE SLICE_37) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_45") + (INSTANCE SLICE_45) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_50") + (INSTANCE SLICE_50) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_57") + (INSTANCE SLICE_57) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_59") + (INSTANCE SLICE_59) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_61") + (INSTANCE SLICE_61) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_62") + (INSTANCE SLICE_62) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_64") + (INSTANCE SLICE_64) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_65") + (INSTANCE SLICE_65) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_66") + (INSTANCE SLICE_66) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_67") + (INSTANCE SLICE_67) + (DELAY + (ABSOLUTE + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_68") + (INSTANCE SLICE_68) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_69") + (INSTANCE SLICE_69) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_70") + (INSTANCE SLICE_70) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "i30_SLICE_71") + (INSTANCE i30\/SLICE_71) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (457:589:721)(457:589:721)) + (IOPATH B1 OFX0 (457:589:721)(457:589:721)) + (IOPATH A1 OFX0 (457:589:721)(457:589:721)) + (IOPATH D0 OFX0 (457:589:721)(457:589:721)) + (IOPATH C0 OFX0 (457:589:721)(457:589:721)) + (IOPATH B0 OFX0 (457:589:721)(457:589:721)) + (IOPATH A0 OFX0 (457:589:721)(457:589:721)) + (IOPATH M0 OFX0 (322:349:376)(322:349:376)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_72") + (INSTANCE SLICE_72) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_73") + (INSTANCE SLICE_73) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_74") + (INSTANCE SLICE_74) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_75") + (INSTANCE SLICE_75) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_76") + (INSTANCE SLICE_76) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_80") + (INSTANCE SLICE_80) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_81") + (INSTANCE SLICE_81) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_84") + (INSTANCE SLICE_84) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_85") + (INSTANCE SLICE_85) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + ) + ) + (CELL + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (negedge CLK) (247:277:307)(-116:-104:-92)) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_102") + (INSTANCE SLICE_102) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_103") + (INSTANCE SLICE_103) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_104") + (INSTANCE SLICE_104) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (negedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD LSR (negedge CLK) (236:260:285)(-236:-194:-152)) + ) + ) + (CELL + (CELLTYPE "SLICE_105") + (INSTANCE SLICE_105) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_106") + (INSTANCE SLICE_106) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD M0 (posedge CLK) (256:302:348)(-105:-71:-37)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_7_") + (INSTANCE RD\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD7 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD7 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD7) (3330:3330:3330)) + (WIDTH (negedge RD7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_6_") + (INSTANCE RD\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD6 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD6 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD6) (3330:3330:3330)) + (WIDTH (negedge RD6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_5_") + (INSTANCE RD\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD5 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD5 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD5) (3330:3330:3330)) + (WIDTH (negedge RD5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_4_") + (INSTANCE RD\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD4 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD4 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD4) (3330:3330:3330)) + (WIDTH (negedge RD4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_3_") + (INSTANCE RD\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD3 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD3 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD3) (3330:3330:3330)) + (WIDTH (negedge RD3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_2_") + (INSTANCE RD\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD2 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD2 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD2) (3330:3330:3330)) + (WIDTH (negedge RD2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_1_") + (INSTANCE RD\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD1 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD1 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD1) (3330:3330:3330)) + (WIDTH (negedge RD1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RD_0_") + (INSTANCE RD\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD0 (2349:3502:4656)(2349:3502:4656)(2349:3502:4656)(2349:3502:4656) + (2349:3502:4656)(2349:3502:4656)) + (IOPATH PADDO RD0 (3220:3334:3448)(3220:3334:3448)) + (IOPATH RD0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD0) (3330:3330:3330)) + (WIDTH (negedge RD0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Dout_7_") + (INSTANCE Dout\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout7 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_6_") + (INSTANCE Dout\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout6 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_5_") + (INSTANCE Dout\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout5 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_4_") + (INSTANCE Dout\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout4 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_3_") + (INSTANCE Dout\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout3 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_2_") + (INSTANCE Dout\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout2 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1_") + (INSTANCE Dout\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0_") + (INSTANCE Dout\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "LED") + (INSTANCE LED_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO LED (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_") + (INSTANCE RBA\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_0_") + (INSTANCE RBA\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_11_") + (INSTANCE RA\[11\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA11 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_10_") + (INSTANCE RA\[10\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA10 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_9_") + (INSTANCE RA\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA9 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_8_") + (INSTANCE RA\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA8 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_7_") + (INSTANCE RA\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA7 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_6_") + (INSTANCE RA\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA6 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_5_") + (INSTANCE RA\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA5 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_4_") + (INSTANCE RA\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA4 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_3_") + (INSTANCE RA\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA3 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_2_") + (INSTANCE RA\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA2 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_1_") + (INSTANCE RA\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA1 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RA_0_") + (INSTANCE RA\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA0 (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRCS") + (INSTANCE nRCS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RCKE") + (INSTANCE RCKE_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RCKE (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRWE") + (INSTANCE nRWE_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRWE (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRRAS") + (INSTANCE nRRAS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRRAS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nRCAS") + (INSTANCE nRCAS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCAS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMH") + (INSTANCE RDQMH_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMH (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "RDQML") + (INSTANCE RDQML_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQML (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "nUFMCS") + (INSTANCE nUFMCS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nUFMCS (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "UFMCLK") + (INSTANCE UFMCLK_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMCLK (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "UFMSDI") + (INSTANCE UFMSDI_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMSDI (3220:3334:3448)(3220:3334:3448)) + ) + ) + ) + (CELL + (CELLTYPE "PHI2") + (INSTANCE PHI2_I) + (DELAY + (ABSOLUTE + (IOPATH PHI2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI2) (3330:3330:3330)) + (WIDTH (negedge PHI2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_9_") + (INSTANCE MAin\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (3330:3330:3330)) + (WIDTH (negedge MAin9) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_8_") + (INSTANCE MAin\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (3330:3330:3330)) + (WIDTH (negedge MAin8) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_7_") + (INSTANCE MAin\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (3330:3330:3330)) + (WIDTH (negedge MAin7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_6_") + (INSTANCE MAin\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (3330:3330:3330)) + (WIDTH (negedge MAin6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_5_") + (INSTANCE MAin\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (3330:3330:3330)) + (WIDTH (negedge MAin5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_4_") + (INSTANCE MAin\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (3330:3330:3330)) + (WIDTH (negedge MAin4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_3_") + (INSTANCE MAin\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (3330:3330:3330)) + (WIDTH (negedge MAin3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_2_") + (INSTANCE MAin\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (3330:3330:3330)) + (WIDTH (negedge MAin2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_1_") + (INSTANCE MAin\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (3330:3330:3330)) + (WIDTH (negedge MAin1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "MAin_0_") + (INSTANCE MAin\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (3330:3330:3330)) + (WIDTH (negedge MAin0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "CROW_1_") + (INSTANCE CROW\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (3330:3330:3330)) + (WIDTH (negedge CROW1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "CROW_0_") + (INSTANCE CROW\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (3330:3330:3330)) + (WIDTH (negedge CROW0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_7_") + (INSTANCE Din\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (3330:3330:3330)) + (WIDTH (negedge Din7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_6_") + (INSTANCE Din\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (3330:3330:3330)) + (WIDTH (negedge Din6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_5_") + (INSTANCE Din\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (3330:3330:3330)) + (WIDTH (negedge Din5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_4_") + (INSTANCE Din\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (3330:3330:3330)) + (WIDTH (negedge Din4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_3_") + (INSTANCE Din\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (3330:3330:3330)) + (WIDTH (negedge Din3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_2_") + (INSTANCE Din\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (3330:3330:3330)) + (WIDTH (negedge Din2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_1_") + (INSTANCE Din\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (3330:3330:3330)) + (WIDTH (negedge Din1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_0_") + (INSTANCE Din\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (3330:3330:3330)) + (WIDTH (negedge Din0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nCCAS") + (INSTANCE nCCAS_I) + (DELAY + (ABSOLUTE + (IOPATH nCCAS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCCAS) (3330:3330:3330)) + (WIDTH (negedge nCCAS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nCRAS") + (INSTANCE nCRAS_I) + (DELAY + (ABSOLUTE + (IOPATH nCRAS PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCRAS) (3330:3330:3330)) + (WIDTH (negedge nCRAS) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nFWE") + (INSTANCE nFWE_I) + (DELAY + (ABSOLUTE + (IOPATH nFWE PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nFWE) (3330:3330:3330)) + (WIDTH (negedge nFWE) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RCLK") + (INSTANCE RCLK_I) + (DELAY + (ABSOLUTE + (IOPATH RCLK PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RCLK) (3330:3330:3330)) + (WIDTH (negedge RCLK) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "UFMSDO") + (INSTANCE UFMSDO_I) + (DELAY + (ABSOLUTE + (IOPATH UFMSDO PADDI (1223:1297:1372)(1223:1297:1372)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge UFMSDO) (3330:3330:3330)) + (WIDTH (negedge UFMSDO) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_76/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_80/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_82/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_85/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_85/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_105/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/F0 SLICE_0/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_16/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_27/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_30/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_35/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_37/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_45/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_57/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_59/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_61/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_62/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_65/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_66/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_67/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_68/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_69/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_70/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_75/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_78/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_79/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_81/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_84/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_86/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_97/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_98/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_106/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/FCO SLICE_0/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/FCO SLICE_9/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_76/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_80/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_85/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_105/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_57/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_70/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_76/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_80/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_82/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_85/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_105/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/F1 SLICE_1/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/FCO SLICE_1/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_45/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_68/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_95/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_95/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/FCO SLICE_6/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_86/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_105/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_95/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_95/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/FCO SLICE_3/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_95/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_44/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_95/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/F1 SLICE_4/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/F0 SLICE_4/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/FCO SLICE_8/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_68/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/F1 SLICE_5/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q1 SLICE_5/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q1 SLICE_66/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q1 SLICE_96/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_96/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_96/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_45/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_57/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_70/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_76/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_82/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_86/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_95/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/F1 SLICE_6/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/F0 SLICE_6/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_82/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_85/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/F0 SLICE_7/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/FCO SLICE_7/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_44/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_86/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_86/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/F1 SLICE_8/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/F0 SLICE_8/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q1 SLICE_9/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q1 SLICE_85/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q1 SLICE_105/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 SLICE_9/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 SLICE_85/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 SLICE_105/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F1 SLICE_9/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_10/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_24/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_33/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_50/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_89/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_89/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_89/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_90/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_102/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_106/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_10/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_24/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_33/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_33/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_75/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_77/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_88/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_101/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_10/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_50/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_90/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_90/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_90/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_93/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_100/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_10/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_24/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_33/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_88/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_90/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_90/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_101/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/F1 SLICE_10/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10/F1 SLICE_10/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F0 SLICE_10/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_10/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_73/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10/F0 SLICE_10/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F0 SLICE_10/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_10/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_15/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_88/C1 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_10/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_15/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_20/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_24/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_33/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_50/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_86/M0 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_93/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_99/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_100/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_101/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_102/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_103/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_10/Q0 SLICE_88/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_15/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_73/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_74/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_79/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_83/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_91/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_91/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_104/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_15/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_79/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_82/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_101/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F1 SLICE_15/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F1 SLICE_79/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_15/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_79/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_91/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_103/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_15/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_19/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_73/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_74/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_79/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_83/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_91/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_97/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_102/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15/Q0 SLICE_15/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15/Q0 SLICE_77/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15/F1 SLICE_15/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_15/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_25/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_25/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_74/D0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_79/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_104/B1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_104/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_106/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_15/F0 SLICE_15/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_16/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_88/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_89/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_90/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_92/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_104/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/F0 SLICE_16/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/F0 SLICE_25/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_16/Q0 SLICE_16/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F0 SLICE_19/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_19/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_24/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_25/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_75/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_77/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_89/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_89/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_89/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_102/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F0 SLICE_19/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F0 SLICE_77/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_19/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_75/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F1 SLICE_19/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F1 SLICE_19/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F1 SLICE_77/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F0 SLICE_19/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F0 SLICE_88/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F1 SLICE_19/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_73/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_83/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20/F0 SLICE_20/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F1 SLICE_20/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20/Q0 SLICE_35/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_20/Q0 SLICE_84/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F1 SLICE_24/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F1 SLICE_50/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F1 SLICE_83/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/Q0 SLICE_24/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/Q0 SLICE_33/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_24/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_50/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_90/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_90/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_90/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_93/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_99/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_106/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/F0 SLICE_24/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F0 SLICE_24/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_24/Q0 SLICE_57/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_25/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_50/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_75/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_77/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_89/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_89/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_92/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_103/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_25/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_30/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_30/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_74/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_76/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_82/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_87/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_91/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_104/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_65/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 i30\/SLICE_71/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 i30\/SLICE_71/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_81/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_96/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_30/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_59/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 i30\/SLICE_71/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 i30\/SLICE_71/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_81/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_96/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q1 SLICE_96/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F0 SLICE_26/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_32/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_35/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_35/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_44/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_45/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_57/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_62/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_70/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_70/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_72/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_76/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_80/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_84/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_92/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_92/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27/F0 SLICE_27/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F0 SLICE_27/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27/Q0 SLICE_30/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_27/Q0 SLICE_50/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q0 SLICE_30/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q0 SLICE_36/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/F1 LED_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_32/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_36/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_59/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_61/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_62/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_66/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_67/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_69/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_69/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 i30\/SLICE_71/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_72/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_78/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_86/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_92/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_30/Q1 SLICE_92/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_32/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_59/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_61/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_62/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_62/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_68/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 i30\/SLICE_71/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_78/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_87/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_92/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_92/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_94/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_94/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_32/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_59/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_64/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_84/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_32/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_33/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_35/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_59/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_61/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_62/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_64/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_72/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_74/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_76/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_82/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_87/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_87/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_91/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_92/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_94/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_94/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/Q0 SLICE_104/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/F1 SLICE_32/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_32/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_62/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_92/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_98/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q1 SLICE_32/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q1 SLICE_64/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q1 SLICE_79/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/Q0 RA\[10\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50/Q0 SLICE_33/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33/Q0 RA\[11\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_33/F1 SLICE_73/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q1 SLICE_35/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q1 SLICE_69/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q1 SLICE_84/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q1 SLICE_35/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q1 SLICE_84/A1 (0:0:0)(0:0:0)) + (INTERCONNECT i30\/SLICE_71/OFX0 SLICE_35/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F0 SLICE_35/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_35/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_59/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_61/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_62/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q0 SLICE_36/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F1 SLICE_44/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F1 SLICE_45/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F1 SLICE_70/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/Q1 SLICE_36/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/F0 SLICE_36/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/Q0 SLICE_36/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_61/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_69/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_78/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 RCKE_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_37/F0 SLICE_37/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_72/F1 SLICE_37/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F1 SLICE_44/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_44/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_70/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_82/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/Q0 SLICE_44/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F1 SLICE_44/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F0 SLICE_44/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F0 SLICE_45/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 UFMCLK_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_45/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_57/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_76/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_80/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_85/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F1 SLICE_45/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 SLICE_45/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/Q0 SLICE_45/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45/F1 SLICE_45/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45/F0 SLICE_45/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_45/Q0 UFMSDI_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50/F1 SLICE_50/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_50/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_77/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_88/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_92/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_97/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_100/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_103/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_106/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_50/F0 SLICE_50/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F1 SLICE_50/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_57/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_80/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_95/A1 (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDO_I/PADDI SLICE_57/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/F1 SLICE_57/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/F1 SLICE_84/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_57/F0 SLICE_57/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F0 SLICE_57/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_59/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_61/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59/F1 SLICE_59/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F0 SLICE_59/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F0 SLICE_64/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59/F0 SLICE_59/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59/Q0 nRCAS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/F1 SLICE_61/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F1 SLICE_61/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F1 SLICE_62/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/F0 SLICE_61/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/Q0 nRCS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_62/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F0 SLICE_62/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/Q0 nRRAS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_64/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F1 SLICE_64/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F0 SLICE_64/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F0 SLICE_64/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F0 SLICE_65/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 nRWE_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_65/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_67/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 i30\/SLICE_71/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_81/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_87/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_65/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_66/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_66/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_81/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_87/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F1 SLICE_65/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_65/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_78/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_94/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_65/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F0 SLICE_65/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_93/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_93/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_98/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_98/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_99/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_100/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_101/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_101/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_102/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_102/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_103/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_103/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_66/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_67/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_72/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_87/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_94/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F0 SLICE_66/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 i30\/SLICE_71/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F0 SLICE_67/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F0 SLICE_68/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/Q1 SLICE_68/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/Q0 SLICE_68/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F0 SLICE_74/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F1 SLICE_86/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F0 SLICE_69/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_70/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_76/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/Q1 SLICE_70/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70/F1 SLICE_70/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70/F0 SLICE_70/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70/Q0 nUFMCS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_72/F0 SLICE_72/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q1 SLICE_72/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q1 SLICE_98/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F0 SLICE_73/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F0 SLICE_74/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_73/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_74/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_79/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_83/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_91/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_91/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_104/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_73/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_74/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_77/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_83/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_88/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_91/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_97/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_97/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_101/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F1 SLICE_99/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F1 SLICE_100/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/Q1 SLICE_74/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 SLICE_74/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/Q0 SLICE_74/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F0 SLICE_89/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F0 SLICE_89/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_101/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q1 SLICE_102/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F0 SLICE_75/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/F0 SLICE_75/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/F0 SLICE_83/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/Q0 SLICE_75/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/Q1 SLICE_75/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_75/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_78/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_79/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_81/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_84/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_97/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_98/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_106/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F1 SLICE_88/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_76/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_93/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_93/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_98/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_76/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_98/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q0 SLICE_98/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_93/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_97/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F0 SLICE_78/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F0 SLICE_78/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F0 SLICE_81/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/Q0 SLICE_78/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_78/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/Q1 SLICE_81/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q0 SLICE_79/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F1 SLICE_81/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q0 SLICE_81/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F0 SLICE_82/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_82/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_100/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_102/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q0 SLICE_102/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q1 SLICE_101/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F0 SLICE_83/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F0 SLICE_84/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F1 SLICE_84/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q0 SLICE_84/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q1 SLICE_106/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_86/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F0 SLICE_86/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F0 SLICE_87/D1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_87/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_87/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 RBA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 RBA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F1 SLICE_88/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F1 SLICE_88/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/Q0 RD\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/Q1 RD\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q0 RD\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q1 RD\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q0 RD\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q1 RD\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_91/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_99/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_103/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q0 SLICE_103/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q1 SLICE_103/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/Q0 RD\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/Q1 RD\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F0 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/Q0 SLICE_100/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/Q1 SLICE_99/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/Q0 SLICE_97/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/Q1 SLICE_97/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F1 RDQMH_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/Q0 SLICE_99/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_99/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_99/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_104/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/Q1 SLICE_99/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F0 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/Q1 SLICE_100/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_100/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_100/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_104/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/Q0 SLICE_100/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 RA\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F0 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F1 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F0 RA\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F1 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F0 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F1 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[7\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[6\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[5\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[4\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[3\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[2\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[1\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 RD\[0\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_106/Q0 SLICE_106/M1 (0:0:0)(0:0:0)) + (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo new file mode 100644 index 0000000..49fcc79 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mapvo.vo @@ -0,0 +1,3692 @@ + +// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +// ldbanno -n Verilog -o RAM2GS_LCMXO2_640HC_impl1_mapvo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd +// Netlist created on Tue Aug 15 05:03:24 2023 +// Netlist written on Tue Aug 15 05:03:26 2023 +// Design is for device LCMXO2-640HC +// Design is for package TQFP100 +// Design is for performance grade 4 + +`timescale 1 ns / 1 ps + +module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, + RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, + UFMCLK, UFMSDI, UFMSDO ); + input PHI2; + input [9:0] MAin; + input [1:0] CROW; + input [7:0] Din; + input nCCAS, nCRAS, nFWE, RCLK, UFMSDO; + output [7:0] Dout; + output LED; + output [1:0] RBA; + output [11:0] RA; + output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI; + inout [7:0] RD; + wire FS_14, FS_13, n81, n82, RCLK_c, n1998, n1999, FS_12, FS_11, n83, n84, + n1997, FS_8, FS_7, n87, n88, n1995, n1996, FS_6, FS_5, n89, n90, + n1994, FS_2, FS_1, n93, n94, n1992, n1993, FS_0, n95, CASr2, CASr3, + FS_10, FS_9, n85, n86, FS_17, n78, n2000, FS_4, FS_3, n91, n92, FS_16, + FS_15, n79, n80, Din_c_4, Din_c_6, Din_c_1, Din_c_7, n2382, n8, n2225, + n2180, ADSubmitted_N_246, PHI2_N_120_enable_2, C1Submitted_N_237, + PHI2_c, ADSubmitted, n26, MAin_c_5, n22, MAin_c_2, MAin_c_1, + C1Submitted, n2365, nFWE_c, n1398, nCCAS_c, nCCAS_N_3, CASr, n2254, + Din_c_5, n2191, n2183, n15_adj_1, n2208, n2363, CmdEnable_N_248, + PHI2_N_120_enable_1, CmdEnable, \n2447\001/BUF1 , PHI2_N_120_enable_7, + CmdSubmitted, n1314, n8MEGEN, Din_c_0, Cmdn8MEGEN_N_264, + PHI2_N_120_enable_6, Cmdn8MEGEN, Din_c_3, n2373, nCRAS_c, FWEr, CBR, + \n2447\000/BUF1 , RCLK_c_enable_28, InitReady, n2447, + RCLK_c_enable_16, LEDEN, nCRAS_c__inv, RASr, LED_c, RASr2, + nRowColSel_N_35, nRCAS_N_165, Ready, n2381, nRCS_N_139, n2036, + nRWE_N_177, RA_0, XOR8MEG, RA11_N_184, RA_c, n6_adj_2, PHI2r2, PHI2r3, + n15_adj_4, RCKEEN_N_121, RCLK_c_enable_6, RCKEEN, RCLK_c_enable_10, + RASr3, RCKE_N_132, PHI2r, RCKE_c, \n2447\002/BUF1 , Ready_N_292, + n2267, n13_adj_6, CmdUFMCLK, n1893, UFMCLK_N_224, n2366, UFMCLK_c, + n10, n7, n4, CmdUFMSDI, n2174, UFMSDI_N_231, UFMSDI_c, n2260, Din_c_2, + XOR8MEG_N_110, PHI2_N_120_enable_3, n2375, UFMSDO_c, n2367, + n8MEGEN_N_91, RCLK_c_enable_15, nRCS_N_142, nRCAS_N_166, n2371, + nRCAS_N_161, nRCAS_c, nRCS_N_141, nRCS_N_137, nRCS_N_136, nRCS_c, + n2379, nRRAS_N_156, nRRAS_c, nRWE_N_178, n1765, nRWE_N_171, + RCLK_c_enable_5, nRWE_c, nRowColSel_N_34, nRowColSel_N_33, n2376, + n1060, n2372, n917, nRowColSel, nRowColSel_N_32, n827, n2227, n1406, + Bank_3, Bank_6, n2287, n13, n2374, n2368, CmdUFMCS, n64, nUFMCS_N_199, + nUFMCS_c, n6_adj_3, Ready_N_296, n2204, n2369, MAin_c_0, + PHI2_N_120_enable_8, Bank_5, n2277, Bank_2, n2220, RowA_0, RowA_1, + n2370, n2228, n732, n733, RCLK_c_enable_27, n2055, MAin_c_9, MAin_c_8, + RowA_8, RowA_9, n2210, nRWE_N_182, nRCS_N_146, n728, n729, n727, n730, + n2378, n726, n12, MAin_c_4, RowA_4, RowA_5, n1277, n4_adj_7, n2377, + n738, n737, n14, n15, n6, CROW_c_1, CROW_c_0, RBA_c_0, RBA_c_1, + n7_adj_5, n2362, WRD_6, WRD_7, WRD_4, WRD_5, WRD_0, WRD_1, MAin_c_3, + RowA_2, RowA_3, WRD_2, WRD_3, RA_1_9, Bank_0, RDQML_c, Bank_1, n734, + n735, RA_1_8, RDQMH_c, Bank_4, MAin_c_7, RowA_7, RA_1_7, Bank_7, + MAin_c_6, RowA_6, RA_1_6, RA_1_5, RA_1_0, RA_1_4, RA_1_1, RA_1_3, + RA_1_2, n984, n736, Dout_c, Dout_0, Dout_1, Dout_2, Dout_3, Dout_4, + Dout_5, Dout_6, VCCI; + + SLICE_0 SLICE_0( .A1(FS_14), .A0(FS_13), .DI1(n81), .DI0(n82), .CLK(RCLK_c), + .FCI(n1998), .F0(n82), .Q0(FS_13), .F1(n81), .Q1(FS_14), .FCO(n1999)); + SLICE_1 SLICE_1( .A1(FS_12), .A0(FS_11), .DI1(n83), .DI0(n84), .CLK(RCLK_c), + .FCI(n1997), .F0(n84), .Q0(FS_11), .F1(n83), .Q1(FS_12), .FCO(n1998)); + SLICE_2 SLICE_2( .A1(FS_8), .A0(FS_7), .DI1(n87), .DI0(n88), .CLK(RCLK_c), + .FCI(n1995), .F0(n88), .Q0(FS_7), .F1(n87), .Q1(FS_8), .FCO(n1996)); + SLICE_3 SLICE_3( .A1(FS_6), .A0(FS_5), .DI1(n89), .DI0(n90), .CLK(RCLK_c), + .FCI(n1994), .F0(n90), .Q0(FS_5), .F1(n89), .Q1(FS_6), .FCO(n1995)); + SLICE_4 SLICE_4( .A1(FS_2), .A0(FS_1), .DI1(n93), .DI0(n94), .CLK(RCLK_c), + .FCI(n1992), .F0(n94), .Q0(FS_1), .F1(n93), .Q1(FS_2), .FCO(n1993)); + SLICE_5 SLICE_5( .A1(FS_0), .DI1(n95), .M0(CASr2), .CLK(RCLK_c), .Q0(CASr3), + .F1(n95), .Q1(FS_0), .FCO(n1992)); + SLICE_6 SLICE_6( .A1(FS_10), .A0(FS_9), .DI1(n85), .DI0(n86), .CLK(RCLK_c), + .FCI(n1996), .F0(n86), .Q0(FS_9), .F1(n85), .Q1(FS_10), .FCO(n1997)); + SLICE_7 SLICE_7( .A0(FS_17), .DI0(n78), .CLK(RCLK_c), .FCI(n2000), .F0(n78), + .Q0(FS_17)); + SLICE_8 SLICE_8( .A1(FS_4), .A0(FS_3), .DI1(n91), .DI0(n92), .CLK(RCLK_c), + .FCI(n1993), .F0(n92), .Q0(FS_3), .F1(n91), .Q1(FS_4), .FCO(n1994)); + SLICE_9 SLICE_9( .A1(FS_16), .A0(FS_15), .DI1(n79), .DI0(n80), .CLK(RCLK_c), + .FCI(n1999), .F0(n80), .Q0(FS_15), .F1(n79), .Q1(FS_16), .FCO(n2000)); + SLICE_10 SLICE_10( .D1(Din_c_4), .C1(Din_c_6), .B1(Din_c_1), .A1(Din_c_7), + .D0(n2382), .C0(n8), .B0(n2225), .A0(n2180), .DI0(ADSubmitted_N_246), + .CE(PHI2_N_120_enable_2), .LSR(C1Submitted_N_237), .CLK(PHI2_c), + .F0(ADSubmitted_N_246), .Q0(ADSubmitted), .F1(n8)); + SLICE_15 SLICE_15( .D1(n26), .C1(MAin_c_5), .B1(n22), .A1(MAin_c_2), + .D0(MAin_c_1), .C0(C1Submitted), .B0(n2365), .A0(nFWE_c), .DI0(n1398), + .LSR(C1Submitted_N_237), .CLK(PHI2_c), .F0(n1398), .Q0(C1Submitted), + .F1(n2365)); + SLICE_16 SLICE_16( .A0(nCCAS_c), .DI0(nCCAS_N_3), .M1(CASr), .CLK(RCLK_c), + .F0(nCCAS_N_3), .Q0(CASr), .Q1(CASr2)); + SLICE_19 SLICE_19( .D1(n2254), .C1(Din_c_5), .B1(n2191), .A1(n2183), + .D0(n15_adj_1), .C0(n2208), .B0(MAin_c_1), .A0(n2363), + .DI0(CmdEnable_N_248), .CE(PHI2_N_120_enable_1), .CLK(PHI2_c), + .F0(CmdEnable_N_248), .Q0(CmdEnable), .F1(n15_adj_1)); + SLICE_20 SLICE_20( .DI0(\n2447\001/BUF1 ), .CE(PHI2_N_120_enable_7), + .CLK(PHI2_c), .F0(\n2447\001/BUF1 ), .Q0(CmdSubmitted)); + SLICE_24 SLICE_24( .C1(Din_c_5), .B1(Din_c_7), .A1(Din_c_6), .D0(n1314), + .C0(Din_c_4), .B0(n8MEGEN), .A0(Din_c_0), .DI0(Cmdn8MEGEN_N_264), + .CE(PHI2_N_120_enable_6), .CLK(PHI2_c), .F0(Cmdn8MEGEN_N_264), + .Q0(Cmdn8MEGEN), .F1(n1314)); + SLICE_25 SLICE_25( .C1(Din_c_3), .B1(Din_c_5), .A1(nFWE_c), .A0(nFWE_c), + .DI0(n2373), .M1(nCCAS_N_3), .CLK(nCRAS_c), .F0(n2373), .Q0(FWEr), + .F1(n2180), .Q1(CBR)); + SLICE_26 SLICE_26( .DI0(\n2447\000/BUF1 ), .CE(RCLK_c_enable_28), + .CLK(RCLK_c), .F0(\n2447\000/BUF1 ), .Q0(InitReady)); + SLICE_27 SLICE_27( .DI0(n2447), .CE(RCLK_c_enable_16), .CLK(RCLK_c), + .F0(n2447), .Q0(LEDEN)); + SLICE_30 SLICE_30( .C1(CBR), .B1(LEDEN), .A1(nCRAS_c), .A0(nCRAS_c), + .DI0(nCRAS_c__inv), .M1(RASr), .CLK(RCLK_c), .F0(nCRAS_c__inv), .Q0(RASr), + .F1(LED_c), .Q1(RASr2)); + SLICE_32 SLICE_32( .C1(nRowColSel_N_35), .B1(InitReady), .A1(RASr2), + .D0(nRCAS_N_165), .C0(Ready), .B0(n2381), .A0(nRCS_N_139), .DI0(n2036), + .LSR(nRWE_N_177), .CLK(RCLK_c), .F0(n2036), .Q0(RA_0), .F1(n2381)); + SLICE_33 SLICE_33( .C1(Din_c_4), .B1(Din_c_7), .A1(Din_c_6), .C0(n8MEGEN), + .B0(XOR8MEG), .A0(Din_c_6), .DI0(RA11_N_184), .LSR(Ready), .CLK(PHI2_c), + .F0(RA11_N_184), .Q0(RA_c), .F1(n6_adj_2)); + SLICE_35 SLICE_35( .D1(InitReady), .C1(CmdSubmitted), .B1(PHI2r2), + .A1(PHI2r3), .C0(Ready), .B0(n15_adj_4), .A0(InitReady), + .DI0(RCKEEN_N_121), .CE(RCLK_c_enable_6), .CLK(RCLK_c), .F0(RCKEEN_N_121), + .Q0(RCKEEN), .F1(RCLK_c_enable_10)); + SLICE_36 SLICE_36( .D0(RASr3), .C0(RASr2), .B0(RCKEEN), .A0(RASr), + .DI0(RCKE_N_132), .M1(PHI2r), .CLK(RCLK_c), .F0(RCKE_N_132), .Q0(RCKE_c), + .Q1(PHI2r2)); + SLICE_37 SLICE_37( .DI0(\n2447\002/BUF1 ), .CE(Ready_N_292), .CLK(RCLK_c), + .F0(\n2447\002/BUF1 ), .Q0(Ready)); + SLICE_44 SLICE_44( .D1(FS_1), .C1(n2267), .B1(n13_adj_6), .A1(FS_4), + .C0(InitReady), .B0(CmdUFMCLK), .A0(n1893), .DI0(UFMCLK_N_224), + .CE(RCLK_c_enable_10), .LSR(n2366), .CLK(RCLK_c), .F0(UFMCLK_N_224), + .Q0(UFMCLK_c), .F1(n1893)); + SLICE_45 SLICE_45( .D1(n10), .C1(FS_10), .B1(FS_8), .A1(n7), .D0(n4), + .C0(InitReady), .B0(CmdUFMSDI), .A0(n2174), .DI0(UFMSDI_N_231), + .CE(RCLK_c_enable_10), .LSR(n2366), .CLK(RCLK_c), .F0(UFMSDI_N_231), + .Q0(UFMSDI_c), .F1(n2174)); + SLICE_50 SLICE_50( .D1(LEDEN), .C1(n1314), .B1(Din_c_1), .A1(Din_c_4), + .D0(Din_c_3), .C0(n2260), .B0(Din_c_2), .A0(Din_c_0), .DI0(XOR8MEG_N_110), + .CE(PHI2_N_120_enable_3), .CLK(PHI2_c), .F0(XOR8MEG_N_110), .Q0(XOR8MEG), + .F1(n2260)); + SLICE_57 SLICE_57( .D1(FS_10), .C1(FS_11), .B1(n2375), .A1(n10), + .D0(Cmdn8MEGEN), .C0(UFMSDO_c), .B0(n2367), .A0(InitReady), + .DI0(n8MEGEN_N_91), .CE(RCLK_c_enable_15), .CLK(RCLK_c), .F0(n8MEGEN_N_91), + .Q0(n8MEGEN), .F1(n2367)); + SLICE_59 SLICE_59( .D1(CBR), .C1(nRowColSel_N_35), .B1(RASr2), + .A1(nRCS_N_142), .D0(nRCAS_N_166), .C0(Ready), .B0(nRCAS_N_165), + .A0(n2371), .DI0(nRCAS_N_161), .CE(RCLK_c_enable_6), .CLK(RCLK_c), + .F0(nRCAS_N_161), .Q0(nRCAS_c), .F1(nRCAS_N_166)); + SLICE_61 SLICE_61( .D1(nRCS_N_142), .C1(nRowColSel_N_35), .B1(RASr2), + .A1(RCKE_c), .C0(Ready), .B0(nRCS_N_141), .A0(nRCS_N_137), + .DI0(nRCS_N_136), .CE(RCLK_c_enable_6), .CLK(RCLK_c), .F0(nRCS_N_136), + .Q0(nRCS_c), .F1(nRCS_N_141)); + SLICE_62 SLICE_62( .D1(RASr2), .C1(nRowColSel_N_35), .B1(InitReady), + .A1(nRCS_N_139), .D0(nRowColSel_N_35), .C0(Ready), .B0(n2379), + .A0(nRCS_N_137), .DI0(nRRAS_N_156), .CE(RCLK_c_enable_6), .CLK(RCLK_c), + .F0(nRRAS_N_156), .Q0(nRRAS_c), .F1(nRCS_N_137)); + SLICE_64 SLICE_64( .B1(nRCAS_N_165), .A1(nRWE_N_177), .D0(n2371), .C0(Ready), + .B0(nRWE_N_178), .A0(n1765), .DI0(nRWE_N_171), .CE(RCLK_c_enable_5), + .CLK(RCLK_c), .F0(nRWE_N_171), .Q0(nRWE_c), .F1(n1765)); + SLICE_65 SLICE_65( .B1(nRowColSel_N_34), .A1(nRowColSel_N_33), .D0(n2376), + .C0(n1060), .B0(n2372), .A0(FWEr), .DI0(n917), .CE(RCLK_c_enable_5), + .CLK(RCLK_c), .F0(n917), .Q0(nRowColSel), .F1(n1060)); + SLICE_66 SLICE_66( .B1(CASr2), .A1(nRowColSel_N_33), .B0(nRowColSel_N_32), + .A0(nRowColSel_N_33), .DI0(n827), .LSR(RASr2), .CLK(RCLK_c), .F0(n827), + .Q0(nRowColSel_N_32), .F1(n2227)); + SLICE_67 SLICE_67( .B0(nRowColSel_N_32), .A0(RASr2), .DI0(n1406), + .LSR(nRowColSel_N_34), .CLK(RCLK_c), .F0(n1406), .Q0(nRowColSel_N_33)); + SLICE_68 SLICE_68( .B1(FS_0), .A1(FS_8), .B0(Bank_3), .A0(Bank_6), + .M0(n1406), .LSR(nRowColSel_N_35), .CLK(RCLK_c), .F0(n2287), + .Q0(nRowColSel_N_34), .F1(n13)); + SLICE_69 SLICE_69( .B1(RASr2), .A1(RCKE_c), .A0(RASr2), .DI0(n2374), + .M1(PHI2r2), .CLK(RCLK_c), .F0(n2374), .Q0(nRowColSel_N_35), .F1(n2379), + .Q1(PHI2r3)); + SLICE_70 SLICE_70( .D1(FS_10), .C1(InitReady), .B1(n2368), .A1(FS_11), + .D0(InitReady), .C0(CmdUFMCS), .B0(n64), .A0(n13_adj_6), + .DI0(nUFMCS_N_199), .CE(RCLK_c_enable_10), .CLK(RCLK_c), .F0(nUFMCS_N_199), + .Q0(nUFMCS_c), .F1(n64)); + i30_SLICE_71 \i30/SLICE_71 ( .C1(RASr2), .B1(FWEr), .A1(CBR), + .D0(nRowColSel_N_34), .C0(FWEr), .B0(n2227), .A0(CBR), + .M0(nRowColSel_N_35), .OFX0(n15_adj_4)); + SLICE_72 SLICE_72( .D1(Ready), .C1(nRowColSel_N_32), .B1(n6_adj_3), + .A1(RASr2), .B0(Ready_N_296), .A0(InitReady), .F0(n6_adj_3), + .F1(Ready_N_292)); + SLICE_73 SLICE_73( .D1(n2204), .C1(n2180), .B1(n26), .A1(n2369), + .D0(n6_adj_2), .C0(CmdEnable), .B0(MAin_c_0), .A0(MAin_c_1), .F0(n2204), + .F1(PHI2_N_120_enable_8)); + SLICE_74 SLICE_74( .D1(Bank_5), .C1(n2287), .B1(n2277), .A1(Bank_2), + .D0(nFWE_c), .C0(n2204), .B0(n26), .A0(n2369), .M1(MAin_c_1), + .M0(MAin_c_0), .LSR(Ready), .CLK(nCRAS_c), .F0(n2220), .Q0(RowA_0), + .F1(n26), .Q1(RowA_1)); + SLICE_75 SLICE_75( .D1(n2370), .C1(n2183), .B1(n2228), .A1(Din_c_5), + .B0(Din_c_3), .A0(Din_c_6), .M1(n732), .M0(n733), .CE(RCLK_c_enable_27), + .CLK(RCLK_c), .F0(n2183), .Q0(n732), .F1(n2055), .Q1(nRWE_N_177)); + SLICE_76 SLICE_76( .C1(n10), .B1(FS_14), .A1(FS_12), .D0(InitReady), + .C0(n2368), .B0(FS_11), .A0(FS_10), .M1(MAin_c_9), .M0(MAin_c_8), + .LSR(Ready), .CLK(nCRAS_c), .F0(RCLK_c_enable_16), .Q0(RowA_8), .F1(n2368), + .Q1(RowA_9)); + SLICE_77 SLICE_77( .D1(n2208), .C1(C1Submitted), .B1(n2191), .A1(Din_c_5), + .D0(MAin_c_0), .C0(Din_c_6), .B0(Din_c_3), .A0(Din_c_2), .F0(n2191), + .F1(n2210)); + SLICE_78 SLICE_78( .D1(nRowColSel_N_35), .C1(nRWE_N_182), .B1(n1060), + .A1(nRCS_N_146), .B0(RASr2), .A0(RCKE_c), .M1(n728), .M0(n729), + .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(nRWE_N_182), .Q0(n728), + .F1(nRWE_N_178), .Q1(n727)); + SLICE_79 SLICE_79( .C1(MAin_c_5), .B1(n22), .A1(MAin_c_2), .D0(MAin_c_1), + .C0(nFWE_c), .B0(n26), .A0(n2369), .M1(n730), .M0(nRWE_N_177), + .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(PHI2_N_120_enable_2), .Q0(n730), + .F1(n2369), .Q1(n729)); + SLICE_80 SLICE_80( .B1(FS_14), .A1(FS_12), .D0(FS_11), .C0(InitReady), + .B0(n2375), .A0(n10), .F0(n2366), .F1(n2375)); + SLICE_81 SLICE_81( .B1(CBR), .A1(FWEr), .D0(nRowColSel_N_33), .C0(n2378), + .B0(nRowColSel_N_34), .A0(nRCS_N_146), .M1(n726), .M0(n727), + .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(nRCS_N_142), .Q0(n726), + .F1(n2378), .Q1(Ready_N_296)); + SLICE_82 SLICE_82( .D1(FS_17), .C1(FS_14), .B1(n12), .A1(FS_11), + .B0(n13_adj_6), .A0(FS_10), .M1(MAin_c_5), .M0(MAin_c_4), .LSR(Ready), + .CLK(nCRAS_c), .F0(RCLK_c_enable_28), .Q0(RowA_4), .F1(n13_adj_6), + .Q1(RowA_5)); + SLICE_83 SLICE_83( .D1(n1314), .C1(n1277), .B1(CmdEnable), .A1(n2228), + .D0(MAin_c_1), .C0(MAin_c_0), .B0(n26), .A0(n2369), .F0(n1277), + .F1(PHI2_N_120_enable_3)); + SLICE_84 SLICE_84( .C1(CmdSubmitted), .B1(PHI2r2), .A1(PHI2r3), + .D0(n4_adj_7), .C0(InitReady), .B0(n2377), .A0(n2367), .M1(n738), + .M0(nRCAS_N_165), .CE(RCLK_c_enable_27), .CLK(RCLK_c), + .F0(RCLK_c_enable_15), .Q0(n738), .F1(n2377), .Q1(n737)); + SLICE_85 SLICE_85( .D1(n10), .C1(FS_11), .B1(FS_14), .A1(FS_12), .D0(FS_16), + .C0(FS_15), .B0(FS_13), .A0(FS_17), .F0(n10), .F1(n2267)); + SLICE_86 SLICE_86( .C1(FS_6), .B1(FS_9), .A1(FS_3), .D0(n14), .C0(n13), + .B0(n15), .A0(FS_4), .M1(RASr2), .M0(PHI2_c), .CLK(RCLK_c), .F0(n4_adj_7), + .Q0(PHI2r), .F1(n14), .Q1(RASr3)); + SLICE_87 SLICE_87( .D1(n6), .C1(nRowColSel_N_32), .B1(nRowColSel_N_33), + .A1(nRowColSel_N_35), .B0(nRowColSel_N_34), .A0(Ready), .M1(CROW_c_1), + .M0(CROW_c_0), .LSR(Ready), .CLK(nCRAS_c), .F0(n6), .Q0(RBA_c_0), + .F1(RCLK_c_enable_6), .Q1(RBA_c_1)); + SLICE_88 SLICE_88( .D1(n2363), .C1(C1Submitted_N_237), .B1(ADSubmitted), + .A1(n7_adj_5), .D0(n2362), .C0(MAin_c_0), .B0(n2055), .A0(Din_c_2), + .M1(Din_c_7), .M0(Din_c_6), .CLK(nCCAS_c), .F0(C1Submitted_N_237), + .Q0(WRD_6), .F1(PHI2_N_120_enable_1), .Q1(WRD_7)); + SLICE_89 SLICE_89( .D1(Din_c_5), .C1(Din_c_3), .B1(Din_c_4), .A1(n2220), + .D0(Din_c_3), .C0(Din_c_4), .B0(n2220), .A0(Din_c_5), .M1(Din_c_5), + .M0(Din_c_4), .CLK(nCCAS_c), .F0(PHI2_N_120_enable_6), .Q0(WRD_4), + .F1(PHI2_N_120_enable_7), .Q1(WRD_5)); + SLICE_90 SLICE_90( .D1(Din_c_0), .C1(Din_c_4), .B1(Din_c_1), .A1(Din_c_7), + .C0(Din_c_0), .B0(Din_c_1), .A0(Din_c_7), .M1(Din_c_1), .M0(Din_c_0), + .CLK(nCCAS_c), .F0(n2370), .Q0(WRD_0), .F1(n2208), .Q1(WRD_1)); + SLICE_91 SLICE_91( .C1(MAin_c_1), .B1(n26), .A1(n2369), .D0(MAin_c_1), + .C0(MAin_c_0), .B0(n26), .A0(n2369), .M1(MAin_c_3), .M0(MAin_c_2), + .LSR(Ready), .CLK(nCRAS_c), .F0(n2225), .Q0(RowA_2), .F1(n2362), + .Q1(RowA_3)); + SLICE_92 SLICE_92( .D1(Ready), .C1(nRowColSel_N_35), .B1(InitReady), + .A1(RASr2), .D0(nRCS_N_139), .C0(nRowColSel_N_35), .B0(InitReady), + .A0(RASr2), .M1(Din_c_3), .M0(Din_c_2), .CLK(nCCAS_c), .F0(n2371), + .Q0(WRD_2), .F1(RCLK_c_enable_27), .Q1(WRD_3)); + SLICE_93 SLICE_93( .B1(nRowColSel), .A1(MAin_c_9), .C0(nRowColSel), + .B0(MAin_c_9), .A0(RowA_9), .M1(Din_c_1), .M0(Din_c_0), .CLK(PHI2_c), + .F0(RA_1_9), .Q0(Bank_0), .F1(RDQML_c), .Q1(Bank_1)); + SLICE_94 SLICE_94( .B1(nRowColSel_N_35), .A1(Ready), .D0(nRowColSel_N_35), + .C0(nRowColSel_N_32), .B0(n1060), .A0(Ready), .F0(RCLK_c_enable_5), + .F1(n2372)); + SLICE_95 SLICE_95( .D1(FS_5), .C1(FS_9), .B1(FS_7), .A1(n2375), .D0(FS_2), + .C0(FS_1), .B0(FS_7), .A0(FS_5), .F0(n15), .F1(n7)); + SLICE_96 SLICE_96( .B1(CASr3), .A1(CBR), .D0(CASr2), .C0(FWEr), .B0(CASr3), + .A0(CBR), .F0(nRCS_N_146), .F1(n2376)); + SLICE_97 SLICE_97( .C1(MAin_c_1), .B1(n2210), .A1(MAin_c_0), .B0(Din_c_2), + .A0(MAin_c_0), .M1(n734), .M0(n735), .CE(RCLK_c_enable_27), .CLK(RCLK_c), + .F0(n2254), .Q0(n734), .F1(n7_adj_5), .Q1(n733)); + SLICE_98 SLICE_98( .B1(nRowColSel), .A1(MAin_c_9), .C0(nRowColSel), + .B0(MAin_c_8), .A0(RowA_8), .M1(nRCS_N_139), .M0(Ready_N_296), + .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(RA_1_8), .Q0(nRCS_N_139), + .F1(RDQMH_c), .Q1(nRCAS_N_165)); + SLICE_99 SLICE_99( .D1(Bank_1), .C1(Bank_4), .B1(MAin_c_3), .A1(MAin_c_7), + .C0(nRowColSel), .B0(MAin_c_7), .A0(RowA_7), .M0(Din_c_0), + .CE(PHI2_N_120_enable_8), .CLK(PHI2_c), .F0(RA_1_7), .Q0(CmdUFMSDI), + .F1(n22)); + SLICE_100 SLICE_100( .D1(Bank_0), .C1(Bank_7), .B1(MAin_c_4), .A1(MAin_c_6), + .C0(nRowColSel), .B0(MAin_c_6), .A0(RowA_6), .M1(Din_c_2), .M0(Din_c_1), + .CE(PHI2_N_120_enable_8), .CLK(PHI2_c), .F0(RA_1_6), .Q0(CmdUFMCLK), + .F1(n2277), .Q1(CmdUFMCS)); + SLICE_101 SLICE_101( .C1(nRowColSel), .B1(MAin_c_0), .A1(RowA_0), + .C0(nRowColSel), .B0(MAin_c_5), .A0(RowA_5), .M1(Din_c_7), .M0(Din_c_6), + .CLK(PHI2_c), .F0(RA_1_5), .Q0(Bank_6), .F1(RA_1_0), .Q1(Bank_7)); + SLICE_102 SLICE_102( .C1(nRowColSel), .B1(MAin_c_1), .A1(RowA_1), + .C0(nRowColSel), .B0(MAin_c_4), .A0(RowA_4), .M1(Din_c_5), .M0(Din_c_4), + .CLK(PHI2_c), .F0(RA_1_4), .Q0(Bank_4), .F1(RA_1_1), .Q1(Bank_5)); + SLICE_103 SLICE_103( .C1(nRowColSel), .B1(MAin_c_2), .A1(RowA_2), + .C0(nRowColSel), .B0(MAin_c_3), .A0(RowA_3), .M1(Din_c_3), .M0(Din_c_2), + .CLK(PHI2_c), .F0(RA_1_3), .Q0(Bank_2), .F1(RA_1_2), .Q1(Bank_3)); + SLICE_104 SLICE_104( .B1(nFWE_c), .A1(nCCAS_c), .C0(nFWE_c), .B0(n26), + .A0(n2369), .M1(MAin_c_7), .M0(MAin_c_6), .LSR(Ready), .CLK(nCRAS_c), + .F0(n2363), .Q0(RowA_6), .F1(n984), .Q1(RowA_7)); + SLICE_105 SLICE_105( .B1(FS_6), .A1(FS_11), .D0(FS_16), .C0(FS_15), + .B0(FS_12), .A0(FS_13), .F0(n12), .F1(n4)); + SLICE_106 SLICE_106( .B1(Din_c_2), .A1(Din_c_0), .B0(Din_c_4), .A0(nFWE_c), + .M1(n736), .M0(n737), .CE(RCLK_c_enable_27), .CLK(RCLK_c), .F0(n2228), + .Q0(n736), .F1(n2382), .Q1(n735)); + RD_7_ \RD[7]_I ( .PADDI(Dout_c), .PADDT(n984), .PADDO(WRD_7), .RD7(RD[7])); + RD_6_ \RD[6]_I ( .PADDI(Dout_0), .PADDT(n984), .PADDO(WRD_6), .RD6(RD[6])); + RD_5_ \RD[5]_I ( .PADDI(Dout_1), .PADDT(n984), .PADDO(WRD_5), .RD5(RD[5])); + RD_4_ \RD[4]_I ( .PADDI(Dout_2), .PADDT(n984), .PADDO(WRD_4), .RD4(RD[4])); + RD_3_ \RD[3]_I ( .PADDI(Dout_3), .PADDT(n984), .PADDO(WRD_3), .RD3(RD[3])); + RD_2_ \RD[2]_I ( .PADDI(Dout_4), .PADDT(n984), .PADDO(WRD_2), .RD2(RD[2])); + RD_1_ \RD[1]_I ( .PADDI(Dout_5), .PADDT(n984), .PADDO(WRD_1), .RD1(RD[1])); + RD_0_ \RD[0]_I ( .PADDI(Dout_6), .PADDT(n984), .PADDO(WRD_0), .RD0(RD[0])); + Dout_7_ \Dout[7]_I ( .PADDO(Dout_c), .Dout7(Dout[7])); + Dout_6_ \Dout[6]_I ( .PADDO(Dout_0), .Dout6(Dout[6])); + Dout_5_ \Dout[5]_I ( .PADDO(Dout_1), .Dout5(Dout[5])); + Dout_4_ \Dout[4]_I ( .PADDO(Dout_2), .Dout4(Dout[4])); + Dout_3_ \Dout[3]_I ( .PADDO(Dout_3), .Dout3(Dout[3])); + Dout_2_ \Dout[2]_I ( .PADDO(Dout_4), .Dout2(Dout[2])); + Dout_1_ \Dout[1]_I ( .PADDO(Dout_5), .Dout1(Dout[1])); + Dout_0_ \Dout[0]_I ( .PADDO(Dout_6), .Dout0(Dout[0])); + LED LED_I( .PADDO(LED_c), .LED(LED)); + RBA_1_ \RBA[1]_I ( .PADDO(RBA_c_1), .RBA1(RBA[1])); + RBA_0_ \RBA[0]_I ( .PADDO(RBA_c_0), .RBA0(RBA[0])); + RA_11_ \RA[11]_I ( .PADDO(RA_c), .RA11(RA[11])); + RA_10_ \RA[10]_I ( .PADDO(RA_0), .RA10(RA[10])); + RA_9_ \RA[9]_I ( .PADDO(RA_1_9), .RA9(RA[9])); + RA_8_ \RA[8]_I ( .PADDO(RA_1_8), .RA8(RA[8])); + RA_7_ \RA[7]_I ( .PADDO(RA_1_7), .RA7(RA[7])); + RA_6_ \RA[6]_I ( .PADDO(RA_1_6), .RA6(RA[6])); + RA_5_ \RA[5]_I ( .PADDO(RA_1_5), .RA5(RA[5])); + RA_4_ \RA[4]_I ( .PADDO(RA_1_4), .RA4(RA[4])); + RA_3_ \RA[3]_I ( .PADDO(RA_1_3), .RA3(RA[3])); + RA_2_ \RA[2]_I ( .PADDO(RA_1_2), .RA2(RA[2])); + RA_1_ \RA[1]_I ( .PADDO(RA_1_1), .RA1(RA[1])); + RA_0_ \RA[0]_I ( .PADDO(RA_1_0), .RA0(RA[0])); + nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS)); + RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE)); + nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE)); + nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS)); + nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS)); + RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH)); + RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML)); + nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS)); + UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK)); + UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI)); + PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2)); + MAin_9_ \MAin[9]_I ( .PADDI(MAin_c_9), .MAin9(MAin[9])); + MAin_8_ \MAin[8]_I ( .PADDI(MAin_c_8), .MAin8(MAin[8])); + MAin_7_ \MAin[7]_I ( .PADDI(MAin_c_7), .MAin7(MAin[7])); + MAin_6_ \MAin[6]_I ( .PADDI(MAin_c_6), .MAin6(MAin[6])); + MAin_5_ \MAin[5]_I ( .PADDI(MAin_c_5), .MAin5(MAin[5])); + MAin_4_ \MAin[4]_I ( .PADDI(MAin_c_4), .MAin4(MAin[4])); + MAin_3_ \MAin[3]_I ( .PADDI(MAin_c_3), .MAin3(MAin[3])); + MAin_2_ \MAin[2]_I ( .PADDI(MAin_c_2), .MAin2(MAin[2])); + MAin_1_ \MAin[1]_I ( .PADDI(MAin_c_1), .MAin1(MAin[1])); + MAin_0_ \MAin[0]_I ( .PADDI(MAin_c_0), .MAin0(MAin[0])); + CROW_1_ \CROW[1]_I ( .PADDI(CROW_c_1), .CROW1(CROW[1])); + CROW_0_ \CROW[0]_I ( .PADDI(CROW_c_0), .CROW0(CROW[0])); + Din_7_ \Din[7]_I ( .PADDI(Din_c_7), .Din7(Din[7])); + Din_6_ \Din[6]_I ( .PADDI(Din_c_6), .Din6(Din[6])); + Din_5_ \Din[5]_I ( .PADDI(Din_c_5), .Din5(Din[5])); + Din_4_ \Din[4]_I ( .PADDI(Din_c_4), .Din4(Din[4])); + Din_3_ \Din[3]_I ( .PADDI(Din_c_3), .Din3(Din[3])); + Din_2_ \Din[2]_I ( .PADDI(Din_c_2), .Din2(Din[2])); + Din_1_ \Din[1]_I ( .PADDI(Din_c_1), .Din1(Din[1])); + Din_0_ \Din[0]_I ( .PADDI(Din_c_0), .Din0(Din[0])); + nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS)); + nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS)); + nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE)); + RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK)); + UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO)); + VHI VHI_INST( .Z(VCCI)); + PUR PUR_INST( .PUR(VCCI)); + GSR GSR_INST( .GSR(VCCI)); +endmodule + +module SLICE_0 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i14( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i13( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_15( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module vcc ( output PWR1 ); + + VHI INST1( .Z(PWR1)); +endmodule + +module gnd ( output PWR0 ); + + VLO INST1( .Z(PWR0)); +endmodule + +module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'hfaaa; + defparam inst1.INIT1 = 16'hfaaa; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_1 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i12( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i11( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_13( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i8( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i7( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_9( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i6( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i5( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_7( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i2( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i1( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_3( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_5 ( input A1, DI1, M0, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, M0_dly; + + vmuxregsre FS_610__i0( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CASr3_384( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 FS_610_add_4_1( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'hF000; + defparam inst1.INIT1 = 16'h0555; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i10( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i9( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_11( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_7 ( input A0, DI0, CLK, FCI, output F0, Q0 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + vmuxregsre FS_610__i17( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu20002 FS_610_add_4_19( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), + .CO1()); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'hfaaa; + defparam inst1.INIT1 = 16'h0000; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i4( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_5( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_9 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre FS_610__i16( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i15( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_17( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_10 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut4 i3_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40003 i1_4_lut_adj_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 ADSubmitted_407( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut4 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40003 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + +module SLICE_15 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40005 i13_2_lut_rep_16_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40006 i1110_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0007 C1Submitted_406( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40005 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40006 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE0F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0007 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_16 ( input A0, DI0, M1, CLK, output F0, Q0, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40008 i2045( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CASr2_383( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre CASr_382( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40008 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_19 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40009 i26_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 i2_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdEnable_405( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40009 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0CA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40010 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_20 ( input DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40011 \n2447\001/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdSubmitted_411( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40011 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_24 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40012 i1_2_lut_3_lut_adj_15( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40013 Cmdn8MEGEN_I_93_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Cmdn8MEGEN_410( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40013 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCC5C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_25 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly; + + lut40014 i2_3_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 i2_1_lut_rep_24( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre CBR_390( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre FWEr_389( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + endspecify + +endmodule + +module lut40014 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_26 ( input DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 \n2447\000/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre InitReady_394( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_27 ( input DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 m1_lut( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre LEDEN_419( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_30 ( input C1, B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40015 i2010_3_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 i2044( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre RASr2_380( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RASr_379( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40015 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_32 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40016 i2_3_lut_rep_32( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40017 i2_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0007 RA10_400( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40016 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_33 ( input C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40018 i1_2_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40019 RA11_I_54_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0004 RA11_385( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40018 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_35 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40020 i1_2_lut_4_lut_adj_25( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 i29_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre RCKEEN_401( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h20FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_36 ( input D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, Q1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, M1_dly; + + lut40022 i1404_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre PHI2r2_377( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre RCKE_395( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40022 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCFC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_37 ( input DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 \n2447\002/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre Ready_404( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_44 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40023 i1970_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 i1603_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 UFMCLK_416( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_45 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut4 i4_4_lut_adj_17( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40024 i1589_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 UFMSDI_417( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40025 i1962_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40026 i2_3_lut_4_lut_adj_11( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre XOR8MEG_408( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40026 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40027 i2_3_lut_rep_18_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40028 n8MEGEN_I_14_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre n8MEGEN_418( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40028 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBF04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40029 nRCAS_I_43_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40030 nRCAS_I_0_452_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0031 nRCAS_398( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3AFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40030 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFE0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0031 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_61 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40032 nRCS_I_31_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 nRCS_I_0_448_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0031 nRCS_396( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1F10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40033 i3_4_lut_adj_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40029 nRCS_N_137_I_0_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0031 nRRAS_397( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_64 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40034 i1477_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40035 nRWE_I_0_455_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0031 nRWE_399( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCFC5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_65 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40034 i786_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40036 i1432_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre nRowColSel_402( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40036 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_66 ( input B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40037 i1_2_lut_adj_23( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 i1439_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0004 S_FSM_i4( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input B0, A0, DI0, LSR, CLK, output F0, Q0 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40038 i1_2_lut_adj_10( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 S_FSM_i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40038 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_68 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; + + lut40034 i4_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 i1989_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0004 S_FSM_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_69 ( input B1, A1, A0, DI0, M1, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40034 i1491_2_lut_rep_30( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 RASr2_I_0_1_lut_rep_25( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre PHI2r3_378( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre S_FSM_i1( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40040 i1_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40041 i1448_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0031 nUFMCS_415( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3FBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module i30_SLICE_71 ( input C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); + wire GNDI, \i30/SLICE_71/i30/SLICE_71_K1_H1 , \i30/SLICE_71/i30/GATE_H0 ; + + lut40042 \i30/SLICE_71_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\i30/SLICE_71/i30/SLICE_71_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40043 \i30/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\i30/SLICE_71/i30/GATE_H0 )); + selmux2 \i30/SLICE_71_K0K1MUX ( .D0(\i30/SLICE_71/i30/GATE_H0 ), + .D1(\i30/SLICE_71/i30/SLICE_71_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40042 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1F1F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40043 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5540) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module SLICE_72 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40044 i1_4_lut_4_lut_adj_12( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 i2_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40044 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40003 i2_3_lut_4_lut_adj_14( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 i4_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40033 i12_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40045 i1_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 RowA_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_75 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40027 i3_4_lut_adj_18( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 i1_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_76 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40012 i1_2_lut_rep_19_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40026 i1_2_lut_rep_15_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0007 RowA_i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_77 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40046 i3_4_lut_adj_22( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40046 i3_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40046 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40047 nRCS_N_146_bdd_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40048 i1423_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i13( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i12( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40047 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40016 i11_3_lut_rep_20( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40049 MAin_c_0_bdd_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i11( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i10( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_80 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40034 i3_2_lut_rep_26( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40050 i2005_3_lut_rep_17_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_81 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40034 i1_2_lut_rep_29( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40051 i1427_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i15( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i14( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFCDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_82 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40052 i6_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 i1_2_lut_adj_3( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0007 RowA_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40053 i2_4_lut_adj_21( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40054 i2_3_lut_4_lut_adj_6( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_84 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40055 i2_3_lut_rep_28( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40024 i1573_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40056 i1969_2_lut_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 i3_4_lut_adj_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_86 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40012 i5_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut4 i1_4_lut_adj_8( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr3_381( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre PHI2r_376( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_87 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40040 i4_4_lut_adj_16( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40048 i1_2_lut_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0004 RBA__i2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RBA__i1( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_88 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40057 i34_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40053 i1_4_lut_adj_13( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre WRD_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0C5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40058 i2_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40059 i1_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre WRD_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_90 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40049 i1_2_lut_3_lut_4_lut_adj_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40055 i1_2_lut_rep_21_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre WRD_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_91 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40060 i1_2_lut_rep_13_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40061 i1_2_lut_3_lut_4_lut_adj_5( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0004 RowA_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40060 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40061 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40062 i2008_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40005 i1_2_lut_rep_22_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre WRD_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_93 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40063 i2001_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i10_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40048 i771_2_lut_rep_23_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40064 i2_3_lut_4_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40065 i2_4_lut_adj_20( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 i6_4_lut_adj_9( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_96 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40034 i1_2_lut_rep_27( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40027 i2_3_lut_4_lut_adj_24( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_97 ( input C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40066 i13_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 i1956_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre IS_FSM__i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC5C5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_98 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40037 i1416_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i9_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre IS_FSM__i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_99 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40052 i8_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 MAin_9__I_0_427_i8_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdUFMSDI_414( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_100 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40052 i1979_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 MAin_9__I_0_427_i7_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdUFMCS_412( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CmdUFMCLK_413( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_101 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40021 MAin_9__I_0_427_i1_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i6_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_102 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40021 MAin_9__I_0_427_i2_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i5_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_103 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40021 MAin_9__I_0_427_i3_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 MAin_9__I_0_427_i4_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_104 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40034 i1417_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40067 i1_2_lut_rep_14_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0004 RowA_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0004 RowA_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_105 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40039 i1_2_lut_adj_19( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40052 i5_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_106 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40039 i1_2_lut_rep_33( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 i1930_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre IS_FSM__i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); + + xo2iobuf Dout_pad_7__713( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), + .PADI(RD7)); + + specify + (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD7) = (0:0:0,0:0:0); + (RD7 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD7, 0:0:0); + $width (negedge RD7, 0:0:0); + endspecify + +endmodule + +module xo2iobuf ( input I, T, output Z, PAD, input PADI ); + + IBPD INST1( .I(PADI), .O(Z)); + OBZPD INST2( .I(I), .T(T), .O(PAD)); +endmodule + +module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); + + xo2iobuf Dout_pad_6__714( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), + .PADI(RD6)); + + specify + (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD6) = (0:0:0,0:0:0); + (RD6 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD6, 0:0:0); + $width (negedge RD6, 0:0:0); + endspecify + +endmodule + +module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); + + xo2iobuf Dout_pad_5__715( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), + .PADI(RD5)); + + specify + (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD5) = (0:0:0,0:0:0); + (RD5 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD5, 0:0:0); + $width (negedge RD5, 0:0:0); + endspecify + +endmodule + +module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); + + xo2iobuf Dout_pad_4__716( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), + .PADI(RD4)); + + specify + (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD4) = (0:0:0,0:0:0); + (RD4 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD4, 0:0:0); + $width (negedge RD4, 0:0:0); + endspecify + +endmodule + +module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); + + xo2iobuf Dout_pad_3__717( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), + .PADI(RD3)); + + specify + (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD3) = (0:0:0,0:0:0); + (RD3 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD3, 0:0:0); + $width (negedge RD3, 0:0:0); + endspecify + +endmodule + +module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); + + xo2iobuf Dout_pad_2__718( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), + .PADI(RD2)); + + specify + (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD2) = (0:0:0,0:0:0); + (RD2 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD2, 0:0:0); + $width (negedge RD2, 0:0:0); + endspecify + +endmodule + +module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); + + xo2iobuf Dout_pad_1__719( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), + .PADI(RD1)); + + specify + (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD1) = (0:0:0,0:0:0); + (RD1 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD1, 0:0:0); + $width (negedge RD1, 0:0:0); + endspecify + +endmodule + +module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); + + xo2iobuf Dout_pad_0__720( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), + .PADI(RD0)); + + specify + (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD0) = (0:0:0,0:0:0); + (RD0 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD0, 0:0:0); + $width (negedge RD0, 0:0:0); + endspecify + +endmodule + +module Dout_7_ ( input PADDO, output Dout7 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_7( .I(PADDO), .T(GNDI), .PAD(Dout7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0068 ( input I, T, output PAD ); + + OBZPD INST5( .I(I), .T(T), .O(PAD)); +endmodule + +module Dout_6_ ( input PADDO, output Dout6 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_6( .I(PADDO), .T(GNDI), .PAD(Dout6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_5_ ( input PADDO, output Dout5 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_5( .I(PADDO), .T(GNDI), .PAD(Dout5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_4_ ( input PADDO, output Dout4 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_4( .I(PADDO), .T(GNDI), .PAD(Dout4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_3_ ( input PADDO, output Dout3 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_3( .I(PADDO), .T(GNDI), .PAD(Dout3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_2_ ( input PADDO, output Dout2 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_2( .I(PADDO), .T(GNDI), .PAD(Dout2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_1_ ( input PADDO, output Dout1 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_1( .I(PADDO), .T(GNDI), .PAD(Dout1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_0_ ( input PADDO, output Dout0 ); + wire GNDI; + + xo2iobuf0068 Dout_pad_0( .I(PADDO), .T(GNDI), .PAD(Dout0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module LED ( input PADDO, output LED ); + wire GNDI; + + xo2iobuf0068 LED_pad( .I(PADDO), .T(GNDI), .PAD(LED)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => LED) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_1_ ( input PADDO, output RBA1 ); + wire GNDI; + + xo2iobuf0068 RBA_pad_1( .I(PADDO), .T(GNDI), .PAD(RBA1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RBA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_0_ ( input PADDO, output RBA0 ); + wire GNDI; + + xo2iobuf0068 RBA_pad_0( .I(PADDO), .T(GNDI), .PAD(RBA0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RBA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_11_ ( input PADDO, output RA11 ); + wire GNDI; + + xo2iobuf0068 RA_pad_11( .I(PADDO), .T(GNDI), .PAD(RA11)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_10_ ( input PADDO, output RA10 ); + wire GNDI; + + xo2iobuf0068 RA_pad_10( .I(PADDO), .T(GNDI), .PAD(RA10)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_9_ ( input PADDO, output RA9 ); + wire GNDI; + + xo2iobuf0068 RA_pad_9( .I(PADDO), .T(GNDI), .PAD(RA9)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_8_ ( input PADDO, output RA8 ); + wire GNDI; + + xo2iobuf0068 RA_pad_8( .I(PADDO), .T(GNDI), .PAD(RA8)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_7_ ( input PADDO, output RA7 ); + wire GNDI; + + xo2iobuf0068 RA_pad_7( .I(PADDO), .T(GNDI), .PAD(RA7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_6_ ( input PADDO, output RA6 ); + wire GNDI; + + xo2iobuf0068 RA_pad_6( .I(PADDO), .T(GNDI), .PAD(RA6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_5_ ( input PADDO, output RA5 ); + wire GNDI; + + xo2iobuf0068 RA_pad_5( .I(PADDO), .T(GNDI), .PAD(RA5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_4_ ( input PADDO, output RA4 ); + wire GNDI; + + xo2iobuf0068 RA_pad_4( .I(PADDO), .T(GNDI), .PAD(RA4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_3_ ( input PADDO, output RA3 ); + wire GNDI; + + xo2iobuf0068 RA_pad_3( .I(PADDO), .T(GNDI), .PAD(RA3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2_ ( input PADDO, output RA2 ); + wire GNDI; + + xo2iobuf0068 RA_pad_2( .I(PADDO), .T(GNDI), .PAD(RA2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_1_ ( input PADDO, output RA1 ); + wire GNDI; + + xo2iobuf0068 RA_pad_1( .I(PADDO), .T(GNDI), .PAD(RA1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_0_ ( input PADDO, output RA0 ); + wire GNDI; + + xo2iobuf0068 RA_pad_0( .I(PADDO), .T(GNDI), .PAD(RA0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCS ( input PADDO, output nRCS ); + wire GNDI; + + xo2iobuf0068 nRCS_pad( .I(PADDO), .T(GNDI), .PAD(nRCS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RCKE ( input PADDO, output RCKE ); + wire GNDI; + + xo2iobuf0068 RCKE_pad( .I(PADDO), .T(GNDI), .PAD(RCKE)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RCKE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRWE ( input PADDO, output nRWE ); + wire GNDI; + + xo2iobuf0068 nRWE_pad( .I(PADDO), .T(GNDI), .PAD(nRWE)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRWE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRRAS ( input PADDO, output nRRAS ); + wire GNDI; + + xo2iobuf0068 nRRAS_pad( .I(PADDO), .T(GNDI), .PAD(nRRAS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRRAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCAS ( input PADDO, output nRCAS ); + wire GNDI; + + xo2iobuf0068 nRCAS_pad( .I(PADDO), .T(GNDI), .PAD(nRCAS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRCAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQMH ( input PADDO, output RDQMH ); + wire GNDI; + + xo2iobuf0068 RDQMH_pad( .I(PADDO), .T(GNDI), .PAD(RDQMH)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RDQMH) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQML ( input PADDO, output RDQML ); + wire GNDI; + + xo2iobuf0068 RDQML_pad( .I(PADDO), .T(GNDI), .PAD(RDQML)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RDQML) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nUFMCS ( input PADDO, output nUFMCS ); + wire GNDI; + + xo2iobuf0068 nUFMCS_pad( .I(PADDO), .T(GNDI), .PAD(nUFMCS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nUFMCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module UFMCLK ( input PADDO, output UFMCLK ); + wire GNDI; + + xo2iobuf0068 UFMCLK_pad( .I(PADDO), .T(GNDI), .PAD(UFMCLK)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => UFMCLK) = (0:0:0,0:0:0); + endspecify + +endmodule + +module UFMSDI ( input PADDO, output UFMSDI ); + wire GNDI; + + xo2iobuf0068 UFMSDI_pad( .I(PADDO), .T(GNDI), .PAD(UFMSDI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => UFMSDI) = (0:0:0,0:0:0); + endspecify + +endmodule + +module PHI2 ( output PADDI, input PHI2 ); + + xo2iobuf0069 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + + specify + (PHI2 => PADDI) = (0:0:0,0:0:0); + $width (posedge PHI2, 0:0:0); + $width (negedge PHI2, 0:0:0); + endspecify + +endmodule + +module xo2iobuf0069 ( output Z, input PAD ); + + IBPD INST1( .I(PAD), .O(Z)); +endmodule + +module MAin_9_ ( output PADDI, input MAin9 ); + + xo2iobuf0069 MAin_pad_9( .Z(PADDI), .PAD(MAin9)); + + specify + (MAin9 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin9, 0:0:0); + $width (negedge MAin9, 0:0:0); + endspecify + +endmodule + +module MAin_8_ ( output PADDI, input MAin8 ); + + xo2iobuf0069 MAin_pad_8( .Z(PADDI), .PAD(MAin8)); + + specify + (MAin8 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin8, 0:0:0); + $width (negedge MAin8, 0:0:0); + endspecify + +endmodule + +module MAin_7_ ( output PADDI, input MAin7 ); + + xo2iobuf0069 MAin_pad_7( .Z(PADDI), .PAD(MAin7)); + + specify + (MAin7 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin7, 0:0:0); + $width (negedge MAin7, 0:0:0); + endspecify + +endmodule + +module MAin_6_ ( output PADDI, input MAin6 ); + + xo2iobuf0069 MAin_pad_6( .Z(PADDI), .PAD(MAin6)); + + specify + (MAin6 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin6, 0:0:0); + $width (negedge MAin6, 0:0:0); + endspecify + +endmodule + +module MAin_5_ ( output PADDI, input MAin5 ); + + xo2iobuf0069 MAin_pad_5( .Z(PADDI), .PAD(MAin5)); + + specify + (MAin5 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin5, 0:0:0); + $width (negedge MAin5, 0:0:0); + endspecify + +endmodule + +module MAin_4_ ( output PADDI, input MAin4 ); + + xo2iobuf0069 MAin_pad_4( .Z(PADDI), .PAD(MAin4)); + + specify + (MAin4 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin4, 0:0:0); + $width (negedge MAin4, 0:0:0); + endspecify + +endmodule + +module MAin_3_ ( output PADDI, input MAin3 ); + + xo2iobuf0069 MAin_pad_3( .Z(PADDI), .PAD(MAin3)); + + specify + (MAin3 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin3, 0:0:0); + $width (negedge MAin3, 0:0:0); + endspecify + +endmodule + +module MAin_2_ ( output PADDI, input MAin2 ); + + xo2iobuf0069 MAin_pad_2( .Z(PADDI), .PAD(MAin2)); + + specify + (MAin2 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin2, 0:0:0); + $width (negedge MAin2, 0:0:0); + endspecify + +endmodule + +module MAin_1_ ( output PADDI, input MAin1 ); + + xo2iobuf0069 MAin_pad_1( .Z(PADDI), .PAD(MAin1)); + + specify + (MAin1 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin1, 0:0:0); + $width (negedge MAin1, 0:0:0); + endspecify + +endmodule + +module MAin_0_ ( output PADDI, input MAin0 ); + + xo2iobuf0069 MAin_pad_0( .Z(PADDI), .PAD(MAin0)); + + specify + (MAin0 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin0, 0:0:0); + $width (negedge MAin0, 0:0:0); + endspecify + +endmodule + +module CROW_1_ ( output PADDI, input CROW1 ); + + xo2iobuf0069 CROW_pad_1( .Z(PADDI), .PAD(CROW1)); + + specify + (CROW1 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW1, 0:0:0); + $width (negedge CROW1, 0:0:0); + endspecify + +endmodule + +module CROW_0_ ( output PADDI, input CROW0 ); + + xo2iobuf0069 CROW_pad_0( .Z(PADDI), .PAD(CROW0)); + + specify + (CROW0 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW0, 0:0:0); + $width (negedge CROW0, 0:0:0); + endspecify + +endmodule + +module Din_7_ ( output PADDI, input Din7 ); + + xo2iobuf0069 Din_pad_7( .Z(PADDI), .PAD(Din7)); + + specify + (Din7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din7, 0:0:0); + $width (negedge Din7, 0:0:0); + endspecify + +endmodule + +module Din_6_ ( output PADDI, input Din6 ); + + xo2iobuf0069 Din_pad_6( .Z(PADDI), .PAD(Din6)); + + specify + (Din6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din6, 0:0:0); + $width (negedge Din6, 0:0:0); + endspecify + +endmodule + +module Din_5_ ( output PADDI, input Din5 ); + + xo2iobuf0069 Din_pad_5( .Z(PADDI), .PAD(Din5)); + + specify + (Din5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din5, 0:0:0); + $width (negedge Din5, 0:0:0); + endspecify + +endmodule + +module Din_4_ ( output PADDI, input Din4 ); + + xo2iobuf0069 Din_pad_4( .Z(PADDI), .PAD(Din4)); + + specify + (Din4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din4, 0:0:0); + $width (negedge Din4, 0:0:0); + endspecify + +endmodule + +module Din_3_ ( output PADDI, input Din3 ); + + xo2iobuf0069 Din_pad_3( .Z(PADDI), .PAD(Din3)); + + specify + (Din3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din3, 0:0:0); + $width (negedge Din3, 0:0:0); + endspecify + +endmodule + +module Din_2_ ( output PADDI, input Din2 ); + + xo2iobuf0069 Din_pad_2( .Z(PADDI), .PAD(Din2)); + + specify + (Din2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din2, 0:0:0); + $width (negedge Din2, 0:0:0); + endspecify + +endmodule + +module Din_1_ ( output PADDI, input Din1 ); + + xo2iobuf0069 Din_pad_1( .Z(PADDI), .PAD(Din1)); + + specify + (Din1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din1, 0:0:0); + $width (negedge Din1, 0:0:0); + endspecify + +endmodule + +module Din_0_ ( output PADDI, input Din0 ); + + xo2iobuf0069 Din_pad_0( .Z(PADDI), .PAD(Din0)); + + specify + (Din0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din0, 0:0:0); + $width (negedge Din0, 0:0:0); + endspecify + +endmodule + +module nCCAS ( output PADDI, input nCCAS ); + + xo2iobuf0069 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + + specify + (nCCAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCCAS, 0:0:0); + $width (negedge nCCAS, 0:0:0); + endspecify + +endmodule + +module nCRAS ( output PADDI, input nCRAS ); + + xo2iobuf0069 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + + specify + (nCRAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCRAS, 0:0:0); + $width (negedge nCRAS, 0:0:0); + endspecify + +endmodule + +module nFWE ( output PADDI, input nFWE ); + + xo2iobuf0069 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + + specify + (nFWE => PADDI) = (0:0:0,0:0:0); + $width (posedge nFWE, 0:0:0); + $width (negedge nFWE, 0:0:0); + endspecify + +endmodule + +module RCLK ( output PADDI, input RCLK ); + + xo2iobuf0069 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + + specify + (RCLK => PADDI) = (0:0:0,0:0:0); + $width (posedge RCLK, 0:0:0); + $width (negedge RCLK, 0:0:0); + endspecify + +endmodule + +module UFMSDO ( output PADDI, input UFMSDO ); + + xo2iobuf0069 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); + + specify + (UFMSDO => PADDI) = (0:0:0,0:0:0); + $width (posedge UFMSDO, 0:0:0); + $width (negedge UFMSDO, 0:0:0); + endspecify + +endmodule diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html new file mode 100644 index 0000000..06c3af4 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html @@ -0,0 +1,368 @@ + +Project Summary + + +
    
+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+
+Design Information
+
+Command line:   map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
+     RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr
+     RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf D:/One
+     Drive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_i
+     mpl1.lpf -lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_
+     LCMXO2_640HC.lpf -c 0 -gui -msgset
+     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-640HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
+Mapped on:  08/15/23  05:03:24
+
+
+Design Summary
+   Number of registers:    102 out of   877 (12%)
+      PFU registers:          102 out of   640 (16%)
+      PIO registers:            0 out of   237 (0%)
+   Number of SLICEs:        75 out of   320 (23%)
+      SLICEs as Logic/ROM:     75 out of   320 (23%)
+      SLICEs as RAM:            0 out of   240 (0%)
+      SLICEs as Carry:         10 out of   320 (3%)
+   Number of LUT4s:        143 out of   640 (22%)
+      Number used as logic LUTs:        123
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       20
+      Number used as shift registers:     0
+   Number of PIO sites used: 67 + 4(JTAG) out of 79 (90%)
+   Number of block RAMs:  0 out of 2 (0%)
+   Number of GSRs:        0 out of 1 (0%)
+   EFB used :        No
+   JTAG used :       No
+   Readback used :   No
+   Oscillator used : No
+   Startup used :    No
+   POR :             On
+   Bandgap :         On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  4
+     Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+   Number of Clock Enables:  14
+     Net RCLK_c_enable_6: 4 loads, 4 LSLICEs
+     Net RCLK_c_enable_5: 2 loads, 2 LSLICEs
+
+     Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
+     Net RCLK_c_enable_10: 3 loads, 3 LSLICEs
+     Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_16: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_28: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_15: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs
+     Net Ready_N_292: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs
+   Number of LSRs:  7
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+     Net nRWE_N_177: 1 loads, 1 LSLICEs
+     Net C1Submitted_N_237: 2 loads, 2 LSLICEs
+     Net n2366: 2 loads, 2 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net Ready: 18 loads
+     Net InitReady: 15 loads
+     Net RASr2: 15 loads
+     Net nRowColSel_N_35: 13 loads
+     Net nRowColSel: 12 loads
+     Net Din_c_4: 10 loads
+     Net MAin_c_1: 10 loads
+     Net Din_c_5: 9 loads
+     Net MAin_c_0: 9 loads
+     Net Din_c_0: 8 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+   No errors or warnings present.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| RD[7]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[6]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+| RD[5]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[4]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[3]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[2]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[1]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RD[0]               | BIDIR     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[7]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[6]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[5]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[4]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[3]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[2]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[1]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Dout[0]             | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| LED                 | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RBA[1]              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RBA[0]              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[11]              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[10]              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[9]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[8]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[7]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[6]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[5]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[4]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[3]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[2]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RA[1]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+| RA[0]               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nRCS                | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RCKE                | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nRWE                | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nRRAS               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nRCAS               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RDQMH               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RDQML               | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nUFMCS              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| UFMCLK              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| UFMSDI              | OUTPUT    | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| PHI2                | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[9]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[8]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[7]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[6]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[5]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[4]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[3]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[2]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[1]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| MAin[0]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| CROW[1]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| CROW[0]             | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[7]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[6]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[5]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[4]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+| Din[3]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[2]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[1]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| Din[0]              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nCCAS               | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nCRAS               | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| nFWE                | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| RCLK                | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+| UFMSDO              | INPUT     | LVCMOS25  |            |
++---------------------+-----------+-----------+------------+
+
+
+
+Removed logic
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal PHI2_N_120 was merged into signal PHI2_c
+Signal n1407 was merged into signal nRowColSel_N_34
+Signal n2380 was merged into signal Ready
+Signal n1408 was merged into signal nRowColSel_N_35
+Signal nRWE_N_176 was merged into signal nRWE_N_177
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_610_add_4_19/S1 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_19/CO undriven or does not drive anything - clipped.
+Signal FS_610_add_4_1/S0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_1/CI undriven or does not drive anything - clipped.
+Block i2046 was optimized away.
+Block i1118_1_lut was optimized away.
+Block i637_1_lut_rep_31 was optimized away.
+Block i1119_1_lut was optimized away.
+Block nRWE_I_50_1_lut was optimized away.
+Block i1 was optimized away.
+
+     
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 35 MB
+        
+
+
+
+
+
+
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html new file mode 100644 index 0000000..635ff81 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html @@ -0,0 +1,346 @@ + +PAD Specification File + + +
    PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-640HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.39
+
+Tue Aug 15 05:03:32 2023
+
+Pinout by Port Name:
++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site  | PG Enable | BC Enable | Properties                                               |
++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
+| CROW[0]   | 10/3     | LVCMOS25_IN   | PL3D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| CROW[1]   | 16/3     | LVCMOS25_IN   | PL6A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[0]    | 3/3      | LVCMOS25_IN   | PL2C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[1]    | 96/0     | LVCMOS25_IN   | PT6D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[2]    | 88/0     | LVCMOS25_IN   | PT9A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[3]    | 97/0     | LVCMOS25_IN   | PT6C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[4]    | 99/0     | LVCMOS25_IN   | PT6A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[5]    | 98/0     | LVCMOS25_IN   | PT6B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[6]    | 2/3      | LVCMOS25_IN   | PL2B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Din[7]    | 1/3      | LVCMOS25_IN   | PL2A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| Dout[0]   | 76/0     | LVCMOS25_OUT  | PT11D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[1]   | 86/0     | LVCMOS25_OUT  | PT9C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[2]   | 87/0     | LVCMOS25_OUT  | PT9B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[3]   | 85/0     | LVCMOS25_OUT  | PT9D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[4]   | 83/0     | LVCMOS25_OUT  | PT10B |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[5]   | 84/0     | LVCMOS25_OUT  | PT10A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[6]   | 78/0     | LVCMOS25_OUT  | PT11A |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| Dout[7]   | 82/0     | LVCMOS25_OUT  | PT10C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| LED       | 34/2     | LVCMOS25_OUT  | PB6C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| MAin[0]   | 14/3     | LVCMOS25_IN   | PL5C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[1]   | 12/3     | LVCMOS25_IN   | PL5A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[2]   | 13/3     | LVCMOS25_IN   | PL5B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[3]   | 21/3     | LVCMOS25_IN   | PL7B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[4]   | 20/3     | LVCMOS25_IN   | PL7A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[5]   | 19/3     | LVCMOS25_IN   | PL6D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[6]   | 24/3     | LVCMOS25_IN   | PL7C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[7]   | 18/3     | LVCMOS25_IN   | PL6C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[8]   | 25/3     | LVCMOS25_IN   | PL7D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| MAin[9]   | 32/2     | LVCMOS25_IN   | PB6B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| PHI2      | 8/3      | LVCMOS25_IN   | PL3B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| RA[0]     | 66/1     | LVCMOS25_OUT  | PR3D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[10]    | 64/1     | LVCMOS25_OUT  | PR5B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[11]    | 59/1     | LVCMOS25_OUT  | PR6B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[1]     | 67/1     | LVCMOS25_OUT  | PR3C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[2]     | 69/1     | LVCMOS25_OUT  | PR3A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[3]     | 71/1     | LVCMOS25_OUT  | PR2C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[4]     | 74/1     | LVCMOS25_OUT  | PR2B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[5]     | 70/1     | LVCMOS25_OUT  | PR2D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[6]     | 68/1     | LVCMOS25_OUT  | PR3B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[7]     | 75/1     | LVCMOS25_OUT  | PR2A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[8]     | 65/1     | LVCMOS25_OUT  | PR5A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RA[9]     | 63/1     | LVCMOS25_OUT  | PR5C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RBA[0]    | 58/1     | LVCMOS25_OUT  | PR6C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RBA[1]    | 60/1     | LVCMOS25_OUT  | PR6A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RCKE      | 53/1     | LVCMOS25_OUT  | PR7B  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RCLK      | 62/1     | LVCMOS25_IN   | PR5D  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| RDQMH     | 51/1     | LVCMOS25_OUT  | PR7D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RDQML     | 48/2     | LVCMOS25_OUT  | PB14C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| RD[0]     | 36/2     | LVCMOS25_BIDI | PB10A |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[1]     | 37/2     | LVCMOS25_BIDI | PB10B |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[2]     | 38/2     | LVCMOS25_BIDI | PB10C |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[3]     | 39/2     | LVCMOS25_BIDI | PB10D |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[4]     | 40/2     | LVCMOS25_BIDI | PB12A |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[5]     | 41/2     | LVCMOS25_BIDI | PB12B |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[6]     | 42/2     | LVCMOS25_BIDI | PB12C |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[7]     | 43/2     | LVCMOS25_BIDI | PB12D |           |           | DRIVE:8mA PULL:DOWN CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| UFMCLK    | 29/2     | LVCMOS25_OUT  | PB4C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| UFMSDI    | 30/2     | LVCMOS25_OUT  | PB4D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| UFMSDO    | 27/2     | LVCMOS25_IN   | PB4A  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| nCCAS     | 9/3      | LVCMOS25_IN   | PL3C  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| nCRAS     | 17/3     | LVCMOS25_IN   | PL6B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| nFWE      | 28/2     | LVCMOS25_IN   | PB4B  |           |           | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL                      |
+| nRCAS     | 52/1     | LVCMOS25_OUT  | PR7C  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| nRCS      | 57/1     | LVCMOS25_OUT  | PR6D  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| nRRAS     | 54/1     | LVCMOS25_OUT  | PR7A  |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| nRWE      | 49/2     | LVCMOS25_OUT  | PB14D |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
+| nUFMCS    | 77/0     | LVCMOS25_OUT  | PT11C |           |           | DRIVE:8mA PULL:DOWN SLEW:SLOW                            |
++-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 2.5V  |
+| 1    | 2.5V  |
+| 2    | 2.5V  |
+| 3    | 2.5V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type   | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| 1/3      | Din[7]                | LOCATED    | LVCMOS25_IN   | PL2A  |               |           |           |
+| 2/3      | Din[6]                | LOCATED    | LVCMOS25_IN   | PL2B  |               |           |           |
+| 3/3      | Din[0]                | LOCATED    | LVCMOS25_IN   | PL2C  | PCLKT3_2      |           |           |
+| 4/3      |     unused, PULL:DOWN |            |               | PL2D  | PCLKC3_2      |           |           |
+| 7/3      |     unused, PULL:DOWN |            |               | PL3A  |               |           |           |
+| 8/3      | PHI2                  | LOCATED    | LVCMOS25_IN   | PL3B  |               |           |           |
+| 9/3      | nCCAS                 | LOCATED    | LVCMOS25_IN   | PL3C  |               |           |           |
+| 10/3     | CROW[0]               | LOCATED    | LVCMOS25_IN   | PL3D  |               |           |           |
+| 12/3     | MAin[1]               | LOCATED    | LVCMOS25_IN   | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | MAin[2]               | LOCATED    | LVCMOS25_IN   | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | MAin[0]               | LOCATED    | LVCMOS25_IN   | PL5C  |               |           |           |
+| 15/3     |     unused, PULL:DOWN |            |               | PL5D  |               |           |           |
+| 16/3     | CROW[1]               | LOCATED    | LVCMOS25_IN   | PL6A  |               |           |           |
+| 17/3     | nCRAS                 | LOCATED    | LVCMOS25_IN   | PL6B  |               |           |           |
+| 18/3     | MAin[7]               | LOCATED    | LVCMOS25_IN   | PL6C  |               |           |           |
+| 19/3     | MAin[5]               | LOCATED    | LVCMOS25_IN   | PL6D  |               |           |           |
+| 20/3     | MAin[4]               | LOCATED    | LVCMOS25_IN   | PL7A  | PCLKT3_0      |           |           |
+| 21/3     | MAin[3]               | LOCATED    | LVCMOS25_IN   | PL7B  | PCLKC3_0      |           |           |
+| 24/3     | MAin[6]               | LOCATED    | LVCMOS25_IN   | PL7C  |               |           |           |
+| 25/3     | MAin[8]               | LOCATED    | LVCMOS25_IN   | PL7D  |               |           |           |
+| 27/2     | UFMSDO                | LOCATED    | LVCMOS25_IN   | PB4A  | CSSPIN        |           |           |
+| 28/2     | nFWE                  | LOCATED    | LVCMOS25_IN   | PB4B  |               |           |           |
+| 29/2     | UFMCLK                | LOCATED    | LVCMOS25_OUT  | PB4C  |               |           |           |
+| 30/2     | UFMSDI                | LOCATED    | LVCMOS25_OUT  | PB4D  |               |           |           |
+| 31/2     |     unused, PULL:DOWN |            |               | PB6A  | MCLK/CCLK     |           |           |
+| 32/2     | MAin[9]               | LOCATED    | LVCMOS25_IN   | PB6B  | SO/SPISO      |           |           |
+| 34/2     | LED                   | LOCATED    | LVCMOS25_OUT  | PB6C  | PCLKT2_0      |           |           |
+| 35/2     |     unused, PULL:DOWN |            |               | PB6D  | PCLKC2_0      |           |           |
+| 36/2     | RD[0]                 | LOCATED    | LVCMOS25_BIDI | PB10A |               |           |           |
+| 37/2     | RD[1]                 | LOCATED    | LVCMOS25_BIDI | PB10B |               |           |           |
+| 38/2     | RD[2]                 | LOCATED    | LVCMOS25_BIDI | PB10C | PCLKT2_1      |           |           |
+| 39/2     | RD[3]                 | LOCATED    | LVCMOS25_BIDI | PB10D | PCLKC2_1      |           |           |
+| 40/2     | RD[4]                 | LOCATED    | LVCMOS25_BIDI | PB12A |               |           |           |
+| 41/2     | RD[5]                 | LOCATED    | LVCMOS25_BIDI | PB12B |               |           |           |
+| 42/2     | RD[6]                 | LOCATED    | LVCMOS25_BIDI | PB12C |               |           |           |
+| 43/2     | RD[7]                 | LOCATED    | LVCMOS25_BIDI | PB12D |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |               | PB14A |               |           |           |
+| 47/2     |     unused, PULL:DOWN |            |               | PB14B |               |           |           |
+| 48/2     | RDQML                 | LOCATED    | LVCMOS25_OUT  | PB14C | SN            |           |           |
+| 49/2     | nRWE                  | LOCATED    | LVCMOS25_OUT  | PB14D | SI/SISPI      |           |           |
+| 51/1     | RDQMH                 | LOCATED    | LVCMOS25_OUT  | PR7D  |               |           |           |
+| 52/1     | nRCAS                 | LOCATED    | LVCMOS25_OUT  | PR7C  |               |           |           |
+| 53/1     | RCKE                  | LOCATED    | LVCMOS25_OUT  | PR7B  |               |           |           |
+| 54/1     | nRRAS                 | LOCATED    | LVCMOS25_OUT  | PR7A  |               |           |           |
+| 57/1     | nRCS                  | LOCATED    | LVCMOS25_OUT  | PR6D  |               |           |           |
+| 58/1     | RBA[0]                | LOCATED    | LVCMOS25_OUT  | PR6C  |               |           |           |
+| 59/1     | RA[11]                | LOCATED    | LVCMOS25_OUT  | PR6B  |               |           |           |
+| 60/1     | RBA[1]                | LOCATED    | LVCMOS25_OUT  | PR6A  |               |           |           |
+| 62/1     | RCLK                  | LOCATED    | LVCMOS25_IN   | PR5D  | PCLKC1_0      |           |           |
+| 63/1     | RA[9]                 | LOCATED    | LVCMOS25_OUT  | PR5C  | PCLKT1_0      |           |           |
+| 64/1     | RA[10]                | LOCATED    | LVCMOS25_OUT  | PR5B  |               |           |           |
+| 65/1     | RA[8]                 | LOCATED    | LVCMOS25_OUT  | PR5A  |               |           |           |
+| 66/1     | RA[0]                 | LOCATED    | LVCMOS25_OUT  | PR3D  |               |           |           |
+| 67/1     | RA[1]                 | LOCATED    | LVCMOS25_OUT  | PR3C  |               |           |           |
+| 68/1     | RA[6]                 | LOCATED    | LVCMOS25_OUT  | PR3B  |               |           |           |
+| 69/1     | RA[2]                 | LOCATED    | LVCMOS25_OUT  | PR3A  |               |           |           |
+| 70/1     | RA[5]                 | LOCATED    | LVCMOS25_OUT  | PR2D  |               |           |           |
+| 71/1     | RA[3]                 | LOCATED    | LVCMOS25_OUT  | PR2C  |               |           |           |
+| 74/1     | RA[4]                 | LOCATED    | LVCMOS25_OUT  | PR2B  |               |           |           |
+| 75/1     | RA[7]                 | LOCATED    | LVCMOS25_OUT  | PR2A  |               |           |           |
+| 76/0     | Dout[0]               | LOCATED    | LVCMOS25_OUT  | PT11D | DONE          |           |           |
+| 77/0     | nUFMCS                |            | LVCMOS25_OUT  | PT11C | INITN         |           |           |
+| 78/0     | Dout[6]               | LOCATED    | LVCMOS25_OUT  | PT11A |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |               | PT10D | PROGRAMN      |           |           |
+| 82/0     | Dout[7]               | LOCATED    | LVCMOS25_OUT  | PT10C | JTAGENB       |           |           |
+| 83/0     | Dout[4]               | LOCATED    | LVCMOS25_OUT  | PT10B |               |           |           |
+| 84/0     | Dout[5]               | LOCATED    | LVCMOS25_OUT  | PT10A |               |           |           |
+| 85/0     | Dout[3]               | LOCATED    | LVCMOS25_OUT  | PT9D  | SDA/PCLKC0_0  |           |           |
+| 86/0     | Dout[1]               | LOCATED    | LVCMOS25_OUT  | PT9C  | SCL/PCLKT0_0  |           |           |
+| 87/0     | Dout[2]               | LOCATED    | LVCMOS25_OUT  | PT9B  | PCLKC0_1      |           |           |
+| 88/0     | Din[2]                | LOCATED    | LVCMOS25_IN   | PT9A  | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |               | PT7D  | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |               | PT7C  | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |               | PT7B  | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |               | PT7A  | TDO           |           |           |
+| 96/0     | Din[1]                | LOCATED    | LVCMOS25_IN   | PT6D  |               |           |           |
+| 97/0     | Din[3]                | LOCATED    | LVCMOS25_IN   | PT6C  |               |           |           |
+| 98/0     | Din[5]                | LOCATED    | LVCMOS25_IN   | PT6B  |               |           |           |
+| 99/0     | Din[4]                | LOCATED    | LVCMOS25_IN   | PT6A  |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |               | PT11B |               |           |           |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT7D     | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT7C     | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT7B     | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT7A     | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "10";
+LOCATE  COMP  "CROW[1]"  SITE  "16";
+LOCATE  COMP  "Din[0]"  SITE  "3";
+LOCATE  COMP  "Din[1]"  SITE  "96";
+LOCATE  COMP  "Din[2]"  SITE  "88";
+LOCATE  COMP  "Din[3]"  SITE  "97";
+LOCATE  COMP  "Din[4]"  SITE  "99";
+LOCATE  COMP  "Din[5]"  SITE  "98";
+LOCATE  COMP  "Din[6]"  SITE  "2";
+LOCATE  COMP  "Din[7]"  SITE  "1";
+LOCATE  COMP  "Dout[0]"  SITE  "76";
+LOCATE  COMP  "Dout[1]"  SITE  "86";
+LOCATE  COMP  "Dout[2]"  SITE  "87";
+LOCATE  COMP  "Dout[3]"  SITE  "85";
+LOCATE  COMP  "Dout[4]"  SITE  "83";
+LOCATE  COMP  "Dout[5]"  SITE  "84";
+LOCATE  COMP  "Dout[6]"  SITE  "78";
+LOCATE  COMP  "Dout[7]"  SITE  "82";
+LOCATE  COMP  "LED"  SITE  "34";
+LOCATE  COMP  "MAin[0]"  SITE  "14";
+LOCATE  COMP  "MAin[1]"  SITE  "12";
+LOCATE  COMP  "MAin[2]"  SITE  "13";
+LOCATE  COMP  "MAin[3]"  SITE  "21";
+LOCATE  COMP  "MAin[4]"  SITE  "20";
+LOCATE  COMP  "MAin[5]"  SITE  "19";
+LOCATE  COMP  "MAin[6]"  SITE  "24";
+LOCATE  COMP  "MAin[7]"  SITE  "18";
+LOCATE  COMP  "MAin[8]"  SITE  "25";
+LOCATE  COMP  "MAin[9]"  SITE  "32";
+LOCATE  COMP  "PHI2"  SITE  "8";
+LOCATE  COMP  "RA[0]"  SITE  "66";
+LOCATE  COMP  "RA[10]"  SITE  "64";
+LOCATE  COMP  "RA[11]"  SITE  "59";
+LOCATE  COMP  "RA[1]"  SITE  "67";
+LOCATE  COMP  "RA[2]"  SITE  "69";
+LOCATE  COMP  "RA[3]"  SITE  "71";
+LOCATE  COMP  "RA[4]"  SITE  "74";
+LOCATE  COMP  "RA[5]"  SITE  "70";
+LOCATE  COMP  "RA[6]"  SITE  "68";
+LOCATE  COMP  "RA[7]"  SITE  "75";
+LOCATE  COMP  "RA[8]"  SITE  "65";
+LOCATE  COMP  "RA[9]"  SITE  "63";
+LOCATE  COMP  "RBA[0]"  SITE  "58";
+LOCATE  COMP  "RBA[1]"  SITE  "60";
+LOCATE  COMP  "RCKE"  SITE  "53";
+LOCATE  COMP  "RCLK"  SITE  "62";
+LOCATE  COMP  "RDQMH"  SITE  "51";
+LOCATE  COMP  "RDQML"  SITE  "48";
+LOCATE  COMP  "RD[0]"  SITE  "36";
+LOCATE  COMP  "RD[1]"  SITE  "37";
+LOCATE  COMP  "RD[2]"  SITE  "38";
+LOCATE  COMP  "RD[3]"  SITE  "39";
+LOCATE  COMP  "RD[4]"  SITE  "40";
+LOCATE  COMP  "RD[5]"  SITE  "41";
+LOCATE  COMP  "RD[6]"  SITE  "42";
+LOCATE  COMP  "RD[7]"  SITE  "43";
+LOCATE  COMP  "UFMCLK"  SITE  "29";
+LOCATE  COMP  "UFMSDI"  SITE  "30";
+LOCATE  COMP  "UFMSDO"  SITE  "27";
+LOCATE  COMP  "nCCAS"  SITE  "9";
+LOCATE  COMP  "nCRAS"  SITE  "17";
+LOCATE  COMP  "nFWE"  SITE  "28";
+LOCATE  COMP  "nRCAS"  SITE  "52";
+LOCATE  COMP  "nRCS"  SITE  "57";
+LOCATE  COMP  "nRRAS"  SITE  "54";
+LOCATE  COMP  "nRWE"  SITE  "49";
+LOCATE  COMP  "nUFMCS"  SITE  "77";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:34 2023
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html new file mode 100644 index 0000000..f7c9130 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html @@ -0,0 +1,327 @@ + +Place & Route Report + + +
    PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:28 2023
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
+RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
+RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset
+D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
+
+
+Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            -5.122       452301       0.304        0            07           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 7 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
+Tue Aug 15 05:03:28 2023
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
+Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)   67+4(JTAG)/80      89% used
+                  67+4(JTAG)/79      90% bonded
+
+   SLICE             75/320          23% used
+
+
+
+Number of Signals: 285
+Number of Connections: 674
+WARNING - par: Placement timing preferences are hard to meet. However, placement will continue. Use static timing analysis to identify errors.
+
+Pin Constraint Summary:
+   66 out of 67 pins locked (98% locked).
+
+The following 2 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 40)
+    PHI2_c (driver: PHI2, clk load #: 13)
+
+WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0)
+
+WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+No signal is selected as Global Set/Reset.
+.
+Starting Placer Phase 0.
+.............
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+...............
+Placer score = 121531.
+Finished Placer Phase 1.  REAL time: 4 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  119079
+Finished Placer Phase 2.  REAL time: 4 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 0 out of 8 (0%)
+  General PIO: 3 out of 80 (3%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13
+  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7, ce load = 0, sr load = 0
+
+  PRIMARY  : 2 out of 8 (25%)
+  SECONDARY: 1 out of 8 (12%)
+
+
+
+
+I/O Usage Summary (final):
+   67 + 4(JTAG) out of 80 (88.8%) PIO sites used.
+   67 + 4(JTAG) out of 79 (89.9%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 14 / 19 ( 73%) | 2.5V       | -         |
+| 1        | 20 / 20 (100%) | 2.5V       | -         |
+| 2        | 16 / 20 ( 80%) | 2.5V       | -         |
+| 3        | 17 / 20 ( 85%) | 2.5V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 3 secs 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+0 connections routed; 674 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=6 clock_loads=4
+
+Completed router resource preassignment. Real time: 7 secs 
+
+Start NBR router at 05:03:35 08/15/23
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 05:03:35 08/15/23
+
+Start NBR section for initial routing at 05:03:35 08/15/23
+Level 1, iteration 1
+2(0.00%) conflicts; 536(79.53%) untouched conns; 481988 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.914ns/-481.988ns; real time: 7 secs 
+Level 2, iteration 1
+7(0.02%) conflicts; 473(70.18%) untouched conns; 424953 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.988ns/-424.953ns; real time: 7 secs 
+Level 3, iteration 1
+12(0.03%) conflicts; 254(37.69%) untouched conns; 455640 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -5.118ns/-455.640ns; real time: 7 secs 
+Level 4, iteration 1
+6(0.01%) conflicts; 0(0.00%) untouched conn; 465237 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -5.122ns/-465.237ns; real time: 7 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 05:03:35 08/15/23
+Level 4, iteration 1
+6(0.01%) conflicts; 0(0.00%) untouched conn; 461186 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.992ns/-461.186ns; real time: 7 secs 
+Level 4, iteration 2
+3(0.01%) conflicts; 0(0.00%) untouched conn; 460933 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.992ns/-460.933ns; real time: 7 secs 
+Level 4, iteration 3
+2(0.00%) conflicts; 0(0.00%) untouched conn; 461063 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.992ns/-461.063ns; real time: 7 secs 
+Level 4, iteration 4
+1(0.00%) conflict; 0(0.00%) untouched conn; 461063 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -4.992ns/-461.063ns; real time: 7 secs 
+Level 4, iteration 5
+0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -5.122ns/-468.515ns; real time: 7 secs 
+
+Start NBR section for performance tuning (iteration 1) at 05:03:35 08/15/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -5.122ns/-468.515ns; real time: 7 secs 
+
+Start NBR section for re-routing at 05:03:35 08/15/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -5.122ns/-468.515ns; real time: 7 secs 
+
+Start NBR section for post-routing at 05:03:35 08/15/23
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 260 (38.58%)
+  Estimated worst slack<setup> : -5.122ns
+  Timing score<setup> : 452301
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=6 clock_loads=4
+
+Total CPU time 7 secs 
+Total REAL time: 7 secs 
+Completely routed.
+End of route.  674 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 452301 
+
+Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = -5.122
+PAR_SUMMARY::Timing score<setup/<ns>> = 452.301
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.304
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 7 secs 
+Total REAL time to completion: 7 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html new file mode 100644 index 0000000..d0630a7 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html @@ -0,0 +1,83 @@ + +Project Summary + + +
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    RAM2GS_LCMXO2_640HC project summary
    Module Name:RAM2GS_LCMXO2_640HCSynthesis:Lattice LSE
    Implementation Name:impl1Strategy Name:Strategy1
    Last Process:JEDEC FileState:Passed
    Target Device:LCMXO2-640HC-4TG100CDevice Family:MachXO2
    Device Type:LCMXO2-640HCPackage Type:TQFP100
    Performance grade:4Operating conditions:COM
    Logic preference file:RAM2GS_LCMXO2_640HC.lpf
    Physical Preference file:impl1/RAM2GS_LCMXO2_640HC_impl1.prf
    Product Version:3.12.1.454Patch Version:
    Updated:2023/08/15 05:03:41
    Implementation Location:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1
    Project File:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html new file mode 100644 index 0000000..ea92308 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html @@ -0,0 +1,430 @@ + +Lattice Map TRACE Report + + +
    Map TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:25 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (245 errors)
    • 
+                459 items scored, 245 timing errors detected.
+Warning: 139.762MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (104 errors)
    • 
+                113 items scored, 104 timing errors detected.
+Warning:  50.592MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+            459 items scored, 245 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 3.815ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i13  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               6.873ns  (28.2% logic, 71.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      6.873ns physical path delay SLICE_0 to SLICE_57 exceeds
+      3.340ns delay constraint less
+      0.282ns CE_SET requirement (totaling 3.058ns) by 3.815ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452    SLICE_0.CLK to     SLICE_0.Q0 SLICE_0 (from RCLK_c)
+ROUTE         3   e 1.234     SLICE_0.Q0 to    SLICE_85.B0 FS_13
+CTOF_DEL    ---     0.495    SLICE_85.B0 to    SLICE_85.F0 SLICE_85
+ROUTE         5   e 1.234    SLICE_85.F0 to    SLICE_57.A1 n10
+CTOF_DEL    ---     0.495    SLICE_57.A1 to    SLICE_57.F1 SLICE_57
+ROUTE         2   e 1.234    SLICE_57.F1 to    SLICE_84.A0 n2367
+CTOF_DEL    ---     0.495    SLICE_84.A0 to    SLICE_84.F0 SLICE_84
+ROUTE         1   e 1.234    SLICE_84.F0 to    SLICE_57.CE RCLK_c_enable_15 (to RCLK_c)
+                  --------
+                    6.873   (28.2% logic, 71.8% route), 4 logic levels.
+
+Warning: 139.762MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+            113 items scored, 104 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 4.837ns (weighted slack = -9.674ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               9.577ns  (30.6% logic, 69.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.577ns physical path delay SLICE_101 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.307ns CE_SET requirement (totaling 4.740ns) by 4.837ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452  SLICE_101.CLK to   SLICE_101.Q1 SLICE_101 (from PHI2_c)
+ROUTE         1   e 1.234   SLICE_101.Q1 to   SLICE_100.C1 Bank_7
+CTOF_DEL    ---     0.495   SLICE_100.C1 to   SLICE_100.F1 SLICE_100
+ROUTE         1   e 1.234   SLICE_100.F1 to    SLICE_74.B1 n2277
+CTOF_DEL    ---     0.495    SLICE_74.B1 to    SLICE_74.F1 SLICE_74
+ROUTE         8   e 1.234    SLICE_74.F1 to    SLICE_91.B1 n26
+CTOF_DEL    ---     0.495    SLICE_91.B1 to    SLICE_91.F1 SLICE_91
+ROUTE         1   e 1.234    SLICE_91.F1 to    SLICE_88.D0 n2362
+CTOF_DEL    ---     0.495    SLICE_88.D0 to    SLICE_88.F0 SLICE_88
+ROUTE         3   e 0.480    SLICE_88.F0 to    SLICE_88.C1 C1Submitted_N_237
+CTOF_DEL    ---     0.495    SLICE_88.C1 to    SLICE_88.F1 SLICE_88
+ROUTE         1   e 1.234    SLICE_88.F1 to    SLICE_19.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    9.577   (30.6% logic, 69.4% route), 6 logic levels.
+
+Warning:  50.592MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 299.401000 MHz ; |  299.401 MHz|  139.762 MHz|   4 *
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |   99.079 MHz|   50.592 MHz|   6 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+2 preferences(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+n26                                     |       8|      78|     22.35%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 349  Score: 848079
+Cumulative negative slack: 584487
+
+Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:25 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (0 errors)
    •             459 items scored, 0 timing errors detected.
+
+
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+            459 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.351ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.332ns  (40.1% logic, 59.9% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.332ns physical path delay SLICE_106 to SLICE_106 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
+
+ Physical Path Details:
+
+      Data path SLICE_106 to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133  SLICE_106.CLK to   SLICE_106.Q0 SLICE_106 (from RCLK_c)
+ROUTE         1   e 0.199   SLICE_106.Q0 to   SLICE_106.M1 n736 (to RCLK_c)
+                  --------
+                    0.332   (40.1% logic, 59.9% route), 1 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.447ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.434ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133   SLICE_15.CLK to    SLICE_15.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2   e 0.199    SLICE_15.Q0 to    SLICE_15.C0 C1Submitted
+CTOF_DEL    ---     0.101    SLICE_15.C0 to    SLICE_15.F0 SLICE_15
+ROUTE         1   e 0.001    SLICE_15.F0 to   SLICE_15.DI0 n1398 (to PHI2_c)
+                  --------
+                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 299.401000 MHz ; |     0.000 ns|     0.351 ns|   1  
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |     0.000 ns|     0.447 ns|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 349 (setup), 0 (hold)
+Score: 848079 (setup), 0 (hold)
+Cumulative negative slack: 584487 (584487+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html new file mode 100644 index 0000000..7c66cde --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html @@ -0,0 +1,2245 @@ + +Lattice TRACE Report + + +
    Place & Route TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:36 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (264 errors)
    • 
+                459 items scored, 264 timing errors detected.
+Warning: 160.205MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (85 errors)
    • 
+                113 items scored, 85 timing errors detected.
+Warning:  65.729MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+            459 items scored, 264 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 2.902ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI_417  (to RCLK_c +)
+
+   Delay:               6.076ns  (40.0% logic, 60.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.076ns physical path delay SLICE_1 to SLICE_45 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.902ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_45:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C8C.CLK to       R6C8C.Q1 SLICE_1 (from RCLK_c)
+ROUTE         5     0.984       R6C8C.Q1 to       R4C8D.D1 FS_12
+CTOF_DEL    ---     0.495       R4C8D.D1 to       R4C8D.F1 SLICE_80
+ROUTE         3     1.598       R4C8D.F1 to       R4C7B.C1 n2375
+CTOF_DEL    ---     0.495       R4C7B.C1 to       R4C7B.F1 SLICE_95
+ROUTE         1     0.436       R4C7B.F1 to       R4C7A.C1 n7
+CTOF_DEL    ---     0.495       R4C7A.C1 to       R4C7A.F1 SLICE_45
+ROUTE         1     0.626       R4C7A.F1 to       R4C7A.D0 n2174
+CTOF_DEL    ---     0.495       R4C7A.D0 to       R4C7A.F0 SLICE_45
+ROUTE         1     0.000       R4C7A.F0 to      R4C7A.DI0 UFMSDI_N_231 (to RCLK_c)
+                  --------
+                    6.076   (40.0% logic, 60.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C8C.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_45:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C7A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.710ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i14  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI_417  (to RCLK_c +)
+
+   Delay:               5.884ns  (41.3% logic, 58.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.884ns physical path delay SLICE_0 to SLICE_45 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.710ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_45:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C8D.CLK to       R6C8D.Q1 SLICE_0 (from RCLK_c)
+ROUTE         5     0.792       R6C8D.Q1 to       R4C8D.C1 FS_14
+CTOF_DEL    ---     0.495       R4C8D.C1 to       R4C8D.F1 SLICE_80
+ROUTE         3     1.598       R4C8D.F1 to       R4C7B.C1 n2375
+CTOF_DEL    ---     0.495       R4C7B.C1 to       R4C7B.F1 SLICE_95
+ROUTE         1     0.436       R4C7B.F1 to       R4C7A.C1 n7
+CTOF_DEL    ---     0.495       R4C7A.C1 to       R4C7A.F1 SLICE_45
+ROUTE         1     0.626       R4C7A.F1 to       R4C7A.D0 n2174
+CTOF_DEL    ---     0.495       R4C7A.D0 to       R4C7A.F0 SLICE_45
+ROUTE         1     0.000       R4C7A.F0 to      R4C7A.DI0 UFMSDI_N_231 (to RCLK_c)
+                  --------
+                    5.884   (41.3% logic, 58.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C8D.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_45:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C7A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.665ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr2_383  (from RCLK_c +)
+   Destination:    FF         Data in        nRCS_396  (to RCLK_c +)
+
+   Delay:               5.839ns  (41.7% logic, 58.3% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.839ns physical path delay SLICE_16 to SLICE_61 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.665ns
+
+ Physical Path Details:
+
+      Data path SLICE_16 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C9B.CLK to       R4C9B.Q1 SLICE_16 (from RCLK_c)
+ROUTE         3     1.000       R4C9B.Q1 to       R6C9D.A0 CASr2
+CTOF_DEL    ---     0.495       R6C9D.A0 to       R6C9D.F0 SLICE_96
+ROUTE         2     0.976       R6C9D.F0 to       R6C9C.A0 nRCS_N_146
+CTOF_DEL    ---     0.495       R6C9C.A0 to       R6C9C.F0 SLICE_81
+ROUTE         2     0.995       R6C9C.F0 to      R6C11D.A1 nRCS_N_142
+CTOF_DEL    ---     0.495      R6C11D.A1 to      R6C11D.F1 SLICE_61
+ROUTE         1     0.436      R6C11D.F1 to      R6C11D.C0 nRCS_N_141
+CTOF_DEL    ---     0.495      R6C11D.C0 to      R6C11D.F0 SLICE_61
+ROUTE         1     0.000      R6C11D.F0 to     R6C11D.DI0 nRCS_N_136 (to RCLK_c)
+                  --------
+                    5.839   (41.7% logic, 58.3% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C9B.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to     R6C11D.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.621ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               5.679ns  (34.1% logic, 65.9% route), 4 logic levels.
+
+ Constraint Details:
+
+      5.679ns physical path delay SLICE_9 to SLICE_57 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 3.058ns) by 2.621ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C9A.CLK to       R6C9A.Q0 SLICE_9 (from RCLK_c)
+ROUTE         3     1.320       R6C9A.Q0 to       R4C8A.A0 FS_15
+CTOF_DEL    ---     0.495       R4C8A.A0 to       R4C8A.F0 SLICE_85
+ROUTE         5     0.793       R4C8A.F0 to       R4C8B.C1 n10
+CTOF_DEL    ---     0.495       R4C8B.C1 to       R4C8B.F1 SLICE_57
+ROUTE         2     0.976       R4C8B.F1 to       R4C8C.A0 n2367
+CTOF_DEL    ---     0.495       R4C8C.A0 to       R4C8C.F0 SLICE_84
+ROUTE         1     0.653       R4C8C.F0 to       R4C8B.CE RCLK_c_enable_15 (to RCLK_c)
+                  --------
+                    5.679   (34.1% logic, 65.9% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C9A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C8B.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.513ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               5.571ns  (34.8% logic, 65.2% route), 4 logic levels.
+
+ Constraint Details:
+
+      5.571ns physical path delay SLICE_1 to SLICE_57 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 3.058ns) by 2.513ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C8C.CLK to       R6C8C.Q1 SLICE_1 (from RCLK_c)
+ROUTE         5     0.984       R6C8C.Q1 to       R4C8D.D1 FS_12
+CTOF_DEL    ---     0.495       R4C8D.D1 to       R4C8D.F1 SLICE_80
+ROUTE         3     1.021       R4C8D.F1 to       R4C8B.B1 n2375
+CTOF_DEL    ---     0.495       R4C8B.B1 to       R4C8B.F1 SLICE_57
+ROUTE         2     0.976       R4C8B.F1 to       R4C8C.A0 n2367
+CTOF_DEL    ---     0.495       R4C8C.A0 to       R4C8C.F0 SLICE_84
+ROUTE         1     0.653       R4C8C.F0 to       R4C8B.CE RCLK_c_enable_15 (to RCLK_c)
+                  --------
+                    5.571   (34.8% logic, 65.2% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C8C.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C8B.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.487ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i3  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               5.545ns  (34.9% logic, 65.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      5.545ns physical path delay SLICE_8 to SLICE_57 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.282ns CE_SET requirement (totaling 3.058ns) by 2.487ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7C.CLK to       R6C7C.Q0 SLICE_8 (from RCLK_c)
+ROUTE         2     1.306       R6C7C.Q0 to       R4C7D.A1 FS_3
+CTOF_DEL    ---     0.495       R4C7D.A1 to       R4C7D.F1 SLICE_86
+ROUTE         1     1.004       R4C7D.F1 to       R4C7D.B0 n14
+CTOF_DEL    ---     0.495       R4C7D.B0 to       R4C7D.F0 SLICE_86
+ROUTE         1     0.645       R4C7D.F0 to       R4C8C.D0 n4_adj_7
+CTOF_DEL    ---     0.495       R4C8C.D0 to       R4C8C.F0 SLICE_84
+ROUTE         1     0.653       R4C8C.F0 to       R4C8B.CE RCLK_c_enable_15 (to RCLK_c)
+                  --------
+                    5.545   (34.9% logic, 65.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C7C.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_57:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C8B.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.479ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        nUFMCS_415  (to RCLK_c +)
+
+   Delay:               5.653ns  (43.0% logic, 57.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.653ns physical path delay SLICE_9 to SLICE_70 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.479ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C9A.CLK to       R6C9A.Q0 SLICE_9 (from RCLK_c)
+ROUTE         3     1.320       R6C9A.Q0 to       R4C8A.A0 FS_15
+CTOF_DEL    ---     0.495       R4C8A.A0 to       R4C8A.F0 SLICE_85
+ROUTE         5     0.640       R4C8A.F0 to       R4C9D.D1 n10
+CTOF_DEL    ---     0.495       R4C9D.D1 to       R4C9D.F1 SLICE_76
+ROUTE         2     0.635       R4C9D.F1 to       R4C9A.D1 n2368
+CTOF_DEL    ---     0.495       R4C9A.D1 to       R4C9A.F1 SLICE_70
+ROUTE         1     0.626       R4C9A.F1 to       R4C9A.D0 n64
+CTOF_DEL    ---     0.495       R4C9A.D0 to       R4C9A.F0 SLICE_70
+ROUTE         1     0.000       R4C9A.F0 to      R4C9A.DI0 nUFMCS_N_199 (to RCLK_c)
+                  --------
+                    5.653   (43.0% logic, 57.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C9A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_70:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C9A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.452ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               5.626ns  (43.2% logic, 56.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.626ns physical path delay SLICE_9 to SLICE_44 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.452ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C9A.CLK to       R6C9A.Q0 SLICE_9 (from RCLK_c)
+ROUTE         3     1.320       R6C9A.Q0 to       R4C8A.A0 FS_15
+CTOF_DEL    ---     0.495       R4C8A.A0 to       R4C8A.F0 SLICE_85
+ROUTE         5     0.672       R4C8A.F0 to       R4C8A.D1 n10
+CTOF_DEL    ---     0.495       R4C8A.D1 to       R4C8A.F1 SLICE_85
+ROUTE         1     0.766       R4C8A.F1 to       R4C6B.C1 n2267
+CTOF_DEL    ---     0.495       R4C6B.C1 to       R4C6B.F1 SLICE_44
+ROUTE         1     0.436       R4C6B.F1 to       R4C6B.C0 n1893
+CTOF_DEL    ---     0.495       R4C6B.C0 to       R4C6B.F0 SLICE_44
+ROUTE         1     0.000       R4C6B.F0 to      R4C6B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    5.626   (43.2% logic, 56.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C9A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C6B.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.438ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr3_384  (from RCLK_c +)
+   Destination:    FF         Data in        nRCS_396  (to RCLK_c +)
+
+   Delay:               5.612ns  (43.3% logic, 56.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.612ns physical path delay SLICE_5 to SLICE_61 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.438ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C7A.CLK to       R6C7A.Q0 SLICE_5 (from RCLK_c)
+ROUTE         2     0.773       R6C7A.Q0 to       R6C9D.C0 CASr3
+CTOF_DEL    ---     0.495       R6C9D.C0 to       R6C9D.F0 SLICE_96
+ROUTE         2     0.976       R6C9D.F0 to       R6C9C.A0 nRCS_N_146
+CTOF_DEL    ---     0.495       R6C9C.A0 to       R6C9C.F0 SLICE_81
+ROUTE         2     0.995       R6C9C.F0 to      R6C11D.A1 nRCS_N_142
+CTOF_DEL    ---     0.495      R6C11D.A1 to      R6C11D.F1 SLICE_61
+ROUTE         1     0.436      R6C11D.F1 to      R6C11D.C0 nRCS_N_141
+CTOF_DEL    ---     0.495      R6C11D.C0 to      R6C11D.F0 SLICE_61
+ROUTE         1     0.000      R6C11D.F0 to     R6C11D.DI0 nRCS_N_136 (to RCLK_c)
+                  --------
+                    5.612   (43.3% logic, 56.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C7A.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_61:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to     R6C11D.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.423ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i13  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               5.597ns  (43.5% logic, 56.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      5.597ns physical path delay SLICE_0 to SLICE_44 exceeds
+      3.340ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 3.174ns) by 2.423ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R6C8D.CLK to       R6C8D.Q0 SLICE_0 (from RCLK_c)
+ROUTE         3     1.433       R6C8D.Q0 to       R6C6C.B0 FS_13
+CTOF_DEL    ---     0.495       R6C6C.B0 to       R6C6C.F0 SLICE_105
+ROUTE         1     0.315       R6C6C.F0 to       R6C6A.D1 n12
+CTOF_DEL    ---     0.495       R6C6A.D1 to       R6C6A.F1 SLICE_82
+ROUTE         3     0.981       R6C6A.F1 to       R4C6B.D1 n13_adj_6
+CTOF_DEL    ---     0.495       R4C6B.D1 to       R4C6B.F1 SLICE_44
+ROUTE         1     0.436       R4C6B.F1 to       R4C6B.C0 n1893
+CTOF_DEL    ---     0.495       R4C6B.C0 to       R4C6B.F0 SLICE_44
+ROUTE         1     0.000       R4C6B.F0 to      R4C6B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    5.597   (43.5% logic, 56.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R6C8D.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     3.070       62.PADDI to      R4C6B.CLK RCLK_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning: 160.205MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+            113 items scored, 85 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 2.561ns (weighted slack = -5.122ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               7.301ns  (40.1% logic, 59.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.301ns physical path delay SLICE_103 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 2.561ns
+
+ Physical Path Details:
+
+      Data path SLICE_103 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q1 SLICE_103 (from PHI2_c)
+ROUTE         1     1.023       R5C9B.Q1 to       R5C7A.B0 Bank_3
+CTOF_DEL    ---     0.495       R5C7A.B0 to       R5C7A.F0 SLICE_68
+ROUTE         1     0.626       R5C7A.F0 to       R5C7D.D1 n2287
+CTOF_DEL    ---     0.495       R5C7D.D1 to       R5C7D.F1 SLICE_74
+ROUTE         8     0.693       R5C7D.F1 to       R5C8A.D1 n26
+CTOF_DEL    ---     0.495       R5C8A.D1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     0.635       R5C9A.F0 to       R5C9A.D1 C1Submitted_N_237
+CTOF_DEL    ---     0.495       R5C9A.D1 to       R5C9A.F1 SLICE_88
+ROUTE         1     0.653       R5C9A.F1 to       R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    7.301   (40.1% logic, 59.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_103:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.184ns (weighted slack = -4.368ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               6.946ns  (35.0% logic, 65.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.946ns physical path delay SLICE_103 to SLICE_10 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.285ns LSR_SET requirement (totaling 4.762ns) by 2.184ns
+
+ Physical Path Details:
+
+      Data path SLICE_103 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q1 SLICE_103 (from PHI2_c)
+ROUTE         1     1.023       R5C9B.Q1 to       R5C7A.B0 Bank_3
+CTOF_DEL    ---     0.495       R5C7A.B0 to       R5C7A.F0 SLICE_68
+ROUTE         1     0.626       R5C7A.F0 to       R5C7D.D1 n2287
+CTOF_DEL    ---     0.495       R5C7D.D1 to       R5C7D.F1 SLICE_74
+ROUTE         8     0.693       R5C7D.F1 to       R5C8A.D1 n26
+CTOF_DEL    ---     0.495       R5C8A.D1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     1.428       R5C9A.F0 to      R3C8A.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    6.946   (35.0% logic, 65.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_103:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R3C8A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.184ns (weighted slack = -4.368ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i3  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               6.946ns  (35.0% logic, 65.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.946ns physical path delay SLICE_103 to SLICE_15 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.285ns LSR_SET requirement (totaling 4.762ns) by 2.184ns
+
+ Physical Path Details:
+
+      Data path SLICE_103 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q1 SLICE_103 (from PHI2_c)
+ROUTE         1     1.023       R5C9B.Q1 to       R5C7A.B0 Bank_3
+CTOF_DEL    ---     0.495       R5C7A.B0 to       R5C7A.F0 SLICE_68
+ROUTE         1     0.626       R5C7A.F0 to       R5C7D.D1 n2287
+CTOF_DEL    ---     0.495       R5C7D.D1 to       R5C7D.F1 SLICE_74
+ROUTE         8     0.693       R5C7D.F1 to       R5C8A.D1 n26
+CTOF_DEL    ---     0.495       R5C8A.D1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     1.428       R5C9A.F0 to      R3C8B.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    6.946   (35.0% logic, 65.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_103:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R3C8B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.161ns (weighted slack = -4.322ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.901ns  (42.4% logic, 57.6% route), 6 logic levels.
+
+ Constraint Details:
+
+      6.901ns physical path delay SLICE_101 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 2.161ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C7C.CLK to       R4C7C.Q0 SLICE_101 (from PHI2_c)
+ROUTE         1     0.623       R4C7C.Q0 to       R5C7A.D0 Bank_6
+CTOF_DEL    ---     0.495       R5C7A.D0 to       R5C7A.F0 SLICE_68
+ROUTE         1     0.626       R5C7A.F0 to       R5C7D.D1 n2287
+CTOF_DEL    ---     0.495       R5C7D.D1 to       R5C7D.F1 SLICE_74
+ROUTE         8     0.693       R5C7D.F1 to       R5C8A.D1 n26
+CTOF_DEL    ---     0.495       R5C8A.D1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     0.635       R5C9A.F0 to       R5C9A.D1 C1Submitted_N_237
+CTOF_DEL    ---     0.495       R5C9A.D1 to       R5C9A.F1 SLICE_88
+ROUTE         1     0.653       R5C9A.F1 to       R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.901   (42.4% logic, 57.6% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R4C7C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.092ns (weighted slack = -4.184ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.832ns  (42.8% logic, 57.2% route), 6 logic levels.
+
+ Constraint Details:
+
+      6.832ns physical path delay SLICE_101 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 2.092ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C7C.CLK to       R4C7C.Q1 SLICE_101 (from PHI2_c)
+ROUTE         1     0.744       R4C7C.Q1 to       R5C7B.C1 Bank_7
+CTOF_DEL    ---     0.495       R5C7B.C1 to       R5C7B.F1 SLICE_100
+ROUTE         1     0.436       R5C7B.F1 to       R5C7D.C1 n2277
+CTOF_DEL    ---     0.495       R5C7D.C1 to       R5C7D.F1 SLICE_74
+ROUTE         8     0.693       R5C7D.F1 to       R5C8A.D1 n26
+CTOF_DEL    ---     0.495       R5C8A.D1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     0.635       R5C9A.F0 to       R5C9A.D1 C1Submitted_N_237
+CTOF_DEL    ---     0.495       R5C9A.D1 to       R5C9A.F1 SLICE_88
+ROUTE         1     0.653       R5C9A.F1 to       R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.832   (42.8% logic, 57.2% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R4C7C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 2.081ns (weighted slack = -4.162ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i4  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.821ns  (42.9% logic, 57.1% route), 6 logic levels.
+
+ Constraint Details:
+
+      6.821ns physical path delay SLICE_102 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 2.081ns
+
+ Physical Path Details:
+
+      Data path SLICE_102 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C6A.CLK to       R5C6A.Q0 SLICE_102 (from PHI2_c)
+ROUTE         1     0.766       R5C6A.Q0 to       R5C8D.C1 Bank_4
+CTOF_DEL    ---     0.495       R5C8D.C1 to       R5C8D.F1 SLICE_99
+ROUTE         2     0.635       R5C8D.F1 to       R5C8B.D1 n22
+CTOF_DEL    ---     0.495       R5C8B.D1 to       R5C8B.F1 SLICE_79
+ROUTE         7     0.461       R5C8B.F1 to       R5C8A.C1 n2369
+CTOF_DEL    ---     0.495       R5C8A.C1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     0.635       R5C9A.F0 to       R5C9A.D1 C1Submitted_N_237
+CTOF_DEL    ---     0.495       R5C9A.D1 to       R5C9A.F1 SLICE_88
+ROUTE         1     0.653       R5C9A.F1 to       R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.821   (42.9% logic, 57.1% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_102:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C6A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.971ns (weighted slack = -3.942ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.711ns  (43.6% logic, 56.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      6.711ns physical path delay SLICE_93 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 1.971ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C8C.CLK to       R5C8C.Q0 SLICE_93 (from PHI2_c)
+ROUTE         1     0.623       R5C8C.Q0 to       R5C7B.D1 Bank_0
+CTOF_DEL    ---     0.495       R5C7B.D1 to       R5C7B.F1 SLICE_100
+ROUTE         1     0.436       R5C7B.F1 to       R5C7D.C1 n2277
+CTOF_DEL    ---     0.495       R5C7D.C1 to       R5C7D.F1 SLICE_74
+ROUTE         8     0.693       R5C7D.F1 to       R5C8A.D1 n26
+CTOF_DEL    ---     0.495       R5C8A.D1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     0.635       R5C9A.F0 to       R5C9A.D1 C1Submitted_N_237
+CTOF_DEL    ---     0.495       R5C9A.D1 to       R5C9A.F1 SLICE_88
+ROUTE         1     0.653       R5C9A.F1 to       R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.711   (43.6% logic, 56.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.941ns (weighted slack = -3.882ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i1  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               6.681ns  (43.8% logic, 56.2% route), 6 logic levels.
+
+ Constraint Details:
+
+      6.681ns physical path delay SLICE_93 to SLICE_19 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.307ns CE_SET requirement (totaling 4.740ns) by 1.941ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C8C.CLK to       R5C8C.Q1 SLICE_93 (from PHI2_c)
+ROUTE         1     0.626       R5C8C.Q1 to       R5C8D.D1 Bank_1
+CTOF_DEL    ---     0.495       R5C8D.D1 to       R5C8D.F1 SLICE_99
+ROUTE         2     0.635       R5C8D.F1 to       R5C8B.D1 n22
+CTOF_DEL    ---     0.495       R5C8B.D1 to       R5C8B.F1 SLICE_79
+ROUTE         7     0.461       R5C8B.F1 to       R5C8A.C1 n2369
+CTOF_DEL    ---     0.495       R5C8A.C1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     0.635       R5C9A.F0 to       R5C9A.D1 C1Submitted_N_237
+CTOF_DEL    ---     0.495       R5C9A.D1 to       R5C9A.F1 SLICE_88
+ROUTE         1     0.653       R5C9A.F1 to       R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    6.681   (43.8% logic, 56.2% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C8C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.784ns (weighted slack = -3.568ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               6.546ns  (37.2% logic, 62.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.546ns physical path delay SLICE_101 to SLICE_10 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.285ns LSR_SET requirement (totaling 4.762ns) by 1.784ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C7C.CLK to       R4C7C.Q0 SLICE_101 (from PHI2_c)
+ROUTE         1     0.623       R4C7C.Q0 to       R5C7A.D0 Bank_6
+CTOF_DEL    ---     0.495       R5C7A.D0 to       R5C7A.F0 SLICE_68
+ROUTE         1     0.626       R5C7A.F0 to       R5C7D.D1 n2287
+CTOF_DEL    ---     0.495       R5C7D.D1 to       R5C7D.F1 SLICE_74
+ROUTE         8     0.693       R5C7D.F1 to       R5C8A.D1 n26
+CTOF_DEL    ---     0.495       R5C8A.D1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     1.428       R5C9A.F0 to      R3C8A.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    6.546   (37.2% logic, 62.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R4C7C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R3C8A.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 1.784ns (weighted slack = -3.568ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               6.546ns  (37.2% logic, 62.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.546ns physical path delay SLICE_101 to SLICE_15 exceeds
+      5.047ns delay constraint less
+      0.000ns skew and
+      0.285ns LSR_SET requirement (totaling 4.762ns) by 1.784ns
+
+ Physical Path Details:
+
+      Data path SLICE_101 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C7C.CLK to       R4C7C.Q0 SLICE_101 (from PHI2_c)
+ROUTE         1     0.623       R4C7C.Q0 to       R5C7A.D0 Bank_6
+CTOF_DEL    ---     0.495       R5C7A.D0 to       R5C7A.F0 SLICE_68
+ROUTE         1     0.626       R5C7A.F0 to       R5C7D.D1 n2287
+CTOF_DEL    ---     0.495       R5C7D.D1 to       R5C7D.F1 SLICE_74
+ROUTE         8     0.693       R5C7D.F1 to       R5C8A.D1 n26
+CTOF_DEL    ---     0.495       R5C8A.D1 to       R5C8A.F1 SLICE_91
+ROUTE         1     0.744       R5C8A.F1 to       R5C9A.C0 n2362
+CTOF_DEL    ---     0.495       R5C9A.C0 to       R5C9A.F0 SLICE_88
+ROUTE         3     1.428       R5C9A.F0 to      R3C8B.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    6.546   (37.2% logic, 62.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_101:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R4C7C.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.539        8.PADDI to      R3C8B.CLK PHI2_c
+                  --------
+                    3.539   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning:  65.729MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 299.401000 MHz ; |  299.401 MHz|  160.205 MHz|   5 *
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |   99.079 MHz|   65.729 MHz|   6 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+2 preferences(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+n26                                     |       8|      63|     18.05%
+                                        |        |        |
+n1996                                   |       1|      49|     14.04%
+                                        |        |        |
+n1997                                   |       1|      46|     13.18%
+                                        |        |        |
+n1995                                   |       1|      45|     12.89%
+                                        |        |        |
+n1998                                   |       1|      38|     10.89%
+                                        |        |        |
+n1994                                   |       1|      37|     10.60%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 349  Score: 452301
+Cumulative negative slack: 370485
+
+Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:36 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf 
+Design file:     ram2gs_lcmxo2_640hc_impl1.ncd
+Preference file: ram2gs_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 299.401000 MHz (0 errors)
    •             459 items scored, 0 timing errors detected.
+
+
  • FREQUENCY NET "PHI2_c" 99.079000 MHz (0 errors)
    •             113 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+            459 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_106 to SLICE_106 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_106 to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C8D.CLK to       R3C8D.Q0 SLICE_106 (from RCLK_c)
+ROUTE         1     0.152       R3C8D.Q0 to       R3C8D.M1 n736 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R3C8D.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_106:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R3C8D.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr_382  (from RCLK_c +)
+   Destination:    FF         Data in        CASr2_383  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_16 to SLICE_16 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_16 to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C9B.CLK to       R4C9B.Q0 SLICE_16 (from RCLK_c)
+ROUTE         1     0.152       R4C9B.Q0 to       R4C9B.M1 CASr (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R4C9B.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R4C9B.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i8  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i9  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_75 to SLICE_75 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_75 to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9D.CLK to       R3C9D.Q0 SLICE_75 (from RCLK_c)
+ROUTE         1     0.152       R3C9D.Q0 to       R3C9D.M1 n732 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R3C9D.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R3C9D.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_79 to SLICE_79 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_79 to SLICE_79:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C8B.CLK to       R5C8B.Q0 SLICE_79 (from RCLK_c)
+ROUTE         1     0.152       R5C8B.Q0 to       R5C8B.M1 n730 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_79:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R5C8B.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_79:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R5C8B.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_81 to SLICE_81 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_81 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R6C9C.CLK to       R6C9C.Q0 SLICE_81 (from RCLK_c)
+ROUTE         1     0.152       R6C9C.Q0 to       R6C9C.M1 n726 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R6C9C.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R6C9C.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i7  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i8  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_97 to SLICE_75 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q1 SLICE_97 (from RCLK_c)
+ROUTE         1     0.152       R3C9A.Q1 to       R3C9D.M0 n733 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R3C9A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_75:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R3C9D.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.304ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
+
+   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.285ns physical path delay SLICE_97 to SLICE_97 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.304ns
+
+ Physical Path Details:
+
+      Data path SLICE_97 to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C9A.CLK to       R3C9A.Q0 SLICE_97 (from RCLK_c)
+ROUTE         1     0.152       R3C9A.Q0 to       R3C9A.M1 n734 (to RCLK_c)
+                  --------
+                    0.285   (46.7% logic, 53.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R3C9A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_97:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to      R3C9A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr_379  (from RCLK_c +)
+   Destination:    FF         Data in        RASr2_380  (to RCLK_c +)
+
+   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.287ns physical path delay SLICE_30 to SLICE_30 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+      Data path SLICE_30 to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R5C10B.CLK to      R5C10B.Q0 SLICE_30 (from RCLK_c)
+ROUTE         2     0.154      R5C10B.Q0 to      R5C10B.M1 RASr (to RCLK_c)
+                  --------
+                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to     R5C10B.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_30:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to     R5C10B.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.306ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              PHI2r2_377  (from RCLK_c +)
+   Destination:    FF         Data in        PHI2r3_378  (to RCLK_c +)
+
+   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.287ns physical path delay SLICE_36 to SLICE_69 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.306ns
+
+ Physical Path Details:
+
+      Data path SLICE_36 to SLICE_69:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R4C10A.CLK to      R4C10A.Q1 SLICE_36 (from RCLK_c)
+ROUTE         3     0.154      R4C10A.Q1 to      R4C10C.M1 PHI2r2 (to RCLK_c)
+                  --------
+                    0.287   (46.3% logic, 53.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_36:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to     R4C10A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_69:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to     R4C10C.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.307ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
+
+   Delay:               0.288ns  (46.2% logic, 53.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.288ns physical path delay SLICE_98 to SLICE_98 meets
+     -0.019ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.307ns
+
+ Physical Path Details:
+
+      Data path SLICE_98 to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133     R6C11A.CLK to      R6C11A.Q0 SLICE_98 (from RCLK_c)
+ROUTE         4     0.155      R6C11A.Q0 to      R6C11A.M1 nRCS_N_139 (to RCLK_c)
+                  --------
+                    0.288   (46.2% logic, 53.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to     R6C11A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_98:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.059       62.PADDI to     R6C11A.CLK RCLK_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+            113 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C8B.CLK to       R3C8B.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2     0.132       R3C8B.Q0 to       R3C8B.A0 C1Submitted
+CTOF_DEL    ---     0.101       R3C8B.A0 to       R3C8B.F0 SLICE_15
+ROUTE         1     0.000       R3C8B.F0 to      R3C8B.DI0 n1398 (to PHI2_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C8B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C8B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.851ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_408  (to PHI2_c -)
+
+   Delay:               0.823ns  (28.4% logic, 71.6% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.823ns physical path delay SLICE_19 to SLICE_50 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.851ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_50:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C9D.CLK to       R5C9D.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.332       R5C9D.Q0 to       R5C6B.D1 CmdEnable
+CTOF_DEL    ---     0.101       R5C6B.D1 to       R5C6B.F1 SLICE_83
+ROUTE         1     0.257       R5C6B.F1 to       R4C6A.CE PHI2_N_120_enable_3 (to PHI2_c)
+                  --------
+                    0.823   (28.4% logic, 71.6% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_50:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R4C6A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.906ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_407  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               0.878ns  (26.7% logic, 73.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.878ns physical path delay SLICE_10 to SLICE_19 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.906ns
+
+ Physical Path Details:
+
+      Data path SLICE_10 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C8A.CLK to       R3C8A.Q0 SLICE_10 (from PHI2_c)
+ROUTE         1     0.501       R3C8A.Q0 to       R5C9A.B1 ADSubmitted
+CTOF_DEL    ---     0.101       R5C9A.B1 to       R5C9A.F1 SLICE_88
+ROUTE         1     0.143       R5C9A.F1 to       R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    0.878   (26.7% logic, 73.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_10:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C8A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.937ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               0.909ns  (48.0% logic, 52.0% route), 4 logic levels.
+
+ Constraint Details:
+
+      0.909ns physical path delay SLICE_15 to SLICE_19 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 0.937ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C8B.CLK to       R3C8B.Q0 SLICE_15 (from PHI2_c)
+ROUTE         2     0.136       R3C8B.Q0 to       R3C9B.D1 C1Submitted
+CTOF_DEL    ---     0.101       R3C9B.D1 to       R3C9B.F1 SLICE_77
+ROUTE         1     0.056       R3C9B.F1 to       R3C9A.C1 n2210
+CTOF_DEL    ---     0.101       R3C9A.C1 to       R3C9A.F1 SLICE_97
+ROUTE         1     0.138       R3C9A.F1 to       R5C9A.C1 n7_adj_5
+CTOF_DEL    ---     0.101       R5C9A.C1 to       R5C9A.F1 SLICE_88
+ROUTE         1     0.143       R5C9A.F1 to       R5C9D.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    0.909   (48.0% logic, 52.0% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C8B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.059ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
+                   FF                        CmdUFMCLK_413
+
+   Delay:               1.031ns  (32.5% logic, 67.5% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.031ns physical path delay SLICE_19 to SLICE_100 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.059ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C9D.CLK to       R5C9D.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.224       R5C9D.Q0 to       R5C6D.C0 CmdEnable
+CTOF_DEL    ---     0.101       R5C6D.C0 to       R5C6D.F0 SLICE_73
+ROUTE         2     0.212       R5C6D.F0 to       R5C6D.A1 n2204
+CTOF_DEL    ---     0.101       R5C6D.A1 to       R5C6D.F1 SLICE_73
+ROUTE         2     0.260       R5C6D.F1 to       R5C7B.CE PHI2_N_120_enable_8 (to PHI2_c)
+                  --------
+                    1.031   (32.5% logic, 67.5% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C7B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.059ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:               1.031ns  (32.5% logic, 67.5% route), 3 logic levels.
+
+ Constraint Details:
+
+      1.031ns physical path delay SLICE_19 to SLICE_99 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.059ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C9D.CLK to       R5C9D.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.224       R5C9D.Q0 to       R5C6D.C0 CmdEnable
+CTOF_DEL    ---     0.101       R5C6D.C0 to       R5C6D.F0 SLICE_73
+ROUTE         2     0.212       R5C6D.F0 to       R5C6D.A1 n2204
+CTOF_DEL    ---     0.101       R5C6D.A1 to       R5C6D.F1 SLICE_73
+ROUTE         2     0.260       R5C6D.F1 to       R5C8D.CE PHI2_N_120_enable_8 (to PHI2_c)
+                  --------
+                    1.031   (32.5% logic, 67.5% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C8D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.106ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_411  (to PHI2_c -)
+
+   Delay:               1.078ns  (40.4% logic, 59.6% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.078ns physical path delay SLICE_19 to SLICE_20 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.106ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C9D.CLK to       R5C9D.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.224       R5C9D.Q0 to       R5C6D.C0 CmdEnable
+CTOF_DEL    ---     0.101       R5C6D.C0 to       R5C6D.F0 SLICE_73
+ROUTE         2     0.137       R5C6D.F0 to       R5C7D.D0 n2204
+CTOF_DEL    ---     0.101       R5C7D.D0 to       R5C7D.F0 SLICE_74
+ROUTE         2     0.138       R5C7D.F0 to       R3C7C.D1 n2220
+CTOF_DEL    ---     0.101       R3C7C.D1 to       R3C7C.F1 SLICE_89
+ROUTE         1     0.143       R3C7C.F1 to       R3C7D.CE PHI2_N_120_enable_7 (to PHI2_c)
+                  --------
+                    1.078   (40.4% logic, 59.6% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_20:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C7D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.106ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_410  (to PHI2_c -)
+
+   Delay:               1.078ns  (40.4% logic, 59.6% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.078ns physical path delay SLICE_19 to SLICE_24 meets
+     -0.028ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.028ns) by 1.106ns
+
+ Physical Path Details:
+
+      Data path SLICE_19 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C9D.CLK to       R5C9D.Q0 SLICE_19 (from PHI2_c)
+ROUTE         2     0.224       R5C9D.Q0 to       R5C6D.C0 CmdEnable
+CTOF_DEL    ---     0.101       R5C6D.C0 to       R5C6D.F0 SLICE_73
+ROUTE         2     0.137       R5C6D.F0 to       R5C7D.D0 n2204
+CTOF_DEL    ---     0.101       R5C7D.D0 to       R5C7D.F0 SLICE_74
+ROUTE         2     0.138       R5C7D.F0 to       R3C7C.D0 n2220
+CTOF_DEL    ---     0.101       R3C7C.D0 to       R3C7C.F0 SLICE_89
+ROUTE         1     0.143       R3C7C.F0 to       R3C7B.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    1.078   (40.4% logic, 59.6% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_24:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C7B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 5.504ns (weighted slack = 11.008ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_408  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_385  (to PHI2_c +)
+
+   Delay:               0.444ns  (52.7% logic, 47.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.444ns physical path delay SLICE_50 to SLICE_33 meets
+     -0.013ns DIN_HLD and
+     -5.047ns delay constraint less
+      0.000ns skew requirement (totaling -5.060ns) by 5.504ns
+
+ Physical Path Details:
+
+      Data path SLICE_50 to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C6A.CLK to       R4C6A.Q0 SLICE_50 (from PHI2_c)
+ROUTE         1     0.210       R4C6A.Q0 to       R4C6C.A0 XOR8MEG
+CTOF_DEL    ---     0.101       R4C6C.A0 to       R4C6C.F0 SLICE_33
+ROUTE         1     0.000       R4C6C.F0 to      R4C6C.DI0 RA11_N_184 (to PHI2_c)
+                  --------
+                    0.444   (52.7% logic, 47.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_50:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R4C6A.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R4C6C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 5.899ns (weighted slack = 11.798ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i1  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.839ns  (52.0% logic, 48.0% route), 4 logic levels.
+
+ Constraint Details:
+
+      0.839ns physical path delay SLICE_93 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+     -5.047ns delay constraint less
+      0.000ns skew requirement (totaling -5.060ns) by 5.899ns
+
+ Physical Path Details:
+
+      Data path SLICE_93 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C8C.CLK to       R5C8C.Q1 SLICE_93 (from PHI2_c)
+ROUTE         1     0.133       R5C8C.Q1 to       R5C8D.D1 Bank_1
+CTOF_DEL    ---     0.101       R5C8D.D1 to       R5C8D.F1 SLICE_99
+ROUTE         2     0.214       R5C8D.F1 to       R3C8B.A1 n22
+CTOF_DEL    ---     0.101       R3C8B.A1 to       R3C8B.F1 SLICE_15
+ROUTE         1     0.056       R3C8B.F1 to       R3C8B.C0 n2365
+CTOF_DEL    ---     0.101       R3C8B.C0 to       R3C8B.F0 SLICE_15
+ROUTE         1     0.000       R3C8B.F0 to      R3C8B.DI0 n1398 (to PHI2_c)
+                  --------
+                    0.839   (52.0% logic, 48.0% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R5C8C.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     1.240        8.PADDI to      R3C8B.CLK PHI2_c
+                  --------
+                    1.240   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 299.401000 MHz ; |     0.000 ns|     0.304 ns|   1  
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 99.079000 MHz ;  |     0.000 ns|     0.379 ns|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 6
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 299.401000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 99.079000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 349 (setup), 0 (hold)
+Score: 452301 (setup), 0 (hold)
+Cumulative negative slack: 370485 (370485+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_drc.log b/CPLD/LCMXO2-640HC/impl1/RAM2GS_drc.log new file mode 100644 index 0000000..e161627 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_drc.log @@ -0,0 +1,15 @@ +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 309 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse.twr b/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse.twr new file mode 100644 index 0000000..4586322 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse.twr @@ -0,0 +1,297 @@ +-------------------------------------------------------------------------------- +Lattice Synthesis Timing Report, Version +Tue Aug 15 05:03:23 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Design: RAM2GS +Constraint file: +Report level: verbose report, limited to 3 items per constraint +-------------------------------------------------------------------------------- + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c] + 122 items scored, 119 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 7.418ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i1 (from PHI2_c +) + Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -) + + Delay: 9.633ns (30.2% logic, 69.8% route), 6 logic levels. + + Constraint Details: + + 9.633ns data_path Bank_i1 to CmdEnable_405 violates + 2.500ns delay constraint less + 0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns + + Path Details: Bank_i1 to CmdEnable_405 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q Bank_i1 (from PHI2_c) +Route 1 e 0.941 Bank[1] +LUT4 --- 0.493 D to Z i8_4_lut +Route 2 e 1.141 n22 +LUT4 --- 0.493 B to Z i11_3_lut_rep_20 +Route 7 e 1.502 n2369 +LUT4 --- 0.493 A to Z i1_2_lut_rep_13_3_lut +Route 1 e 0.941 n2362 +LUT4 --- 0.493 D to Z i1_4_lut_adj_13 +Route 3 e 1.258 C1Submitted_N_237 +LUT4 --- 0.493 C to Z i34_4_lut +Route 1 e 0.941 PHI2_N_120_enable_1 + -------- + 9.633 (30.2% logic, 69.8% route), 6 logic levels. + + +Error: The following path violates requirements by 7.418ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i4 (from PHI2_c +) + Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -) + + Delay: 9.633ns (30.2% logic, 69.8% route), 6 logic levels. + + Constraint Details: + + 9.633ns data_path Bank_i4 to CmdEnable_405 violates + 2.500ns delay constraint less + 0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns + + Path Details: Bank_i4 to CmdEnable_405 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c) +Route 1 e 0.941 Bank[4] +LUT4 --- 0.493 C to Z i8_4_lut +Route 2 e 1.141 n22 +LUT4 --- 0.493 B to Z i11_3_lut_rep_20 +Route 7 e 1.502 n2369 +LUT4 --- 0.493 A to Z i1_2_lut_rep_13_3_lut +Route 1 e 0.941 n2362 +LUT4 --- 0.493 D to Z i1_4_lut_adj_13 +Route 3 e 1.258 C1Submitted_N_237 +LUT4 --- 0.493 C to Z i34_4_lut +Route 1 e 0.941 PHI2_N_120_enable_1 + -------- + 9.633 (30.2% logic, 69.8% route), 6 logic levels. + + +Error: The following path violates requirements by 7.256ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i3 (from PHI2_c +) + Destination: FD1P3AX SP CmdEnable_405 (to PHI2_c -) + + Delay: 9.471ns (30.7% logic, 69.3% route), 6 logic levels. + + Constraint Details: + + 9.471ns data_path Bank_i3 to CmdEnable_405 violates + 2.500ns delay constraint less + 0.285ns LCE_S requirement (totaling 2.215ns) by 7.256ns + + Path Details: Bank_i3 to CmdEnable_405 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q Bank_i3 (from PHI2_c) +Route 1 e 0.941 Bank[3] +LUT4 --- 0.493 B to Z i1989_2_lut +Route 1 e 0.941 n2287 +LUT4 --- 0.493 C to Z i12_4_lut +Route 8 e 1.540 n26 +LUT4 --- 0.493 B to Z i1_2_lut_rep_13_3_lut +Route 1 e 0.941 n2362 +LUT4 --- 0.493 D to Z i1_4_lut_adj_13 +Route 3 e 1.258 C1Submitted_N_237 +LUT4 --- 0.493 C to Z i34_4_lut +Route 1 e 0.941 PHI2_N_120_enable_1 + -------- + 9.471 (30.7% logic, 69.3% route), 6 logic levels. + +Warning: 9.918 ns is the maximum delay for this constraint. + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c] + 498 items scored, 186 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 3.319ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i13 (from RCLK_c +) + Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +) + + Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels. + + Constraint Details: + + 8.159ns data_path FS_610__i13 to nUFMCS_415 violates + 5.000ns delay constraint less + 0.160ns L_S requirement (totaling 4.840ns) by 3.319ns + + Path Details: FS_610__i13 to nUFMCS_415 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q FS_610__i13 (from RCLK_c) +Route 3 e 1.315 FS[13] +LUT4 --- 0.493 B to Z i3_4_lut_adj_7 +Route 5 e 1.405 n10 +LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut +Route 2 e 1.141 n2368 +LUT4 --- 0.493 B to Z i1_2_lut_4_lut +Route 1 e 0.941 n64 +LUT4 --- 0.493 B to Z i1448_4_lut +Route 1 e 0.941 nUFMCS_N_199 + -------- + 8.159 (29.6% logic, 70.4% route), 5 logic levels. + + +Error: The following path violates requirements by 3.319ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i15 (from RCLK_c +) + Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +) + + Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels. + + Constraint Details: + + 8.159ns data_path FS_610__i15 to nUFMCS_415 violates + 5.000ns delay constraint less + 0.160ns L_S requirement (totaling 4.840ns) by 3.319ns + + Path Details: FS_610__i15 to nUFMCS_415 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q FS_610__i15 (from RCLK_c) +Route 3 e 1.315 FS[15] +LUT4 --- 0.493 C to Z i3_4_lut_adj_7 +Route 5 e 1.405 n10 +LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut +Route 2 e 1.141 n2368 +LUT4 --- 0.493 B to Z i1_2_lut_4_lut +Route 1 e 0.941 n64 +LUT4 --- 0.493 B to Z i1448_4_lut +Route 1 e 0.941 nUFMCS_N_199 + -------- + 8.159 (29.6% logic, 70.4% route), 5 logic levels. + + +Error: The following path violates requirements by 3.319ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i16 (from RCLK_c +) + Destination: FD1P3AY D nUFMCS_415 (to RCLK_c +) + + Delay: 8.159ns (29.6% logic, 70.4% route), 5 logic levels. + + Constraint Details: + + 8.159ns data_path FS_610__i16 to nUFMCS_415 violates + 5.000ns delay constraint less + 0.160ns L_S requirement (totaling 4.840ns) by 3.319ns + + Path Details: FS_610__i16 to nUFMCS_415 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.444 CK to Q FS_610__i16 (from RCLK_c) +Route 3 e 1.315 FS[16] +LUT4 --- 0.493 D to Z i3_4_lut_adj_7 +Route 5 e 1.405 n10 +LUT4 --- 0.493 C to Z i1_2_lut_rep_19_3_lut +Route 2 e 1.141 n2368 +LUT4 --- 0.493 B to Z i1_2_lut_4_lut +Route 1 e 0.941 n64 +LUT4 --- 0.493 B to Z i1448_4_lut +Route 1 e 0.941 nUFMCS_N_199 + -------- + 8.159 (29.6% logic, 70.4% route), 5 logic levels. + +Warning: 8.319 ns is the maximum delay for this constraint. + + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 5.000 ns| 19.836 ns| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 5.000 ns| 8.319 ns| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + +-------------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +-------------------------------------------------------------------------------- +n26 | 8| 84| 27.54% + | | | +n1997 | 1| 36| 11.80% + | | | +n1996 | 1| 35| 11.48% + | | | +n1995 | 1| 33| 10.82% + | | | +n10 | 5| 32| 10.49% + | | | +n1998 | 1| 32| 10.49% + | | | +-------------------------------------------------------------------------------- + + +Timing summary: +--------------- + +Timing errors: 305 Score: 1313492 + +Constraints cover 621 paths, 182 nets, and 471 connections (64.2% coverage) + + +Peak memory: 56156160 bytes, TRCE: 2355200 bytes, DLYMAN: 0 bytes +CPU_TIME_REPORT: 0 secs diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html new file mode 100644 index 0000000..22e783c --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html @@ -0,0 +1,362 @@ + +Lattice Synthesis Timing Report + + +
    Lattice Synthesis Timing Report
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Tue Aug 15 05:03:23 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
+            122 items scored, 119 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 7.418ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i1  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
+
+   Delay:                   9.633ns  (30.2% logic, 69.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.633ns data_path Bank_i1 to CmdEnable_405 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
+
+ Path Details: Bank_i1 to CmdEnable_405
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i1 (from PHI2_c)
+Route         1   e 0.941                                  Bank[1]
+LUT4        ---     0.493              D to Z              i8_4_lut
+Route         2   e 1.141                                  n22
+LUT4        ---     0.493              B to Z              i11_3_lut_rep_20
+Route         7   e 1.502                                  n2369
+LUT4        ---     0.493              A to Z              i1_2_lut_rep_13_3_lut
+Route         1   e 0.941                                  n2362
+LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
+Route         3   e 1.258                                  C1Submitted_N_237
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_120_enable_1
+                  --------
+                    9.633  (30.2% logic, 69.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 7.418ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i4  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
+
+   Delay:                   9.633ns  (30.2% logic, 69.8% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.633ns data_path Bank_i4 to CmdEnable_405 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 7.418ns
+
+ Path Details: Bank_i4 to CmdEnable_405
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i4 (from PHI2_c)
+Route         1   e 0.941                                  Bank[4]
+LUT4        ---     0.493              C to Z              i8_4_lut
+Route         2   e 1.141                                  n22
+LUT4        ---     0.493              B to Z              i11_3_lut_rep_20
+Route         7   e 1.502                                  n2369
+LUT4        ---     0.493              A to Z              i1_2_lut_rep_13_3_lut
+Route         1   e 0.941                                  n2362
+LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
+Route         3   e 1.258                                  C1Submitted_N_237
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_120_enable_1
+                  --------
+                    9.633  (30.2% logic, 69.8% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 7.256ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdEnable_405  (to PHI2_c -)
+
+   Delay:                   9.471ns  (30.7% logic, 69.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      9.471ns data_path Bank_i3 to CmdEnable_405 violates
+      2.500ns delay constraint less
+      0.285ns LCE_S requirement (totaling 2.215ns) by 7.256ns
+
+ Path Details: Bank_i3 to CmdEnable_405
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 0.941                                  Bank[3]
+LUT4        ---     0.493              B to Z              i1989_2_lut
+Route         1   e 0.941                                  n2287
+LUT4        ---     0.493              C to Z              i12_4_lut
+Route         8   e 1.540                                  n26
+LUT4        ---     0.493              B to Z              i1_2_lut_rep_13_3_lut
+Route         1   e 0.941                                  n2362
+LUT4        ---     0.493              D to Z              i1_4_lut_adj_13
+Route         3   e 1.258                                  C1Submitted_N_237
+LUT4        ---     0.493              C to Z              i34_4_lut
+Route         1   e 0.941                                  PHI2_N_120_enable_1
+                  --------
+                    9.471  (30.7% logic, 69.3% route), 6 logic levels.
+
+Warning: 9.918 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            498 items scored, 186 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 3.319ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i13  (from RCLK_c +)
+   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
+
+   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.159ns data_path FS_610__i13 to nUFMCS_415 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
+
+ Path Details: FS_610__i13 to nUFMCS_415
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_610__i13 (from RCLK_c)
+Route         3   e 1.315                                  FS[13]
+LUT4        ---     0.493              B to Z              i3_4_lut_adj_7
+Route         5   e 1.405                                  n10
+LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
+Route         2   e 1.141                                  n2368
+LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
+Route         1   e 0.941                                  n64
+LUT4        ---     0.493              B to Z              i1448_4_lut
+Route         1   e 0.941                                  nUFMCS_N_199
+                  --------
+                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
+
+
+Error:  The following path violates requirements by 3.319ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i15  (from RCLK_c +)
+   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
+
+   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.159ns data_path FS_610__i15 to nUFMCS_415 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
+
+ Path Details: FS_610__i15 to nUFMCS_415
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_610__i15 (from RCLK_c)
+Route         3   e 1.315                                  FS[15]
+LUT4        ---     0.493              C to Z              i3_4_lut_adj_7
+Route         5   e 1.405                                  n10
+LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
+Route         2   e 1.141                                  n2368
+LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
+Route         1   e 0.941                                  n64
+LUT4        ---     0.493              B to Z              i1448_4_lut
+Route         1   e 0.941                                  nUFMCS_N_199
+                  --------
+                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
+
+
+Error:  The following path violates requirements by 3.319ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i16  (from RCLK_c +)
+   Destination:    FD1P3AY    D              nUFMCS_415  (to RCLK_c +)
+
+   Delay:                   8.159ns  (29.6% logic, 70.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.159ns data_path FS_610__i16 to nUFMCS_415 violates
+      5.000ns delay constraint less
+      0.160ns L_S requirement (totaling 4.840ns) by 3.319ns
+
+ Path Details: FS_610__i16 to nUFMCS_415
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.444             CK to Q              FS_610__i16 (from RCLK_c)
+Route         3   e 1.315                                  FS[16]
+LUT4        ---     0.493              D to Z              i3_4_lut_adj_7
+Route         5   e 1.405                                  n10
+LUT4        ---     0.493              C to Z              i1_2_lut_rep_19_3_lut
+Route         2   e 1.141                                  n2368
+LUT4        ---     0.493              B to Z              i1_2_lut_4_lut
+Route         1   e 0.941                                  n64
+LUT4        ---     0.493              B to Z              i1448_4_lut
+Route         1   e 0.941                                  nUFMCS_N_199
+                  --------
+                    8.159  (29.6% logic, 70.4% route), 5 logic levels.
+
+Warning: 8.319 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |     5.000 ns|    19.836 ns|     6 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|     8.319 ns|     5 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n26                                     |       8|      84|     27.54%
+                                        |        |        |
+n1997                                   |       1|      36|     11.80%
+                                        |        |        |
+n1996                                   |       1|      35|     11.48%
+                                        |        |        |
+n1995                                   |       1|      33|     10.82%
+                                        |        |        |
+n10                                     |       5|      32|     10.49%
+                                        |        |        |
+n1998                                   |       1|      32|     10.49%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 305  Score: 1313492
+
+Constraints cover  621 paths, 182 nets, and 471 connections (64.2% coverage)
+
+
+Peak memory: 56156160 bytes, TRCE: 2355200 bytes, DLYMAN: 0 bytes
+CPU_TIME_REPORT: 0 secs 
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2GS_prim.v b/CPLD/LCMXO2-640HC/impl1/RAM2GS_prim.v new file mode 100644 index 0000000..c5879ca --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2GS_prim.v @@ -0,0 +1,802 @@ +// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.12.1.454 +// Netlist written on Tue Aug 15 05:03:23 2023 +// +// Verilog Description of module RAM2GS +// + +module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, + LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, + nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1[8:14]) + input PHI2; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + input [9:0]MAin; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + input [1:0]CROW; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + input [7:0]Din; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + output [7:0]Dout; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + input nCCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + input nCRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + input nFWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) + output LED; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) + output [1:0]RBA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + output [11:0]RA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + inout [7:0]RD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + output nRCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) + input RCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + output RCKE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) + output nRWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) + output nRRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) + output nRCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) + output RDQMH; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) + output RDQML; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) + output nUFMCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) + output UFMCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) + output UFMSDI; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) + input UFMSDO; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) + + wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + wire nCCAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + wire nCRAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + wire PHI2_N_120 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(38[6:13]) + wire nCRAS_c__inv /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + + wire GND_net, VCC_net, PHI2r, PHI2r2, PHI2r3, RASr, RASr2, + RASr3, CASr, CASr2, CASr3, FWEr, CBR, LEDEN, LED_c, + Din_c_7, Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, + Din_c_0; + wire [7:0]Bank; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(31[12:16]) + + wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, + MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, + nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, + nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, RA_0; + wire [9:0]RowA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(51[12:16]) + + wire RA_1_9, RA_1_8, RA_1_7, RA_1_6, RA_1_5, RA_1_4, RA_1_3, + RA_1_2, RA_1_1, RA_1_0, RDQML_c, RDQMH_c; + wire [7:0]WRD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(59[12:15]) + + wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted, + CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI, + CmdUFMCS, InitReady, Ready, n10; + wire [17:0]FS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15]) + + wire RA11_N_184, PHI2_N_120_enable_8, n2036, n1765, n1893, n7, + n917, n4, n2277, RCKE_N_132, nRowColSel_N_35, nRWE_N_182, + nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32, nRCS_N_146, + n15, n2260, nRCS_N_142, n2362, nRCS_N_141, nRCAS_N_166, + nRWE_N_178, n2180, nRCS_N_139, nRCAS_N_165, nRWE_N_177, nRWE_N_176, + n14, n6, n13, n1993, n2254, Ready_N_296, RCLK_c_enable_28, + nRCS_N_137, Ready_N_292, nRCS_N_136, nRRAS_N_156, nRCAS_N_161, + nRWE_N_171, n2220, RCKEEN_N_121, n15_adj_1, n2371, ADSubmitted_N_246, + CmdEnable_N_248, C1Submitted_N_237, PHI2_N_120_enable_3, n2174, + n6_adj_2, Cmdn8MEGEN_N_264, XOR8MEG_N_110, n2204, n1996, n6_adj_3, + RCLK_c_enable_10, n2191, n2208, n22, n8MEGEN_N_91, UFMCLK_N_224, + UFMSDI_N_231, n26, nUFMCS_N_199, n2055, PHI2_N_120_enable_2, + n1999, n2287, n726, n727, n728, n729, n730, n732, n733, + n734, n735, n736, n737, n738, n2267, n1398, n2183, n1995, + PHI2_N_120_enable_1, n1060, n1408, n2228, n2447, n1406, + PHI2_N_120_enable_6, n2225, n827, n2370, n1277, n15_adj_4, + Dout_c, n78, n79, n80, n81, n82, n83, n84, n85, n86, + n87, n88, n89, n90, n91, n92, n93, n94, n95, n2382, + RCLK_c_enable_15, n9, n2369, n7_adj_5, n13_adj_6, n2381, + n2210, n2380, n2227, n2368, PHI2_N_120_enable_7, n12, n1994, + RCLK_c_enable_27, n2367, n1407, n2379, n2378, n2377, n2366, + n2365, n2376, n1998, n2375, n4_adj_7, n2374, RCLK_c_enable_6, + Dout_0, Dout_1, n984, Dout_2, n8, Dout_3, Dout_4, n1314, + Dout_5, Dout_6, RCLK_c_enable_16, n2363, n13_adj_8, n2000, + n2373, RCLK_c_enable_5, n1992, n1997, n2372, n64; + + VHI i2 (.Z(VCC_net)); + INV i2046 (.A(PHI2_c), .Z(PHI2_N_120)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + FD1S3AX PHI2r2_377 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r2_377.GSR = "ENABLED"; + LUT4 nRCAS_I_43_4_lut (.A(nRCS_N_142), .B(RASr2), .C(nRowColSel_N_35), + .D(CBR), .Z(nRCAS_N_166)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(186[13] 231[7]) + defparam nRCAS_I_43_4_lut.init = 16'h3afa; + LUT4 nRCAS_I_0_452_3_lut_4_lut (.A(n2371), .B(nRCAS_N_165), .C(Ready), + .D(nRCAS_N_166), .Z(nRCAS_N_161)) /* synthesis lut_function=(A ((D)+!C)+!A (B ((D)+!C)+!B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRCAS_I_0_452_3_lut_4_lut.init = 16'hfe0e; + LUT4 nRWE_I_0_455_4_lut (.A(n1765), .B(nRWE_N_178), .C(Ready), .D(n2371), + .Z(nRWE_N_171)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRWE_I_0_455_4_lut.init = 16'hcfc5; + FD1S3AX PHI2r3_378 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r3_378.GSR = "ENABLED"; + FD1S3AX RASr_379 (.D(nCRAS_c__inv), .CK(RCLK_c), .Q(RASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr_379.GSR = "ENABLED"; + FD1S3AX RASr2_380 (.D(RASr), .CK(RCLK_c), .Q(RASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr2_380.GSR = "ENABLED"; + FD1S3AX RASr3_381 (.D(RASr2), .CK(RCLK_c), .Q(RASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr3_381.GSR = "ENABLED"; + FD1S3AX CASr_382 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr_382.GSR = "ENABLED"; + FD1S3AX CASr2_383 (.D(CASr), .CK(RCLK_c), .Q(CASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr2_383.GSR = "ENABLED"; + FD1S3AX CASr3_384 (.D(CASr2), .CK(RCLK_c), .Q(CASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr3_384.GSR = "ENABLED"; + FD1S3IX RA11_385 (.D(RA11_N_184), .CK(PHI2_c), .CD(n2380), .Q(RA_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam RA11_385.GSR = "ENABLED"; + CCU2D FS_610_add_4_15 (.A0(FS[13]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1998), + .COUT(n1999), .S0(n82), .S1(n81)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_15.INIT0 = 16'hfaaa; + defparam FS_610_add_4_15.INIT1 = 16'hfaaa; + defparam FS_610_add_4_15.INJECT1_0 = "NO"; + defparam FS_610_add_4_15.INJECT1_1 = "NO"; + FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i0.GSR = "ENABLED"; + FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i0.GSR = "ENABLED"; + FD1S3AX FWEr_389 (.D(n2373), .CK(nCRAS_c__inv), .Q(FWEr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam FWEr_389.GSR = "ENABLED"; + FD1S3AX CBR_390 (.D(nCCAS_N_3), .CK(nCRAS_c__inv), .Q(CBR)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam CBR_390.GSR = "ENABLED"; + FD1S3AX RCKE_395 (.D(RCKE_N_132), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(141[9] 144[5]) + defparam RCKE_395.GSR = "ENABLED"; + FD1P3AY nRCS_396 (.D(nRCS_N_136), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRCS_396.GSR = "ENABLED"; + LUT4 i1477_2_lut (.A(nRWE_N_177), .B(nRCAS_N_165), .Z(n1765)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1477_2_lut.init = 16'heeee; + FD1P3AX nRowColSel_402 (.D(n917), .SP(RCLK_c_enable_5), .CK(RCLK_c), + .Q(nRowColSel)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRowColSel_402.GSR = "ENABLED"; + CCU2D FS_610_add_4_13 (.A0(FS[11]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1997), + .COUT(n1998), .S0(n84), .S1(n83)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_13.INIT0 = 16'hfaaa; + defparam FS_610_add_4_13.INIT1 = 16'hfaaa; + defparam FS_610_add_4_13.INJECT1_0 = "NO"; + defparam FS_610_add_4_13.INJECT1_1 = "NO"; + LUT4 i2_2_lut (.A(InitReady), .B(Ready_N_296), .Z(n6_adj_3)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam i2_2_lut.init = 16'h8888; + FD1P3AX CmdEnable_405 (.D(CmdEnable_N_248), .SP(PHI2_N_120_enable_1), + .CK(PHI2_N_120), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdEnable_405.GSR = "ENABLED"; + LUT4 i4_4_lut (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n6_adj_2), + .Z(n2204)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; + defparam i4_4_lut.init = 16'h4000; + FD1P3IX ADSubmitted_407 (.D(ADSubmitted_N_246), .SP(PHI2_N_120_enable_2), + .CD(C1Submitted_N_237), .CK(PHI2_N_120), .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam ADSubmitted_407.GSR = "ENABLED"; + LUT4 i26_4_lut (.A(n2183), .B(n2191), .C(Din_c_5), .D(n2254), .Z(n15_adj_1)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ; + defparam i26_4_lut.init = 16'hc0ca; + LUT4 i1_2_lut_3_lut_4_lut (.A(n2369), .B(n26), .C(n2204), .D(nFWE_c), + .Z(n2220)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; + defparam i1_2_lut_3_lut_4_lut.init = 16'h0020; + FD1P3AY nRRAS_397 (.D(nRRAS_N_156), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRRAS_397.GSR = "ENABLED"; + LUT4 nRWE_I_50_1_lut (.A(nRWE_N_177), .Z(nRWE_N_176)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(255[14] 262[8]) + defparam nRWE_I_50_1_lut.init = 16'h5555; + BB Dout_pad_7__713 (.I(WRD[7]), .T(n984), .B(RD[7]), .O(Dout_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + FD1P3AY nRCAS_398 (.D(nRCAS_N_161), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRCAS_398.GSR = "ENABLED"; + FD1P3AY nRWE_399 (.D(nRWE_N_171), .SP(RCLK_c_enable_5), .CK(RCLK_c), + .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRWE_399.GSR = "ENABLED"; + FD1S3JX RA10_400 (.D(n2036), .CK(RCLK_c), .PD(nRWE_N_176), .Q(RA_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam RA10_400.GSR = "ENABLED"; + FD1P3AX RCKEEN_401 (.D(RCKEEN_N_121), .SP(RCLK_c_enable_6), .CK(RCLK_c), + .Q(RCKEEN)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam RCKEEN_401.GSR = "ENABLED"; + FD1S3AX FS_610__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i0.GSR = "ENABLED"; + FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_c__inv), .CD(n2380), .Q(RBA_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RBA__i1.GSR = "ENABLED"; + LUT4 i1_4_lut (.A(Din_c_5), .B(n2220), .C(Din_c_4), .D(Din_c_3), + .Z(PHI2_N_120_enable_6)) /* synthesis lut_function=(A (B (C (D)))+!A (B)) */ ; + defparam i1_4_lut.init = 16'hc444; + LUT4 i29_3_lut (.A(InitReady), .B(n15_adj_4), .C(Ready), .Z(RCKEEN_N_121)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam i29_3_lut.init = 16'hcaca; + LUT4 Cmdn8MEGEN_I_93_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_4), + .D(n1314), .Z(Cmdn8MEGEN_N_264)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(321[13] 335[7]) + defparam Cmdn8MEGEN_I_93_4_lut.init = 16'hcc5c; + LUT4 i1956_2_lut (.A(MAin_c_0), .B(Din_c_2), .Z(n2254)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1956_2_lut.init = 16'heeee; + FD1P3AX IS_FSM__i0 (.D(Ready_N_296), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(nRCS_N_139)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i0.GSR = "ENABLED"; + CCU2D FS_610_add_4_9 (.A0(FS[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1995), + .COUT(n1996), .S0(n88), .S1(n87)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_9.INIT0 = 16'hfaaa; + defparam FS_610_add_4_9.INIT1 = 16'hfaaa; + defparam FS_610_add_4_9.INJECT1_0 = "NO"; + defparam FS_610_add_4_9.INJECT1_1 = "NO"; + FD1S3JX C1Submitted_406 (.D(n1398), .CK(PHI2_N_120), .PD(C1Submitted_N_237), + .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam C1Submitted_406.GSR = "ENABLED"; + FD1P3AY nUFMCS_415 (.D(nUFMCS_N_199), .SP(RCLK_c_enable_10), .CK(RCLK_c), + .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam nUFMCS_415.GSR = "ENABLED"; + LUT4 i2_4_lut (.A(n2220), .B(Din_c_4), .C(Din_c_3), .D(Din_c_5), + .Z(PHI2_N_120_enable_7)) /* synthesis lut_function=(A (B (C+!(D)))) */ ; + defparam i2_4_lut.init = 16'h8088; + FD1S3AX S_FSM_i1 (.D(n2374), .CK(RCLK_c), .Q(nRowColSel_N_35)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i1.GSR = "ENABLED"; + CCU2D FS_610_add_4_7 (.A0(FS[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1994), + .COUT(n1995), .S0(n90), .S1(n89)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_7.INIT0 = 16'hfaaa; + defparam FS_610_add_4_7.INIT1 = 16'hfaaa; + defparam FS_610_add_4_7.INJECT1_0 = "NO"; + defparam FS_610_add_4_7.INJECT1_1 = "NO"; + LUT4 i1_2_lut (.A(Din_c_6), .B(Din_c_3), .Z(n2183)) /* synthesis lut_function=(!((B)+!A)) */ ; + defparam i1_2_lut.init = 16'h2222; + LUT4 i1_2_lut_rep_15_4_lut (.A(FS[10]), .B(FS[11]), .C(n2368), .D(InitReady), + .Z(RCLK_c_enable_16)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; + defparam i1_2_lut_rep_15_4_lut.init = 16'h0008; + CCU2D FS_610_add_4_3 (.A0(FS[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1992), + .COUT(n1993), .S0(n94), .S1(n93)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_3.INIT0 = 16'hfaaa; + defparam FS_610_add_4_3.INIT1 = 16'hfaaa; + defparam FS_610_add_4_3.INJECT1_0 = "NO"; + defparam FS_610_add_4_3.INJECT1_1 = "NO"; + LUT4 RA11_I_54_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_184)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(99[22:51]) + defparam RA11_I_54_3_lut.init = 16'hc6c6; + LUT4 i9_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(n9)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ; + defparam i9_2_lut_3_lut.init = 16'h1f1f; + LUT4 i1491_2_lut_rep_30 (.A(RCKE_c), .B(RASr2), .Z(n2379)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1491_2_lut_rep_30.init = 16'heeee; + LUT4 nRCS_I_31_3_lut_4_lut (.A(RCKE_c), .B(RASr2), .C(nRowColSel_N_35), + .D(nRCS_N_142), .Z(nRCS_N_141)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C+(D))))) */ ; + defparam nRCS_I_31_3_lut_4_lut.init = 16'h1f10; + FD1P3IX UFMCLK_416 (.D(UFMCLK_N_224), .SP(RCLK_c_enable_10), .CD(n2366), + .CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam UFMCLK_416.GSR = "ENABLED"; + LUT4 MAin_9__I_0_427_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), + .Z(RA_1_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i10_3_lut.init = 16'hcaca; + LUT4 i3_4_lut (.A(Din_c_2), .B(Din_c_3), .C(Din_c_6), .D(MAin_c_0), + .Z(n2191)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i3_4_lut.init = 16'h0800; + LUT4 i1_2_lut_rep_21_3_lut (.A(Din_c_7), .B(Din_c_1), .C(Din_c_0), + .Z(n2370)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i1_2_lut_rep_21_3_lut.init = 16'h2020; + LUT4 MAin_9__I_0_427_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), + .Z(RA_1_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i9_3_lut.init = 16'hcaca; + LUT4 MAin_9__I_0_427_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), + .Z(RA_1_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i8_3_lut.init = 16'hcaca; + LUT4 MAin_9__I_0_427_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), + .Z(RA_1_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i7_3_lut.init = 16'hcaca; + LUT4 MAin_9__I_0_427_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), + .Z(RA_1_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i6_3_lut.init = 16'hcaca; + CCU2D FS_610_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n1992), + .S1(n95)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_1.INIT0 = 16'hF000; + defparam FS_610_add_4_1.INIT1 = 16'h0555; + defparam FS_610_add_4_1.INJECT1_0 = "NO"; + defparam FS_610_add_4_1.INJECT1_1 = "NO"; + LUT4 MAin_9__I_0_427_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), + .Z(RA_1_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i5_3_lut.init = 16'hcaca; + FD1S3AX PHI2r_376 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r_376.GSR = "ENABLED"; + LUT4 i1962_4_lut (.A(Din_c_4), .B(Din_c_1), .C(n1314), .D(LEDEN), + .Z(n2260)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ; + defparam i1962_4_lut.init = 16'hfefa; + LUT4 i1423_2_lut (.A(RCKE_c), .B(RASr2), .Z(nRWE_N_182)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(168[14] 184[8]) + defparam i1423_2_lut.init = 16'hdddd; + LUT4 MAin_9__I_0_427_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), + .Z(RA_1_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i4_3_lut.init = 16'hcaca; + FD1S3IX S_FSM_i3 (.D(n1406), .CK(RCLK_c), .CD(n1407), .Q(nRowColSel_N_33)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i3.GSR = "ENABLED"; + FD1S3IX S_FSM_i4 (.D(n827), .CK(RCLK_c), .CD(n2374), .Q(nRowColSel_N_32)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i4.GSR = "ENABLED"; + LUT4 i1_2_lut_3_lut_4_lut_adj_1 (.A(Din_c_7), .B(Din_c_1), .C(Din_c_4), + .D(Din_c_0), .Z(n2208)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i1_2_lut_3_lut_4_lut_adj_1.init = 16'h0200; + LUT4 MAin_c_0_bdd_4_lut (.A(n2369), .B(n26), .C(nFWE_c), .D(MAin_c_1), + .Z(PHI2_N_120_enable_2)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; + defparam MAin_c_0_bdd_4_lut.init = 16'h0200; + FD1P3IX UFMSDI_417 (.D(UFMSDI_N_231), .SP(RCLK_c_enable_10), .CD(n2366), + .CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam UFMSDI_417.GSR = "ENABLED"; + LUT4 MAin_9__I_0_427_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), + .Z(RA_1_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i3_3_lut.init = 16'hcaca; + LUT4 MAin_9__I_0_427_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), + .Z(RA_1_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i2_3_lut.init = 16'hcaca; + LUT4 i1448_4_lut (.A(n13_adj_6), .B(n64), .C(CmdUFMCS), .D(InitReady), + .Z(nUFMCS_N_199)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (C+!(D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(345[12] 409[6]) + defparam i1448_4_lut.init = 16'h3fbb; + LUT4 i2_3_lut_rep_18_4_lut (.A(n10), .B(n2375), .C(FS[11]), .D(FS[10]), + .Z(n2367)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; + defparam i2_3_lut_rep_18_4_lut.init = 16'h1000; + LUT4 i3_4_lut_adj_2 (.A(nRCS_N_139), .B(InitReady), .C(nRowColSel_N_35), + .D(RASr2), .Z(nRCS_N_137)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; + defparam i3_4_lut_adj_2.init = 16'hbfff; + LUT4 MAin_9__I_0_427_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), + .Z(RA_1_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i1_3_lut.init = 16'hcaca; + LUT4 i1416_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(58[17:46]) + defparam i1416_2_lut.init = 16'hbbbb; + LUT4 i2001_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ; + defparam i2001_2_lut.init = 16'h7777; + LUT4 i2_3_lut_4_lut (.A(n2363), .B(MAin_c_1), .C(n2208), .D(n15_adj_1), + .Z(CmdEnable_N_248)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; + defparam i2_3_lut_4_lut.init = 16'h4000; + LUT4 i2005_3_lut_rep_17_4_lut (.A(n10), .B(n2375), .C(InitReady), + .D(FS[11]), .Z(n2366)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ; + defparam i2005_3_lut_rep_17_4_lut.init = 16'h0001; + FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i0.GSR = "ENABLED"; + LUT4 i1427_4_lut (.A(nRCS_N_146), .B(nRowColSel_N_34), .C(n2378), + .D(nRowColSel_N_33), .Z(nRCS_N_142)) /* synthesis lut_function=(A (B+(C (D)))+!A (B+(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(195[13] 231[7]) + defparam i1427_4_lut.init = 16'hfcdd; + LUT4 i3_3_lut_4_lut (.A(Din_c_7), .B(Din_c_1), .C(Din_c_6), .D(Din_c_4), + .Z(n8)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i3_3_lut_4_lut.init = 16'h0002; + LUT4 i1_2_lut_adj_3 (.A(FS[10]), .B(n13_adj_6), .Z(RCLK_c_enable_28)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_adj_3.init = 16'h8888; + LUT4 i1119_1_lut (.A(nRowColSel_N_35), .Z(n1408)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1119_1_lut.init = 16'h5555; + LUT4 nRCS_N_146_bdd_4_lut (.A(nRCS_N_146), .B(n1060), .C(nRWE_N_182), + .D(nRowColSel_N_35), .Z(nRWE_N_178)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ; + defparam nRCS_N_146_bdd_4_lut.init = 16'hf0dd; + LUT4 i11_3_lut_rep_20 (.A(MAin_c_2), .B(n22), .C(MAin_c_5), .Z(n2369)) /* synthesis lut_function=(A (B (C))) */ ; + defparam i11_3_lut_rep_20.init = 16'h8080; + LUT4 i13_2_lut_rep_16_4_lut (.A(MAin_c_2), .B(n22), .C(MAin_c_5), + .D(n26), .Z(n2365)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; + defparam i13_2_lut_rep_16_4_lut.init = 16'hff7f; + GSR GSR_INST (.GSR(VCC_net)); + LUT4 i1_4_lut_adj_4 (.A(n2180), .B(n2225), .C(n8), .D(n2382), .Z(ADSubmitted_N_246)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i1_4_lut_adj_4.init = 16'h2000; + LUT4 i6_4_lut (.A(FS[11]), .B(n12), .C(FS[14]), .D(FS[17]), .Z(n13_adj_6)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i6_4_lut.init = 16'h8000; + LUT4 i8_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]), + .Z(n22)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i8_4_lut.init = 16'h8000; + LUT4 i1_2_lut_3_lut_4_lut_adj_5 (.A(n2369), .B(n26), .C(MAin_c_0), + .D(MAin_c_1), .Z(n2225)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; + defparam i1_2_lut_3_lut_4_lut_adj_5.init = 16'hdfff; + LUT4 i5_4_lut (.A(FS[13]), .B(FS[12]), .C(FS[15]), .D(FS[16]), .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i5_4_lut.init = 16'h8000; + LUT4 i12_4_lut (.A(Bank[2]), .B(n2277), .C(n2287), .D(Bank[5]), + .Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; + defparam i12_4_lut.init = 16'hbfff; + LUT4 i2_3_lut_4_lut_adj_6 (.A(n2369), .B(n26), .C(MAin_c_0), .D(MAin_c_1), + .Z(n1277)) /* synthesis lut_function=((B+((D)+!C))+!A) */ ; + defparam i2_3_lut_4_lut_adj_6.init = 16'hffdf; + LUT4 i637_1_lut_rep_31 (.A(Ready), .Z(n2380)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i637_1_lut_rep_31.init = 16'h5555; + LUT4 i1573_4_lut (.A(n2367), .B(n2377), .C(InitReady), .D(n4_adj_7), + .Z(RCLK_c_enable_15)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15]) + defparam i1573_4_lut.init = 16'hcac0; + LUT4 i3_4_lut_adj_7 (.A(FS[17]), .B(FS[13]), .C(FS[15]), .D(FS[16]), + .Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i3_4_lut_adj_7.init = 16'hfffe; + LUT4 i786_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_34), .Z(n1060)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(195[13] 231[7]) + defparam i786_2_lut.init = 16'heeee; + LUT4 i1_4_lut_adj_8 (.A(FS[4]), .B(n15), .C(n13), .D(n14), .Z(n4_adj_7)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; + defparam i1_4_lut_adj_8.init = 16'h0002; + LUT4 i2_2_lut_3_lut_4_lut (.A(nRCS_N_139), .B(n2381), .C(Ready), .D(nRCAS_N_165), + .Z(n2036)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam i2_2_lut_3_lut_4_lut.init = 16'hfffb; + LUT4 i2_3_lut_4_lut_4_lut (.A(Ready), .B(n1060), .C(nRowColSel_N_32), + .D(nRowColSel_N_35), .Z(RCLK_c_enable_5)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i2_3_lut_4_lut_4_lut.init = 16'hfffd; + CCU2D FS_610_add_4_11 (.A0(FS[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1996), + .COUT(n1997), .S0(n86), .S1(n85)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_11.INIT0 = 16'hfaaa; + defparam FS_610_add_4_11.INIT1 = 16'hfaaa; + defparam FS_610_add_4_11.INJECT1_0 = "NO"; + defparam FS_610_add_4_11.INJECT1_1 = "NO"; + LUT4 i1603_3_lut (.A(n1893), .B(CmdUFMCLK), .C(InitReady), .Z(UFMCLK_N_224)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15]) + defparam i1603_3_lut.init = 16'hcaca; + LUT4 i1979_4_lut (.A(MAin_c_6), .B(MAin_c_4), .C(Bank[7]), .D(Bank[0]), + .Z(n2277)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i1979_4_lut.init = 16'h8000; + FD1P3AX IS_FSM__i15 (.D(n726), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(Ready_N_296)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i15.GSR = "ENABLED"; + LUT4 i771_2_lut_rep_23_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2372)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i771_2_lut_rep_23_2_lut.init = 16'hdddd; + LUT4 i6_4_lut_adj_9 (.A(FS[5]), .B(FS[7]), .C(FS[1]), .D(FS[2]), + .Z(n15)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i6_4_lut_adj_9.init = 16'hfffe; + LUT4 i1970_4_lut (.A(FS[4]), .B(n13_adj_6), .C(n2267), .D(FS[1]), + .Z(n1893)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15]) + defparam i1970_4_lut.init = 16'h3a0a; + LUT4 i1_2_lut_2_lut (.A(Ready), .B(nRowColSel_N_34), .Z(n6)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i1_2_lut_2_lut.init = 16'hdddd; + PFUMX i30 (.BLUT(n13_adj_8), .ALUT(n9), .C0(nRowColSel_N_35), .Z(n15_adj_4)); + FD1P3AX IS_FSM__i14 (.D(n727), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n726)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i14.GSR = "ENABLED"; + FD1P3AX IS_FSM__i13 (.D(n728), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n727)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i13.GSR = "ENABLED"; + LUT4 i1989_2_lut (.A(Bank[6]), .B(Bank[3]), .Z(n2287)) /* synthesis lut_function=(A (B)) */ ; + defparam i1989_2_lut.init = 16'h8888; + LUT4 i2_3_lut_rep_32 (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), + .Z(n2381)) /* synthesis lut_function=(A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20]) + defparam i2_3_lut_rep_32.init = 16'h8080; + LUT4 i1_2_lut_rep_22_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), + .D(nRCS_N_139), .Z(n2371)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20]) + defparam i1_2_lut_rep_22_4_lut.init = 16'hff7f; + FD1P3AX IS_FSM__i12 (.D(n729), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n728)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i12.GSR = "ENABLED"; + FD1P3AX XOR8MEG_408 (.D(XOR8MEG_N_110), .SP(PHI2_N_120_enable_3), .CK(PHI2_N_120), + .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam XOR8MEG_408.GSR = "ENABLED"; + FD1P3AX n8MEGEN_418 (.D(n8MEGEN_N_91), .SP(RCLK_c_enable_15), .CK(RCLK_c), + .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam n8MEGEN_418.GSR = "ENABLED"; + CCU2D FS_610_add_4_19 (.A0(FS[17]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2000), + .S0(n78)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_19.INIT0 = 16'hfaaa; + defparam FS_610_add_4_19.INIT1 = 16'h0000; + defparam FS_610_add_4_19.INJECT1_0 = "NO"; + defparam FS_610_add_4_19.INJECT1_1 = "NO"; + FD1P3AX LEDEN_419 (.D(n2447), .SP(RCLK_c_enable_16), .CK(RCLK_c), + .Q(LEDEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam LEDEN_419.GSR = "ENABLED"; + FD1P3AX Ready_404 (.D(n2447), .SP(Ready_N_292), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam Ready_404.GSR = "ENABLED"; + FD1P3AX CmdUFMCLK_413 (.D(Din_c_1), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), + .Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMCLK_413.GSR = "ENABLED"; + FD1P3AX CmdUFMSDI_414 (.D(Din_c_0), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), + .Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMSDI_414.GSR = "ENABLED"; + FD1P3AX Cmdn8MEGEN_410 (.D(Cmdn8MEGEN_N_264), .SP(PHI2_N_120_enable_6), + .CK(PHI2_N_120), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam Cmdn8MEGEN_410.GSR = "ENABLED"; + FD1P3AX CmdSubmitted_411 (.D(n2447), .SP(PHI2_N_120_enable_7), .CK(PHI2_N_120), + .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdSubmitted_411.GSR = "ENABLED"; + FD1P3AX CmdUFMCS_412 (.D(Din_c_2), .SP(PHI2_N_120_enable_8), .CK(PHI2_N_120), + .Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMCS_412.GSR = "ENABLED"; + FD1P3AX IS_FSM__i11 (.D(n730), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n729)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i11.GSR = "ENABLED"; + LUT4 i2008_2_lut_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_35), + .D(Ready), .Z(RCLK_c_enable_27)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(233[8:20]) + defparam i2008_2_lut_4_lut.init = 16'h0080; + LUT4 i1404_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), .Z(RCKE_N_132)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(15[12:17]) + defparam i1404_4_lut.init = 16'hcfc8; + LUT4 i1118_1_lut (.A(nRowColSel_N_34), .Z(n1407)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1118_1_lut.init = 16'h5555; + FD1P3AX IS_FSM__i10 (.D(nRWE_N_177), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n730)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i10.GSR = "ENABLED"; + LUT4 i1_2_lut_adj_10 (.A(RASr2), .B(nRowColSel_N_32), .Z(n1406)) /* synthesis lut_function=(!((B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam i1_2_lut_adj_10.init = 16'h2222; + LUT4 i1439_2_lut (.A(nRowColSel_N_33), .B(nRowColSel_N_32), .Z(n827)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1439_2_lut.init = 16'heeee; + FD1P3AX IS_FSM__i9 (.D(n732), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(nRWE_N_177)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i9.GSR = "ENABLED"; + LUT4 i1432_4_lut (.A(FWEr), .B(n2372), .C(n1060), .D(n2376), .Z(n917)) /* synthesis lut_function=(!(A (B+!(C+!(D)))+!A (B+!(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i1432_4_lut.init = 16'h3032; + LUT4 i1_2_lut_rep_33 (.A(Din_c_0), .B(Din_c_2), .Z(n2382)) /* synthesis lut_function=(A (B)) */ ; + defparam i1_2_lut_rep_33.init = 16'h8888; + LUT4 i1_4_lut_4_lut (.A(CBR), .B(n2227), .C(FWEr), .D(nRowColSel_N_34), + .Z(n13_adj_8)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[27:31]) + defparam i1_4_lut_4_lut.init = 16'h5540; + LUT4 i4_2_lut (.A(FS[8]), .B(FS[0]), .Z(n13)) /* synthesis lut_function=(A+(B)) */ ; + defparam i4_2_lut.init = 16'heeee; + LUT4 i1589_4_lut (.A(n2174), .B(CmdUFMSDI), .C(InitReady), .D(n4), + .Z(UFMSDI_N_231)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(83[6:15]) + defparam i1589_4_lut.init = 16'hcac0; + LUT4 i2_1_lut_rep_24 (.A(nFWE_c), .Z(n2373)) /* synthesis lut_function=(!(A)) */ ; + defparam i2_1_lut_rep_24.init = 16'h5555; + LUT4 i2_3_lut_4_lut_adj_11 (.A(Din_c_0), .B(Din_c_2), .C(n2260), .D(Din_c_3), + .Z(XOR8MEG_N_110)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; + defparam i2_3_lut_4_lut_adj_11.init = 16'h0008; + FD1P3AX IS_FSM__i8 (.D(n733), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n732)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i8.GSR = "ENABLED"; + FD1P3AX IS_FSM__i7 (.D(n734), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n733)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i7.GSR = "ENABLED"; + FD1P3AX IS_FSM__i6 (.D(n735), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n734)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i6.GSR = "ENABLED"; + FD1P3AX IS_FSM__i5 (.D(n736), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n735)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i5.GSR = "ENABLED"; + FD1P3AX IS_FSM__i4 (.D(n737), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n736)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i4.GSR = "ENABLED"; + FD1P3AX IS_FSM__i3 (.D(n738), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n737)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i3.GSR = "ENABLED"; + FD1P3AX IS_FSM__i2 (.D(nRCAS_N_165), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(n738)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i2.GSR = "ENABLED"; + FD1P3AX IS_FSM__i1 (.D(nRCS_N_139), .SP(RCLK_c_enable_27), .CK(RCLK_c), + .Q(nRCAS_N_165)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i1.GSR = "ENABLED"; + FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_c__inv), .CD(n2380), .Q(RBA_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RBA__i2.GSR = "ENABLED"; + FD1S3AX FS_610__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i17.GSR = "ENABLED"; + FD1S3AX FS_610__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i16.GSR = "ENABLED"; + FD1S3AX FS_610__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i15.GSR = "ENABLED"; + FD1S3AX FS_610__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i14.GSR = "ENABLED"; + FD1S3AX FS_610__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i13.GSR = "ENABLED"; + FD1S3AX FS_610__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i12.GSR = "ENABLED"; + FD1S3AX FS_610__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i11.GSR = "ENABLED"; + FD1S3AX FS_610__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i10.GSR = "ENABLED"; + FD1S3AX FS_610__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i9.GSR = "ENABLED"; + FD1S3AX FS_610__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i8.GSR = "ENABLED"; + FD1S3AX FS_610__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i7.GSR = "ENABLED"; + FD1S3AX FS_610__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i6.GSR = "ENABLED"; + FD1S3AX FS_610__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i5.GSR = "ENABLED"; + FD1S3AX FS_610__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i4.GSR = "ENABLED"; + FD1S3AX FS_610__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i3.GSR = "ENABLED"; + FD1S3AX FS_610__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i2.GSR = "ENABLED"; + FD1S3AX FS_610__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i1.GSR = "ENABLED"; + FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i7.GSR = "ENABLED"; + FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i6.GSR = "ENABLED"; + FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i5.GSR = "ENABLED"; + FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i4.GSR = "ENABLED"; + FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i3.GSR = "ENABLED"; + FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i2.GSR = "ENABLED"; + FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i1.GSR = "ENABLED"; + FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_c__inv), .PD(n2380), .Q(RowA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i9.GSR = "ENABLED"; + FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i8.GSR = "ENABLED"; + FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i7.GSR = "ENABLED"; + FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i6.GSR = "ENABLED"; + FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_c__inv), .PD(n2380), .Q(RowA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i5.GSR = "ENABLED"; + FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i4.GSR = "ENABLED"; + FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i3.GSR = "ENABLED"; + FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i2.GSR = "ENABLED"; + FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_c__inv), .CD(n2380), .Q(RowA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i1.GSR = "ENABLED"; + FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i7.GSR = "ENABLED"; + LUT4 i2_3_lut_3_lut (.A(nFWE_c), .B(Din_c_5), .C(Din_c_3), .Z(n2180)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; + defparam i2_3_lut_3_lut.init = 16'h4040; + LUT4 i1_2_lut_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4), .Z(n6_adj_2)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) + defparam i1_2_lut_3_lut.init = 16'h1010; + LUT4 RASr2_I_0_1_lut_rep_25 (.A(RASr2), .Z(n2374)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46]) + defparam RASr2_I_0_1_lut_rep_25.init = 16'h5555; + LUT4 i1_4_lut_4_lut_adj_12 (.A(RASr2), .B(n6_adj_3), .C(nRowColSel_N_32), + .D(Ready), .Z(Ready_N_292)) /* synthesis lut_function=(A (D)+!A (B (C+(D))+!B (D))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46]) + defparam i1_4_lut_4_lut_adj_12.init = 16'hff40; + LUT4 i1_4_lut_adj_13 (.A(Din_c_2), .B(n2055), .C(MAin_c_0), .D(n2362), + .Z(C1Submitted_N_237)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; + defparam i1_4_lut_adj_13.init = 16'h0004; + FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i6.GSR = "ENABLED"; + FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i5.GSR = "ENABLED"; + FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i4.GSR = "ENABLED"; + FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i3.GSR = "ENABLED"; + FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i2.GSR = "ENABLED"; + FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i1.GSR = "ENABLED"; + CCU2D FS_610_add_4_5 (.A0(FS[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1993), + .COUT(n1994), .S0(n92), .S1(n91)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_5.INIT0 = 16'hfaaa; + defparam FS_610_add_4_5.INIT1 = 16'hfaaa; + defparam FS_610_add_4_5.INJECT1_0 = "NO"; + defparam FS_610_add_4_5.INJECT1_1 = "NO"; + BB Dout_pad_6__714 (.I(WRD[6]), .T(n984), .B(RD[6]), .O(Dout_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + LUT4 i2_3_lut_4_lut_adj_14 (.A(n2369), .B(n26), .C(n2180), .D(n2204), + .Z(PHI2_N_120_enable_8)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; + defparam i2_3_lut_4_lut_adj_14.init = 16'h2000; + BB Dout_pad_5__715 (.I(WRD[5]), .T(n984), .B(RD[5]), .O(Dout_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_4__716 (.I(WRD[4]), .T(n984), .B(RD[4]), .O(Dout_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_3__717 (.I(WRD[3]), .T(n984), .B(RD[3]), .O(Dout_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_2__718 (.I(WRD[2]), .T(n984), .B(RD[2]), .O(Dout_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + LUT4 i1_2_lut_3_lut_adj_15 (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), + .Z(n1314)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) + defparam i1_2_lut_3_lut_adj_15.init = 16'hfefe; + BB Dout_pad_1__719 (.I(WRD[1]), .T(n984), .B(RD[1]), .O(Dout_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_0__720 (.I(WRD[0]), .T(n984), .B(RD[0]), .O(Dout_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + OB Dout_pad_7 (.I(Dout_c), .O(Dout[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_6 (.I(Dout_0), .O(Dout[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_5 (.I(Dout_1), .O(Dout[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_4 (.I(Dout_2), .O(Dout[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_3 (.I(Dout_3), .O(Dout[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_2 (.I(Dout_4), .O(Dout[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_1 (.I(Dout_5), .O(Dout[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_0 (.I(Dout_6), .O(Dout[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB LED_pad (.I(LED_c), .O(LED)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) + OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + OB RA_pad_11 (.I(RA_c), .O(RA[11])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_10 (.I(RA_0), .O(RA[10])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_9 (.I(RA_1_9), .O(RA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_8 (.I(RA_1_8), .O(RA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_7 (.I(RA_1_7), .O(RA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_6 (.I(RA_1_6), .O(RA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_5 (.I(RA_1_5), .O(RA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_4 (.I(RA_1_4), .O(RA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_3 (.I(RA_1_3), .O(RA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_2 (.I(RA_1_2), .O(RA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_1 (.I(RA_1_1), .O(RA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_0 (.I(RA_1_0), .O(RA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB nRCS_pad (.I(nRCS_c), .O(nRCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) + OB RCKE_pad (.I(RCKE_c), .O(RCKE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) + OB nRWE_pad (.I(nRWE_c), .O(nRWE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) + OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) + OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) + OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) + OB RDQML_pad (.I(RDQML_c), .O(RDQML)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) + OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) + OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) + OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) + IB PHI2_pad (.I(PHI2), .O(PHI2_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + IB Din_pad_7 (.I(Din[7]), .O(Din_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_6 (.I(Din[6]), .O(Din_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_5 (.I(Din[5]), .O(Din_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_4 (.I(Din[4]), .O(Din_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_3 (.I(Din[3]), .O(Din_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_2 (.I(Din[2]), .O(Din_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_1 (.I(Din[1]), .O(Din_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_0 (.I(Din[0]), .O(Din_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + IB nFWE_pad (.I(nFWE), .O(nFWE_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) + IB RCLK_pad (.I(RCLK), .O(RCLK_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) + CCU2D FS_610_add_4_17 (.A0(FS[15]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1999), + .COUT(n2000), .S0(n80), .S1(n79)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_17.INIT0 = 16'hfaaa; + defparam FS_610_add_4_17.INIT1 = 16'hfaaa; + defparam FS_610_add_4_17.INJECT1_0 = "NO"; + defparam FS_610_add_4_17.INJECT1_1 = "NO"; + LUT4 i1_2_lut_rep_14_3_lut (.A(n2369), .B(n26), .C(nFWE_c), .Z(n2363)) /* synthesis lut_function=((B+(C))+!A) */ ; + defparam i1_2_lut_rep_14_3_lut.init = 16'hfdfd; + LUT4 i1_2_lut_rep_13_3_lut (.A(n2369), .B(n26), .C(MAin_c_1), .Z(n2362)) /* synthesis lut_function=((B+!(C))+!A) */ ; + defparam i1_2_lut_rep_13_3_lut.init = 16'hdfdf; + LUT4 i2010_3_lut_3_lut (.A(nCRAS_c), .B(LEDEN), .C(CBR), .Z(LED_c)) /* synthesis lut_function=(A+((C)+!B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[17:23]) + defparam i2010_3_lut_3_lut.init = 16'hfbfb; + LUT4 i5_3_lut (.A(FS[3]), .B(FS[9]), .C(FS[6]), .Z(n14)) /* synthesis lut_function=(A+(B+(C))) */ ; + defparam i5_3_lut.init = 16'hfefe; + LUT4 i4_4_lut_adj_16 (.A(nRowColSel_N_35), .B(nRowColSel_N_33), .C(nRowColSel_N_32), + .D(n6), .Z(RCLK_c_enable_6)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i4_4_lut_adj_16.init = 16'hfffe; + LUT4 i4_4_lut_adj_17 (.A(n7), .B(FS[8]), .C(FS[10]), .D(n10), .Z(n2174)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i4_4_lut_adj_17.init = 16'h0002; + LUT4 i34_4_lut (.A(n7_adj_5), .B(ADSubmitted), .C(C1Submitted_N_237), + .D(n2363), .Z(PHI2_N_120_enable_1)) /* synthesis lut_function=(A (B (C))+!A (B (C+!(D))+!B !(C+(D)))) */ ; + defparam i34_4_lut.init = 16'hc0c5; + LUT4 i13_3_lut (.A(MAin_c_0), .B(n2210), .C(MAin_c_1), .Z(n7_adj_5)) /* synthesis lut_function=(A (B (C))+!A (B+!(C))) */ ; + defparam i13_3_lut.init = 16'hc5c5; + LUT4 i1_2_lut_4_lut (.A(FS[11]), .B(n2368), .C(InitReady), .D(FS[10]), + .Z(n64)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i1_2_lut_4_lut.init = 16'hfffe; + LUT4 nRCS_N_137_I_0_4_lut (.A(nRCS_N_137), .B(n2379), .C(Ready), .D(nRowColSel_N_35), + .Z(nRRAS_N_156)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B ((D)+!C)+!B !(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRCS_N_137_I_0_4_lut.init = 16'h3afa; + LUT4 i3_4_lut_adj_18 (.A(Din_c_5), .B(n2228), .C(n2183), .D(n2370), + .Z(n2055)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i3_4_lut_adj_18.init = 16'h1000; + LUT4 i1930_2_lut (.A(nFWE_c), .B(Din_c_4), .Z(n2228)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1930_2_lut.init = 16'heeee; + LUT4 i1110_2_lut_3_lut_4_lut (.A(nFWE_c), .B(n2365), .C(C1Submitted), + .D(MAin_c_1), .Z(n1398)) /* synthesis lut_function=(A (C)+!A (B (C)+!B !((D)+!C))) */ ; + defparam i1110_2_lut_3_lut_4_lut.init = 16'he0f0; + LUT4 i1_2_lut_adj_19 (.A(FS[11]), .B(FS[6]), .Z(n4)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_adj_19.init = 16'h8888; + LUT4 i2_4_lut_adj_20 (.A(n2375), .B(FS[7]), .C(FS[9]), .D(FS[5]), + .Z(n7)) /* synthesis lut_function=(!(A+(B (C)+!B !(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i2_4_lut_adj_20.init = 16'h1404; + LUT4 i1417_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n984)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1417_2_lut.init = 16'heeee; + LUT4 i2_4_lut_adj_21 (.A(n2228), .B(CmdEnable), .C(n1277), .D(n1314), + .Z(PHI2_N_120_enable_3)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; + defparam i2_4_lut_adj_21.init = 16'h0004; + LUT4 i3_4_lut_adj_22 (.A(Din_c_5), .B(n2191), .C(C1Submitted), .D(n2208), + .Z(n2210)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i3_4_lut_adj_22.init = 16'h0800; + LUT4 i1_2_lut_adj_23 (.A(nRowColSel_N_33), .B(CASr2), .Z(n2227)) /* synthesis lut_function=(A+!(B)) */ ; + defparam i1_2_lut_adj_23.init = 16'hbbbb; + FD1P3AX InitReady_394 (.D(n2447), .SP(RCLK_c_enable_28), .CK(RCLK_c), + .Q(InitReady)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(134[9] 138[5]) + defparam InitReady_394.GSR = "ENABLED"; + LUT4 nRCS_I_0_448_3_lut (.A(nRCS_N_137), .B(nRCS_N_141), .C(Ready), + .Z(nRCS_N_136)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRCS_I_0_448_3_lut.init = 16'hcaca; + LUT4 i1969_2_lut_3_lut_4_lut (.A(FS[12]), .B(FS[14]), .C(FS[11]), + .D(n10), .Z(n2267)) /* synthesis lut_function=(A+(B+((D)+!C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1969_2_lut_3_lut_4_lut.init = 16'hffef; + LUT4 i1_2_lut_rep_19_3_lut (.A(FS[12]), .B(FS[14]), .C(n10), .Z(n2368)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_rep_19_3_lut.init = 16'hfefe; + LUT4 i2_3_lut_4_lut_adj_24 (.A(CBR), .B(CASr3), .C(FWEr), .D(CASr2), + .Z(nRCS_N_146)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam i2_3_lut_4_lut_adj_24.init = 16'h1000; + LUT4 i3_2_lut_rep_26 (.A(FS[12]), .B(FS[14]), .Z(n2375)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i3_2_lut_rep_26.init = 16'heeee; + LUT4 i1_2_lut_rep_27 (.A(CBR), .B(CASr3), .Z(n2376)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam i1_2_lut_rep_27.init = 16'heeee; + LUT4 i2_3_lut_rep_28 (.A(PHI2r3), .B(PHI2r2), .C(CmdSubmitted), .Z(n2377)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) + defparam i2_3_lut_rep_28.init = 16'h2020; + INV i2044 (.A(nCRAS_c), .Z(nCRAS_c__inv)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + FD1S3IX S_FSM_i2 (.D(n1406), .CK(RCLK_c), .CD(n1408), .Q(nRowColSel_N_34)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i2.GSR = "ENABLED"; + INV i2045 (.A(nCCAS_c), .Z(nCCAS_N_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + VLO i1 (.Z(GND_net)); + TSALL TSALL_INST (.TSALL(GND_net)); + PUR PUR_INST (.PUR(VCC_net)); + defparam PUR_INST.RST_PULSE = 1; + LUT4 i1_2_lut_4_lut_adj_25 (.A(PHI2r3), .B(PHI2r2), .C(CmdSubmitted), + .D(InitReady), .Z(RCLK_c_enable_10)) /* synthesis lut_function=(!(A (B (D)+!B !(C+!(D)))+!A (D))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) + defparam i1_2_lut_4_lut_adj_25.init = 16'h20ff; + LUT4 i1_2_lut_rep_29 (.A(FWEr), .B(CBR), .Z(n2378)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1_2_lut_rep_29.init = 16'heeee; + LUT4 m1_lut (.Z(n2447)) /* synthesis lut_function=1, syn_instantiated=1 */ ; + defparam m1_lut.init = 16'hffff; + LUT4 n8MEGEN_I_14_3_lut_4_lut (.A(InitReady), .B(n2367), .C(UFMSDO_c), + .D(Cmdn8MEGEN), .Z(n8MEGEN_N_91)) /* synthesis lut_function=(A (D)+!A !(B (C)+!B !(D))) */ ; + defparam n8MEGEN_I_14_3_lut_4_lut.init = 16'hbf04; + +endmodule +// +// Verilog Description of module TSALL +// module not written out since it is a black-box. +// + +// +// Verilog Description of module PUR +// module not written out since it is a black-box. +// + diff --git a/CPLD/LCMXO2-640HC/impl1/automake.log b/CPLD/LCMXO2-640HC/impl1/automake.log new file mode 100644 index 0000000..93ca373 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/automake.log @@ -0,0 +1,1033 @@ + +synthesis -f "RAM2GS_LCMXO2_640HC_impl1_lattice.synproj" +synthesis: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:22 2023 + + +Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml + + +Synthesis options: +The -a option is MachXO2. +The -s option is 4. +The -t option is TQFP100. +The -d option is LCMXO2-640HC. +Using package TQFP100. +Using performance grade 4. + + +########################################################## + +### Lattice Family : MachXO2 + +### Device : LCMXO2-640HC + +### Package : TQFP100 + +### Speed : 4 + +########################################################## + + + + +Optimization goal = Balanced +Top-level module name = RAM2GS. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added) +-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1 (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added) +Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v +NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 +Compile design. +Compile Design Begin +Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 +Top module name (Verilog): RAM2GS + + + + +Last elaborated design is RAM2GS() +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Top-level module name = RAM2GS. + +original encoding -> new encoding (one-hot encoding) + + 0000 -> 0000000000000001 + + 0001 -> 0000000000000010 + + 0010 -> 0000000000000100 + + 0011 -> 0000000000001000 + + 0100 -> 0000000000010000 + + 0101 -> 0000000000100000 + + 0110 -> 0000000001000000 + + 0111 -> 0000000010000000 + + 1000 -> 0000000100000000 + + 1001 -> 0000001000000000 + + 1010 -> 0000010000000000 + + 1011 -> 0000100000000000 + + 1100 -> 0001000000000000 + + 1101 -> 0010000000000000 + + 1110 -> 0100000000000000 + + 1111 -> 1000000000000000 + + +original encoding -> new encoding (one-hot encoding) + + 00 -> 0001 + + 01 -> 0010 + + 10 -> 0100 + + 11 -> 1000 + + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. + +Applying 200.000000 MHz constraint to all clocks + + +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 309 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd. + +################### Begin Area Report (RAM2GS)###################### +Number of register bits => 102 of 877 (11 % ) +BB => 8 +CCU2D => 10 +FD1P3AX => 29 +FD1P3AY => 5 +FD1P3IX => 3 +FD1S3AX => 47 +FD1S3IX => 14 +FD1S3JX => 4 +GSR => 1 +IB => 26 +INV => 3 +LUT4 => 122 +OB => 33 +PFUMX => 1 +################### End Area Report ################## + +################### Begin BlackBox Report ###################### +TSALL => 1 +################### End BlackBox Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 4 + Net : RCLK_c, loads : 62 + Net : PHI2_c, loads : 11 + Net : nCCAS_c, loads : 2 + Net : nCRAS_c, loads : 2 +Clock Enable Nets +Number of Clock Enables: 14 +Top 10 highest fanout Clock Enables: + Net : RCLK_c_enable_27, loads : 16 + Net : RCLK_c_enable_6, loads : 4 + Net : PHI2_N_120_enable_8, loads : 3 + Net : RCLK_c_enable_10, loads : 3 + Net : RCLK_c_enable_5, loads : 2 + Net : PHI2_N_120_enable_3, loads : 1 + Net : Ready_N_292, loads : 1 + Net : PHI2_N_120_enable_2, loads : 1 + Net : RCLK_c_enable_15, loads : 1 + Net : PHI2_N_120_enable_6, loads : 1 +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : RCLK_c_enable_27, loads : 16 + Net : InitReady, loads : 15 + Net : nCRAS_c__inv, loads : 15 + Net : RASr2, loads : 14 + Net : nRowColSel_N_35, loads : 13 + Net : n2380, loads : 13 + Net : nRowColSel, loads : 12 + Net : Ready, loads : 12 + Net : Din_c_4, loads : 10 + Net : MAin_c_1, loads : 10 +################### End Clock Report ################## + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 200.000 MHz| 50.413 MHz| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 200.000 MHz| 120.207 MHz| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + + +Peak Memory Usage: 53.555 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 0.828 secs +-------------------------------------------------------------- + +map -a "MachXO2" -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial "RAM2GS_LCMXO2_640HC_impl1.ngd" -o "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -pr "RAM2GS_LCMXO2_640HC_impl1.prf" -mp "RAM2GS_LCMXO2_640HC_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf" -c 0 +map: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + Process the file: RAM2GS_LCMXO2_640HC_impl1.ngd + Picdevice="LCMXO2-640HC" + + Pictype="TQFP100" + + Picspeed=4 + + Remove unused logic + + Do not produce over sized NCDs. + +Part used: LCMXO2-640HCTQFP100, Performance used: 4. + +Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. + +Running general design DRC... + +Removing unused logic... + +Optimizing... + + + + +Design Summary: + Number of registers: 102 out of 877 (12%) + PFU registers: 102 out of 640 (16%) + PIO registers: 0 out of 237 (0%) + Number of SLICEs: 75 out of 320 (23%) + SLICEs as Logic/ROM: 75 out of 320 (23%) + SLICEs as RAM: 0 out of 240 (0%) + SLICEs as Carry: 10 out of 320 (3%) + Number of LUT4s: 143 out of 640 (22%) + Number used as logic LUTs: 123 + Number used as distributed RAM: 0 + Number used as ripple logic: 20 + Number used as shift registers: 0 + Number of PIO sites used: 67 + 4(JTAG) out of 79 (90%) + Number of block RAMs: 0 out of 2 (0%) + Number of GSRs: 0 out of 1 (0%) + EFB used : No + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + POR : On + Bandgap : On + Number of Power Controller: 0 out of 1 (0%) + Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) + Number of DCCA: 0 out of 8 (0%) + Number of DCMA: 0 out of 2 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. + Number of clocks: 4 + Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Number of Clock Enables: 14 + Net RCLK_c_enable_6: 4 loads, 4 LSLICEs + Net RCLK_c_enable_5: 2 loads, 2 LSLICEs + Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_2: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_6: 1 loads, 1 LSLICEs + Net RCLK_c_enable_27: 8 loads, 8 LSLICEs + Net RCLK_c_enable_10: 3 loads, 3 LSLICEs + Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_16: 1 loads, 1 LSLICEs + Net RCLK_c_enable_28: 1 loads, 1 LSLICEs + Net RCLK_c_enable_15: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_3: 1 loads, 1 LSLICEs + Net Ready_N_292: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_8: 2 loads, 2 LSLICEs + Number of LSRs: 7 + Net RASr2: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net nRWE_N_177: 1 loads, 1 LSLICEs + Net C1Submitted_N_237: 2 loads, 2 LSLICEs + Net n2366: 2 loads, 2 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 18 loads + Net InitReady: 15 loads + Net RASr2: 15 loads + Net nRowColSel_N_35: 13 loads + Net nRowColSel: 12 loads + Net Din_c_4: 10 loads + Net MAin_c_1: 10 loads + Net Din_c_5: 9 loads + Net MAin_c_0: 9 loads + Net Din_c_0: 8 loads + + + Number of warnings: 0 + Number of errors: 0 + + + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 35 MB + +Dumping design to file RAM2GS_LCMXO2_640HC_impl1_map.ncd. + +ncd2vdb "RAM2GS_LCMXO2_640HC_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb" + +Loading device for application ncd2vdb from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. + +trce -f "RAM2GS_LCMXO2_640HC_impl1.mt" -o "RAM2GS_LCMXO2_640HC_impl1.tw1" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:25 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd +Preference file: ram2gs_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,4 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 349 Score: 848079 +Cumulative negative slack: 584487 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:25 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd +Preference file: ram2gs_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 349 (setup), 0 (hold) +Score: 848079 (setup), 0 (hold) +Cumulative negative slack: 584487 (584487+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 41 MB + + +ldbanno "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -n Verilog -o "RAM2GS_LCMXO2_640HC_impl1_mapvo.vo" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a Verilog netlist using the orca library type based on the RAM2GS_LCMXO2_640HC_impl1_map design file. + + +Loading design for application ldbanno from file RAM2GS_LCMXO2_640HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application ldbanno from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Converting design RAM2GS_LCMXO2_640HC_impl1_map.ncd into .ldb format. +Writing Verilog netlist to file RAM2GS_LCMXO2_640HC_impl1_mapvo.vo +Writing SDF timing to file RAM2GS_LCMXO2_640HC_impl1_mapvo.sdf + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 37 MB + +ldbanno "RAM2GS_LCMXO2_640HC_impl1_map.ncd" -n VHDL -o "RAM2GS_LCMXO2_640HC_impl1_mapvho.vho" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a VHDL netlist using the orca library type based on the RAM2GS_LCMXO2_640HC_impl1_map design file. + + +Loading design for application ldbanno from file RAM2GS_LCMXO2_640HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application ldbanno from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Converting design RAM2GS_LCMXO2_640HC_impl1_map.ncd into .ldb format. +Writing VHDL netlist to file RAM2GS_LCMXO2_640HC_impl1_mapvho.vho +Writing SDF timing to file RAM2GS_LCMXO2_640HC_impl1_mapvho.sdf + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 36 MB + +mpartrce -p "RAM2GS_LCMXO2_640HC_impl1.p2t" -f "RAM2GS_LCMXO2_640HC_impl1.p3t" -tf "RAM2GS_LCMXO2_640HC_impl1.pt" "RAM2GS_LCMXO2_640HC_impl1_map.ncd" "RAM2GS_LCMXO2_640HC_impl1.ncd" + +---- MParTrce Tool ---- +Removing old design directory at request of -rem command line option to this program. +Running par. Please wait . . . + +Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd" +Tue Aug 15 05:03:28 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Preference file: RAM2GS_LCMXO2_640HC_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO2_640HC_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67+4(JTAG)/80 89% used + 67+4(JTAG)/79 90% bonded + + SLICE 75/320 23% used + + + +Number of Signals: 285 +Number of Connections: 674 + + +Pin Constraint Summary: + 66 out of 67 pins locked (98% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + + + + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + + +No signal is selected as Global Set/Reset. +. +Starting Placer Phase 0. +............. +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +............... +Placer score = 121531. +Finished Placer Phase 1. REAL time: 4 secs + +Starting Placer Phase 2. +. +Placer score = 119079 +Finished Placer Phase 2. REAL time: 4 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 0 out of 8 (0%) + General PIO: 3 out of 80 (3%) + DCM : 0 out of 2 (0%) + DCC : 0 out of 8 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 8 (25%) + SECONDARY: 1 out of 8 (12%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 + 4(JTAG) out of 80 (88.8%) PIO sites used. + 67 + 4(JTAG) out of 79 (89.9%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+-----------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref | ++----------+----------------+------------+-----------+ +| 0 | 14 / 19 ( 73%) | 2.5V | - | +| 1 | 20 / 20 (100%) | 2.5V | - | +| 2 | 16 / 20 ( 80%) | 2.5V | - | +| 3 | 17 / 20 ( 85%) | 2.5V | - | ++----------+----------------+------------+-----------+ + +Total placer CPU time: 3 secs + +Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. + +0 connections routed; 674 unrouted. +Starting router resource preassignment + + + + + +Completed router resource preassignment. Real time: 7 secs + +Start NBR router at 05:03:35 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:35 08/15/23 + +Start NBR section for initial routing at 05:03:35 08/15/23 +Level 1, iteration 1 +2(0.00%) conflicts; 536(79.53%) untouched conns; 481988 (nbr) score; +Estimated worst slack/total negative slack: -4.914ns/-481.988ns; real time: 7 secs +Level 2, iteration 1 +7(0.02%) conflicts; 473(70.18%) untouched conns; 424953 (nbr) score; +Estimated worst slack/total negative slack: -4.988ns/-424.953ns; real time: 7 secs +Level 3, iteration 1 +12(0.03%) conflicts; 254(37.69%) untouched conns; 455640 (nbr) score; +Estimated worst slack/total negative slack: -5.118ns/-455.640ns; real time: 7 secs +Level 4, iteration 1 +6(0.01%) conflicts; 0(0.00%) untouched conn; 465237 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-465.237ns; real time: 7 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:35 08/15/23 +Level 4, iteration 1 +6(0.01%) conflicts; 0(0.00%) untouched conn; 461186 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.186ns; real time: 7 secs +Level 4, iteration 2 +3(0.01%) conflicts; 0(0.00%) untouched conn; 460933 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-460.933ns; real time: 7 secs +Level 4, iteration 3 +2(0.00%) conflicts; 0(0.00%) untouched conn; 461063 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs +Level 4, iteration 4 +1(0.00%) conflict; 0(0.00%) untouched conn; 461063 (nbr) score; +Estimated worst slack/total negative slack: -4.992ns/-461.063ns; real time: 7 secs +Level 4, iteration 5 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:35 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for re-routing at 05:03:35 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 468515 (nbr) score; +Estimated worst slack/total negative slack: -5.122ns/-468.515ns; real time: 7 secs + +Start NBR section for post-routing at 05:03:35 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 260 (38.58%) + Estimated worst slack : -5.122ns + Timing score : 452301 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + + + +Total CPU time 7 secs +Total REAL time: 7 secs +Completely routed. +End of route. 674 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 452301 + +Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -5.122 +PAR_SUMMARY::Timing score> = 452.301 +PAR_SUMMARY::Worst slack> = 0.304 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 7 secs +Total REAL time to completion: 7 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Exiting par with exit code 0 +Exiting mpartrce with exit code 0 + +trce -f "RAM2GS_LCMXO2_640HC_impl1.pt" -o "RAM2GS_LCMXO2_640HC_impl1.twr" "RAM2GS_LCMXO2_640HC_impl1.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:36 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Design file: ram2gs_lcmxo2_640hc_impl1.ncd +Preference file: ram2gs_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,4 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 349 Score: 452301 +Cumulative negative slack: 370485 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:36 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf +Design file: ram2gs_lcmxo2_640hc_impl1.ncd +Preference file: ram2gs_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 572 paths, 2 nets, and 409 connections (60.68% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 349 (setup), 0 (hold) +Score: 452301 (setup), 0 (hold) +Cumulative negative slack: 370485 (370485+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 40 MB + + +iotiming "RAM2GS_LCMXO2_640HC_impl1.ncd" "RAM2GS_LCMXO2_640HC_impl1.prf" +I/O Timing Report: +: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application iotiming from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: 4 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: 5 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 6 +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: 6 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: M +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Running Performance Grade: M +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... +Done. + +tmcheck -par "RAM2GS_LCMXO2_640HC_impl1.par" + +bitgen -f "RAM2GS_LCMXO2_640HC_impl1.t2b" -w "RAM2GS_LCMXO2_640HC_impl1.ncd" -jedec "RAM2GS_LCMXO2_640HC_impl1.prf" + + +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + + +Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2GS_LCMXO2_640HC_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| RamCfg | Reset** | ++---------------------------------+---------------------------------+ +| MCCLK_FREQ | 2.08** | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| JTAG_PORT | ENABLE** | ++---------------------------------+---------------------------------+ +| SDM_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| SLAVE_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MASTER_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| I2C_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MUX_CONFIGURATION_PORTS | DISABLE** | ++---------------------------------+---------------------------------+ +| CONFIGURATION | CFG** | ++---------------------------------+---------------------------------+ +| COMPRESS_CONFIG | ON** | ++---------------------------------+---------------------------------+ +| MY_ASSP | OFF** | ++---------------------------------+---------------------------------+ +| ONE_TIME_PROGRAM | OFF** | ++---------------------------------+---------------------------------+ +| ENABLE_TRANSFR | DISABLE** | ++---------------------------------+---------------------------------+ +| SHAREDEBRINIT | DISABLE** | ++---------------------------------+---------------------------------+ +| BACKGROUND_RECONFIG | OFF** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... + +Bitstream Status: Final Version 1.95. + +Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed". + +=========== +UFM Summary. +=========== +UFM Size: 191 Pages (128*191 Bits). +UFM Utilization: General Purpose Flash Memory. + +Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190). +Initialized UFM Pages: 0 Page. + +Total CPU Time: 1 secs +Total REAL Time: 2 secs +Peak Memory Usage: 245 MB diff --git a/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html new file mode 100644 index 0000000..659885d --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html @@ -0,0 +1,9 @@ + 
    Setting log file to 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
+(VERI-1482) Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-411,10) (VERI-9000) elaborating module 'RAM2GS'
+Done: design load finished with (0) errors, and (0) warnings
+
+
    \ No newline at end of file diff --git a/CPLD/LCMXO2-640HC/impl1/impl1.xcf b/CPLD/LCMXO2-640HC/impl1/impl1.xcf new file mode 100644 index 0000000..de47345 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/impl1.xcf @@ -0,0 +1,56 @@ + + + + + + JTAG + + + 1 + Lattice + MachXO2 + LCMXO2-640HC + 0x012b9043 + All + LCMXO2-640HC + + 8 + 11111111 + 1 + 0 + + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.jed + 08/15/23 04:55:55 + 0x5769 + FLASH Erase,Program,Verify + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB + EzUSB-0 + \\?\usb#vid_1134&amp;pid_8001#5&amp;887acb0&amp;0&amp;13# + + TRST ABSENT; + ISPEN ABSENT; + + + diff --git a/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior b/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior new file mode 100644 index 0000000..81484d3 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior @@ -0,0 +1,139 @@ +Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 6 +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: M +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +// Design: RAM2GS +// Package: TQFP100 +// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd +// Version: Diamond (64-bit) 3.12.1.454 +// Written on Tue Aug 15 05:03:37 2023 +// M: Minimum Performance Grade +// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml + +I/O Timing Report (All units are in ns) + +Worst Case Results across Performance Grades (M, 6, 5, 4): + +// Input Setup and Hold Times + +Port Clock Edge Setup Performance_Grade Hold Performance_Grade +---------------------------------------------------------------------- +CROW[0] nCRAS F 0.993 4 0.541 4 +CROW[1] nCRAS F 0.293 4 1.148 4 +Din[0] PHI2 F 4.804 4 1.483 4 +Din[0] nCCAS F 1.539 4 -0.150 M +Din[1] PHI2 F 4.733 4 0.702 4 +Din[1] nCCAS F 1.638 4 -0.177 M +Din[2] PHI2 F 4.046 4 1.702 4 +Din[2] nCCAS F 1.651 4 -0.121 M +Din[3] PHI2 F 4.770 4 1.575 4 +Din[3] nCCAS F 1.973 4 -0.207 M +Din[4] PHI2 F 5.656 4 0.720 4 +Din[4] nCCAS F 1.606 4 -0.156 M +Din[5] PHI2 F 4.165 4 1.131 4 +Din[5] nCCAS F 0.618 4 0.435 4 +Din[6] PHI2 F 5.309 4 1.478 4 +Din[6] nCCAS F 1.331 4 -0.053 M +Din[7] PHI2 F 5.874 4 1.774 4 +Din[7] nCCAS F 2.023 4 -0.205 M +MAin[0] PHI2 F 5.149 4 0.137 M +MAin[0] nCRAS F -0.022 M 1.415 4 +MAin[1] PHI2 F 4.216 4 1.539 4 +MAin[1] nCRAS F 1.716 4 -0.018 M +MAin[2] PHI2 F 3.754 4 0.553 4 +MAin[2] nCRAS F -0.164 M 1.715 4 +MAin[3] PHI2 F 5.957 4 -0.100 M +MAin[3] nCRAS F 0.033 4 1.356 4 +MAin[4] PHI2 F 5.652 4 -0.180 M +MAin[4] nCRAS F -0.173 M 1.726 4 +MAin[5] PHI2 F 4.938 4 0.693 6 +MAin[5] nCRAS F 0.005 4 1.395 4 +MAin[6] PHI2 F 5.535 4 -0.147 M +MAin[6] nCRAS F 0.012 4 1.387 4 +MAin[7] PHI2 F 5.951 4 -0.083 M +MAin[7] nCRAS F 0.858 4 0.664 4 +MAin[8] nCRAS F 0.526 4 0.915 4 +MAin[9] nCRAS F 0.038 4 1.342 4 +PHI2 RCLK R 2.772 4 -0.342 M +UFMSDO RCLK R 0.780 4 0.632 4 +nCCAS RCLK R 0.557 4 0.872 4 +nCCAS nCRAS F 2.108 4 -0.053 M +nCRAS RCLK R 2.536 4 -0.169 M +nFWE PHI2 F 5.830 4 0.629 4 +nFWE nCRAS F 1.386 4 0.176 4 + + +// Clock to Output Delay + +Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade +------------------------------------------------------------------------ +LED RCLK R 11.611 4 3.288 M +LED nCRAS F 12.009 4 3.367 M +RA[0] RCLK R 12.268 4 3.492 M +RA[0] nCRAS F 11.741 4 3.284 M +RA[10] RCLK R 10.004 4 2.964 M +RA[11] PHI2 R 10.669 4 3.160 M +RA[1] RCLK R 12.975 4 3.665 M +RA[1] nCRAS F 11.918 4 3.321 M +RA[2] RCLK R 12.531 4 3.533 M +RA[2] nCRAS F 11.755 4 3.277 M +RA[3] RCLK R 11.851 4 3.375 M +RA[3] nCRAS F 12.624 4 3.513 M +RA[4] RCLK R 13.380 4 3.775 M +RA[4] nCRAS F 12.857 4 3.569 M +RA[5] RCLK R 12.767 4 3.632 M +RA[5] nCRAS F 12.469 4 3.456 M +RA[6] RCLK R 12.163 4 3.468 M +RA[6] nCRAS F 12.141 4 3.394 M +RA[7] RCLK R 11.990 4 3.375 M +RA[7] nCRAS F 12.172 4 3.381 M +RA[8] RCLK R 11.712 4 3.314 M +RA[8] nCRAS F 12.431 4 3.457 M +RA[9] RCLK R 11.412 4 3.233 M +RA[9] nCRAS F 12.128 4 3.377 M +RBA[0] nCRAS F 10.844 4 3.124 M +RBA[1] nCRAS F 10.216 4 2.967 M +RCKE RCLK R 10.964 4 3.209 M +RDQMH RCLK R 12.109 4 3.426 M +RDQML RCLK R 10.974 4 3.140 M +RD[0] nCCAS F 8.747 4 2.603 M +RD[1] nCCAS F 8.747 4 2.603 M +RD[2] nCCAS F 8.737 4 2.605 M +RD[3] nCCAS F 9.239 4 2.740 M +RD[4] nCCAS F 9.283 4 2.726 M +RD[5] nCCAS F 9.355 4 2.761 M +RD[6] nCCAS F 9.106 4 2.681 M +RD[7] nCCAS F 9.181 4 2.711 M +UFMCLK RCLK R 10.078 4 3.002 M +UFMSDI RCLK R 10.108 4 2.996 M +nRCAS RCLK R 10.525 4 3.100 M +nRCS RCLK R 10.119 4 2.984 M +nRRAS RCLK R 10.200 4 3.024 M +nRWE RCLK R 9.984 4 2.972 M +nUFMCS RCLK R 10.165 4 3.020 M +WARNING: you must also run trce with hold speed: 4 +WARNING: you must also run trce with hold speed: 6 +WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd b/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd new file mode 100644 index 0000000..018a633 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1_trce.asd @@ -0,0 +1,13 @@ +[ActiveSupport TRCE] +; Setup Analysis +Fmax_0 = 160.205 MHz (299.401 MHz); +Fmax_1 = 65.729 MHz (99.079 MHz); +Failed = 2 (Total 2); +Clock_ports = 4; +Clock_nets = 4; +; Hold Analysis +Fmax_0 = 0.304 ns (0.000 ns); +Fmax_1 = 0.379 ns (0.000 ns); +Failed = 0 (Total 2); +Clock_ports = 4; +Clock_nets = 4; diff --git a/CPLD/LCMXO2-640HC/impl1/synthesis.log b/CPLD/LCMXO2-640HC/impl1/synthesis.log new file mode 100644 index 0000000..c8e59c3 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/synthesis.log @@ -0,0 +1,237 @@ +synthesis: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:22 2023 + + +Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml + +Synthesis options: +The -a option is MachXO2. +The -s option is 4. +The -t option is TQFP100. +The -d option is LCMXO2-640HC. +Using package TQFP100. +Using performance grade 4. + + +########################################################## + +### Lattice Family : MachXO2 + +### Device : LCMXO2-640HC + +### Package : TQFP100 + +### Speed : 4 + +########################################################## + + + +INFO - synthesis: User-Selected Strategy Settings +Optimization goal = Balanced +Top-level module name = RAM2GS. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added) +-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1 (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added) +Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v +NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 +Compile design. +Compile Design Begin +Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 +Top module name (Verilog): RAM2GS +INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209 +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Top-level module name = RAM2GS. +INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding +original encoding -> new encoding (one-hot encoding) + + 0000 -> 0000000000000001 + + 0001 -> 0000000000000010 + + 0010 -> 0000000000000100 + + 0011 -> 0000000000001000 + + 0100 -> 0000000000010000 + + 0101 -> 0000000000100000 + + 0110 -> 0000000001000000 + + 0111 -> 0000000010000000 + + 1000 -> 0000000100000000 + + 1001 -> 0000001000000000 + + 1010 -> 0000010000000000 + + 1011 -> 0000100000000000 + + 1100 -> 0001000000000000 + + 1101 -> 0010000000000000 + + 1110 -> 0100000000000000 + + 1111 -> 1000000000000000 + +INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding +original encoding -> new encoding (one-hot encoding) + + 00 -> 0001 + + 01 -> 0010 + + 10 -> 0100 + + 11 -> 1000 + + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. +WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored. +Applying 200.000000 MHz constraint to all clocks + +WARNING - synthesis: No user .sdc file. +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd. + +################### Begin Area Report (RAM2GS)###################### +Number of register bits => 102 of 877 (11 % ) +BB => 8 +CCU2D => 10 +FD1P3AX => 29 +FD1P3AY => 5 +FD1P3IX => 3 +FD1S3AX => 47 +FD1S3IX => 14 +FD1S3JX => 4 +GSR => 1 +IB => 26 +INV => 3 +LUT4 => 122 +OB => 33 +PFUMX => 1 +################### End Area Report ################## + +################### Begin BlackBox Report ###################### +TSALL => 1 +################### End BlackBox Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 4 + Net : RCLK_c, loads : 62 + Net : PHI2_c, loads : 11 + Net : nCCAS_c, loads : 2 + Net : nCRAS_c, loads : 2 +Clock Enable Nets +Number of Clock Enables: 14 +Top 10 highest fanout Clock Enables: + Net : RCLK_c_enable_27, loads : 16 + Net : RCLK_c_enable_6, loads : 4 + Net : PHI2_N_120_enable_8, loads : 3 + Net : RCLK_c_enable_10, loads : 3 + Net : RCLK_c_enable_5, loads : 2 + Net : PHI2_N_120_enable_3, loads : 1 + Net : Ready_N_292, loads : 1 + Net : PHI2_N_120_enable_2, loads : 1 + Net : RCLK_c_enable_15, loads : 1 + Net : PHI2_N_120_enable_6, loads : 1 +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : RCLK_c_enable_27, loads : 16 + Net : InitReady, loads : 15 + Net : nCRAS_c__inv, loads : 15 + Net : RASr2, loads : 14 + Net : nRowColSel_N_35, loads : 13 + Net : n2380, loads : 13 + Net : nRowColSel, loads : 12 + Net : Ready, loads : 12 + Net : Din_c_4, loads : 10 + Net : MAin_c_1, loads : 10 +################### End Clock Report ################## + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 200.000 MHz| 50.413 MHz| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 200.000 MHz| 120.207 MHz| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + + +Peak Memory Usage: 53.555 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 0.828 secs +-------------------------------------------------------------- diff --git a/CPLD/LCMXO2-640HC/impl1/synthesis_lse.html b/CPLD/LCMXO2-640HC/impl1/synthesis_lse.html new file mode 100644 index 0000000..c8b6b6a --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/synthesis_lse.html @@ -0,0 +1,302 @@ + +Synthesis and Ngdbuild Report + + +
    Synthesis and Ngdbuild  Report
+synthesis:  version Diamond (64-bit) 3.12.1.454
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:22 2023
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml 
+
+Synthesis options:
+The -a option is MachXO2.
+The -s option is 4.
+The -t option is TQFP100.
+The -d option is LCMXO2-640HC.
+Using package TQFP100.
+Using performance grade 4.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO2
+
+### Device  : LCMXO2-640HC
+
+### Package : TQFP100
+
+### Speed   : 4
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1 (searchpath added)
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC (searchpath added)
+Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
+NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Top-level module name = RAM2GS.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO2_640HC_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 102 of 877 (11 % )
+BB => 8
+CCU2D => 10
+FD1P3AX => 29
+FD1P3AY => 5
+FD1P3IX => 3
+FD1S3AX => 47
+FD1S3IX => 14
+FD1S3JX => 4
+GSR => 1
+IB => 26
+INV => 3
+LUT4 => 122
+OB => 33
+PFUMX => 1
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 4
+  Net : RCLK_c, loads : 62
+  Net : PHI2_c, loads : 11
+  Net : nCCAS_c, loads : 2
+  Net : nCRAS_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 14
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_27, loads : 16
+  Net : RCLK_c_enable_6, loads : 4
+  Net : PHI2_N_120_enable_8, loads : 3
+  Net : RCLK_c_enable_10, loads : 3
+  Net : RCLK_c_enable_5, loads : 2
+  Net : PHI2_N_120_enable_3, loads : 1
+  Net : Ready_N_292, loads : 1
+  Net : PHI2_N_120_enable_2, loads : 1
+  Net : RCLK_c_enable_15, loads : 1
+  Net : PHI2_N_120_enable_6, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : RCLK_c_enable_27, loads : 16
+  Net : InitReady, loads : 15
+  Net : nCRAS_c__inv, loads : 15
+  Net : RASr2, loads : 14
+  Net : nRowColSel_N_35, loads : 13
+  Net : n2380, loads : 13
+  Net : nRowColSel, loads : 12
+  Net : Ready, loads : 12
+  Net : Din_c_4, loads : 10
+  Net : MAin_c_1, loads : 10
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |  200.000 MHz|   50.413 MHz|     6 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|  120.207 MHz|     5 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 53.555  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.828  secs
+--------------------------------------------------------------
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO2-640HC/impl1/xxx_lse_cp_file_list new file mode 100644 index 0000000..1c1a02c --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/xxx_lse_cp_file_list @@ -0,0 +1,250 @@ +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v diff --git a/CPLD/LCMXO2-640HC/impl1/xxx_lse_sign_file b/CPLD/LCMXO2-640HC/impl1/xxx_lse_sign_file new file mode 100644 index 0000000..7e27975 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/xxx_lse_sign_file @@ -0,0 +1,250 @@ +LSE_CPS_ID_1 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" +LSE_CPS_ID_2 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_3 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:186[13] 231[7]" +LSE_CPS_ID_4 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_5 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_6 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_7 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_8 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_9 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_10 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_11 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_12 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_13 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_14 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_15 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_16 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_17 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_18 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_19 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:141[9] 144[5]" +LSE_CPS_ID_20 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_21 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_22 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_23 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_24 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_25 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_26 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_27 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:255[14] 262[8]" +LSE_CPS_ID_28 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_29 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_30 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_31 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_32 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_33 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_34 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_35 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_36 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:321[13] 335[7]" +LSE_CPS_ID_37 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_38 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_39 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_40 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_41 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_42 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_43 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_44 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:99[22:51]" +LSE_CPS_ID_45 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_46 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_47 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_48 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_49 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_50 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_51 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_52 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_53 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_54 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_55 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:168[14] 184[8]" +LSE_CPS_ID_56 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_57 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_58 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_59 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_60 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_61 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_62 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_63 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:345[12] 409[6]" +LSE_CPS_ID_64 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_65 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:58[17:46]" +LSE_CPS_ID_66 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_67 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:195[13] 231[7]" +LSE_CPS_ID_68 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_69 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_70 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_71 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_72 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_73 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_74 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_75 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:83[6:15]" +LSE_CPS_ID_76 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_77 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:195[13] 231[7]" +LSE_CPS_ID_78 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_79 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_80 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_81 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:83[6:15]" +LSE_CPS_ID_82 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_83 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_84 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:86[13:15]" +LSE_CPS_ID_85 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_86 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_87 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_88 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:233[8:20]" +LSE_CPS_ID_89 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:233[8:20]" +LSE_CPS_ID_90 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_91 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_92 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_93 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_94 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_95 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_96 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_97 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_98 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_99 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_100 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_101 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_102 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:233[8:20]" +LSE_CPS_ID_103 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:15[12:17]" +LSE_CPS_ID_104 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_105 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_106 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_107 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_108 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_109 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_110 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[27:31]" +LSE_CPS_ID_111 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:83[6:15]" +LSE_CPS_ID_112 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_113 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_114 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_115 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_116 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_117 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_118 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_119 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_120 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_121 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_122 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_123 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_124 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_125 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_126 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_127 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_128 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_129 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_130 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_131 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_132 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_133 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_134 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_135 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_136 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_137 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_138 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_139 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_140 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_141 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_142 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_143 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_144 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_145 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_146 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_147 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_148 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_149 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_150 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_151 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_152 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_153 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_154 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_155 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" +LSE_CPS_ID_156 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[40:46]" +LSE_CPS_ID_157 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[40:46]" +LSE_CPS_ID_158 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_159 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_160 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_161 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_162 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_163 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_164 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_165 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_166 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_167 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_168 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_169 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_170 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" +LSE_CPS_ID_171 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_172 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_173 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_174 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_175 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_176 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_177 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_178 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_179 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_180 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_181 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:22[9:12]" +LSE_CPS_ID_182 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" +LSE_CPS_ID_183 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" +LSE_CPS_ID_184 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_185 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_186 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_187 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_188 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_189 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_190 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_191 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_192 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_193 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_194 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_195 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_196 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[13:17]" +LSE_CPS_ID_197 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:45[13:17]" +LSE_CPS_ID_198 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[45:49]" +LSE_CPS_ID_199 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[23:28]" +LSE_CPS_ID_200 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[34:39]" +LSE_CPS_ID_201 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[16:21]" +LSE_CPS_ID_202 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[9:14]" +LSE_CPS_ID_203 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:63[13:19]" +LSE_CPS_ID_204 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:64[13:19]" +LSE_CPS_ID_205 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:65[13:19]" +LSE_CPS_ID_206 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" +LSE_CPS_ID_207 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_208 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_209 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_210 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_211 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_212 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_213 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_214 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_215 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_216 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_217 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" +LSE_CPS_ID_218 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" +LSE_CPS_ID_219 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_220 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_221 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_222 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_223 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_224 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_225 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_226 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_227 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" +LSE_CPS_ID_228 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" +LSE_CPS_ID_229 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:36[8:12]" +LSE_CPS_ID_230 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:41[8:12]" +LSE_CPS_ID_231 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:66[8:14]" +LSE_CPS_ID_232 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_233 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[17:23]" +LSE_CPS_ID_234 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_235 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_236 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_237 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_238 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_239 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:134[9] 138[5]" +LSE_CPS_ID_240 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_241 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_242 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_243 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_244 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_245 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_246 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" +LSE_CPS_ID_247 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" +LSE_CPS_ID_248 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_249 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" +LSE_CPS_ID_250 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" diff --git a/CPLD/LCMXO256C/.run_manager.ini b/CPLD/LCMXO256C/.run_manager.ini new file mode 100644 index 0000000..8c0aa7b --- /dev/null +++ b/CPLD/LCMXO256C/.run_manager.ini @@ -0,0 +1,9 @@ +[Runmanager] +Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) +windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) + +[impl1%3CStrategy1%3E] +isChecked=false +isHidden=false +isExpanded=false diff --git a/CPLD/LCMXO256C/.setting.ini b/CPLD/LCMXO256C/.setting.ini new file mode 100644 index 0000000..42d73b0 --- /dev/null +++ b/CPLD/LCMXO256C/.setting.ini @@ -0,0 +1,5 @@ +[General] +AutoAssign=false +Map.auto_tasks=MapEqu, MapTrace, MapVerilogSimFile, MapVHDLSimFile +Export.auto_tasks=Bitgen +PAR.auto_tasks=PARTrace, IOTiming diff --git a/CPLD/LCMXO256C/.spread_sheet.ini b/CPLD/LCMXO256C/.spread_sheet.ini new file mode 100644 index 0000000..6c511f4 --- /dev/null +++ b/CPLD/LCMXO256C/.spread_sheet.ini @@ -0,0 +1,3 @@ +[General] +COLUMN_POS_INFO_NAME_-1_0=Prioritize +COLUMN_POS_INFO_NAME_-1_1=PIO Register diff --git a/CPLD/LCMXO256C/.spreadsheet_view.ini b/CPLD/LCMXO256C/.spreadsheet_view.ini new file mode 100644 index 0000000..3815c07 --- /dev/null +++ b/CPLD/LCMXO256C/.spreadsheet_view.ini @@ -0,0 +1,65 @@ +[General] +pin_sort_type=0 +pin_sort_ascending=true +sig_sort_type=0 +sig_sort_ascending=true +active_Sheet=Port Assignments + +[Port%20Assignments] +Name="166,0" +Group%20By="84,1" +Pin="63,2" +BANK="62,3" +IO_TYPE="147,4" +PULLMODE="92,5" +DRIVE="67,6" +SLEWRATE="92,7" +OPENDRAIN="97,8" +Outload%20%28pF%29="103,9" +MaxSkew="87,10" +Clock%20Load%20Only="121,11" +sort_columns="Name,Ascending" + +[Pin%20Assignments] +Pin="90,0" +Pad%20Name="89,1" +Dual%20Function="109,2" +Polarity="77,3" +BANK="0,4" +IO_TYPE="147,5" +Signal%20Name="123,6" +Signal%20Type="115,7" +sort_columns="Pin,Ascending" + +[Clock%20Resource] +Clock%20Type="100,ELLIPSIS" +Clock%20Name="100,ELLIPSIS" +Selection="100,ELLIPSIS" + +[Global%20Preferences] +Preference%20Name="222,ELLIPSIS" +Preference%20Value="236,ELLIPSIS" + +[Cell%20Mapping] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Din\Dout="100,ELLIPSIS" +PIO%20Register="100,ELLIPSIS" + +[Route%20Priority] +Type="100,ELLIPSIS" +Name="100,ELLIPSIS" +Prioritize="100,ELLIPSIS" + +[Timing%20Preferences] +Preference%20Name="129,ELLIPSIS" +Preference%20Value="105,ELLIPSIS" +Preference%20Unit="98,ELLIPSIS" + +[Group] +Group%20Type\Name="134,ELLIPSIS" +Value="39,ELLIPSIS" + +[Misc%20Preferences] +Preference%20Name="117,ELLIPSIS" +Preference%20Value="105,ELLIPSIS" diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ccl b/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ccl new file mode 100644 index 0000000..dcf391b --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ccl @@ -0,0 +1 @@ +VERSION=20110520 diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf b/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf new file mode 100644 index 0000000..e3d6ead --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf b/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf new file mode 100644 index 0000000..64fb54f --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf @@ -0,0 +1,137 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +IOBUF ALLPORTS PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "CROW[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "CROW[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "PHI2" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RCLK" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nCCAS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nCRAS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[8]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[9]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "UFMSDO" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nFWE" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "LED" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[8]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[9]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[10]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[11]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RBA[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RBA[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RCKE" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RDQMH" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RDQML" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "UFMCLK" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "UFMSDI" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nRCAS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nRCS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nRRAS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nRWE" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nUFMCS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[9]" SITE "51" ; +LOCATE COMP "UFMSDO" SITE "55" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[7]" SITE "71" ; diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C1.sty b/CPLD/LCMXO256C/RAM2GS_LCMXO256C1.sty new file mode 100644 index 0000000..feec63c --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C1.sty @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcl.html b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcl.html new file mode 100644 index 0000000..f31653f --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcl.html @@ -0,0 +1,94 @@ + +Lattice TCL Log + + +
    pn230815043617
+#Start recording tcl command: 8/15/2023 04:36:06
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C
+D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C
+RAM2GS_LCMXO640C
+#Start recording tcl command: 8/15/2023 04:36:17
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf"
+prj_project saveas -name "RAM2GS_LCMXO640C" -dir "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C"
+#Stop recording: 8/15/2023 04:36:17
+
+
+
+pn230815044855
+#Start recording tcl command: 8/15/2023 04:40:11
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf"
+prj_run Export -impl impl1
+pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/impl1.xcf"
+pgr_program run
+prj_project close
+#Stop recording: 8/15/2023 04:48:55
+
+
+
+pn230815050150
+#Start recording tcl command: 8/15/2023 05:01:45
+#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C
+prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf"
+#Stop recording: 8/15/2023 05:01:50
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815043617.tcr b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815043617.tcr new file mode 100644 index 0000000..418d2c6 --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815043617.tcr @@ -0,0 +1,9 @@ +#Start recording tcl command: 8/15/2023 04:36:06 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C +RAM2GS_LCMXO640C +#Start recording tcl command: 8/15/2023 04:36:17 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C +prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf" +prj_project saveas -name "RAM2GS_LCMXO640C" -dir "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C" +#Stop recording: 8/15/2023 04:36:17 diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815044855.tcr b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815044855.tcr new file mode 100644 index 0000000..d2c430a --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815044855.tcr @@ -0,0 +1,8 @@ +#Start recording tcl command: 8/15/2023 04:40:11 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C +prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf" +prj_run Export -impl impl1 +pgr_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/impl1.xcf" +pgr_program run +prj_project close +#Stop recording: 8/15/2023 04:48:55 diff --git a/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815050150.tcr b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815050150.tcr new file mode 100644 index 0000000..d106ad4 --- /dev/null +++ b/CPLD/LCMXO256C/RAM2GS_LCMXO256C_tcr.dir/pn230815050150.tcr @@ -0,0 +1,4 @@ +#Start recording tcl command: 8/15/2023 05:01:45 +#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C +prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf" +#Stop recording: 8/15/2023 05:01:50 diff --git a/CPLD/LCMXO256C/hdlparser.log b/CPLD/LCMXO256C/hdlparser.log new file mode 100644 index 0000000..0c6993f --- /dev/null +++ b/CPLD/LCMXO256C/hdlparser.log @@ -0,0 +1,3 @@ +-- all messages logged in file hdlparser.log +-- Analyzing Verilog file 'C:/lscc/diamond/3.12/cae_library/synthesis/verilog/machxo.v' (VERI-1482) +-- Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v' (VERI-1482) diff --git a/CPLD/LCMXO256C/impl1/.build_status b/CPLD/LCMXO256C/impl1/.build_status new file mode 100644 index 0000000..67a7f04 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/.build_status @@ -0,0 +1,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_LCMXO256C_impl1_map.vdb b/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_LCMXO256C_impl1_map.vdb new file mode 100644 index 0000000..b00bbf8 Binary files /dev/null and b/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_LCMXO256C_impl1_map.vdb differ diff --git a/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_rtl.vdb b/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_rtl.vdb new file mode 100644 index 0000000..c710a28 Binary files /dev/null and b/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_rtl.vdb differ diff --git a/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_tech.vdb b/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_tech.vdb new file mode 100644 index 0000000..7480697 Binary files /dev/null and b/CPLD/LCMXO256C/impl1/.vdbs/RAM2GS_tech.vdb differ diff --git a/CPLD/LCMXO256C/impl1/.vdbs/dbStat.txt b/CPLD/LCMXO256C/impl1/.vdbs/dbStat.txt new file mode 100644 index 0000000..0a575a4 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/.vdbs/dbStat.txt @@ -0,0 +1 @@ +RAM2GS_rtl.vdb diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt new file mode 100644 index 0000000..deaaf52 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.alt @@ -0,0 +1,75 @@ +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Tue Aug 15 05:03:33 2023 * +NOTE DESIGN NAME: RAM2GS * +NOTE DEVICE NAME: LCMXO256C-3TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[7] : 71 : inout * +NOTE PINS RD[6] : 70 : inout * +NOTE PINS RD[5] : 69 : inout * +NOTE PINS RD[4] : 68 : inout * +NOTE PINS RD[3] : 67 : inout * +NOTE PINS RD[2] : 66 : inout * +NOTE PINS RD[1] : 65 : inout * +NOTE PINS RD[0] : 64 : inout * +NOTE PINS Dout[7] : 3 : out * +NOTE PINS Dout[6] : 2 : out * +NOTE PINS Dout[5] : 5 : out * +NOTE PINS Dout[4] : 4 : out * +NOTE PINS Dout[3] : 6 : out * +NOTE PINS Dout[2] : 8 : out * +NOTE PINS Dout[1] : 7 : out * +NOTE PINS Dout[0] : 1 : out * +NOTE PINS LED : 57 : out * +NOTE PINS RBA[1] : 83 : out * +NOTE PINS RBA[0] : 63 : out * +NOTE PINS RA[11] : 79 : out * +NOTE PINS RA[10] : 87 : out * +NOTE PINS RA[9] : 85 : out * +NOTE PINS RA[8] : 96 : out * +NOTE PINS RA[7] : 100 : out * +NOTE PINS RA[6] : 91 : out * +NOTE PINS RA[5] : 95 : out * +NOTE PINS RA[4] : 99 : out * +NOTE PINS RA[3] : 97 : out * +NOTE PINS RA[2] : 94 : out * +NOTE PINS RA[1] : 89 : out * +NOTE PINS RA[0] : 98 : out * +NOTE PINS nRCS : 77 : out * +NOTE PINS RCKE : 82 : out * +NOTE PINS nRWE : 72 : out * +NOTE PINS nRRAS : 73 : out * +NOTE PINS nRCAS : 78 : out * +NOTE PINS RDQMH : 76 : out * +NOTE PINS RDQML : 61 : out * +NOTE PINS nUFMCS : 53 : out * +NOTE PINS UFMCLK : 58 : out * +NOTE PINS UFMSDI : 56 : out * +NOTE PINS PHI2 : 39 : in * +NOTE PINS MAin[9] : 51 : in * +NOTE PINS MAin[8] : 50 : in * +NOTE PINS MAin[7] : 44 : in * +NOTE PINS MAin[6] : 49 : in * +NOTE PINS MAin[5] : 45 : in * +NOTE PINS MAin[4] : 46 : in * +NOTE PINS MAin[3] : 47 : in * +NOTE PINS MAin[2] : 37 : in * +NOTE PINS MAin[1] : 38 : in * +NOTE PINS MAin[0] : 23 : in * +NOTE PINS CROW[1] : 34 : in * +NOTE PINS CROW[0] : 32 : in * +NOTE PINS Din[7] : 19 : in * +NOTE PINS Din[6] : 20 : in * +NOTE PINS Din[5] : 17 : in * +NOTE PINS Din[4] : 18 : in * +NOTE PINS Din[3] : 16 : in * +NOTE PINS Din[2] : 14 : in * +NOTE PINS Din[1] : 15 : in * +NOTE PINS Din[0] : 21 : in * +NOTE PINS nCCAS : 27 : in * +NOTE PINS nCRAS : 43 : in * +NOTE PINS nFWE : 22 : in * +NOTE PINS RCLK : 86 : in * +NOTE PINS UFMSDO : 55 : in * +NOTE CONFIGURATION MODE: NONE * +NOTE COMPRESSION: off * diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.arearep b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.arearep new file mode 100644 index 0000000..e9c8bb7 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.arearep @@ -0,0 +1,23 @@ +---------------------------------------------------------------------- +Report for cell RAM2GS.TECH +Register bits: 102 of 490 (20.816%) +I/O cells: 67 + Cell usage: + cell count Res Usage(%) + BB 8 100.0 + CCU2 9 100.0 + FD1P3AX 28 100.0 + FD1P3AY 3 100.0 + FD1P3IX 2 100.0 + FD1S3AX 47 100.0 + FD1S3AY 1 100.0 + FD1S3IX 16 100.0 + FD1S3JX 5 100.0 + GSR 1 100.0 + IB 26 100.0 + INV 3 100.0 + LUT4 126 100.0 + OB 33 100.0 + ORCALUT4 1 100.0 + PFUMX 6 100.0 + TOTAL 315 diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn new file mode 100644 index 0000000..63c7186 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bgn @@ -0,0 +1,45 @@ +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:33 2023 + + +Command: bitgen -w -g ES:No -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf + +Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2GS_LCMXO256C_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| ES | No** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... +Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit". +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 44 MB diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bit b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bit new file mode 100644 index 0000000..6a513fb Binary files /dev/null and b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.bit differ diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.ncd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.ncd new file mode 100644 index 0000000..113a28f Binary files /dev/null and b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.ncd differ diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad new file mode 100644 index 0000000..4582186 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.pad @@ -0,0 +1,271 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO256C +Performance Grade: 3 +PACKAGE: TQFP100 +Package Status: Final Version 1.19 + +Tue Aug 15 05:03:28 2023 + +Pinout by Port Name: ++-----------+----------+---------------+------+------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | Properties | ++-----------+----------+---------------+------+------------------------------+ +| CROW[0] | 32/1 | LVCMOS33_IN | PB2C | SLEW:FAST PULL:UP | +| CROW[1] | 34/1 | LVCMOS33_IN | PB2D | SLEW:FAST PULL:UP | +| Din[0] | 21/1 | LVCMOS33_IN | PL8A | SLEW:FAST PULL:UP | +| Din[1] | 15/1 | LVCMOS33_IN | PL6A | SLEW:FAST PULL:UP | +| Din[2] | 14/1 | LVCMOS33_IN | PL5D | SLEW:FAST PULL:UP | +| Din[3] | 16/1 | LVCMOS33_IN | PL6B | SLEW:FAST PULL:UP | +| Din[4] | 18/1 | LVCMOS33_IN | PL7B | SLEW:FAST PULL:UP | +| Din[5] | 17/1 | LVCMOS33_IN | PL7A | SLEW:FAST PULL:UP | +| Din[6] | 20/1 | LVCMOS33_IN | PL7D | SLEW:FAST PULL:UP | +| Din[7] | 19/1 | LVCMOS33_IN | PL7C | SLEW:FAST PULL:UP | +| Dout[0] | 1/1 | LVCMOS33_OUT | PL2A | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[1] | 7/1 | LVCMOS33_OUT | PL4A | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[2] | 8/1 | LVCMOS33_OUT | PL4B | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[3] | 6/1 | LVCMOS33_OUT | PL3D | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[4] | 4/1 | LVCMOS33_OUT | PL3B | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[5] | 5/1 | LVCMOS33_OUT | PL3C | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[6] | 2/1 | LVCMOS33_OUT | PL2B | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[7] | 3/1 | LVCMOS33_OUT | PL3A | DRIVE:8mA SLEW:FAST PULL:UP | +| LED | 57/0 | LVCMOS33_OUT | PR7B | DRIVE:8mA SLEW:FAST PULL:UP | +| MAin[0] | 23/1 | LVCMOS33_IN | PL9A | SLEW:FAST PULL:UP | +| MAin[1] | 38/1 | LVCMOS33_IN | PB3C | SLEW:FAST PULL:UP | +| MAin[2] | 37/1 | LVCMOS33_IN | PB3B | SLEW:FAST PULL:UP | +| MAin[3] | 47/1 | LVCMOS33_IN | PB5A | SLEW:FAST PULL:UP | +| MAin[4] | 46/1 | LVCMOS33_IN | PB4D | SLEW:FAST PULL:UP | +| MAin[5] | 45/1 | LVCMOS33_IN | PB4C | SLEW:FAST PULL:UP | +| MAin[6] | 49/1 | LVCMOS33_IN | PB5C | SLEW:FAST PULL:UP | +| MAin[7] | 44/1 | LVCMOS33_IN | PB4B | SLEW:FAST PULL:UP | +| MAin[8] | 50/1 | LVCMOS33_IN | PB5D | SLEW:FAST PULL:UP | +| MAin[9] | 51/0 | LVCMOS33_IN | PR9B | SLEW:FAST PULL:UP | +| PHI2 | 39/1 | LVCMOS33_IN | PB3D | SLEW:FAST PULL:UP | +| RA[0] | 98/0 | LVCMOS33_OUT | PT2C | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[10] | 87/0 | LVCMOS33_OUT | PT3D | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[11] | 79/0 | LVCMOS33_OUT | PT5A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[1] | 89/0 | LVCMOS33_OUT | PT3C | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[2] | 94/0 | LVCMOS33_OUT | PT3A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[3] | 97/0 | LVCMOS33_OUT | PT2D | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[4] | 99/0 | LVCMOS33_OUT | PT2B | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[5] | 95/0 | LVCMOS33_OUT | PT2F | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[6] | 91/0 | LVCMOS33_OUT | PT3B | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[7] | 100/0 | LVCMOS33_OUT | PT2A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[8] | 96/0 | LVCMOS33_OUT | PT2E | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[9] | 85/0 | LVCMOS33_OUT | PT4B | DRIVE:8mA SLEW:FAST PULL:UP | +| RBA[0] | 63/0 | LVCMOS33_OUT | PR5D | DRIVE:8mA SLEW:FAST PULL:UP | +| RBA[1] | 83/0 | LVCMOS33_OUT | PT4C | DRIVE:8mA SLEW:FAST PULL:UP | +| RCKE | 82/0 | LVCMOS33_OUT | PT4D | DRIVE:8mA SLEW:FAST PULL:UP | +| RCLK | 86/0 | LVCMOS33_IN | PT4A | SLEW:FAST PULL:UP | +| RDQMH | 76/0 | LVCMOS33_OUT | PR2A | DRIVE:8mA SLEW:FAST PULL:UP | +| RDQML | 61/0 | LVCMOS33_OUT | PR6A | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[0] | 64/0 | LVCMOS33_BIDI | PR5C | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[1] | 65/0 | LVCMOS33_BIDI | PR5B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[2] | 66/0 | LVCMOS33_BIDI | PR5A | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[3] | 67/0 | LVCMOS33_BIDI | PR4B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[4] | 68/0 | LVCMOS33_BIDI | PR4A | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[5] | 69/0 | LVCMOS33_BIDI | PR3D | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[6] | 70/0 | LVCMOS33_BIDI | PR3C | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[7] | 71/0 | LVCMOS33_BIDI | PR3B | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMCLK | 58/0 | LVCMOS33_OUT | PR7A | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMSDI | 56/0 | LVCMOS33_OUT | PR7C | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMSDO | 55/0 | LVCMOS33_IN | PR7D | SLEW:FAST PULL:UP | +| nCCAS | 27/1 | LVCMOS33_IN | PL9B | SLEW:FAST PULL:UP | +| nCRAS | 43/1 | LVCMOS33_IN | PB4A | SLEW:FAST PULL:UP | +| nFWE | 22/1 | LVCMOS33_IN | PL8B | SLEW:FAST PULL:UP | +| nRCAS | 78/0 | LVCMOS33_OUT | PT5B | DRIVE:8mA SLEW:FAST PULL:UP | +| nRCS | 77/0 | LVCMOS33_OUT | PT5C | DRIVE:8mA SLEW:FAST PULL:UP | +| nRRAS | 73/0 | LVCMOS33_OUT | PR2B | DRIVE:8mA SLEW:FAST PULL:UP | +| nRWE | 72/0 | LVCMOS33_OUT | PR3A | DRIVE:8mA SLEW:FAST PULL:UP | +| nUFMCS | 53/0 | LVCMOS33_OUT | PR8B | DRIVE:8mA SLEW:FAST PULL:UP | ++-----------+----------+---------------+------+------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 3.3V | +| 1 | 3.3V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+---------------------+------------+---------------+------+---------------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | ++----------+---------------------+------------+---------------+------+---------------+ +| 1/1 | Dout[0] | LOCATED | LVCMOS33_OUT | PL2A | | +| 2/1 | Dout[6] | LOCATED | LVCMOS33_OUT | PL2B | | +| 3/1 | Dout[7] | LOCATED | LVCMOS33_OUT | PL3A | | +| 4/1 | Dout[4] | LOCATED | LVCMOS33_OUT | PL3B | | +| 5/1 | Dout[5] | LOCATED | LVCMOS33_OUT | PL3C | | +| 6/1 | Dout[3] | LOCATED | LVCMOS33_OUT | PL3D | | +| 7/1 | Dout[1] | LOCATED | LVCMOS33_OUT | PL4A | | +| 8/1 | Dout[2] | LOCATED | LVCMOS33_OUT | PL4B | | +| 9/1 | unused, PULL:UP | | | PL5A | | +| 11/1 | unused, PULL:UP | | | PL5B | | +| 13/1 | unused, PULL:UP | | | PL5C | | +| 14/1 | Din[2] | LOCATED | LVCMOS33_IN | PL5D | GSR_PADN | +| 15/1 | Din[1] | LOCATED | LVCMOS33_IN | PL6A | | +| 16/1 | Din[3] | LOCATED | LVCMOS33_IN | PL6B | TSALLPAD | +| 17/1 | Din[5] | LOCATED | LVCMOS33_IN | PL7A | | +| 18/1 | Din[4] | LOCATED | LVCMOS33_IN | PL7B | | +| 19/1 | Din[7] | LOCATED | LVCMOS33_IN | PL7C | | +| 20/1 | Din[6] | LOCATED | LVCMOS33_IN | PL7D | | +| 21/1 | Din[0] | LOCATED | LVCMOS33_IN | PL8A | | +| 22/1 | nFWE | LOCATED | LVCMOS33_IN | PL8B | | +| 23/1 | MAin[0] | LOCATED | LVCMOS33_IN | PL9A | | +| 27/1 | nCCAS | LOCATED | LVCMOS33_IN | PL9B | | +| 29/1 | unused, PULL:UP | | | PB2A | | +| 30/1 | unused, PULL:UP | | | PB2B | | +| 32/1 | CROW[0] | LOCATED | LVCMOS33_IN | PB2C | | +| 34/1 | CROW[1] | LOCATED | LVCMOS33_IN | PB2D | | +| 36/1 | unused, PULL:UP | | | PB3A | PCLKT1_1 | +| 37/1 | MAin[2] | LOCATED | LVCMOS33_IN | PB3B | | +| 38/1 | MAin[1] | LOCATED | LVCMOS33_IN | PB3C | PCLKT1_0 | +| 39/1 | PHI2 | LOCATED | LVCMOS33_IN | PB3D | | +| 43/1 | nCRAS | LOCATED | LVCMOS33_IN | PB4A | | +| 44/1 | MAin[7] | LOCATED | LVCMOS33_IN | PB4B | | +| 45/1 | MAin[5] | LOCATED | LVCMOS33_IN | PB4C | | +| 46/1 | MAin[4] | LOCATED | LVCMOS33_IN | PB4D | | +| 47/1 | MAin[3] | LOCATED | LVCMOS33_IN | PB5A | | +| 49/1 | MAin[6] | LOCATED | LVCMOS33_IN | PB5C | | +| 50/1 | MAin[8] | LOCATED | LVCMOS33_IN | PB5D | | +| 51/0 | MAin[9] | LOCATED | LVCMOS33_IN | PR9B | | +| 52/0 | unused, PULL:UP | | | PR9A | | +| 53/0 | nUFMCS | LOCATED | LVCMOS33_OUT | PR8B | | +| 54/0 | unused, PULL:UP | | | PR8A | | +| 55/0 | UFMSDO | LOCATED | LVCMOS33_IN | PR7D | | +| 56/0 | UFMSDI | LOCATED | LVCMOS33_OUT | PR7C | | +| 57/0 | LED | LOCATED | LVCMOS33_OUT | PR7B | | +| 58/0 | UFMCLK | LOCATED | LVCMOS33_OUT | PR7A | | +| 59/0 | unused, PULL:UP | | | PR6B | | +| 61/0 | RDQML | LOCATED | LVCMOS33_OUT | PR6A | | +| 63/0 | RBA[0] | LOCATED | LVCMOS33_OUT | PR5D | | +| 64/0 | RD[0] | LOCATED | LVCMOS33_BIDI | PR5C | | +| 65/0 | RD[1] | LOCATED | LVCMOS33_BIDI | PR5B | | +| 66/0 | RD[2] | LOCATED | LVCMOS33_BIDI | PR5A | | +| 67/0 | RD[3] | LOCATED | LVCMOS33_BIDI | PR4B | | +| 68/0 | RD[4] | LOCATED | LVCMOS33_BIDI | PR4A | | +| 69/0 | RD[5] | LOCATED | LVCMOS33_BIDI | PR3D | | +| 70/0 | RD[6] | LOCATED | LVCMOS33_BIDI | PR3C | | +| 71/0 | RD[7] | LOCATED | LVCMOS33_BIDI | PR3B | | +| 72/0 | nRWE | LOCATED | LVCMOS33_OUT | PR3A | | +| 73/0 | nRRAS | LOCATED | LVCMOS33_OUT | PR2B | | +| 76/0 | RDQMH | LOCATED | LVCMOS33_OUT | PR2A | | +| 77/0 | nRCS | LOCATED | LVCMOS33_OUT | PT5C | | +| 78/0 | nRCAS | LOCATED | LVCMOS33_OUT | PT5B | | +| 79/0 | RA[11] | LOCATED | LVCMOS33_OUT | PT5A | | +| 80/0 | unused, PULL:UP | | | PT4F | | +| 81/0 | unused, PULL:UP | | | PT4E | | +| 82/0 | RCKE | LOCATED | LVCMOS33_OUT | PT4D | | +| 83/0 | RBA[1] | LOCATED | LVCMOS33_OUT | PT4C | | +| 85/0 | RA[9] | LOCATED | LVCMOS33_OUT | PT4B | PCLKT0_1 | +| 86/0 | RCLK | LOCATED | LVCMOS33_IN | PT4A | PCLKT0_0 | +| 87/0 | RA[10] | LOCATED | LVCMOS33_OUT | PT3D | | +| 89/0 | RA[1] | LOCATED | LVCMOS33_OUT | PT3C | | +| 91/0 | RA[6] | LOCATED | LVCMOS33_OUT | PT3B | | +| 94/0 | RA[2] | LOCATED | LVCMOS33_OUT | PT3A | | +| 95/0 | RA[5] | LOCATED | LVCMOS33_OUT | PT2F | | +| 96/0 | RA[8] | LOCATED | LVCMOS33_OUT | PT2E | | +| 97/0 | RA[3] | LOCATED | LVCMOS33_OUT | PT2D | | +| 98/0 | RA[0] | LOCATED | LVCMOS33_OUT | PT2C | | +| 99/0 | RA[4] | LOCATED | LVCMOS33_OUT | PT2B | | +| 100/0 | RA[7] | LOCATED | LVCMOS33_OUT | PT2A | | +| PB5B/0 | unused, PULL:UP | | | PB5B | | +| PT5D/0 | unused, PULL:UP | | | PT5D | | +| TCK/1 | | | | TCK | TCK | +| TDI/1 | | | | TDI | TDI | +| TDO/1 | | | | TDO | TDO | +| TMS/1 | | | | TMS | TMS | ++----------+---------------------+------------+---------------+------+---------------+ + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "32"; +LOCATE COMP "CROW[1]" SITE "34"; +LOCATE COMP "Din[0]" SITE "21"; +LOCATE COMP "Din[1]" SITE "15"; +LOCATE COMP "Din[2]" SITE "14"; +LOCATE COMP "Din[3]" SITE "16"; +LOCATE COMP "Din[4]" SITE "18"; +LOCATE COMP "Din[5]" SITE "17"; +LOCATE COMP "Din[6]" SITE "20"; +LOCATE COMP "Din[7]" SITE "19"; +LOCATE COMP "Dout[0]" SITE "1"; +LOCATE COMP "Dout[1]" SITE "7"; +LOCATE COMP "Dout[2]" SITE "8"; +LOCATE COMP "Dout[3]" SITE "6"; +LOCATE COMP "Dout[4]" SITE "4"; +LOCATE COMP "Dout[5]" SITE "5"; +LOCATE COMP "Dout[6]" SITE "2"; +LOCATE COMP "Dout[7]" SITE "3"; +LOCATE COMP "LED" SITE "57"; +LOCATE COMP "MAin[0]" SITE "23"; +LOCATE COMP "MAin[1]" SITE "38"; +LOCATE COMP "MAin[2]" SITE "37"; +LOCATE COMP "MAin[3]" SITE "47"; +LOCATE COMP "MAin[4]" SITE "46"; +LOCATE COMP "MAin[5]" SITE "45"; +LOCATE COMP "MAin[6]" SITE "49"; +LOCATE COMP "MAin[7]" SITE "44"; +LOCATE COMP "MAin[8]" SITE "50"; +LOCATE COMP "MAin[9]" SITE "51"; +LOCATE COMP "PHI2" SITE "39"; +LOCATE COMP "RA[0]" SITE "98"; +LOCATE COMP "RA[10]" SITE "87"; +LOCATE COMP "RA[11]" SITE "79"; +LOCATE COMP "RA[1]" SITE "89"; +LOCATE COMP "RA[2]" SITE "94"; +LOCATE COMP "RA[3]" SITE "97"; +LOCATE COMP "RA[4]" SITE "99"; +LOCATE COMP "RA[5]" SITE "95"; +LOCATE COMP "RA[6]" SITE "91"; +LOCATE COMP "RA[7]" SITE "100"; +LOCATE COMP "RA[8]" SITE "96"; +LOCATE COMP "RA[9]" SITE "85"; +LOCATE COMP "RBA[0]" SITE "63"; +LOCATE COMP "RBA[1]" SITE "83"; +LOCATE COMP "RCKE" SITE "82"; +LOCATE COMP "RCLK" SITE "86"; +LOCATE COMP "RDQMH" SITE "76"; +LOCATE COMP "RDQML" SITE "61"; +LOCATE COMP "RD[0]" SITE "64"; +LOCATE COMP "RD[1]" SITE "65"; +LOCATE COMP "RD[2]" SITE "66"; +LOCATE COMP "RD[3]" SITE "67"; +LOCATE COMP "RD[4]" SITE "68"; +LOCATE COMP "RD[5]" SITE "69"; +LOCATE COMP "RD[6]" SITE "70"; +LOCATE COMP "RD[7]" SITE "71"; +LOCATE COMP "UFMCLK" SITE "58"; +LOCATE COMP "UFMSDI" SITE "56"; +LOCATE COMP "UFMSDO" SITE "55"; +LOCATE COMP "nCCAS" SITE "27"; +LOCATE COMP "nCRAS" SITE "43"; +LOCATE COMP "nFWE" SITE "22"; +LOCATE COMP "nRCAS" SITE "78"; +LOCATE COMP "nRCS" SITE "77"; +LOCATE COMP "nRRAS" SITE "73"; +LOCATE COMP "nRWE" SITE "72"; +LOCATE COMP "nUFMCS" SITE "53"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:28 2023 + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par new file mode 100644 index 0000000..7c17e3d --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1.par @@ -0,0 +1,235 @@ + +Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd" +Tue Aug 15 05:03:23 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf +Preference file: RAM2GS_LCMXO256C_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67/79 84% used + 67/78 85% bonded + SLICE 71/128 55% used + + + +Number of Signals: 262 +Number of Connections: 662 + +Pin Constraint Summary: + 67 out of 67 pins locked (100% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +........ +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +.............. +Placer score = 831129. +Finished Placer Phase 1. REAL time: 5 secs + +Starting Placer Phase 2. +. +Placer score = 828350 +Finished Placer Phase 2. REAL time: 5 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 1 out of 4 (25%) + General PIO: 1 out of 80 (1%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 4 (50%) + SECONDARY: 1 out of 4 (25%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 out of 79 (84.8%) PIO sites used. + 67 out of 78 (85.9%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+------------+------------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | ++----------+----------------+------------+------------+------------+ +| 0 | 36 / 41 ( 87%) | 3.3V | - | - | +| 1 | 31 / 37 ( 83%) | 3.3V | - | - | ++----------+----------------+------------+------------+------------+ + +Total placer CPU time: 4 secs + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + +0 connections routed; 662 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. +WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks. This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew. + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=7 clock_loads=4 + +Completed router resource preassignment. Real time: 5 secs + +Start NBR router at 05:03:28 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:28 08/15/23 + +Start NBR section for initial routing at 05:03:28 08/15/23 +Level 1, iteration 1 +0(0.00%) conflict; 563(85.05%) untouched conns; 712361 (nbr) score; +Estimated worst slack/total negative slack: -9.968ns/-712.361ns; real time: 5 secs +Level 2, iteration 1 +3(0.02%) conflicts; 494(74.62%) untouched conns; 697746 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-697.746ns; real time: 5 secs +Level 3, iteration 1 +6(0.05%) conflicts; 255(38.52%) untouched conns; 756550 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-756.550ns; real time: 5 secs +Level 4, iteration 1 +17(0.14%) conflicts; 0(0.00%) untouched conn; 761255 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-761.256ns; real time: 5 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:28 08/15/23 +Level 4, iteration 1 +12(0.10%) conflicts; 0(0.00%) untouched conn; 765605 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-765.606ns; real time: 5 secs +Level 4, iteration 2 +6(0.05%) conflicts; 0(0.00%) untouched conn; 766423 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.424ns; real time: 5 secs +Level 4, iteration 3 +3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs +Level 4, iteration 4 +3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs +Level 4, iteration 5 +3(0.02%) conflicts; 0(0.00%) untouched conn; 766523 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs +Level 4, iteration 6 +1(0.01%) conflict; 0(0.00%) untouched conn; 766523 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs +Level 4, iteration 7 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 8 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 9 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 10 +0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs + +Start NBR section for re-routing at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 768048 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-768.049ns; real time: 6 secs + +Start NBR section for post-routing at 05:03:29 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 256 (38.67%) + Estimated worst slack : -10.044ns + Timing score : 913247 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=7 clock_loads=4 + +Total CPU time 5 secs +Total REAL time: 6 secs +Completely routed. +End of route. 662 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 913247 + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -10.044 +PAR_SUMMARY::Timing score> = 913.247 +PAR_SUMMARY::Worst slack> = 0.273 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 5 secs +Total REAL time to completion: 6 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd new file mode 100644 index 0000000..34f0f5f --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/5_1_par.asd @@ -0,0 +1,30 @@ +[ActiveSupport PAR] +; Global primary clocks +GLOBAL_PRIMARY_USED = 2; +; Global primary clock #0 +GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; +GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN; +GLOBAL_PRIMARY_0_LOADNUM = 40; +; Global primary clock #1 +GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; +GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_1_LOADNUM = 13; +; # of global secondary clocks +GLOBAL_SECONDARY_USED = 1; +; Global secondary clock #0 +GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c; +GLOBAL_SECONDARY_0_DRIVERTYPE = PIO; +GLOBAL_SECONDARY_0_LOADNUM = 9; +GLOBAL_SECONDARY_0_SIGTYPE = CLK; +; I/O Bank 0 Usage +BANK_0_USED = 36; +BANK_0_AVAIL = 41; +BANK_0_VCCIO = 3.3V; +BANK_0_VREF1 = NA; +BANK_0_VREF2 = NA; +; I/O Bank 1 Usage +BANK_1_USED = 31; +BANK_1_AVAIL = 37; +BANK_1_VCCIO = 3.3V; +BANK_1_VREF1 = NA; +BANK_1_VREF2 = NA; diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par new file mode 100644 index 0000000..1b6d169 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.dir/RAM2GS_LCMXO256C_impl1.par @@ -0,0 +1,28 @@ +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:23 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t +RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir +RAM2GS_LCMXO256C_impl1.prf -gui -msgset +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml + + +Preference file: RAM2GS_LCMXO256C_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 -10.044 913247 0.273 0 06 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 6 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc new file mode 100644 index 0000000..ec074a2 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.drc @@ -0,0 +1 @@ +DRC detected 0 errors and 0 warnings. diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed new file mode 100644 index 0000000..0472a9a --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed @@ -0,0 +1,977 @@ + +* +NOTE JEDEC CREATED BY: Lattice Semiconductor Diamond Deployment Tool 3.12* +NOTE Version: Diamond (64-bit) 3.12.1.454* +NOTE Readback: Off* +NOTE Security: Off* +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Tue Aug 15 05:03:33 2023 * +NOTE DESIGN NAME: RAM2GS * +NOTE DEVICE NAME: LCMXO256C-3TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[7] : 71 : inout * +NOTE PINS RD[6] : 70 : inout * +NOTE PINS RD[5] : 69 : inout * +NOTE PINS RD[4] : 68 : inout * +NOTE PINS RD[3] : 67 : inout * +NOTE PINS RD[2] : 66 : inout * +NOTE PINS RD[1] : 65 : inout * +NOTE PINS RD[0] : 64 : inout * +NOTE PINS Dout[7] : 3 : out * +NOTE PINS Dout[6] : 2 : out * +NOTE PINS Dout[5] : 5 : out * +NOTE PINS Dout[4] : 4 : out * +NOTE PINS Dout[3] : 6 : out * +NOTE PINS Dout[2] : 8 : out * +NOTE PINS Dout[1] : 7 : out * +NOTE PINS Dout[0] : 1 : out * +NOTE PINS LED : 57 : out * +NOTE PINS RBA[1] : 83 : out * +NOTE PINS RBA[0] : 63 : out * +NOTE PINS RA[11] : 79 : out * +NOTE PINS RA[10] : 87 : out * +NOTE PINS RA[9] : 85 : out * +NOTE PINS RA[8] : 96 : out * +NOTE PINS RA[7] : 100 : out * +NOTE PINS RA[6] : 91 : out * +NOTE PINS RA[5] : 95 : out * +NOTE PINS RA[4] : 99 : out * +NOTE PINS RA[3] : 97 : out * +NOTE PINS RA[2] : 94 : out * +NOTE PINS RA[1] : 89 : out * +NOTE PINS RA[0] : 98 : out * +NOTE PINS nRCS : 77 : out * +NOTE PINS RCKE : 82 : out * +NOTE PINS nRWE : 72 : out * +NOTE PINS nRRAS : 73 : out * +NOTE PINS nRCAS : 78 : out * +NOTE PINS RDQMH : 76 : out * +NOTE PINS RDQML : 61 : out * +NOTE PINS nUFMCS : 53 : out * +NOTE PINS UFMCLK : 58 : out * +NOTE PINS UFMSDI : 56 : out * +NOTE PINS PHI2 : 39 : in * +NOTE PINS MAin[9] : 51 : in * +NOTE PINS MAin[8] : 50 : in * +NOTE PINS MAin[7] : 44 : in * +NOTE PINS MAin[6] : 49 : in * +NOTE PINS MAin[5] : 45 : in * +NOTE PINS MAin[4] : 46 : in * +NOTE PINS MAin[3] : 47 : in * +NOTE PINS MAin[2] : 37 : in * +NOTE PINS MAin[1] : 38 : in * +NOTE PINS MAin[0] : 23 : in * +NOTE PINS CROW[1] : 34 : in * +NOTE PINS CROW[0] : 32 : in * +NOTE PINS Din[7] : 19 : in * +NOTE PINS Din[6] : 20 : in * +NOTE PINS Din[5] : 17 : in * +NOTE PINS Din[4] : 18 : in * +NOTE PINS Din[3] : 16 : in * +NOTE PINS Din[2] : 14 : in * +NOTE PINS Din[1] : 15 : in * +NOTE PINS Din[0] : 21 : in * +NOTE PINS nCCAS : 27 : in * +NOTE PINS nCRAS : 43 : in * +NOTE PINS nFWE : 22 : in * +NOTE PINS RCLK : 86 : in * +NOTE PINS UFMSDO : 55 : in * +NOTE CONFIGURATION MODE: NONE * +NOTE COMPRESSION: off * + + +QF56640* +G0* +F0* +L00000 +11111111001111111111011110111100111111111101111011110011111111110111101111001111 +11111101111011111111111111111111101111001111111111010111011100111111111101011110 +11001111111111010111101111111111 +11111111001111111111011110111100111111111101111011110011111111110111101111001111 +11111101111011111111111111111111101111001111111111010111101100111111111101011101 +11001111111111010111011111111111 +11111111111111111111111111111111111111111111111111110011111111110111101111111111 +11111111111111111111111111111111101111111111111111111111111100111111111101011101 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111110011111111110111101111111111 +11111111111111110011111111110111101111111111111111111111111100111111111101011101 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111101111111111111111111111011111011111011111111 +11111111110111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111110111111111111111111111101111111111011111111 +11111111111011111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011111111111111 +11111111111111111111100111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111101111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111110111111111 +11111111111111111111111111111111111111111111111110011111111111111111111111111111 +11110111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111011111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111110111111111 +11111111111111111111111111111111111111111111111100111111111101111111111111111111 +11011111111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011111111101111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111011111111111111111111111111111110111 +11111111111111111101111111111111 +11111111111111111111111111111101111111111111111111111111111110111111111111111111 +11111111111110111111111111111111111111111111111111111111111111111111111111110111 +11111111111111111111111111111111 +11111111111111111011111111111100011111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111110111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111110111110111111111111111111111111111111111111111111111110111111111011 +11111111111111111111111111111111 +11111111111111111011111111111111111111111111111111111110011111111111111111111111 +11111111111111111101111111111111111111111110111111111111111111111111111111101111 +11111111111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111101111 +11111111111111111111111111111111 +11111111111111111111111111111111111111110111111111111111111111111111111111111111 +11111111111111111111111111110111111111111011111111111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111101111101101110011111111111111111111111111110011 +11011111001011011111111111111111111111111010111111110001111111101111111011111101 +11111111111111100111011111111011 +11011111111111111111111111111101001110011010011111001111111111111111111111010010 +11011110110111001111000001111111111110011010111111100101111101111111111101111111 +11011111111111101110110111111011 +11111111111111111111111111111110000111100100111111011111111111111111111111010011 +10011110111111011111011101111111111101111111110111101111110101001111111111111111 +01111111111111101101110111111110 +11111111111111111111111111111101001111011110011101011111111111111111111111110001 +01011111110100011111111101111111111111101111011111101110111101101111111111111111 +11101111111111101111111111111111 +11111111111111111111111111111101001101011110011111111111111110111111111111010011 +11111101101111111111111111110111101111111001101011001011111101101111111111101111 +00111111111111101000100111011101 +11111111111111111111011111111110001011111111110111111111111111011111111111100011 +11111101110111001111111111111111111110101010110111111101111111111111011101110111 +01111100010111111101110111111111 +11111111111111111111111111111111001111011111110111011111111111111111111111110011 +11111011110011011111111111111111111101110001110101111101111111001111111101110111 +11111010110011011100100101111101 +11111111111111111011111111111111001111111111010011111111111111111111111111110010 +11001111110111111111111111101111110111110011010110111111111111101010001101110110 +11101111100111111101011111111111 +11111111111111111110011111111110111111111011111111111111111111111111111111101111 +11111011111111111111111001111111111111101101111110110101111110111111110101111111 +11101111110111110011111111111011 +11011111111111111111011111111110011111111101111111111111111111111111111111100100 +01011101111111111111101101111111111111100010111111011111111110101111111001111111 +11110011111111111111111111111011 +11111111111111111111111111111111001111111111111111111111111111111111111111111111 +11011111111111111111010101111111111111110011110111111111111111111111111111111111 +11110011110111111111111111111111 +11111111111111111110111111111111001111111111111111111111111111111111111111111101 +10011111011111111111111101111100111111100010010111111111111111111111111111111111 +11100011111111111101111111111111 +11110001111111111110011001111111111111111101111111111111111111111111111111111101 +11101101110111111111110111110111011111111111111010011101111111111110101011111111 +11111111111111111011111111111101 +11111011111111111110011111111111010001111111110111111111111111111111111111111111 +10011111110111101111001111111111011111110011110111011111111111111001011101111111 +11110000000011111111111111111111 +11111111111111111111111101111101001111011111111111111111111111111111111111011101 +11011011110111011111111101111111011111011101111100111101111101111011101101111111 +11011111110111011101111111111101 +11111111111111111111111101111111001111111011101111111111111111111111111111111111 +11010110101111111111111111101010011111111111100111111111111111111111010111111111 +11111101110111111101111111111101 +01111111111111111111111111111111111110111101010111111111111111111111111111110011 +11111111110110011111111111010111100101011111111110101000110111111000111101111111 +11111111110111111110011111111011 +01011111111111111111111111111101110111011011110111111111111111111111111111010011 +10011111100111110111111111110111111000011011110111001100000101111011011011111111 +11011110111111111111111111111011 +11111111111111111111111111111111111011011111111111111111111111111111111111110001 +11111111111111111111111111101111111101111011101111111101111101001111011111111111 +11111110010111111111110011111111 +11111111111111111111111111111110111111011111101111111111111111111111111111100011 +11011110111111111111111111111111111101101101110111110011111111001011011111111111 +11101111110111111111111111111110 +10111111111111111111111101111111111100111111111111111111111110110111111111111111 +11101001111111111111111101110110111111110101111111011111110001101011111111111111 +11111111101111011111111110111101 +11111111111111111111011001111110110011011111111111111111111111011111111111101110 +11000101111111111111101101110111011111100010111110011111110111101010011111111111 +11111100110111111111111101111111 +11111111111111111111111111111111110111011111111111111111111111101111111111111111 +11111001111111111010110001101111111111110011110111101101111111101111011111111111 +11111011010110101101111100011101 +11111111111111111011101111111110001111011111111111111111111111111111111111111011 +00111111111111111111011100111111111111100111011011111111101111101101111111111111 +11101110110111111111111111111111 +01111111111111111111111111110110111111111111111111111111111111111111111111101111 +01111111111111011100111011111011101101101011110110101110000110111111111111111111 +11100011111110100111111101111011 +01011111111111111111111111110110110001011111111111111111111111111111111111100010 +11111111111111111100111101111011111011100010010111011111110010111111111111111111 +11110011111111001111111111111011 +11111111111111111111111110101111110110011111111111111111111111111111111111110011 +11111111111110111100111111111101110100110111100111101111110011001111111111111111 +11110011111111111111110000111111 +11111111111111111111111111111110111111011111111111111111111111111111111111100101 +11011111111111111100101101111011111111101101110111101101111111111111111111111111 +11101111111111101111111111111111 +10111111111111111111111111111111111111111111111111111111111110111111111111110111 +11111101010111111111111111110111011111111011111101010101110111101111111100111111 +11111110011111101111111111111101 +11111111111111111111111111111111001111111111111111111111111110011011111111110010 +11111001110111111100101111110110111111110010100111011101111111101111111101111111 +11111110100111101111111111111111 +11111111111111111111111111111101001111111111111111111111111111110111011111010011 +01111111111111110100111111111111111111010111011110111111111101001111111110010111 +11010011110111111101111111011101 +11111111111111111111111111111111111111111111111111111111111111111111111111110111 +11101111101111111111110110101111111111011111111111111011101111111111101011111111 +11111101110111110111111111111101 +11111111111111111111111111111111111100111001111111111111111111111111111111110111 +10111000111111111101111111111110011111111110011111111110110111111111111001010111 +11110111011110011111111111111011 +11111111111111111111111111111111110011011101111111111111111111111111111111011100 +11011101111111110111000101111111011111011010110111111111110111111111011101110111 +11010110100111011111111111111011 +11111111111111111111111111111111110111011111111111111111111111111111111111011110 +01011111010111111111111001111110011111111001110111111110000111110111111011101111 +11110011111110111111111111111110 +11111111111111111111111111111111111111011011111111111111111111111111111111111111 +11011011110111111011011101111111011111101111100111111110111111111110011111111111 +11100011111111111111111111111111 +11111111111111111111111111111111111111010111111111111111111110110111111111010111 +11111001111011111111111110010011111111111101111011011111111011111111111101111111 +11110001111011011110110111111101 +11111111111111111111111111111111111011011101111111111111111111011111111111100011 +11011100000111101111111111100001011111101010111110011111110111111000011111111111 +11100010111110011110110011111111 +11111111111111111111111111111111110100011111111111111111111111101111111111110001 +10111110011111011111111111010010111111111011110001011111111111110111111011111111 +11110011110101111111100111111101 +11111111111111111111111111111111111111011111111111111111111111111111111111110011 +11011010101101111011111111110001111111110011011011111111111111111111011111111111 +11100011011011111111011111111111 +11111111111111111111111111111111111111111111100111111111111111111111111111100011 +11111111110011111011101111101110011111100111111111111111110111111111111001111111 +11100010011101011111111111111011 +11111111111111111111111111111111111111111111110111111111111111111111111111100000 +10011111101101101110101111110111011101100100111111111110100111111111111101111111 +11100010110111011111110101111011 +11111111111111111111111111111111111111111111111111111111111111111111111111110011 +01011111111111011110111101111110111111111111010111111111111111111111111011111111 +11110011100111111111111111111111 +11111111111111111111111111111111111111111111101111111111111111111111111111110011 +11111111111111110011110111111111111101101111111111111111111111111111111111111111 +11101101110110111111110111111111 +11111111111111111111111111111111111111011111011111011111111111111111111111110011 +10111101111011011111111110110111111111110110011111011011110111111111100101111111 +11111111111111111111111111111101 +11111111111111111111111111111111111011111111110111111111111111111111111111110110 +11011111111101011110111101111111111111110110110111011101111111111111111001111111 +11111111111111111111110111111111 +11111111111111111111101101111111111101011111111111111111111111111111111111010101 +01111111111111010110011011010011011111011111100111111111110111111111101101111111 +11010011111011011110111111111101 +11111111111111111111111111111111111111111111111110111111111111111111111111110011 +11011011111010011111111101100111111111111111111010111110101111111111110111111111 +11111111111111111111111111111101 +11111111111111111111011111111111111111111111111111111111111111010111111111110111 +01111111111111111111100111111111111111111101011110011111111111111111111111111101 +11111111111111111111111011111111 +11111111111111111111011111111101111111111111111111111111111111100111111111011110 +11011111111111110100101101111111111111011110111110011111111111111111111101111001 +01111111110111111111111011111111 +11111111111111111111111111111101101111111111111111111111111111111111111111111111 +11111111111111111100111101111111111111111111110111111111111111111111111111111011 +11111101101111111110111111111111 +11111111111111111010111111111111101111111111111111111111111111111111111111101101 +10011111111111111011011001111111111111111111111111111111111111111111101111111010 +01111111110111111110111111111111 +11111111111111111111111111111101001111111111100111111111111111111111111111110111 +10001001111111111100111110110111101111111011110110000011111111111111001011111111 +11111101111011110101111111111111 +11111111111111111111111111111110001111111111110111111111111111111111111111111110 +01011101111011111100001110010111100101111110110111001101111111111001011101111111 +11111110111111101101111111111111 +11111111111111111111111111111111101111111111111111111111111111111111111111111111 +11011101111101011100110101110111101111101111110111111111111111111111010101111111 +11111111110101111111111101111111 +11111111111111111111111111111111101111111110111111111111111111111111111111101110 +11010001111011111000111110101111100011111101000110101111111111111010011101111111 +11111111011111101011111111111111 +11111111111111111111111111111110101100011001111111111111111111010111111111100011 +10111111111001011000111101111111011111111111100110111101111111111111111000111111 +11111111111110111111111111111111 +11111111111111111111111111111110001011011101111111111111111111110111111111110011 +11011111111001111100100001111111111111111110010111011111111111111111111100111101 +11111111111111011111111111111111 +11111111111111111111111111111111001111011111111111111111111111101111111111110001 +11111111111111011100111101111110111111111111110111111011111111111111111011110111 +01111111111111111111111111111111 +11111111111111111111111111111111100111011011111111111111111111111111111111100011 +11011111111111110000011101111111111111111110110111111111111111111111111111011111 +11111111111111111111111111111111 +11111111111111111111111111111111101111111101011111111111111111111101011111110011 +11111100111010011100111110010111011111111011110011011111100011111110001110110111 +11111111110111111111111111111111 +11111111111111111111111111111111101011011111110111101111111111111111011111110011 +11011111011111011100111111100111111111111010110111011111110111111001011111111111 +11111110100111111111111111111111 +11111111111111111111111111111101100110111011111111011111111111111110111111010011 +11111110110111110100111110110111111111011111110100011111111111111111011110100111 +11111111010111111111111111111111 +11111111111111111111111111111111101101011111111111111111111111111111111111111011 +10111011111111111110111111011110111111111101000011011111111111111011010111011111 +11111101110111111111111111111111 +11111111111111111111111111111111111111111111110111111111111111110111111111111111 +01101111111111111000111111111111111111111111011001011111110111111111101101111111 +11111111111010011111111111011011 +11011111111111111111111111111111111111101111111111111111111111111111111111111100 +10010111111111111011100001111111111111011100111101011111110111111111111011111111 +11111111111101011111111111111011 +11111111111111111111111111111111111111111101111111111111111111101111111111111101 +11011111111111111111111111111111111111110011110111111110111111111111111101111111 +11111111111111011111111111111111 +11111111111111111111111111111111111111111110111111111111111111111111111111111111 +11011111111111111100111111111111111111100010110110111111101111111111110101111111 +11111111111110011111111111111110 +11111111111111111111111111111111111111111111111011111111111111010111111111111111 +11111111111111111100111110010110111111110011101101111111111011111111111111111111 +11111111111111111111111100111101 +11111111111111111111111111111111111111111111111101011111111111110111111111111111 +11111111111111111011111111110111011111100000110111011101110111111111111111111111 +11111111111111111111111111011111 +11111111111111111111111111111111111111111111111011011111111111101111111111111111 +11111111111111111111111111100111011111110001010111111111111111111111101101111111 +11111111111111111111111101111101 +11111111111111111111111111111111111111111111111011111111111111111111111111111111 +11111111111111111111111111010111011111110011110111111101111111111111111111111111 +11111111111111111111111101111111 +01111111111111111111111111111111111111101101111001111111111111010111111111111111 +11100101111110111000111111100111111111101110111011011111111111111111111101111111 +11111111111011111111111111111011 +01011111111111111111111111111111111111111111111111111111111111110111111111111111 +11110001111111111000111111110111111111101110111101111111111111111111111111111111 +11111111111111111111111111111011 +11111111111111111111111111111111111111111001111101011111111111101111111111111111 +11111101111111011100111110100111111111111111110110111111111111111111111111111111 +11111111111001011111111111111110 +11111111111111111111111111111111111111110101111111111111111111111111111111111111 +11111101111111111111111111111111111111100010010111111111111111111111111011111111 +11111111111111111111111111111111 +10111111111111111111011111111111111111111011111111111111111111100111111111111111 +11101101111111111111111110110111011111111111111011011101111111111111111111011111 +11111111111111110111111111111101 +11111100111111111111011111111111110001011101111111111111111111100111111111111111 +11110011110111111100111111100111011111111111111100111101111111111111111111110111 +11111111111011111101111111111111 +11100111111111111111111111111111111111011111111111111111111111111111111111111111 +11101101111111111000111111110111011111011111111111111101111111111111111110111111 +11111111111111001111111111111101 +11111111111111111010111111111111111110111111111111111111111111111111111111111111 +11111111101111111011111110010110111111111011111111110111111111111111111110111111 +11111111111111101111111111111111 +01111111111111111111111111111111101111101111010111111111111111111101011111111111 +11101101111111111111111110111110101101111111111111101101111111111111101001111111 +11111111111011111111111111111011 +01011111111111111111111111111101111111111111110111111111111111111111011111111111 +11111111111111111000100001011111001101111111110111111111111111111111110101111111 +11111111111101111111111111111011 +11111111111111111111111111111111111111100101101111111111111111111110111111111111 +11111001111111111100111110110111110001111111101111110001111111111111111011111111 +11111111111111111111111111111111 +11111111111111111111111111111111101111111111111111111111111111111111111111111111 +11110101111111111111111111111111111110111111111111111101111111111111111111111111 +11111111111111111111111111111110 +10111111111111111111111111111111101100111110111111111111111111111111111111111111 +11111111111111111111111110110111101111111111111001010101111111111111100101111111 +11111111111111101111111111111101 +11111111111111111111111111111111111011011111111111111111111111111111111111111111 +11111111111111111000111111110111111111111111111111011101111111111111100101111111 +11111111111111101111111111111111 +11111111111111111111111111111110111111111110110111111111111111111111111111111111 +11111101111111111100111111110111111101111111111110111011111111111111111001111111 +11111111111111110101111111111101 +11111111111111111111111111111111001111111111011111111111111111111111111111111111 +11111101111111111100111110000111110110111111111101111111111111111111111111111111 +11111111111111111111111111111111 +01111111111111111111111111111111001111111101111111111111111110111111111111111111 +11101101111111111000111111111111111101111110011010110001111111111111101001111111 +11111111111011111111111111111011 +01011111111111111111111111111111111111111111111111111111111110011111111111111100 +11111111111111111000111111111111101001111110100101000101111111111111110101111111 +11111111111111111111111111111011 +11111111111111111111111111111111111111111011111111111111111111110111111111111111 +11011001111111111100111111111111111111111101110111101111111111111111111111111111 +11111111111111011111111111111110 +11111111111111111111111111111111001111111111111111111111111111111111111111111101 +01010101111111111111111111111111111111111111110111101111111111111111111011111111 +11111111111101011111111111111111 +10111111111111111111111111111111001111111111111111111111111111111111111111111111 +11101111011111111111111110010111101111111111111001011111110011111111111111111111 +01111111111111111110111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111110111111100111111110111110111111110110111011111100111111111111101111111 +01111111111111111111111111111111 +11111111111111111111111111111101001111111111111111111111111111111111111111111111 +11110101111111111000111111100111111100111101011110111111111111111111111111111010 +11111111111111111111010111111101 +11111111111111111111111111111111001111111111111111111111111111111111111111111111 +11111101111111111011111111010111111111111111100101111111111111111111101111111111 +11111111111111111110111111111111 +11111111111111111111111111111111111101101001111111111111111111111111111111111111 +11101111111111111111111110101111111111111111111011111111110011111111111111111111 +11111111111011111111111111111111 +11111111111111111111111111111111110010011101111111111111111111111111111111111111 +11111111111111111000100001010111111111011111111111111111110111111111111111111111 +11111111111101111111111111111111 +11111111111111111111111111111111111111011101111111111111111111111111111111111111 +11111111111111111100111110110111111111111111111101111111111111111111111111111111 +11111111111111011111111111111111 +11111111111111111111111111111111110111010001111111111111111111111111111111111111 +11110111111111111111111111111111111111100111111111111111101111111111111111111111 +11111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111110111111111111110100111111111111111111110010111111111111111111111111111 +11111111111011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111011111111000111111110111111111101111110111001101111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +11111110111111111100111110110111111111111111101111101001111111111111111111111111 +11111111111011011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111110111111111100111111001111111111110101110110111111111111111111111111111111 +11111111111101111111111111111111 +11111111111111111111111001111111111111111101100111111111111111010111111111111111 +11101101010011111000111110111111111111101111111001001101110111111111101000111111 +11111111111001011111111111111111 +11111111111111111111111101111111111111111111110111111111111111110111111111111111 +11101101110111101000111111011111111111101111110101011111111111111111111101110111 +11111111111101011111111111111111 +11111111111111111111111011111111111111111011101111111111111111101111111111111111 +11110001101111011100111111110111111111111001111111011001111111111111110001010111 +11111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11101111111101111111111111110111111111101011100110010101101111111111111100110111 +11111111111110011111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11101101111111111111111111111111111111111111111110001110100011111111101111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111100111111111111100 +11011111111111111100111111111111111111111101110111011111100111111111100111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +10011101111111111000111111111111111111011110110111111111110111111111111101111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +01110001111111111011111111111111111111111111100110110111011111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111101111111111111111111111111111111111111011 +11101111111111111111111110101111111111111111110011111111111111111111111111111111 +11111111111010011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111010011 +11111111111111111000100001010111111111010110111101111111111111111111111111111111 +11111111111100011111111111111111 +11111110111111111111111111111111111111111101111111111111111111111111111111110011 +11100101111111111100111110110111111111110111110111111111111111111111111111111111 +11111111111111011111111111111111 +11111110111111111111111111111111111111110101111111111111111111111111111111100011 +11111111111111111111111111111111111111101011011111111111111111111111111111111111 +11111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111011 +11111111111111111111111111010111111111111111111111011011111111111111111111111111 +11111111111111011111111111111111 +11111111111111111111111111111111110001111111111111111111111111111111111111100011 +11111111111111111000111111100111111111101111111111011101111111111111111111111111 +11111111111111011111111111111111 +11111111111111111111111111111111111111011111111111111111111111111111111111110011 +11111111111111111100111111111111111111111111111110101101111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111110011 +11111111111111111100111111111111111111111111111011111111111111111111111111111111 +11111111111010111111111111111111 +11111111111111111111011111111111111111101111111111111111111111111111111111101111 +10110101111111111000111110111111111111101110011011111101110011111111111101111111 +11111111111111011111111101111111 +11111111111111111111111111111111111111110111111111111111111111111111111111101111 +11011001111111111000111111011111111111100110111111111111110111111111111111111111 +11111111111111111111111101111111 +11111111111111111110111111111111111111101101111111111111111111111111111111111111 +11111111111111111100111110110111111111111111110101111011111111111111111111111111 +11111111111111111111111110011111 +11111111111111111111111111111111111111111111111111111111111111111111111111100111 +11111111111111111111111111111111111111101111111111111111101111111111111011111111 +11111111111110111111111111011111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111101111111111111111110111111111111111111010011111111100011111111111111111111 +11111111111111111111111101111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111011111011101100111111111111111111110110100111111111110111111111111111111111 +11111111111011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111010111111111011111 +11111111111101011000111111110111111111011111110111011111111111111111111111111111 +11111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111011111111010111111111111101110101011111111111111111111111111111 +11111111111111111111111111111111 +01111111110111111111111111111111000111101011111011111111111111010111111111111111 +11011111111111011111111110110111111111110010101011110010111111001111101111111101 +00111011111011011111110111011011 +01011111010011111111111111111101001000001101111101111111111111110111111111111110 +11111111111111011000100000101111111111010010010101101101111101101111111111111111 +01011011111111111110110111111010 +11111111110011111111111111110111001111010101111111011111111111101111111111111111 +11011101111010111100111111110111111111110111110111101111111111101111101101111111 +01011011111100111111101101111111 +11111111100111111111111110111110101011011111111011111111111111111111111111111111 +01111101111111111111111111011111111111100001110111111101011110001111110111111110 +11110011111111111111111111111111 +10111111110111101111111011110111001111101111101111101111111111100111111111111111 +11111001011111111111111110100110111111110010111111011011110011001110100101011111 +11010011111011111110111010111101 +11111111110011110111111101100010000001111111110111011111111111110111111111111111 +11101101111111111000111111010111011111100011111111111101100110000111010001110111 +01110010110101111101110011111111 +11111111110011111111111100110111001111011101110111111111111111101111111111111111 +11111001110111111100111110110111011111110011110111111101111111001111011101110111 +11111011111111011111010101111111 +11111111110101110111111101111111001111110101110111111111111111111111111111111111 +11111111111111111100111111101111011111100011111110111111111111001111111101110111 +01110011001111011101111111111111 +01111111100111111111111111111110000111110101111111111111111111110111111111111110 +11111111111111111000111111110111111111101111011010011100010010110111111001111111 +01101011001111011111111111111011 +01011111110111111111111111111110001111111101111111111111111111111111111111111110 +11111111111111111000111111111111111111101010111101011111100110111111111101111111 +01101010110111011111111111111011 +11111111111111111111111111111111001111001101111111111111111111101111111111111111 +01011111111111111100111111100111111111111011111111111111110111110111011011111111 +11111011111110111111111111111111 +11111111111111111111111111111110111011011011111111111111111111111111111111111111 +11111111111111111111111111110111111111101111111110111101011110111111011111110110 +01111011111011111101111111111111 +10101111110011111101011111111111001111111001110111111111111110110111111111111111 +11101111110111111111111110100111011111111111101010111111110011111110111101111110 +11111111111101010111111111111101 +11101111110000110110011111111111001111111001111111101111111111000111111111111111 +11111111110111101100111111110111011111111010010111011101110011111001001101111111 +01110011111110011101111111111111 +11111111011001110111111111111101001111111111110111011111111111111111111111111111 +11111111110111011000111111110111011111011001111111111101100101111011111001110011 +01010011111111101101111111111101 +11111111111011000111111111111111111111111111111111111111111110111111111111111111 +11110111101111111011111111000110111111111111110101110111111111101111001111111111 +11111111111111101111111111111101 +01111111111011011111110101111111001101011011100111111111111110110011111111110011 +11111011110111111111111110110111001111111101101001010111110011100111101111111111 +11111101101111011111111111111011 +01011111010000111111111101111101001011111101110011011111111111100011111111010011 +11111101100111111000100000110111011111011111110111011101110101111111010111111111 +11111110010110111111111111111011 +11111111010011110111111011111101000111011111101111111111111111011101011111010011 +11111111111111111100111111100110110100110111110011011111101101111110011111111111 +11111111110111111111111111111111 +11111111010011111111111111111111001111011111111111111111111110111111111111110011 +11111110111111111111111110011011111111100101110100111111111111111111111111111111 +11111111111111111111111111111110 +10111111011011111111111111111101001111101111011111011111111111111111111111010011 +11101101111111111111111110011111101111111110011111011110110101000111111000111111 +11111111111011101110111111111101 +11111111110011110111111111111110001111011111110011011111111111111111111111100011 +10011101111111111000111111110111110111101110111110011111101110011001111101111111 +11111111111111111111011111111111 +11111111110011111111111111111111001111111101111111111111111111111111111111110011 +11111101111111111100111111110111111101110011110111111111110111001111011111111111 +11111111111111011111110111111101 +11111111110011101111111111111111000110010101111110111111111111111111111111100010 +11000001111111111100111111010111111110110110110011111111011010001111111011011111 +11111111111101010111110111111111 +01111111100011111111111111111110001100011111111111011111111111010111111111101110 +11111010011111111000111111100111111001101111101011010100100110001111111101111111 +11111111111101010111111111111011 +01011111110011111111111111110010001011011111111110001111111111100111111111101110 +11111100110111111000111111100111101101101100010111101110110110001111111011111111 +11111111111111001011111111111011 +11111111110011111111111111111111001111011111111111111111111111111111111111111111 +11011110100111111100111111110111111111111110110110101111010111001111111111111111 +11111111111111001101111111111111 +11111111110011111111111111111111000111011111111111111111111111111111111111111111 +01111110111111111111111111110111111111101111110101101101110111101111111111111111 +11111111111110001111111111111110 +10111111111111111111101010011111011111111110010001011111111111100111111111111110 +11101111110111111111111111110111101111111101101111011111110011001111111110110001 +11111110111011111110110111111101 +11111111111111111111111101111111011111111111110111111111111111110111111111111010 +11011111101111111100111111110111111111110110010111111111110111001011011111111111 +11111110010101111111110111111111 +11111111010011111111110111110001011011111111101111011111111111101111111111011001 +01011111111111111000111111101111111101011111110111111111101101001001111111001111 +00111111100111011110000111111101 +11111111110011111111111111111111011111011111011110011111111111111111111111111111 +10010111111111111011111110111111110110111111111110111111111111101110011111111111 +11111110110111011110111111111111 +11111111111101111011111111111111111111101101101111001111111111100111111111011011 +11111110011111111111111111111111111111110011111110111110010011111100100101111111 +11111111111001011111111111111111 +11111111111111111111111111111101011111110001110111011111111111110111111111010011 +11111111110111111000100001110111111111010010100111011111110101110011011101111111 +11011111111101011111111111111110 +11111111111111110011011111111101011111111101111111111111111110100111111111110011 +11111101111111111100111111110111111111110001111011011111100101111111010101111111 +11111011111111111111111101111111 +11111111111111111101111111111111111111101101111110111111111111111111111111100010 +11011101011111111111111110110111111111101011010111111111011111111011011001111111 +11101011111110111111111111111111 +11111111111111101111111111111101111111111111111111111111111111111111111111110011 +11111111111111111111111110110111111111110011111010011111111101111011110111111111 +11110110111111111111110010111111 +11111111111100110111111111111111011001111111100111111111111110111111111111100011 +11111110100111111000111111000111111111100010011111011111111010011001011101111111 +11100110010011111111110111111111 +11111111111101010111111111111111011111111111101111111111111111110111111111110011 +11111111101111111100111111111111111111110010111011011111110111111011011111111111 +11110010110111011111101111111111 +11111111111111110111111111111111111111111110111111111111111111111111111111110011 +11111110011111111100111110111111111111111011110100111111111110111110011111111111 +11110011100111111111111111111111 +11111111111111111111111111111110001111111111100111111111111111111111111111100011 +01111011100111001000111111100111011111100011111111111110100110001101101101110111 +10100110111010011111111111111111 +11111111111111111111111111111111001111011111100111111111111111111111111111100000 +11111101110111011000111111100111011111100011111111011110110110000010010001110111 +01100010111110011111111111111110 +11111111111111111111111111111111001110111111111111111111111111111111111111110011 +11011111111111111100111111110110111111110011111111111111100111000111011111111111 +11111011110101011111111111111111 +11111111111111111111111111111111001111111111111111111111111111111111111111101111 +11111111101110111111111111110011111111101111111011111111011111101111001110101111 +11101111011111011111111111111111 +11110011111111111111111111111111001111101111111011001111111111100111111111110011 +11111111111111111111111111100111111111110011111111111110110011101111101001010011 +11110111111111111111111111111111 +11111111111111111111111111111111001111110111111111011111111111110111111111110000 +11011111110111111100111111100111111111110000111111011111110011001111110001110111 +10110011111111111101111111111111 +11111100111111111111111111111101000111101101111111111111111111101111111111010001 +00011111111111111000111111111111111111010011010111111111010101001111111111101111 +01011011111111111111111111111111 +11111111111111111111111111111111101111011111111100111111111111111111111111111111 +11011110111111111011111111111111111111111110110011111111101111101111111111111101 +11111111111111101111111111111111 +11111111111111111111111110101111011110100101111111111111111111111111111111111111 +01100101111111111111111111111111111111111101111011011111111111110101101101111111 +11111111111110111111111111111111 +11111111111111111111111110110001000001010101111111111111111111111111111111011000 +11001101111111111000100001111111111111011110010111011111111111111011001101111111 +11111111111111011111110111111111 +11111111111111111111111110011111001111011011111111111111111111111111111111111101 +11010101111111111100111111110111111111011011100100011111111111111111011001111111 +11111111111111011111101111111111 +11111111111111111111111110111111010111011111111111111111111111111111111111101111 +10011011111111111111111111110111111111111110110011011111111111111110100111111111 +11111110110111011111111111111111 +11111111111101111111011101111111011110101111101011111111111111111111111111111111 +10111001111111111111111110100111111111011111011111011111111111111110101111011111 +11111111111011111111111111111111 +11111111111110111111111111111111011111011111110111011111111111111111111111101011 +11001101111111111000111111010111111111101100110111001001111111111011010110100111 +11111111111101111111111111111111 +11111111111111010111111111111110011111100100110011111111111111111111111111111011 +11111001111111111100111111101111111111111110100110101101111111111111111100100111 +11111111111111011111111101111111 +11111111111111111110101111111111011111111111111110111111111111111111111111111111 +11111111111111111100111111111111111111101111110011100011111111111001011100111111 +11111111111111011111111111111111 +11111111111111111111101001111111011111101111100111011111111111110111011111100010 +11101101100111111000111111100001011111100001101111110101110111111111111100111101 +01111111111011111111111111111111 +11111111111111111111101101111111011011011111110001011111111111100111111111100010 +11011011110111101000111111100011011111100011110111111100111011111111111001011011 +01111111111111111111111111111111 +11111111111111111111111101111111111111111111111001011111111111111110111111111110 +00010101101111011100111111111100011111110011110111111111110111111111111111111111 +01111111111101011111111111111111 +11111111111111111111110011111111111100110111101110111111111110111111111111101111 +11011101111111111111111111111111111111110011111111111011010111111111101111111010 +01111111111111011111111111111111 +11111111111111111111111111111111011101111111100111111111111111100111111111111111 +11101001111111111111111110110111111111110011110111011111111111111111111111010011 +01111110111111111101111111111111 +11111111111111100111111111111111001011111111110111111111111111110111111111111111 +11110001111111111100111110000111111111110110111110011110111011111111011111110111 +11111110111111111111111111111111 +11111111111111111111111111111101001011111111111111111111111111101111111111011111 +11111101111111111000111111110111111111010011110111111111010111111011101101101111 +11111111010111111111111111111111 +11111111111110110111111111111111011111011111101111111111111111111111111111111111 +11111101111111111011111110111111111111110011011011111111111111111110011111111111 +11111111111111111011111111111111 +01111111111111111011111111111111101011111111111111111100111111111111111111111011 +11111110101111011111111110111110001111111111101011111111111011001111101111111111 +10111111111001011111111111111011 +01011111111111111111111111111101111001111111111111010100111111111111111111011011 +11111111110111111000100110111011010110011110010111111111110001001111111111111111 +01010011111101011111111111111011 +11111111111111111011001111111111110111011111111111110100111111111111111111111011 +11111111111111111100111111110001011101111101111101111111110111111111110111111111 +11011011111111111111111111111111 +11111111111111111101111101111111111111011111111111011100111111111111111111101011 +11111110111110111111101101011011111111101111110111111111111110111111111111111111 +11110111111110111111111111111111 +10111111111111111111111011111111111111011101111111010100111111100110111111110011 +01011101100111011111111111110011111111111110101011011100101111001011101001101111 +11011111111011111011111111111101 +11111111111111111111111111111111111011011011111111111000111001100111011110110010 +11011001110111111000111111100111011111100010110100011101111110001000001001110111 +01110011110101111101111111111111 +11111111111111111111111101111110111111011111111111111100101111111111011101110011 +11011111110111111100111111111111111111111101010011011111110111001011010101110011 +11111010101111111101111111111101 +11111111111111111111111111111111110100011111111110111100111101111111011111100011 +10101111110110111100111110111111011111101111110011101011011110001111011111111111 +11110111110111111111111111111101 +11111111111111111111111110111111111011111111111111111000111111111111111111101111 +01011111101101011000111111111101111111100010001011111111111110110110111111110010 +01100011111011111101010111111011 +11011111111111111111111111111111011011011111111111111000111111111111111111110110 +11111111111110011000111111111111111111100010110111111111111110111011011111111111 +01110011111101111111100111111011 +11111111111111111111011111110111111110011111111111111100111111111111111111111111 +11011111111011011100111111111111111111110001110011011111111111001101011111111010 +01110011111111011110110111111111 +11111111111111111111011110011111111001011111111111111100111111111111111111101111 +11111111111111111111111111111111111111100011110101111111111111001011011111111101 +11110011111111011111111111111110 +11101111111111110110011111111111111011111111110111111100111011111111111101111110 +11100111110111011111111010111111101101111011111011011100100011001011111111111111 +01110011101111111111110111111101 +11101111111111111111011111111011111011111111110111111100100101111111111101111110 +01001101111110011100111100111111011001111011111100011101110111001010001111111111 +01110010010111111111100111111111 +11111111111111110111111111110101111101011111110111110111111111111111101011011111 +11010101110011111000011111010111101111011011111111011101110101001011011101111010 +11011111111111111110111111111101 +11111111111111111110111111111111111011011111101111111100011101111111111111111110 +10011111111111111011111101111101110111111011111011010111001111001101011111111111 +11111110110111111111111111111111 +01111111111111111111100101100011000111111111110111001111111011111110011111110011 +11101111010111111100111111111111100111111111011111111110110111001111111110110111 +11110110111111101111111111111011 +01011111011011111111101101110101101011011111111111010110111101111111011111010011 +11010111110111110110100001111111111111111100111111111111010001111111111101110111 +00010010011111111111111111111011 +11111111010011111111111001111111101100011101111111110110111111111111111111100011 +10111101111111111110111111111111111111111111110111111111100001101111111111110111 +11010011110111111101111111111111 +11111111110011111111110111111111001011011101101110111111111111111110111111010010 +11011101101111111000111111111111111111111111111111111111111101101111101110000111 +11010111111111110101111111111111 +10111111011111111111110101111111111111101001101011110100011010111111111111010001 +01101101111111111100111110111111111111111111111011001111110001001101101001110111 +11010010111011111111111111111101 +11111111100000110111011101111111101011111101110111111110101101011111111111101110 +11010111111111111000001001011111111111111111111110001111110110001011001001111111 +11100010110111111111111111111111 +11111111110001110111111111111110101101111101111101001110110101111111111111110011 +11011111111111111100101100110111111111111111111011010101111111101011111101111111 +11110011110011011111111111111101 +11111111111111000011111011111111001111110001111111111111011101111111111111110010 +10011011111111111000110101111111111111111111111001111111101111101110010111101111 +11111110000101111111111111111101 +01111111100011111111111111111111001110111111110011111000111111111111111111100011 +11111110111011111011011111111111111000111111011111111101111010001111111111101111 +11101011111111111111111111111111 +01011111100011111111111111111111001111011111110101111000111111111111111100101111 +11111111010101111011101111111111111101111110100111111101110110101111111111100111 +11100011111111111111111111111110 +11111111110011111111111111111111100111111110111111011100111111111111111111111011 +11111110111111001111110101111111111111111111111111111011111111001111111111111111 +01110011111111111111111111111111 +11111111100011111111111111111111101111011110100111101100111111111111111111111011 +11111110101111111011111111111111111111111110110111101111111111001111111110111111 +01111011111111111111111111111111 +10111111110111111111111111111111001101011101111111111100111110111111111111110011 +11101111110011111111111110110111111001111110011011010100111111001011101110111111 +11111111111111111111111111111111 +11111111110111111111111111111111001011011111111111111100111111111111111111110010 +11010111111111111111111111101111101101111110100111111101111111001011110111111111 +11110011111111111111111111111111 +11111111010111111111111111111101101110011111111111110100111110110111111111010010 +00111111101111110100111111010111111111111111110101011111010101001101011100010111 +11011111111111111111111111111111 +11111111110111111111111111111111101111111011111111111101111111011111111111110011 +11011111111101111111111111110111111111111110110110011010111111001011011101111111 +11111111111111111111111111111111 +11111111111111111111111111111111111101111111101111111111101110111101011111011111 +10111111110011111111111111111111111111011111111011111111111111111011101111111111 +11111110111111111111111111111111 +11111111111100111111111111111101101011111111110111111111100101111111011111011110 +11011111101101101111101101111111111111011111111111111111111101111010011111111111 +11111110110111111111111111111111 +11111111111111110111111111111111111111111101111111111111101001011110111111110101 +11111111111111011111111111111111111111111111111101111111111111111101010101111111 +11111111010111111111111111111111 +11111111111111011111111111111110111111111101111111111111111101111111111111101111 +01011111111111111111110011111111111111101111111111111111111111011011011101111111 +11111111101111111111111111011111 +11111111111111111111111111111111111011111001111111101111111110111111111111111111 +01111101111111111111111110111111111111111111111011011111111111111111111001111111 +11111110111011111111111111111111 +11111111111111111111111111111110111011011001111111001111111111111111111111101100 +11011101111111111111111111111111111111101111110111011111111111111111111101111111 +11111110111101111111111111111111 +11111111111111111111111111111111111000011111111111011111111110010111111111111111 +11011011111111111111111111010111111111111111101000011111111110111111111011111111 +11111111110111111111111111111111 +11111111111111111111111111111111111111011111111111111111111111111111111111111111 +10101111111111111111111111110111111111110110110011111111111111111111111111111111 +11111111011111111111111101111111 +11111111111111111011111111111110001100111110110111111111111111111111111111101111 +11011101111111011111111111111111111100101110111111111110101111111111111111111111 +11111111111011111111111111111111 +11111111111111111111111111111110110011011110111011011111111111111111111111101111 +11011111111111011111111111111111111101101110010111111111111111110111011111111111 +11111111111101111111111111111111 +11111111111111111111111111111111110111011111100111111111111111111111111111111111 +10011011111010111111111111111111111111111011110111111111110111111111011111111111 +11111111111111011111111111111111 +11111111111111111101111111111110111111011111011111111111111111111111111111101110 +11011111111111111111111111111111111011111111101111111111011111111010011111111111 +11111111111111011111111111111111 +11111111111111111111111111111111001100101111111111111111111111111111111111110011 +11101111111111111111110110110111111111111111111010001111110111111111111111111111 +01111111111111111111111111111111 +11111100111111111111111111111111010011011111111111011111111110111111111111111111 +11111111111111111111101101011111111111111101111110011111110111101111111111111111 +01111111111011111111111111111111 +11111111111111111111111111111101010111010101111111111111111111110111111111011111 +11110101111111111111101011111111111111011111110011011110101101111111111111111011 +11111111111111011111111111111111 +11111111111111111111111111111111111111011101111111011111111111111111111111111111 +11111101111111111111111101101111111111111111111101110111111111111111111111111110 +11111111111111111111111111111111 +11111111111111111111111111111111110111111111111111111111111111111111111111111101 +11111111111011111111111111111111111111111010011110111111111111111101111111111111 +11111111111111111110111111111111 +11111111111111111111111111111101001110011111111111111111111111111111100111111110 +01011111111111110100111111111111111111010010111111011111111111111011011111111111 +11111111111111111111111111111111 +11111111111111111111111111111101001011011111111111111111111111111111111111111110 +11011111111011110110111111110111111111011010110111111111111111111110111111111111 +11111111111111111110111111111111 +11111111111111111111111111111111001111011111111111111111111111111111100111111111 +10011111111111110111111111110111111111111011110111111111111111111011011111111111 +11111111111111111111111111111111 +11111111111111000111111111111101111111111111110111111111101111100111111111111111 +11111100111111110111101110111111111111011111111011010001111111111101111101110111 +11111110111011111111111111111111 +11111111111110110111111111111111000110011101111011111111101101110111111111111111 +11011100110111111100101111110111101111110011111110101100111111110011011011111111 +11111110110101111111111111111111 +11111111111111110111111111111111001011011111111101011111101001101111111111111111 +11111010110111111100110101010111111111111111111011011111111111111011011111111111 +11111110010111111111111111111111 +11111111111111111111111111111111001111001110111011111111110101111111111111111101 +10001110001111111011111110110111110111101111111101101111011111111110011110111111 +11111111100111111111111111111111 +11111111111111111111111111111110111111101111010111111111111111111111000101111111 +11101111110111111000101111010111111111100001111011111111111111111111111100111010 +01111111111011101001111111111111 +11111111111111111111111111111111111111111111110111111111111111111111101101111111 +11110111101111111000100111100111111111100011111111111111111111111111111010111111 +01111111111101111101111111111111 +11111111111111111111111111111111111011101101101111111111111111111110111101111111 +11111111111111011100111101110111111111110001110011011111111111111111111111010111 +01111111111111110111110111111111 +11111111111111111111111111111111111111010111111111111111111111111111101011111111 +11111111111011111111111111110111111111110011110101111111111111111111111111111011 +11111111111111111010111111111111 +11111111111111111110011111111111111011111001111111111111111110110111111111111111 +10101101111111111100111110110111111111110011111011011111111111111111111101110111 +11111110001111111111111111111111 +11111111111111111110011111111111101000011101111111111111111101000111111111111111 +11011111111111111100111111101111111111110110111111111111111111110011011001100111 +11111110110011111111111111111111 +11111111111111111111111111111101111011011011111111111111101010110111111111111111 +11100101111111110100111110110111111111010111111111111111111111110111011111111111 +11111110110111011111111111111111 +11111111111111111111111111111111111111011111111111111111111100111111111111111110 +11011011111111111111111111011111111111110011011100111111111111111100001110111111 +11111111110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111101111111111111111111111111 +11111111111111111111111111111111011111110111111111111111111111111101110111101111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111110111110011111111101111111111111111111111111101111110111111101111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111110111111111111111111111111111 +11111111111111110111111111011111111111111111111111111111111111111111111111111111 +11111111111101011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111011111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111011111111111110111111111111 +11111111111111111011111111101111111111001111111100011111111111111111111011111111 +11111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111110101111111111111111111111111111111111111111101011111111111101111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111101111110111111111111111111111111111 +11111111111111110101111111010110111111011110111101111011111111111111110101101111 +11111111111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111010111111101111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111110111111111111111111111111111111111 +01111111111111111111100111111110001111111110001111111100111111111111111111100111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111101111111100111 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111101111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111011111111111111111111111111 +11111111111111111111111111111111 +11111111111111111111110111111111111111111111111111110111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111001111111 +11111111111111111111111111111111 +11111111111111111111110111111111111111111111111011110111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111111111111111111111011 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011111111111011 +11111111111111111111111111111111 +11111111111111111111111110111111111111111111111011110011111111110101111011001111 +11111101011101110011111111110101100111001111111111010110101100111111111101001111 +11001111111111010011111111111111 +11111111001111111111011110111100111111111101011101110011111111110100111111111111 +11111111111011110011111111110101100111001111111111010110011100111111111101011010 +11001111111111010111101111111111 +11111111111111111111111111111111111111111111111111110011111111110100111111111111 +11111111111111110011111111110100100111111111111111111111111100111111111101011001 +11111111111111111111111111111111 +11111111111111111111111111111111111111111111111111110011111111110111101111111111 +11111111111111110011111111110100111111111111111111111111111100111111111101001011 +11111111111111111111111111111111 +* +C8A2C* +N User Electronic Signature Data* +U00000000000000000000000000000000* +203C diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.log b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.log new file mode 100644 index 0000000..d0353b8 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.log @@ -0,0 +1,4 @@ +---- MParTrce Tool Log File ---- + +==== Par Standard Out ==== +==== End of Par Standard Out ==== diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf new file mode 100644 index 0000000..2743d95 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf @@ -0,0 +1,4 @@ +#BLOCK ASYNCPATHS; +#BLOCK RESETPATHS; + +#FREQUENCY 200.000000 MHz; diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lsedata b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lsedata new file mode 100644 index 0000000..89e99a4 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lsedata @@ -0,0 +1,6331 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp new file mode 100644 index 0000000..348c341 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mrp @@ -0,0 +1,336 @@ + + Lattice Mapping Report File for Design Module 'RAM2GS' + + +Design Information +------------------ + +Command line: map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial + RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr + RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf D:/OneDrive/ + Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf + -lpf + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf -c + 0 -gui -msgset + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml +Target Vendor: LATTICE +Target Device: LCMXO256CTQFP100 +Target Performance: 3 +Mapper: mj5g00, version: Diamond (64-bit) 3.12.1.454 +Mapped on: 08/15/23 05:03:20 + +Design Summary +-------------- + + Number of PFU registers: 102 out of 256 (40%) + Number of SLICEs: 71 out of 128 (55%) + SLICEs as Logic/ROM: 71 out of 128 (55%) + SLICEs as RAM: 0 out of 64 (0%) + SLICEs as Carry: 9 out of 128 (7%) + Number of LUT4s: 142 out of 256 (55%) + Number used as logic LUTs: 124 + Number used as distributed RAM: 0 + Number used as ripple logic: 18 + Number used as shift registers: 0 + Number of external PIOs: 67 out of 78 (86%) + Number of GSRs: 0 out of 1 (0%) + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + Number of TSALL: 0 out of 1 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of + distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and + ripple logic. + Number of clocks: 4 + Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Number of Clock Enables: 13 + Net PHI2_N_120_enable_4: 1 loads, 1 LSLICEs + Net RCLK_c_enable_4: 3 loads, 3 LSLICEs + Net RCLK_c_enable_23: 8 loads, 8 LSLICEs + Net RCLK_c_enable_12: 1 loads, 1 LSLICEs + Net RCLK_c_enable_3: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_5: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_6: 2 loads, 2 LSLICEs + Net RCLK_c_enable_24: 2 loads, 2 LSLICEs + Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs + Net Ready_N_292: 1 loads, 1 LSLICEs + + Page 1 + + + + +Design: RAM2GS Date: 08/15/23 05:03:20 + +Design Summary (cont) +--------------------- + Net RCLK_c_enable_11: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_25: 1 loads, 1 LSLICEs + Number of LSRs: 9 + Net RASr2: 1 loads, 1 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net C1Submitted_N_237: 2 loads, 2 LSLICEs + Net n2469: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net n1846: 2 loads, 2 LSLICEs + Net LEDEN_N_82: 1 loads, 1 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Net nRWE_N_177: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 23 loads + Net InitReady: 17 loads + Net RASr2: 14 loads + Net nRowColSel: 13 loads + Net MAin_c_0: 12 loads + Net nRowColSel_N_35: 12 loads + Net Din_c_3: 11 loads + Net Din_c_6: 11 loads + Net MAin_c_1: 11 loads + Net Din_c_4: 10 loads + + + + + Number of warnings: 0 + Number of errors: 0 + + +Design Errors/Warnings +---------------------- + + No errors or warnings present. + +IO (PIO) Attributes +------------------- + ++---------------------+-----------+-----------+------------+------------+ +| IO Name | Direction | Levelmode | IO | FIXEDDELAY | +| | | IO_TYPE | Register | | ++---------------------+-----------+-----------+------------+------------+ +| RD[7] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[6] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[5] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[4] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[3] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[2] | BIDIR | LVCMOS33 | | | + + Page 2 + + + + +Design: RAM2GS Date: 08/15/23 05:03:20 + +IO (PIO) Attributes (cont) +-------------------------- ++---------------------+-----------+-----------+------------+------------+ +| RD[1] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[0] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[7] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[6] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[5] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[4] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[3] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[2] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[1] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[0] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| LED | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RBA[1] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RBA[0] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[11] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[10] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[9] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[8] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[7] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[6] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[5] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[4] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[3] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[2] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[1] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[0] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRCS | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RCKE | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRWE | OUTPUT | LVCMOS33 | | | + + Page 3 + + + + +Design: RAM2GS Date: 08/15/23 05:03:20 + +IO (PIO) Attributes (cont) +-------------------------- ++---------------------+-----------+-----------+------------+------------+ +| nRRAS | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRCAS | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RDQMH | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RDQML | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nUFMCS | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMCLK | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMSDI | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| PHI2 | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[9] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[8] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[7] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[6] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[5] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[4] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[3] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[2] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[1] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[0] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| CROW[1] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| CROW[0] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[7] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[6] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[5] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[4] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[3] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[2] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[1] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[0] | INPUT | LVCMOS33 | | | + + Page 4 + + + + +Design: RAM2GS Date: 08/15/23 05:03:20 + +IO (PIO) Attributes (cont) +-------------------------- ++---------------------+-----------+-----------+------------+------------+ +| nCCAS | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nCRAS | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nFWE | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RCLK | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMSDO | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ + +Removed logic +------------- + +Block i2 undriven or does not drive anything - clipped. +Block GSR_INST undriven or does not drive anything - clipped. +Signal nCRAS_N_9 was merged into signal nCRAS_c +Signal nCCAS_N_3 was merged into signal nCCAS_c +Signal PHI2_N_120 was merged into signal PHI2_c +Signal RASr2_N_63 was merged into signal RASr2 +Signal n1426 was merged into signal nRowColSel_N_35 +Signal nRWE_N_176 was merged into signal nRWE_N_177 +Signal n1425 was merged into signal nRowColSel_N_34 +Signal nFWE_N_5 was merged into signal nFWE_c +Signal n2477 was merged into signal Ready +Signal GND_net undriven or does not drive anything - clipped. +Signal VCC_net undriven or does not drive anything - clipped. +Signal FS_610_add_4_18/CO1 undriven or does not drive anything - clipped. +Signal FS_610_add_4_18/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_10/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_4/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_12/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_2/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_14/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_6/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_16/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_8/CO0 undriven or does not drive anything - clipped. +Block i2135 was optimized away. +Block i2134 was optimized away. +Block i2136 was optimized away. +Block RASr2_I_0_1_lut was optimized away. +Block i1137_1_lut was optimized away. +Block nRWE_I_50_1_lut was optimized away. +Block i1136_1_lut was optimized away. +Block i1_1_lut was optimized away. +Block i637_1_lut_rep_34 was optimized away. +Block i1 was optimized away. + +Run Time and Memory Usage +------------------------- + + Total CPU Time: 0 secs + Total REAL Time: 0 secs + Peak Memory Usage: 29 MB + + + Page 5 + + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. + Copyright (c) 1995 AT&T Corp. All rights reserved. + Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. + Copyright (c) 2001 Agere Systems All rights reserved. + Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights + reserved. diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt new file mode 100644 index 0000000..2d70ad1 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.mt @@ -0,0 +1,9 @@ +-v +1 + + +-gt + + +-mapchkpnt 0 +-sethld diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e new file mode 100644 index 0000000..737af10 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.n2e @@ -0,0 +1,596 @@ + +comp 0: SLICE_0 (FSLICE) + +comp 1: SLICE_1 (FSLICE) + +comp 2: SLICE_2 (FSLICE) + +comp 3: SLICE_3 (FSLICE) + +comp 4: SLICE_4 (FSLICE) + +comp 5: SLICE_5 (FSLICE) + +comp 6: SLICE_6 (FSLICE) + +comp 7: SLICE_7 (FSLICE) + +comp 8: SLICE_8 (FSLICE) + +comp 9: SLICE_9 (FSLICE) +n1413 = (~n2263*(~ADSubmitted*n2242+ADSubmitted*(~n2459+n2242))+n2263*(ADSubmitted*~n2459)) +ADSubmitted.D = n1413 +ADSubmitted.CLK = ~PHI2_c +ADSubmitted.SP = VCC +ADSubmitted.LSR = C1Submitted_N_237 +n2263 = (~MAin_c_1+(~MAin_c_0+n1326)) + +comp 10: SLICE_14 (FSLICE) +n6_adj_3 = (~MAin_c_1*C1Submitted+MAin_c_1*(C1Submitted*(nFWE_c+n1326))) +C1Submitted.D = n6_adj_3 +C1Submitted.CLK = ~PHI2_c +C1Submitted.SP = VCC +C1Submitted.LSR = C1Submitted_N_237 +n2284 = (C1Submitted+Din_c_6) + +comp 11: SLICE_18 (FSLICE) +CmdEnable_N_248 = (n15*(~n1326*(n2463*MAin_c_1))) +CmdEnable.D = CmdEnable_N_248 +CmdEnable.CLK = ~PHI2_c +CmdEnable.SP = PHI2_N_120_enable_7 +CmdEnable.LSR = GND +n1326 = (~MAin_c_5+(~n2316+(~MAin_c_2+n26))) + +comp 12: SLICE_19 (FSLICE) +n2568\001/BUF1 = VCC +CmdSubmitted.D = n2568\001/BUF1 +CmdSubmitted.CLK = ~PHI2_c +CmdSubmitted.SP = PHI2_N_120_enable_5 +CmdSubmitted.LSR = GND +n2472 = (~PHI2r2*(CmdSubmitted*PHI2r3)) + +comp 13: SLICE_23 (FSLICE) +Cmdn8MEGEN_N_264 = (~n1314*(~Din_c_4*n8MEGEN+Din_c_4*~Din_c_0)+n1314*n8MEGEN) +Cmdn8MEGEN.D = Cmdn8MEGEN_N_264 +Cmdn8MEGEN.CLK = ~PHI2_c +Cmdn8MEGEN.SP = PHI2_N_120_enable_4 +Cmdn8MEGEN.LSR = GND +n1314 = ((Din_c_6+Din_c_7)+Din_c_5) + +comp 14: SLICE_25 (FSLICE) +n2568\000/BUF1 = VCC +InitReady.D = n2568\000/BUF1 +InitReady.CLK = RCLK_c +InitReady.SP = RCLK_c_enable_25 +InitReady.LSR = GND +RCLK_c_enable_23 = (nRowColSel_N_35*(RASr2*(InitReady*~Ready))) + +comp 15: SLICE_26 (FSLICE) +n2568 = VCC +LEDEN.D = n2568 +LEDEN.CLK = RCLK_c +LEDEN.SP = RCLK_c_enable_12 +LEDEN.LSR = GND +LED_N_84 = ((~LEDEN+CBR)+nCRAS_c) + +comp 16: SLICE_31 (FSLICE) +n2209 = ((n2208+Ready)+nRCAS_N_165) +RA_0.D = n2209 +RA_0.CLK = RCLK_c +RA_0.SP = VCC +RA_0.LSR = ~nRWE_N_177 +n56 = (~Ready+nRowColSel_N_34) + +comp 17: SLICE_32 (FSLICE) +RA11_N_184 = (~n8MEGEN*(XOR8MEG@Din_c_6)+n8MEGEN*XOR8MEG) +RA_c.D = RA11_N_184 +RA_c.CLK = PHI2_c +RA_c.SP = VCC +RA_c.LSR = ~Ready +n2478 = (Din_c_6+Din_c_7) + +comp 18: SLICE_34 (FSLICE) +RCKEEN_N_121 = (~Ready*InitReady+Ready*RCKEEN_N_122) +RCKEEN.D = RCKEEN_N_121 +RCKEEN.CLK = RCLK_c +RCKEEN.SP = RCLK_c_enable_4 +RCKEEN.LSR = GND +n2467 = ((InitReady*RASr2)+Ready) + +comp 19: SLICE_35 (FSLICE) +RCKE_N_132 = (~RASr3*(~RASr2*(RCKEEN*RASr)+RASr2*RCKEEN)+RASr3*(~RASr2+RCKEEN)) +RCKE_c.D = RCKE_N_132 +RCKE_c.CLK = RCLK_c +RCKE_c.SP = VCC +RCKE_c.LSR = GND +nRWE_N_182 = (~RCKE_c+RASr2) +CASr2.D = CASr +CASr2.CLK = RCLK_c +CASr2.SP = VCC +CASr2.LSR = GND + +comp 20: SLICE_36 (FSLICE) +n2568\002/BUF1 = VCC +Ready.D = n2568\002/BUF1 +Ready.CLK = RCLK_c +Ready.SP = Ready_N_292 +Ready.LSR = GND +n2469 = (~Ready+nRowColSel_N_35) + +comp 21: SLICE_43 (FSLICE) +UFMCLK_N_224 = (~InitReady*n1160+InitReady*CmdUFMCLK) +UFMCLK_c.D = UFMCLK_N_224 +UFMCLK_c.CLK = RCLK_c +UFMCLK_c.SP = RCLK_c_enable_24 +UFMCLK_c.LSR = n1846 +n1160 = (~FS_1*(~n2462*FS_4)+FS_1*(~n2462*FS_4+n2462*~n62)) + +comp 22: SLICE_44 (FSLICE) +UFMSDI_N_231 = (~CmdUFMSDI*(~InitReady*(~n2462*n2461))+CmdUFMSDI*((~n2462*n2461)+InitReady)) +UFMSDI_c.D = UFMSDI_N_231 +UFMSDI_c.CLK = RCLK_c +UFMSDI_c.SP = RCLK_c_enable_24 +UFMSDI_c.LSR = n1846 +n2462 = (~FS_11+((n2471+n2272)+n2470)) + +comp 23: SLICE_49 (FSLICE) +XOR8MEG_N_110 = (~n2324*(Din_c_2*(~Din_c_3*Din_c_0))) +XOR8MEG.D = XOR8MEG_N_110 +XOR8MEG.CLK = ~PHI2_c +XOR8MEG.SP = PHI2_N_120_enable_1 +XOR8MEG.LSR = GND +n2324 = (~Din_c_1*(Din_c_4+n1314)+Din_c_1*((Din_c_4+LEDEN)+n1314)) + +comp 24: SLICE_56 (FSLICE) +n8MEGEN_N_91 = (~n1325*(~InitReady*~UFMSDO_c+InitReady*Cmdn8MEGEN)+n1325*Cmdn8MEGEN) +n8MEGEN.D = n8MEGEN_N_91 +n8MEGEN.CLK = RCLK_c +n8MEGEN.SP = RCLK_c_enable_11 +n8MEGEN.LSR = GND +n1325 = (~FS_10+(~FS_11+n2464)) + +comp 25: SLICE_58 (FSLICE) +nRCAS_N_161 = (((~CBR*Ready)+(n2427*~Ready)+(n2427*~CBR)+~RASr2)*nRowColSel_N_35)+((nRowColSel_N_34+~n15_adj_1+~Ready)*~nRowColSel_N_35) +nRCAS_c.D = nRCAS_N_161 +nRCAS_c.CLK = RCLK_c +nRCAS_c.SP = RCLK_c_enable_4 +nRCAS_c.LSR = GND + +comp 26: SLICE_60 (FSLICE) +nRCS_N_136 = (~nRowColSel_N_35*(~n2467+n2481)+nRowColSel_N_35*(~n13+n2481)) +nRCS_c.D = nRCS_N_136 +nRCS_c.CLK = RCLK_c +nRCS_c.SP = RCLK_c_enable_4 +nRCS_c.LSR = GND +n13 = (~Ready*(InitReady*RASr2)+Ready*(RASr2+RCKE_c)) + +comp 27: SLICE_61 (FSLICE) +n2138 = (((nRCS_N_139*~Ready)+~n13)*nRowColSel_N_35)+((n56+nRRAS_c+n6+nRowColSel_N_32)*~nRowColSel_N_35) +nRRAS_c.D = n2138 +nRRAS_c.CLK = RCLK_c +nRRAS_c.SP = VCC +nRRAS_c.LSR = GND + +comp 28: SLICE_63 (FSLICE) +nRWE_N_171 = (~n2208*(~Ready*~n33+Ready*nRWE_N_178)+n2208*(~Ready+nRWE_N_178)) +nRWE_c.D = nRWE_N_171 +nRWE_c.CLK = RCLK_c +nRWE_c.SP = RCLK_c_enable_3 +nRWE_c.LSR = GND +n2208 = ((~InitReady+(~RASr2+~nRowColSel_N_35))+nRCS_N_139) + +comp 29: SLICE_64 (FSLICE) +n1410 = (~nRowColSel_N_32*(nRowColSel+n1502)+nRowColSel_N_32*(~nRowColSel_N_28+n1502)) +nRowColSel.D = n1410 +nRowColSel.CLK = RCLK_c +nRowColSel.SP = VCC +nRowColSel.LSR = n2469 +RA_1_9 = (~nRowColSel*RowA_9+nRowColSel*MAin_c_9) + +comp 30: SLICE_65 (FSLICE) +n1503 = (nRowColSel_N_32+nRowColSel_N_33) +nRowColSel_N_32.D = n1503 +nRowColSel_N_32.CLK = RCLK_c +nRowColSel_N_32.SP = VCC +nRowColSel_N_32.LSR = ~RASr2 +n2414 = (InitReady*(Ready_N_296*(~RASr2*nRowColSel_N_32))) + +comp 31: SLICE_66 (FSLICE) +n1093 = (RASr2*~nRowColSel_N_32) +nRowColSel_N_33.D = n1093 +nRowColSel_N_33.CLK = RCLK_c +nRowColSel_N_33.SP = VCC +nRowColSel_N_33.LSR = ~nRowColSel_N_34 +RCLK_c_enable_4 = (((nRowColSel_N_32+n2469)+nRowColSel_N_34)+nRowColSel_N_33) + +comp 32: SLICE_67 (FSLICE) +n11 = (~CASr2+nRowColSel_N_33) +nRowColSel_N_34.D = n1093 +nRowColSel_N_34.CLK = RCLK_c +nRowColSel_N_34.SP = VCC +nRowColSel_N_34.LSR = ~nRowColSel_N_35 +n1417 = (~n2472*nUFMCS_c+n2472*~CmdUFMCS) + +comp 33: SLICE_68 (FSLICE) +n2322 = (((FS_0+FS_1)+FS_6)+FS_3) +nRowColSel_N_35.D = ~RASr2 +nRowColSel_N_35.CLK = RCLK_c +nRowColSel_N_35.SP = VCC +nRowColSel_N_35.LSR = GND +n2471 = (FS_17+FS_12) +CASr3.D = CASr2 +CASr3.CLK = RCLK_c +CASr3.SP = VCC +CASr3.LSR = GND + +comp 34: SLICE_69 (FSLICE) +n2164 = (~InitReady*n62+InitReady*n1417) +nUFMCS_c.D = n2164 +nUFMCS_c.CLK = RCLK_c +nUFMCS_c.SP = VCC +nUFMCS_c.LSR = LEDEN_N_82 +n62 = (FS_14*(FS_12*(n12*FS_17))) + +comp 35: RCKEEN_I_0_445/SLICE_70 (FSLICE) +RCKEEN_N_122 = (((~FWEr*~CBR)+~RASr2)*nRowColSel_N_35)+(((FWEr*n11*~CBR)+(nRowColSel_N_34*~CBR))*~nRowColSel_N_35) + +comp 36: i26/SLICE_71 (FSLICE) +n13_adj_2 = ((~n2284*n2476*MAin_c_1*MAin_c_0)*Din_c_2)+((~ADSubmitted*~MAin_c_0*n2475*~Din_c_5)*~Din_c_2) + +comp 37: i2099/SLICE_72 (FSLICE) +n2481 = (((nRowColSel_N_35*~Ready*nRCS_N_139)+(nRowColSel_N_34*~Ready*nRCS_N_139)+(~nRowColSel_N_35*~Ready)+(nRowColSel_N_34*~nRowColSel_N_35))*n15_adj_1)+(((~Ready*nRCS_N_139)+~nRowColSel_N_35)*~n15_adj_1) + +comp 38: i26_adj_28/SLICE_73 (FSLICE) +n15 = ((MAin_c_0*Din_c_2*Din_c_3*~Din_c_6)*Din_c_5)+((~MAin_c_0*~Din_c_2*~Din_c_3*Din_c_6)*~Din_c_5) + +comp 39: SLICE_74 (FSLICE) +n1 = (~CASr3*(CASr2*(FWEr*~CBR))) +RASr2.D = RASr +RASr2.CLK = RCLK_c +RASr2.SP = VCC +RASr2.LSR = GND +n15_adj_1 = (~n1*(nRowColSel_N_33*(~CBR*~FWEr))+n1*(~nRowColSel_N_33+(~CBR*~FWEr))) +RASr3.D = RASr2 +RASr3.CLK = RCLK_c +RASr3.SP = VCC +RASr3.LSR = GND + +comp 40: SLICE_75 (FSLICE) +n2214 = (FS_11*(~n2272*(~n2328*FS_10))) +RCLK_c_enable_12 = (~InitReady*(FS_11*n2214)) + +comp 41: SLICE_76 (FSLICE) +PHI2_N_120_enable_4 = (n2458*(~Din_c_4*~Din_c_5+Din_c_4*(~Din_c_5+Din_c_3))) +n732.D = n733 +n732.CLK = RCLK_c +n732.SP = RCLK_c_enable_23 +n732.LSR = GND +n2458 = (MAin_c_0*(n10*(~n1326*~nFWE_c))) +nRWE_N_177.D = n732 +nRWE_N_177.CLK = RCLK_c +nRWE_N_177.SP = RCLK_c_enable_23 +nRWE_N_177.LSR = GND + +comp 42: SLICE_77 (FSLICE) +n2290 = ((FS_2+FS_5)+FS_9) +n728.D = n729 +n728.CLK = RCLK_c +n728.SP = RCLK_c_enable_23 +n728.LSR = GND +n8 = (~FS_7*(~n2322*(FS_4*~n2290))) +n727.D = n728 +n727.CLK = RCLK_c +n727.SP = RCLK_c_enable_23 +n727.LSR = GND + +comp 43: SLICE_78 (FSLICE) +n1846 = (~InitReady*(~n2464*~FS_11)) +RowA_6.D = MAin_c_6 +RowA_6.CLK = ~nCRAS_c +RowA_6.SP = VCC +RowA_6.LSR = ~Ready +n2464 = (((FS_16+FS_14)+n2272)+n2471) +RowA_7.D = MAin_c_7 +RowA_7.CLK = ~nCRAS_c +RowA_7.SP = VCC +RowA_7.LSR = ~Ready + +comp 44: SLICE_79 (FSLICE) +C1Submitted_N_237 = (n2468*(~n1280*(n2463*~Din_c_2))) +CASr.D = ~nCCAS_c +CASr.CLK = RCLK_c +CASr.SP = VCC +CASr.LSR = GND +n2468 = (~Din_c_5*(~Din_c_3*Din_c_6)) +PHI2r2.D = PHI2r +PHI2r2.CLK = RCLK_c +PHI2r2.SP = VCC +PHI2r2.LSR = GND + +comp 45: SLICE_80 (FSLICE) +RCLK_c_enable_3 = (((~Ready+nRowColSel_N_32)+n1502)+nRowColSel_N_35) +n726.D = n727 +n726.CLK = RCLK_c +n726.SP = RCLK_c_enable_23 +n726.LSR = GND +n1502 = (nRowColSel_N_34+nRowColSel_N_33) +Ready_N_296.D = n726 +Ready_N_296.CLK = RCLK_c +Ready_N_296.SP = RCLK_c_enable_23 +Ready_N_296.LSR = GND + +comp 46: SLICE_81 (FSLICE) +n26 = (~Bank_5+(~n2278+(~n2314+Bank_2))) +CmdUFMCLK.D = Din_c_1 +CmdUFMCLK.CLK = ~PHI2_c +CmdUFMCLK.SP = PHI2_N_120_enable_6 +CmdUFMCLK.LSR = GND +n2278 = (Bank_3*Bank_6) +CmdUFMCS.D = Din_c_2 +CmdUFMCS.CLK = ~PHI2_c +CmdUFMCS.SP = PHI2_N_120_enable_6 +CmdUFMCS.LSR = GND + +comp 47: SLICE_82 (FSLICE) +n2460 = (nFWE_c+n1326) +n730.D = nRWE_N_177 +n730.CLK = RCLK_c +n730.SP = RCLK_c_enable_23 +n730.LSR = GND +PHI2_N_120_enable_7 = (~MAin_c_1*(~n14*(~n2460*MAin_c_0))+MAin_c_1*(~n14*~n2460)) +n729.D = n730 +n729.CLK = RCLK_c +n729.SP = RCLK_c_enable_23 +n729.LSR = GND + +comp 48: SLICE_83 (FSLICE) +n10 = (~MAin_c_1*(CmdEnable*(~n2478*Din_c_4))) +RASr.D = ~nCRAS_c +RASr.CLK = RCLK_c +RASr.SP = VCC +RASr.LSR = GND +PHI2_N_120_enable_6 = (n2476*(~n2460*(n10*MAin_c_0))) + +comp 49: SLICE_84 (FSLICE) +n2262 = ((~MAin_c_0+n1326)+MAin_c_1) +n738.D = nRCAS_N_165 +n738.CLK = RCLK_c +n738.SP = RCLK_c_enable_23 +n738.LSR = GND +PHI2_N_120_enable_1 = (~n1314*(~n2262*(CmdEnable*~n2473))) +n737.D = n738 +n737.CLK = RCLK_c +n737.SP = RCLK_c_enable_23 +n737.LSR = GND + +comp 50: SLICE_85 (FSLICE) +n2473 = (Din_c_4+nFWE_c) +RBA_c_0.D = CROW_c_0 +RBA_c_0.CLK = ~nCRAS_c +RBA_c_0.SP = VCC +RBA_c_0.LSR = ~Ready +n2242 = (n2474*(Din_c_5*(n2253*~n2473))) +RBA_c_1.D = CROW_c_1 +RBA_c_1.CLK = ~nCRAS_c +RBA_c_1.SP = VCC +RBA_c_1.LSR = ~Ready + +comp 51: SLICE_86 (FSLICE) +n2463 = (n2253*(~nFWE_c*~Din_c_4)) +n734.D = n735 +n734.CLK = RCLK_c +n734.SP = RCLK_c_enable_23 +n734.LSR = GND +n2253 = (~Din_c_1*(Din_c_0*Din_c_7)) +n733.D = n734 +n733.CLK = RCLK_c +n733.SP = RCLK_c_enable_23 +n733.LSR = GND + +comp 52: SLICE_87 (FSLICE) +RCLK_c_enable_11 = (~n8*(InitReady*n2472)+n8*(~InitReady*n7+InitReady*n2472)) +nRCS_N_139.D = Ready_N_296 +nRCS_N_139.CLK = RCLK_c +nRCS_N_139.SP = RCLK_c_enable_23 +nRCS_N_139.LSR = GND +n7 = (n2214*~FS_8) +nRCAS_N_165.D = nRCS_N_139 +nRCAS_N_165.CLK = RCLK_c +nRCAS_N_165.SP = RCLK_c_enable_23 +nRCAS_N_165.LSR = GND + +comp 53: SLICE_88 (FSLICE) +n2451 = (~FS_8*(~FS_5*(~FS_9*FS_7)+FS_5*(FS_9@FS_7))) +Bank_0.D = Din_c_0 +Bank_0.CLK = PHI2_c +Bank_0.SP = VCC +Bank_0.LSR = GND +n2461 = (~FS_10*(FS_6*n2451)) +Bank_1.D = Din_c_1 +Bank_1.CLK = PHI2_c +Bank_1.SP = VCC +Bank_1.LSR = GND + +comp 54: SLICE_89 (FSLICE) +n1280 = ((~MAin_c_1+n1326)+MAin_c_0) +WRD_0.D = Din_c_0 +WRD_0.CLK = ~nCCAS_c +WRD_0.SP = VCC +WRD_0.LSR = GND +n2459 = (MAin_c_1*(~n1326*~nFWE_c)) +WRD_1.D = Din_c_1 +WRD_1.CLK = ~nCCAS_c +WRD_1.SP = VCC +WRD_1.LSR = GND + +comp 55: SLICE_90 (FSLICE) +n2470 = (FS_16+FS_14) +RowA_8.D = MAin_c_8 +RowA_8.CLK = ~nCRAS_c +RowA_8.SP = VCC +RowA_8.LSR = ~Ready +n2328 = (((FS_17+FS_12)+FS_14)+FS_16) +RowA_9.D = MAin_c_9 +RowA_9.CLK = ~nCRAS_c +RowA_9.SP = VCC +RowA_9.LSR = ~Ready + +comp 56: SLICE_91 (FSLICE) +PHI2_N_120_enable_5 = (n2458*(~Din_c_5*Din_c_4+Din_c_5*(Din_c_4*Din_c_3))) +PHI2r3.D = PHI2r2 +PHI2r3.CLK = RCLK_c +PHI2r3.SP = VCC +PHI2r3.LSR = GND +n2476 = (Din_c_5*Din_c_3) +PHI2r.D = PHI2_c +PHI2r.CLK = RCLK_c +PHI2r.SP = VCC +PHI2r.LSR = GND + +comp 57: SLICE_92 (FSLICE) +n2474 = (Din_c_3*(Din_c_2*~Din_c_6)) +WRD_6.D = Din_c_6 +WRD_6.CLK = ~nCCAS_c +WRD_6.SP = VCC +WRD_6.LSR = GND +n2475 = (~Din_c_3*Din_c_6) +WRD_7.D = Din_c_7 +WRD_7.CLK = ~nCCAS_c +WRD_7.SP = VCC +WRD_7.LSR = GND + +comp 58: SLICE_93 (FSLICE) +RDQMH_c = (~nRowColSel+MAin_c_9) +CmdUFMSDI.D = Din_c_0 +CmdUFMSDI.CLK = ~PHI2_c +CmdUFMSDI.SP = PHI2_N_120_enable_6 +CmdUFMSDI.LSR = GND +RDQML_c = (~nRowColSel+~MAin_c_9) + +comp 59: SLICE_94 (FSLICE) +n12 = (FS_11*(FS_16*(FS_13*FS_15))) +n2272 = (FS_13+FS_15) + +comp 60: SLICE_95 (FSLICE) +LEDEN_N_82 = (~InitReady*(~FS_10*(~n2464*~FS_11))) +RowA_4.D = MAin_c_4 +RowA_4.CLK = ~nCRAS_c +RowA_4.SP = VCC +RowA_4.LSR = ~Ready +RCLK_c_enable_25 = (FS_10*n62) +RowA_5.D = MAin_c_5 +RowA_5.CLK = ~nCRAS_c +RowA_5.SP = VCC +RowA_5.LSR = ~Ready + +comp 61: SLICE_96 (FSLICE) +n2316 = (Bank_1*(Bank_4*(MAin_c_3*MAin_c_7))) +RowA_2.D = MAin_c_2 +RowA_2.CLK = ~nCRAS_c +RowA_2.SP = VCC +RowA_2.LSR = ~Ready +RA_1_3 = (~nRowColSel*RowA_3+nRowColSel*MAin_c_3) +RowA_3.D = MAin_c_3 +RowA_3.CLK = ~nCRAS_c +RowA_3.SP = VCC +RowA_3.LSR = ~Ready + +comp 62: SLICE_97 (FSLICE) +n2314 = (Bank_0*(Bank_7*(MAin_c_4*MAin_c_6))) +RowA_0.D = MAin_c_0 +RowA_0.CLK = ~nCRAS_c +RowA_0.SP = VCC +RowA_0.LSR = ~Ready +RA_1_4 = (~nRowColSel*RowA_4+nRowColSel*MAin_c_4) +RowA_1.D = MAin_c_1 +RowA_1.CLK = ~nCRAS_c +RowA_1.SP = VCC +RowA_1.LSR = ~Ready + +comp 63: SLICE_98 (FSLICE) +RA_1_8 = (~nRowColSel*RowA_8+nRowColSel*MAin_c_8) +CBR.D = ~nCCAS_c +CBR.CLK = ~nCRAS_c +CBR.SP = VCC +CBR.LSR = GND +RA_1_0 = (~nRowColSel*RowA_0+nRowColSel*MAin_c_0) +FWEr.D = ~nFWE_c +FWEr.CLK = ~nCRAS_c +FWEr.SP = VCC +FWEr.LSR = GND + +comp 64: SLICE_99 (FSLICE) +RA_1_7 = (~nRowColSel*RowA_7+nRowColSel*MAin_c_7) +Bank_6.D = Din_c_6 +Bank_6.CLK = PHI2_c +Bank_6.SP = VCC +Bank_6.LSR = GND +RA_1_1 = (~nRowColSel*RowA_1+nRowColSel*MAin_c_1) +Bank_7.D = Din_c_7 +Bank_7.CLK = PHI2_c +Bank_7.SP = VCC +Bank_7.LSR = GND + +comp 65: SLICE_100 (FSLICE) +RCLK_c_enable_24 = (~InitReady+(~PHI2r2*(CmdSubmitted*PHI2r3))) +n736.D = n737 +n736.CLK = RCLK_c +n736.SP = RCLK_c_enable_23 +n736.LSR = GND +n6 = (~Ready*((~InitReady+~RASr2)+nRowColSel_N_33)+Ready*nRowColSel_N_33) +n735.D = n736 +n735.CLK = RCLK_c +n735.SP = RCLK_c_enable_23 +n735.LSR = GND + +comp 66: SLICE_101 (FSLICE) +RA_1_6 = (~nRowColSel*RowA_6+nRowColSel*MAin_c_6) +Bank_4.D = Din_c_4 +Bank_4.CLK = PHI2_c +Bank_4.SP = VCC +Bank_4.LSR = GND +RA_1_2 = (~nRowColSel*RowA_2+nRowColSel*MAin_c_2) +Bank_5.D = Din_c_5 +Bank_5.CLK = PHI2_c +Bank_5.SP = VCC +Bank_5.LSR = GND + +comp 67: SLICE_102 (FSLICE) +n2427 = ((~InitReady+nRCS_N_139)+nRCAS_N_165) +Bank_2.D = Din_c_2 +Bank_2.CLK = PHI2_c +Bank_2.SP = VCC +Bank_2.LSR = GND +n33 = (nRCAS_N_165+nRWE_N_177) +Bank_3.D = Din_c_3 +Bank_3.CLK = PHI2_c +Bank_3.SP = VCC +Bank_3.LSR = GND + +comp 68: SLICE_103 (FSLICE) +nRowColSel_N_28 = ((~FWEr+CASr3)+CBR) +WRD_2.D = Din_c_2 +WRD_2.CLK = ~nCCAS_c +WRD_2.SP = VCC +WRD_2.LSR = GND +RA_1_5 = (~nRowColSel*RowA_5+nRowColSel*MAin_c_5) +WRD_3.D = Din_c_3 +WRD_3.CLK = ~nCCAS_c +WRD_3.SP = VCC +WRD_3.LSR = GND + +comp 69: SLICE_104 (FSLICE) +nRWE_N_178 = (~nRowColSel_N_35*(~n1+n1502)+nRowColSel_N_35*nRWE_N_182) +Ready_N_292 = (n2414+Ready) + +comp 70: SLICE_105 (FSLICE) +n14 = (n13_adj_2*(~Din_c_4*n2253)) +WRD_4.D = Din_c_4 +WRD_4.CLK = ~nCCAS_c +WRD_4.SP = VCC +WRD_4.LSR = GND +n984 = (nCCAS_c+nFWE_c) +WRD_5.D = Din_c_5 +WRD_5.CLK = ~nCCAS_c +WRD_5.SP = VCC +WRD_5.LSR = GND diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd new file mode 100644 index 0000000..113a28f Binary files /dev/null and b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ncd differ diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ngd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ngd new file mode 100644 index 0000000..08e5b3e Binary files /dev/null and b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.ngd differ diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t new file mode 100644 index 0000000..16daf53 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p2t @@ -0,0 +1,9 @@ +-w +-l 5 +-i 6 +-n 1 +-t 1 +-s 1 +-c 0 +-e 0 +-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p3t b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p3t new file mode 100644 index 0000000..e625c68 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.p3t @@ -0,0 +1,5 @@ +-rem +-distrce +-log "RAM2GS_LCMXO256C_impl1.log" +-o "RAM2GS_LCMXO256C_impl1.csv" +-pr "RAM2GS_LCMXO256C_impl1.prf" diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad new file mode 100644 index 0000000..4582186 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pad @@ -0,0 +1,271 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO256C +Performance Grade: 3 +PACKAGE: TQFP100 +Package Status: Final Version 1.19 + +Tue Aug 15 05:03:28 2023 + +Pinout by Port Name: ++-----------+----------+---------------+------+------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | Properties | ++-----------+----------+---------------+------+------------------------------+ +| CROW[0] | 32/1 | LVCMOS33_IN | PB2C | SLEW:FAST PULL:UP | +| CROW[1] | 34/1 | LVCMOS33_IN | PB2D | SLEW:FAST PULL:UP | +| Din[0] | 21/1 | LVCMOS33_IN | PL8A | SLEW:FAST PULL:UP | +| Din[1] | 15/1 | LVCMOS33_IN | PL6A | SLEW:FAST PULL:UP | +| Din[2] | 14/1 | LVCMOS33_IN | PL5D | SLEW:FAST PULL:UP | +| Din[3] | 16/1 | LVCMOS33_IN | PL6B | SLEW:FAST PULL:UP | +| Din[4] | 18/1 | LVCMOS33_IN | PL7B | SLEW:FAST PULL:UP | +| Din[5] | 17/1 | LVCMOS33_IN | PL7A | SLEW:FAST PULL:UP | +| Din[6] | 20/1 | LVCMOS33_IN | PL7D | SLEW:FAST PULL:UP | +| Din[7] | 19/1 | LVCMOS33_IN | PL7C | SLEW:FAST PULL:UP | +| Dout[0] | 1/1 | LVCMOS33_OUT | PL2A | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[1] | 7/1 | LVCMOS33_OUT | PL4A | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[2] | 8/1 | LVCMOS33_OUT | PL4B | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[3] | 6/1 | LVCMOS33_OUT | PL3D | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[4] | 4/1 | LVCMOS33_OUT | PL3B | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[5] | 5/1 | LVCMOS33_OUT | PL3C | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[6] | 2/1 | LVCMOS33_OUT | PL2B | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[7] | 3/1 | LVCMOS33_OUT | PL3A | DRIVE:8mA SLEW:FAST PULL:UP | +| LED | 57/0 | LVCMOS33_OUT | PR7B | DRIVE:8mA SLEW:FAST PULL:UP | +| MAin[0] | 23/1 | LVCMOS33_IN | PL9A | SLEW:FAST PULL:UP | +| MAin[1] | 38/1 | LVCMOS33_IN | PB3C | SLEW:FAST PULL:UP | +| MAin[2] | 37/1 | LVCMOS33_IN | PB3B | SLEW:FAST PULL:UP | +| MAin[3] | 47/1 | LVCMOS33_IN | PB5A | SLEW:FAST PULL:UP | +| MAin[4] | 46/1 | LVCMOS33_IN | PB4D | SLEW:FAST PULL:UP | +| MAin[5] | 45/1 | LVCMOS33_IN | PB4C | SLEW:FAST PULL:UP | +| MAin[6] | 49/1 | LVCMOS33_IN | PB5C | SLEW:FAST PULL:UP | +| MAin[7] | 44/1 | LVCMOS33_IN | PB4B | SLEW:FAST PULL:UP | +| MAin[8] | 50/1 | LVCMOS33_IN | PB5D | SLEW:FAST PULL:UP | +| MAin[9] | 51/0 | LVCMOS33_IN | PR9B | SLEW:FAST PULL:UP | +| PHI2 | 39/1 | LVCMOS33_IN | PB3D | SLEW:FAST PULL:UP | +| RA[0] | 98/0 | LVCMOS33_OUT | PT2C | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[10] | 87/0 | LVCMOS33_OUT | PT3D | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[11] | 79/0 | LVCMOS33_OUT | PT5A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[1] | 89/0 | LVCMOS33_OUT | PT3C | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[2] | 94/0 | LVCMOS33_OUT | PT3A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[3] | 97/0 | LVCMOS33_OUT | PT2D | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[4] | 99/0 | LVCMOS33_OUT | PT2B | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[5] | 95/0 | LVCMOS33_OUT | PT2F | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[6] | 91/0 | LVCMOS33_OUT | PT3B | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[7] | 100/0 | LVCMOS33_OUT | PT2A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[8] | 96/0 | LVCMOS33_OUT | PT2E | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[9] | 85/0 | LVCMOS33_OUT | PT4B | DRIVE:8mA SLEW:FAST PULL:UP | +| RBA[0] | 63/0 | LVCMOS33_OUT | PR5D | DRIVE:8mA SLEW:FAST PULL:UP | +| RBA[1] | 83/0 | LVCMOS33_OUT | PT4C | DRIVE:8mA SLEW:FAST PULL:UP | +| RCKE | 82/0 | LVCMOS33_OUT | PT4D | DRIVE:8mA SLEW:FAST PULL:UP | +| RCLK | 86/0 | LVCMOS33_IN | PT4A | SLEW:FAST PULL:UP | +| RDQMH | 76/0 | LVCMOS33_OUT | PR2A | DRIVE:8mA SLEW:FAST PULL:UP | +| RDQML | 61/0 | LVCMOS33_OUT | PR6A | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[0] | 64/0 | LVCMOS33_BIDI | PR5C | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[1] | 65/0 | LVCMOS33_BIDI | PR5B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[2] | 66/0 | LVCMOS33_BIDI | PR5A | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[3] | 67/0 | LVCMOS33_BIDI | PR4B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[4] | 68/0 | LVCMOS33_BIDI | PR4A | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[5] | 69/0 | LVCMOS33_BIDI | PR3D | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[6] | 70/0 | LVCMOS33_BIDI | PR3C | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[7] | 71/0 | LVCMOS33_BIDI | PR3B | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMCLK | 58/0 | LVCMOS33_OUT | PR7A | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMSDI | 56/0 | LVCMOS33_OUT | PR7C | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMSDO | 55/0 | LVCMOS33_IN | PR7D | SLEW:FAST PULL:UP | +| nCCAS | 27/1 | LVCMOS33_IN | PL9B | SLEW:FAST PULL:UP | +| nCRAS | 43/1 | LVCMOS33_IN | PB4A | SLEW:FAST PULL:UP | +| nFWE | 22/1 | LVCMOS33_IN | PL8B | SLEW:FAST PULL:UP | +| nRCAS | 78/0 | LVCMOS33_OUT | PT5B | DRIVE:8mA SLEW:FAST PULL:UP | +| nRCS | 77/0 | LVCMOS33_OUT | PT5C | DRIVE:8mA SLEW:FAST PULL:UP | +| nRRAS | 73/0 | LVCMOS33_OUT | PR2B | DRIVE:8mA SLEW:FAST PULL:UP | +| nRWE | 72/0 | LVCMOS33_OUT | PR3A | DRIVE:8mA SLEW:FAST PULL:UP | +| nUFMCS | 53/0 | LVCMOS33_OUT | PR8B | DRIVE:8mA SLEW:FAST PULL:UP | ++-----------+----------+---------------+------+------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 3.3V | +| 1 | 3.3V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+---------------------+------------+---------------+------+---------------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | ++----------+---------------------+------------+---------------+------+---------------+ +| 1/1 | Dout[0] | LOCATED | LVCMOS33_OUT | PL2A | | +| 2/1 | Dout[6] | LOCATED | LVCMOS33_OUT | PL2B | | +| 3/1 | Dout[7] | LOCATED | LVCMOS33_OUT | PL3A | | +| 4/1 | Dout[4] | LOCATED | LVCMOS33_OUT | PL3B | | +| 5/1 | Dout[5] | LOCATED | LVCMOS33_OUT | PL3C | | +| 6/1 | Dout[3] | LOCATED | LVCMOS33_OUT | PL3D | | +| 7/1 | Dout[1] | LOCATED | LVCMOS33_OUT | PL4A | | +| 8/1 | Dout[2] | LOCATED | LVCMOS33_OUT | PL4B | | +| 9/1 | unused, PULL:UP | | | PL5A | | +| 11/1 | unused, PULL:UP | | | PL5B | | +| 13/1 | unused, PULL:UP | | | PL5C | | +| 14/1 | Din[2] | LOCATED | LVCMOS33_IN | PL5D | GSR_PADN | +| 15/1 | Din[1] | LOCATED | LVCMOS33_IN | PL6A | | +| 16/1 | Din[3] | LOCATED | LVCMOS33_IN | PL6B | TSALLPAD | +| 17/1 | Din[5] | LOCATED | LVCMOS33_IN | PL7A | | +| 18/1 | Din[4] | LOCATED | LVCMOS33_IN | PL7B | | +| 19/1 | Din[7] | LOCATED | LVCMOS33_IN | PL7C | | +| 20/1 | Din[6] | LOCATED | LVCMOS33_IN | PL7D | | +| 21/1 | Din[0] | LOCATED | LVCMOS33_IN | PL8A | | +| 22/1 | nFWE | LOCATED | LVCMOS33_IN | PL8B | | +| 23/1 | MAin[0] | LOCATED | LVCMOS33_IN | PL9A | | +| 27/1 | nCCAS | LOCATED | LVCMOS33_IN | PL9B | | +| 29/1 | unused, PULL:UP | | | PB2A | | +| 30/1 | unused, PULL:UP | | | PB2B | | +| 32/1 | CROW[0] | LOCATED | LVCMOS33_IN | PB2C | | +| 34/1 | CROW[1] | LOCATED | LVCMOS33_IN | PB2D | | +| 36/1 | unused, PULL:UP | | | PB3A | PCLKT1_1 | +| 37/1 | MAin[2] | LOCATED | LVCMOS33_IN | PB3B | | +| 38/1 | MAin[1] | LOCATED | LVCMOS33_IN | PB3C | PCLKT1_0 | +| 39/1 | PHI2 | LOCATED | LVCMOS33_IN | PB3D | | +| 43/1 | nCRAS | LOCATED | LVCMOS33_IN | PB4A | | +| 44/1 | MAin[7] | LOCATED | LVCMOS33_IN | PB4B | | +| 45/1 | MAin[5] | LOCATED | LVCMOS33_IN | PB4C | | +| 46/1 | MAin[4] | LOCATED | LVCMOS33_IN | PB4D | | +| 47/1 | MAin[3] | LOCATED | LVCMOS33_IN | PB5A | | +| 49/1 | MAin[6] | LOCATED | LVCMOS33_IN | PB5C | | +| 50/1 | MAin[8] | LOCATED | LVCMOS33_IN | PB5D | | +| 51/0 | MAin[9] | LOCATED | LVCMOS33_IN | PR9B | | +| 52/0 | unused, PULL:UP | | | PR9A | | +| 53/0 | nUFMCS | LOCATED | LVCMOS33_OUT | PR8B | | +| 54/0 | unused, PULL:UP | | | PR8A | | +| 55/0 | UFMSDO | LOCATED | LVCMOS33_IN | PR7D | | +| 56/0 | UFMSDI | LOCATED | LVCMOS33_OUT | PR7C | | +| 57/0 | LED | LOCATED | LVCMOS33_OUT | PR7B | | +| 58/0 | UFMCLK | LOCATED | LVCMOS33_OUT | PR7A | | +| 59/0 | unused, PULL:UP | | | PR6B | | +| 61/0 | RDQML | LOCATED | LVCMOS33_OUT | PR6A | | +| 63/0 | RBA[0] | LOCATED | LVCMOS33_OUT | PR5D | | +| 64/0 | RD[0] | LOCATED | LVCMOS33_BIDI | PR5C | | +| 65/0 | RD[1] | LOCATED | LVCMOS33_BIDI | PR5B | | +| 66/0 | RD[2] | LOCATED | LVCMOS33_BIDI | PR5A | | +| 67/0 | RD[3] | LOCATED | LVCMOS33_BIDI | PR4B | | +| 68/0 | RD[4] | LOCATED | LVCMOS33_BIDI | PR4A | | +| 69/0 | RD[5] | LOCATED | LVCMOS33_BIDI | PR3D | | +| 70/0 | RD[6] | LOCATED | LVCMOS33_BIDI | PR3C | | +| 71/0 | RD[7] | LOCATED | LVCMOS33_BIDI | PR3B | | +| 72/0 | nRWE | LOCATED | LVCMOS33_OUT | PR3A | | +| 73/0 | nRRAS | LOCATED | LVCMOS33_OUT | PR2B | | +| 76/0 | RDQMH | LOCATED | LVCMOS33_OUT | PR2A | | +| 77/0 | nRCS | LOCATED | LVCMOS33_OUT | PT5C | | +| 78/0 | nRCAS | LOCATED | LVCMOS33_OUT | PT5B | | +| 79/0 | RA[11] | LOCATED | LVCMOS33_OUT | PT5A | | +| 80/0 | unused, PULL:UP | | | PT4F | | +| 81/0 | unused, PULL:UP | | | PT4E | | +| 82/0 | RCKE | LOCATED | LVCMOS33_OUT | PT4D | | +| 83/0 | RBA[1] | LOCATED | LVCMOS33_OUT | PT4C | | +| 85/0 | RA[9] | LOCATED | LVCMOS33_OUT | PT4B | PCLKT0_1 | +| 86/0 | RCLK | LOCATED | LVCMOS33_IN | PT4A | PCLKT0_0 | +| 87/0 | RA[10] | LOCATED | LVCMOS33_OUT | PT3D | | +| 89/0 | RA[1] | LOCATED | LVCMOS33_OUT | PT3C | | +| 91/0 | RA[6] | LOCATED | LVCMOS33_OUT | PT3B | | +| 94/0 | RA[2] | LOCATED | LVCMOS33_OUT | PT3A | | +| 95/0 | RA[5] | LOCATED | LVCMOS33_OUT | PT2F | | +| 96/0 | RA[8] | LOCATED | LVCMOS33_OUT | PT2E | | +| 97/0 | RA[3] | LOCATED | LVCMOS33_OUT | PT2D | | +| 98/0 | RA[0] | LOCATED | LVCMOS33_OUT | PT2C | | +| 99/0 | RA[4] | LOCATED | LVCMOS33_OUT | PT2B | | +| 100/0 | RA[7] | LOCATED | LVCMOS33_OUT | PT2A | | +| PB5B/0 | unused, PULL:UP | | | PB5B | | +| PT5D/0 | unused, PULL:UP | | | PT5D | | +| TCK/1 | | | | TCK | TCK | +| TDI/1 | | | | TDI | TDI | +| TDO/1 | | | | TDO | TDO | +| TMS/1 | | | | TMS | TMS | ++----------+---------------------+------------+---------------+------+---------------+ + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "32"; +LOCATE COMP "CROW[1]" SITE "34"; +LOCATE COMP "Din[0]" SITE "21"; +LOCATE COMP "Din[1]" SITE "15"; +LOCATE COMP "Din[2]" SITE "14"; +LOCATE COMP "Din[3]" SITE "16"; +LOCATE COMP "Din[4]" SITE "18"; +LOCATE COMP "Din[5]" SITE "17"; +LOCATE COMP "Din[6]" SITE "20"; +LOCATE COMP "Din[7]" SITE "19"; +LOCATE COMP "Dout[0]" SITE "1"; +LOCATE COMP "Dout[1]" SITE "7"; +LOCATE COMP "Dout[2]" SITE "8"; +LOCATE COMP "Dout[3]" SITE "6"; +LOCATE COMP "Dout[4]" SITE "4"; +LOCATE COMP "Dout[5]" SITE "5"; +LOCATE COMP "Dout[6]" SITE "2"; +LOCATE COMP "Dout[7]" SITE "3"; +LOCATE COMP "LED" SITE "57"; +LOCATE COMP "MAin[0]" SITE "23"; +LOCATE COMP "MAin[1]" SITE "38"; +LOCATE COMP "MAin[2]" SITE "37"; +LOCATE COMP "MAin[3]" SITE "47"; +LOCATE COMP "MAin[4]" SITE "46"; +LOCATE COMP "MAin[5]" SITE "45"; +LOCATE COMP "MAin[6]" SITE "49"; +LOCATE COMP "MAin[7]" SITE "44"; +LOCATE COMP "MAin[8]" SITE "50"; +LOCATE COMP "MAin[9]" SITE "51"; +LOCATE COMP "PHI2" SITE "39"; +LOCATE COMP "RA[0]" SITE "98"; +LOCATE COMP "RA[10]" SITE "87"; +LOCATE COMP "RA[11]" SITE "79"; +LOCATE COMP "RA[1]" SITE "89"; +LOCATE COMP "RA[2]" SITE "94"; +LOCATE COMP "RA[3]" SITE "97"; +LOCATE COMP "RA[4]" SITE "99"; +LOCATE COMP "RA[5]" SITE "95"; +LOCATE COMP "RA[6]" SITE "91"; +LOCATE COMP "RA[7]" SITE "100"; +LOCATE COMP "RA[8]" SITE "96"; +LOCATE COMP "RA[9]" SITE "85"; +LOCATE COMP "RBA[0]" SITE "63"; +LOCATE COMP "RBA[1]" SITE "83"; +LOCATE COMP "RCKE" SITE "82"; +LOCATE COMP "RCLK" SITE "86"; +LOCATE COMP "RDQMH" SITE "76"; +LOCATE COMP "RDQML" SITE "61"; +LOCATE COMP "RD[0]" SITE "64"; +LOCATE COMP "RD[1]" SITE "65"; +LOCATE COMP "RD[2]" SITE "66"; +LOCATE COMP "RD[3]" SITE "67"; +LOCATE COMP "RD[4]" SITE "68"; +LOCATE COMP "RD[5]" SITE "69"; +LOCATE COMP "RD[6]" SITE "70"; +LOCATE COMP "RD[7]" SITE "71"; +LOCATE COMP "UFMCLK" SITE "58"; +LOCATE COMP "UFMSDI" SITE "56"; +LOCATE COMP "UFMSDO" SITE "55"; +LOCATE COMP "nCCAS" SITE "27"; +LOCATE COMP "nCRAS" SITE "43"; +LOCATE COMP "nFWE" SITE "22"; +LOCATE COMP "nRCAS" SITE "78"; +LOCATE COMP "nRCS" SITE "77"; +LOCATE COMP "nRRAS" SITE "73"; +LOCATE COMP "nRWE" SITE "72"; +LOCATE COMP "nUFMCS" SITE "53"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:28 2023 + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par new file mode 100644 index 0000000..e40d29a --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.par @@ -0,0 +1,263 @@ +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:23 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t +RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir +RAM2GS_LCMXO256C_impl1.prf -gui -msgset +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml + + +Preference file: RAM2GS_LCMXO256C_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 -10.044 913247 0.273 0 06 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 6 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd" +Tue Aug 15 05:03:23 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf +Preference file: RAM2GS_LCMXO256C_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67/79 84% used + 67/78 85% bonded + SLICE 71/128 55% used + + + +Number of Signals: 262 +Number of Connections: 662 + +Pin Constraint Summary: + 67 out of 67 pins locked (100% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +........ +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +.............. +Placer score = 831129. +Finished Placer Phase 1. REAL time: 5 secs + +Starting Placer Phase 2. +. +Placer score = 828350 +Finished Placer Phase 2. REAL time: 5 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 1 out of 4 (25%) + General PIO: 1 out of 80 (1%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 4 (50%) + SECONDARY: 1 out of 4 (25%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 out of 79 (84.8%) PIO sites used. + 67 out of 78 (85.9%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+------------+------------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | ++----------+----------------+------------+------------+------------+ +| 0 | 36 / 41 ( 87%) | 3.3V | - | - | +| 1 | 31 / 37 ( 83%) | 3.3V | - | - | ++----------+----------------+------------+------------+------------+ + +Total placer CPU time: 4 secs + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + +0 connections routed; 662 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. +WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks. This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew. + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=7 clock_loads=4 + +Completed router resource preassignment. Real time: 5 secs + +Start NBR router at 05:03:28 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:28 08/15/23 + +Start NBR section for initial routing at 05:03:28 08/15/23 +Level 1, iteration 1 +0(0.00%) conflict; 563(85.05%) untouched conns; 712361 (nbr) score; +Estimated worst slack/total negative slack: -9.968ns/-712.361ns; real time: 5 secs +Level 2, iteration 1 +3(0.02%) conflicts; 494(74.62%) untouched conns; 697746 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-697.746ns; real time: 5 secs +Level 3, iteration 1 +6(0.05%) conflicts; 255(38.52%) untouched conns; 756550 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-756.550ns; real time: 5 secs +Level 4, iteration 1 +17(0.14%) conflicts; 0(0.00%) untouched conn; 761255 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-761.256ns; real time: 5 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:28 08/15/23 +Level 4, iteration 1 +12(0.10%) conflicts; 0(0.00%) untouched conn; 765605 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-765.606ns; real time: 5 secs +Level 4, iteration 2 +6(0.05%) conflicts; 0(0.00%) untouched conn; 766423 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.424ns; real time: 5 secs +Level 4, iteration 3 +3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs +Level 4, iteration 4 +3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs +Level 4, iteration 5 +3(0.02%) conflicts; 0(0.00%) untouched conn; 766523 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs +Level 4, iteration 6 +1(0.01%) conflict; 0(0.00%) untouched conn; 766523 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs +Level 4, iteration 7 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 8 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 9 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 10 +0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs + +Start NBR section for re-routing at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 768048 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-768.049ns; real time: 6 secs + +Start NBR section for post-routing at 05:03:29 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 256 (38.67%) + Estimated worst slack : -10.044ns + Timing score : 913247 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=7 clock_loads=4 + +Total CPU time 5 secs +Total REAL time: 6 secs +Completely routed. +End of route. 662 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 913247 + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -10.044 +PAR_SUMMARY::Timing score> = 913.247 +PAR_SUMMARY::Worst slack> = 0.273 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 5 secs +Total REAL time to completion: 6 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf new file mode 100644 index 0000000..881ee9b --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.prf @@ -0,0 +1,81 @@ +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:20 2023 + +SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ; +LOCATE COMP "RD[7]" SITE "71" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "MAin[9]" SITE "51" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "UFMSDO" SITE "55" ; +SCHEMATIC END ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +COMMERCIAL ; + +// No timing preferences found. TRCE invokes auto-generation of timing preferences +// Section Autogen +FREQUENCY NET "RCLK_c" 283.768 MHz ; +FREQUENCY NET "PHI2_c" 120.077 MHz ; +// End Section Autogen diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt new file mode 100644 index 0000000..916dbc3 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.pt @@ -0,0 +1,10 @@ +-v +10 + + + + +-gt +-sethld +-sp 3 +-sphld m diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.t2b b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.t2b new file mode 100644 index 0000000..aa05f83 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.t2b @@ -0,0 +1,2 @@ + +-g ES:No diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 new file mode 100644 index 0000000..2cd86e2 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.tw1 @@ -0,0 +1,353 @@ + +Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:21 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1_map.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,3 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + 383 items scored, 213 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 5.089ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i14 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 8.369ns (24.4% logic, 75.6% route), 5 logic levels. + + Constraint Details: + + 8.369ns physical path delay SLICE_1 to SLICE_56 exceeds + 3.524ns delay constraint less + 0.244ns CE_SET requirement (totaling 3.280ns) by 5.089ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_56: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_1.CLK to SLICE_1.Q0 SLICE_1 (from RCLK_c) +ROUTE 5 e 1.441 SLICE_1.Q0 to SLICE_90.C1 FS_14 +CTOF_DEL --- 0.371 SLICE_90.C1 to SLICE_90.F1 SLICE_90 +ROUTE 1 e 1.441 SLICE_90.F1 to SLICE_75.B0 n2328 +CTOF_DEL --- 0.371 SLICE_75.B0 to SLICE_75.F0 SLICE_75 +ROUTE 2 e 1.441 SLICE_75.F0 to SLICE_87.B1 n2214 +CTOF_DEL --- 0.371 SLICE_87.B1 to SLICE_87.F1 SLICE_87 +ROUTE 1 e 0.561 SLICE_87.F1 to SLICE_87.A0 n7 +CTOF_DEL --- 0.371 SLICE_87.A0 to SLICE_87.F0 SLICE_87 +ROUTE 1 e 1.441 SLICE_87.F0 to SLICE_56.CE RCLK_c_enable_11 (to RCLK_c) + -------- + 8.369 (24.4% logic, 75.6% route), 5 logic levels. + +Warning: 116.104MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + 106 items scored, 97 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 7.535ns (weighted slack = -15.070ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 11.061ns (21.8% logic, 78.2% route), 6 logic levels. + + Constraint Details: + + 11.061ns physical path delay SLICE_88 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.638ns LSR_SET requirement (totaling 3.526ns) by 7.535ns + + Physical Path Details: + + Data path SLICE_88 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_88.CLK to SLICE_88.Q0 SLICE_88 (from PHI2_c) +ROUTE 1 e 1.441 SLICE_88.Q0 to SLICE_97.D0 Bank_0 +CTOF_DEL --- 0.371 SLICE_97.D0 to SLICE_97.F0 SLICE_97 +ROUTE 1 e 1.441 SLICE_97.F0 to SLICE_81.B0 n2314 +CTOF_DEL --- 0.371 SLICE_81.B0 to SLICE_81.F0 SLICE_81 +ROUTE 1 e 1.441 SLICE_81.F0 to SLICE_18.B1 n26 +CTOF_DEL --- 0.371 SLICE_18.B1 to SLICE_18.F1 SLICE_18 +ROUTE 8 e 1.441 SLICE_18.F1 to SLICE_89.B0 n1326 +CTOF_DEL --- 0.371 SLICE_89.B0 to SLICE_89.F0 SLICE_89 +ROUTE 1 e 1.441 SLICE_89.F0 to SLICE_79.C0 n1280 +CTOF_DEL --- 0.371 SLICE_79.C0 to SLICE_79.F0 SLICE_79 +ROUTE 2 e 1.441 SLICE_79.F0 to SLICE_14.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 11.061 (21.8% logic, 78.2% route), 6 logic levels. + +Warning: 42.739MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 283.768 MHz| 116.104 MHz| 5 * + | | | +FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 120.077 MHz| 42.739 MHz| 6 * + | | | +---------------------------------------------------------------------------- + + +2 preferences(marked by "*" above) not met. + +---------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +---------------------------------------------------------------------------- +n1326 | 8| 96| 30.97% + | | | +n26 | 1| 72| 23.23% + | | | +---------------------------------------------------------------------------- + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 310 Score: 1346529 +Cumulative negative slack: 874289 + +Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:21 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1_map.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + 383 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.342ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i4 (from RCLK_c +) + Destination: FF Data in IS_FSM__i5 (to RCLK_c +) + + Delay: 0.325ns (38.8% logic, 61.2% route), 1 logic levels. + + Constraint Details: + + 0.325ns physical path delay SLICE_100 to SLICE_100 meets + -0.017ns M_HLD and + 0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns + + Physical Path Details: + + Data path SLICE_100 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 SLICE_100.CLK to SLICE_100.Q0 SLICE_100 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_100.Q0 to SLICE_100.M1 n736 (to RCLK_c) + -------- + 0.325 (38.8% logic, 61.2% route), 1 logic levels. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + 106 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.430ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.411ns (51.3% logic, 48.7% route), 2 logic levels. + + Constraint Details: + + 0.411ns physical path delay SLICE_14 to SLICE_14 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint requirement (totaling -0.019ns) by 0.430ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 SLICE_14.CLK to SLICE_14.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 e 0.199 SLICE_14.Q0 to SLICE_14.C0 C1Submitted +CTOF_DEL --- 0.074 SLICE_14.C0 to SLICE_14.F0 SLICE_14 +ROUTE 1 e 0.001 SLICE_14.F0 to SLICE_14.DI0 n6_adj_3 (to PHI2_c) + -------- + 0.411 (51.3% logic, 48.7% route), 2 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 0.000 ns| 0.342 ns| 1 + | | | +FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 0.000 ns| 0.430 ns| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 310 (setup), 0 (hold) +Score: 1346529 (setup), 0 (hold) +Cumulative negative slack: 874289 (874289+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr new file mode 100644 index 0000000..5fca6c6 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.twr @@ -0,0 +1,2170 @@ + +Loading design for application trce from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:29 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,3 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + 383 items scored, 231 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 4.182ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i17 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 7.525ns (27.2% logic, 72.8% route), 5 logic levels. + + Constraint Details: + + 7.525ns physical path delay SLICE_8 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 4.182ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C5A.CLK to R5C5A.Q1 SLICE_8 (from RCLK_c) +ROUTE 4 1.509 R5C5A.Q1 to R6C4C.A1 FS_17 +CTOF_DEL --- 0.371 R6C4C.A1 to R6C4C.F1 SLICE_68 +ROUTE 2 1.503 R6C4C.F1 to R7C5B.A1 n2471 +CTOF_DEL --- 0.371 R7C5B.A1 to R7C5B.F1 SLICE_44 +ROUTE 2 1.972 R7C5B.F1 to R3C2B.C1 n2462 +CTOF_DEL --- 0.371 R3C2B.C1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 7.525 (27.2% logic, 72.8% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C5A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.947ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i16 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 7.290ns (28.0% logic, 72.0% route), 5 logic levels. + + Constraint Details: + + 7.290ns physical path delay SLICE_8 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 3.947ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C5A.CLK to R5C5A.Q0 SLICE_8 (from RCLK_c) +ROUTE 5 1.526 R5C5A.Q0 to R5C2D.A0 FS_16 +CTOF_DEL --- 0.371 R5C2D.A0 to R5C2D.F0 SLICE_90 +ROUTE 1 1.251 R5C2D.F0 to R7C5B.D1 n2470 +CTOF_DEL --- 0.371 R7C5B.D1 to R7C5B.F1 SLICE_44 +ROUTE 2 1.972 R7C5B.F1 to R3C2B.C1 n2462 +CTOF_DEL --- 0.371 R3C2B.C1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 7.290 (28.0% logic, 72.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C5A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.864ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 7.144ns (28.6% logic, 71.4% route), 5 logic levels. + + Constraint Details: + + 7.144ns physical path delay SLICE_3 to SLICE_56 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 3.280ns) by 3.864ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_56: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C4C.CLK to R5C4C.Q0 SLICE_3 (from RCLK_c) +ROUTE 4 2.038 R5C4C.Q0 to R5C2D.B1 FS_12 +CTOF_DEL --- 0.371 R5C2D.B1 to R5C2D.F1 SLICE_90 +ROUTE 1 0.887 R5C2D.F1 to R4C2D.C0 n2328 +CTOF_DEL --- 0.371 R4C2D.C0 to R4C2D.F0 SLICE_75 +ROUTE 2 0.513 R4C2D.F0 to R4C2C.C1 n2214 +CTOF_DEL --- 0.371 R4C2C.C1 to R4C2C.F1 SLICE_87 +ROUTE 1 0.497 R4C2C.F1 to R4C2C.C0 n7 +CTOF_DEL --- 0.371 R4C2C.C0 to R4C2C.F0 SLICE_87 +ROUTE 1 1.165 R4C2C.F0 to R6C2C.CE RCLK_c_enable_11 (to RCLK_c) + -------- + 7.144 (28.6% logic, 71.4% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_56: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R6C2C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.702ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i13 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 7.045ns (29.0% logic, 71.0% route), 5 logic levels. + + Constraint Details: + + 7.045ns physical path delay SLICE_3 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 3.702ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C4C.CLK to R5C4C.Q1 SLICE_3 (from RCLK_c) +ROUTE 3 1.057 R5C4C.Q1 to R5C2B.A1 FS_13 +CTOF_DEL --- 0.371 R5C2B.A1 to R5C2B.F1 SLICE_94 +ROUTE 3 1.475 R5C2B.F1 to R7C5B.C1 n2272 +CTOF_DEL --- 0.371 R7C5B.C1 to R7C5B.F1 SLICE_44 +ROUTE 2 1.972 R7C5B.F1 to R3C2B.C1 n2462 +CTOF_DEL --- 0.371 R3C2B.C1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 7.045 (29.0% logic, 71.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.669ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i11 (from RCLK_c +) + Destination: FF Data in InitReady_394 (to RCLK_c +) + + Delay: 6.949ns (24.1% logic, 75.9% route), 4 logic levels. + + Constraint Details: + + 6.949ns physical path delay SLICE_5 to SLICE_25 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 3.280ns) by 3.669ns + + Physical Path Details: + + Data path SLICE_5 to SLICE_25: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C4B.CLK to R5C4B.Q1 SLICE_5 (from RCLK_c) +ROUTE 8 1.895 R5C4B.Q1 to R5C2B.C0 FS_11 +CTOF_DEL --- 0.371 R5C2B.C0 to R5C2B.F0 SLICE_94 +ROUTE 1 0.694 R5C2B.F0 to R3C2A.D1 n12 +CTOF_DEL --- 0.371 R3C2A.D1 to R3C2A.F1 SLICE_69 +ROUTE 3 1.057 R3C2A.F1 to R5C2C.A1 n62 +CTOF_DEL --- 0.371 R5C2C.A1 to R5C2C.F1 SLICE_95 +ROUTE 1 1.630 R5C2C.F1 to R6C2A.CE RCLK_c_enable_25 (to RCLK_c) + -------- + 6.949 (24.1% logic, 75.9% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_5: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C4B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_25: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R6C2A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.582ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 6.925ns (29.5% logic, 70.5% route), 5 logic levels. + + Constraint Details: + + 6.925ns physical path delay SLICE_3 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 3.582ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C4C.CLK to R5C4C.Q0 SLICE_3 (from RCLK_c) +ROUTE 4 0.909 R5C4C.Q0 to R6C4C.C1 FS_12 +CTOF_DEL --- 0.371 R6C4C.C1 to R6C4C.F1 SLICE_68 +ROUTE 2 1.503 R6C4C.F1 to R7C5B.A1 n2471 +CTOF_DEL --- 0.371 R7C5B.A1 to R7C5B.F1 SLICE_44 +ROUTE 2 1.972 R7C5B.F1 to R3C2B.C1 n2462 +CTOF_DEL --- 0.371 R3C2B.C1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 6.925 (29.5% logic, 70.5% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.567ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CASr3_384 (from RCLK_c +) + Destination: FF Data in nRCS_396 (to RCLK_c +) + + Delay: 6.910ns (31.5% logic, 68.5% route), 5 logic levels. + + Constraint Details: + + 6.910ns physical path delay SLICE_68 to SLICE_60 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 3.567ns + + Physical Path Details: + + Data path SLICE_68 to SLICE_60: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R6C4C.CLK to R6C4C.Q1 SLICE_68 (from RCLK_c) +ROUTE 2 1.364 R6C4C.Q1 to R8C5C.C0 CASr3 +CTOF_DEL --- 0.371 R8C5C.C0 to R8C5C.F0 SLICE_74 +ROUTE 2 0.513 R8C5C.F0 to R8C5C.C1 n1 +CTOF_DEL --- 0.371 R8C5C.C1 to R8C5C.F1 SLICE_74 +ROUTE 2 1.276 R8C5C.F1 to R8C4D.M0 n15_adj_1 +MTOOFX_DEL --- 0.501 R8C4D.M0 to R8C4D.OFX0 i2099/SLICE_72 +ROUTE 1 1.583 R8C4D.OFX0 to R2C5B.A0 n2481 +CTOF_DEL --- 0.371 R2C5B.A0 to R2C5B.F0 SLICE_60 +ROUTE 1 0.000 R2C5B.F0 to R2C5B.DI0 nRCS_N_136 (to RCLK_c) + -------- + 6.910 (31.5% logic, 68.5% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_68: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R6C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_60: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R2C5B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.552ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in LEDEN_419 (to RCLK_c +) + + Delay: 6.832ns (24.5% logic, 75.5% route), 4 logic levels. + + Constraint Details: + + 6.832ns physical path delay SLICE_3 to SLICE_26 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 3.280ns) by 3.552ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_26: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C4C.CLK to R5C4C.Q0 SLICE_3 (from RCLK_c) +ROUTE 4 2.038 R5C4C.Q0 to R5C2D.B1 FS_12 +CTOF_DEL --- 0.371 R5C2D.B1 to R5C2D.F1 SLICE_90 +ROUTE 1 0.887 R5C2D.F1 to R4C2D.C0 n2328 +CTOF_DEL --- 0.371 R4C2D.C0 to R4C2D.F0 SLICE_75 +ROUTE 2 0.513 R4C2D.F0 to R4C2D.C1 n2214 +CTOF_DEL --- 0.371 R4C2D.C1 to R4C2D.F1 SLICE_75 +ROUTE 1 1.721 R4C2D.F1 to R7C5A.CE RCLK_c_enable_12 (to RCLK_c) + -------- + 6.832 (24.5% logic, 75.5% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C4C.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_26: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R7C5A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.405ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i17 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 6.303ns (26.5% logic, 73.5% route), 4 logic levels. + + Constraint Details: + + 6.303ns physical path delay SLICE_8 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.626ns LSR_SET requirement (totaling 2.898ns) by 3.405ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C5A.CLK to R5C5A.Q1 SLICE_8 (from RCLK_c) +ROUTE 4 1.509 R5C5A.Q1 to R6C4C.A1 FS_17 +CTOF_DEL --- 0.371 R6C4C.A1 to R6C4C.F1 SLICE_68 +ROUTE 2 1.042 R6C4C.F1 to R6C2D.A1 n2471 +CTOF_DEL --- 0.371 R6C2D.A1 to R6C2D.F1 SLICE_78 +ROUTE 3 0.528 R6C2D.F1 to R6C2D.C0 n2464 +CTOF_DEL --- 0.371 R6C2D.C0 to R6C2D.F0 SLICE_78 +ROUTE 2 1.551 R6C2D.F0 to R3C2B.LSR n1846 (to RCLK_c) + -------- + 6.303 (26.5% logic, 73.5% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C5A.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 3.361ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 6.704ns (30.5% logic, 69.5% route), 5 logic levels. + + Constraint Details: + + 6.704ns physical path delay SLICE_1 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 3.361ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R5C4D.CLK to R5C4D.Q1 SLICE_1 (from RCLK_c) +ROUTE 3 0.716 R5C4D.Q1 to R5C2B.D1 FS_15 +CTOF_DEL --- 0.371 R5C2B.D1 to R5C2B.F1 SLICE_94 +ROUTE 3 1.475 R5C2B.F1 to R7C5B.C1 n2272 +CTOF_DEL --- 0.371 R7C5B.C1 to R7C5B.F1 SLICE_44 +ROUTE 2 1.972 R7C5B.F1 to R3C2B.C1 n2462 +CTOF_DEL --- 0.371 R3C2B.C1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 6.704 (30.5% logic, 69.5% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R5C4D.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.353 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.353 (0.0% logic, 100.0% route), 0 logic levels. + +Warning: 129.769MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + 106 items scored, 95 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 5.022ns (weighted slack = -10.044ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 8.548ns (28.3% logic, 71.7% route), 6 logic levels. + + Constraint Details: + + 8.548ns physical path delay SLICE_88 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 5.022ns + + Physical Path Details: + + Data path SLICE_88 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R4C3D.CLK to R4C3D.Q0 SLICE_88 (from PHI2_c) +ROUTE 1 1.155 R4C3D.Q0 to R2C2A.D0 Bank_0 +CTOF_DEL --- 0.371 R2C2A.D0 to R2C2A.F0 SLICE_97 +ROUTE 1 1.348 R2C2A.F0 to R4C4A.C0 n2314 +CTOF_DEL --- 0.371 R4C4A.C0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 1.225 R4C4D.F1 to R5C5B.D0 n1326 +CTOF_DEL --- 0.371 R5C5B.D0 to R5C5B.F0 SLICE_89 +ROUTE 1 0.700 R5C5B.F0 to R6C5C.D0 n1280 +CTOF_DEL --- 0.371 R6C5C.D0 to R6C5C.F0 SLICE_79 +ROUTE 2 1.079 R6C5C.F0 to R5C5D.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 8.548 (28.3% logic, 71.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C3D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C5D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 5.022ns (weighted slack = -10.044ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 8.548ns (28.3% logic, 71.7% route), 6 logic levels. + + Constraint Details: + + 8.548ns physical path delay SLICE_88 to SLICE_9 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 5.022ns + + Physical Path Details: + + Data path SLICE_88 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R4C3D.CLK to R4C3D.Q0 SLICE_88 (from PHI2_c) +ROUTE 1 1.155 R4C3D.Q0 to R2C2A.D0 Bank_0 +CTOF_DEL --- 0.371 R2C2A.D0 to R2C2A.F0 SLICE_97 +ROUTE 1 1.348 R2C2A.F0 to R4C4A.C0 n2314 +CTOF_DEL --- 0.371 R4C4A.C0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 1.225 R4C4D.F1 to R5C5B.D0 n1326 +CTOF_DEL --- 0.371 R5C5B.D0 to R5C5B.F0 SLICE_89 +ROUTE 1 0.700 R5C5B.F0 to R6C5C.D0 n1280 +CTOF_DEL --- 0.371 R6C5C.D0 to R6C5C.F0 SLICE_79 +ROUTE 2 1.079 R6C5C.F0 to R4C5D.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 8.548 (28.3% logic, 71.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C3D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C5D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.893ns (weighted slack = -9.786ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 8.419ns (28.7% logic, 71.3% route), 6 logic levels. + + Constraint Details: + + 8.419ns physical path delay SLICE_99 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.893ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 1.026 R2C4C.Q1 to R2C2A.A0 Bank_7 +CTOF_DEL --- 0.371 R2C2A.A0 to R2C2A.F0 SLICE_97 +ROUTE 1 1.348 R2C2A.F0 to R4C4A.C0 n2314 +CTOF_DEL --- 0.371 R4C4A.C0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 1.225 R4C4D.F1 to R5C5B.D0 n1326 +CTOF_DEL --- 0.371 R5C5B.D0 to R5C5B.F0 SLICE_89 +ROUTE 1 0.700 R5C5B.F0 to R6C5C.D0 n1280 +CTOF_DEL --- 0.371 R6C5C.D0 to R6C5C.F0 SLICE_79 +ROUTE 2 1.079 R6C5C.F0 to R5C5D.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 8.419 (28.7% logic, 71.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C5D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.893ns (weighted slack = -9.786ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 8.419ns (28.7% logic, 71.3% route), 6 logic levels. + + Constraint Details: + + 8.419ns physical path delay SLICE_99 to SLICE_9 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.893ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 1.026 R2C4C.Q1 to R2C2A.A0 Bank_7 +CTOF_DEL --- 0.371 R2C2A.A0 to R2C2A.F0 SLICE_97 +ROUTE 1 1.348 R2C2A.F0 to R4C4A.C0 n2314 +CTOF_DEL --- 0.371 R4C4A.C0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 1.225 R4C4D.F1 to R5C5B.D0 n1326 +CTOF_DEL --- 0.371 R5C5B.D0 to R5C5B.F0 SLICE_89 +ROUTE 1 0.700 R5C5B.F0 to R6C5C.D0 n1280 +CTOF_DEL --- 0.371 R6C5C.D0 to R6C5C.F0 SLICE_79 +ROUTE 2 1.079 R6C5C.F0 to R4C5D.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 8.419 (28.7% logic, 71.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C5D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.392ns (weighted slack = -8.784ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) + FF CmdUFMCLK_413 + + Delay: 8.291ns (29.1% logic, 70.9% route), 6 logic levels. + + Constraint Details: + + 8.291ns physical path delay SLICE_88 to SLICE_81 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.392ns + + Physical Path Details: + + Data path SLICE_88 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R4C3D.CLK to R4C3D.Q0 SLICE_88 (from PHI2_c) +ROUTE 1 1.155 R4C3D.Q0 to R2C2A.D0 Bank_0 +CTOF_DEL --- 0.371 R2C2A.D0 to R2C2A.F0 SLICE_97 +ROUTE 1 1.348 R2C2A.F0 to R4C4A.C0 n2314 +CTOF_DEL --- 0.371 R4C4A.C0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 0.755 R4C4D.F1 to R4C3A.D0 n1326 +CTOF_DEL --- 0.371 R4C3A.D0 to R4C3A.F0 SLICE_82 +ROUTE 2 0.903 R4C3A.F0 to R4C5C.C1 n2460 +CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 SLICE_83 +ROUTE 2 1.089 R4C5C.F1 to R4C4A.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 8.291 (29.1% logic, 70.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C3D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C4A.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.392ns (weighted slack = -8.784ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) + + Delay: 8.291ns (29.1% logic, 70.9% route), 6 logic levels. + + Constraint Details: + + 8.291ns physical path delay SLICE_88 to SLICE_93 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.392ns + + Physical Path Details: + + Data path SLICE_88 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R4C3D.CLK to R4C3D.Q0 SLICE_88 (from PHI2_c) +ROUTE 1 1.155 R4C3D.Q0 to R2C2A.D0 Bank_0 +CTOF_DEL --- 0.371 R2C2A.D0 to R2C2A.F0 SLICE_97 +ROUTE 1 1.348 R2C2A.F0 to R4C4A.C0 n2314 +CTOF_DEL --- 0.371 R4C4A.C0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 0.755 R4C4D.F1 to R4C3A.D0 n1326 +CTOF_DEL --- 0.371 R4C3A.D0 to R4C3A.F0 SLICE_82 +ROUTE 2 0.903 R4C3A.F0 to R4C5C.C1 n2460 +CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 SLICE_83 +ROUTE 2 1.089 R4C5C.F1 to R3C5A.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 8.291 (29.1% logic, 70.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C3D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R3C5A.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.263ns (weighted slack = -8.526ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) + FF CmdUFMCLK_413 + + Delay: 8.162ns (29.6% logic, 70.4% route), 6 logic levels. + + Constraint Details: + + 8.162ns physical path delay SLICE_99 to SLICE_81 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.263ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 1.026 R2C4C.Q1 to R2C2A.A0 Bank_7 +CTOF_DEL --- 0.371 R2C2A.A0 to R2C2A.F0 SLICE_97 +ROUTE 1 1.348 R2C2A.F0 to R4C4A.C0 n2314 +CTOF_DEL --- 0.371 R4C4A.C0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 0.755 R4C4D.F1 to R4C3A.D0 n1326 +CTOF_DEL --- 0.371 R4C3A.D0 to R4C3A.F0 SLICE_82 +ROUTE 2 0.903 R4C3A.F0 to R4C5C.C1 n2460 +CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 SLICE_83 +ROUTE 2 1.089 R4C5C.F1 to R4C4A.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 8.162 (29.6% logic, 70.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C4A.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.263ns (weighted slack = -8.526ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) + + Delay: 8.162ns (29.6% logic, 70.4% route), 6 logic levels. + + Constraint Details: + + 8.162ns physical path delay SLICE_99 to SLICE_93 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.263ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 1.026 R2C4C.Q1 to R2C2A.A0 Bank_7 +CTOF_DEL --- 0.371 R2C2A.A0 to R2C2A.F0 SLICE_97 +ROUTE 1 1.348 R2C2A.F0 to R4C4A.C0 n2314 +CTOF_DEL --- 0.371 R4C4A.C0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 0.755 R4C4D.F1 to R4C3A.D0 n1326 +CTOF_DEL --- 0.371 R4C3A.D0 to R4C3A.F0 SLICE_82 +ROUTE 2 0.903 R4C3A.F0 to R4C5C.C1 n2460 +CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 SLICE_83 +ROUTE 2 1.089 R4C5C.F1 to R3C5A.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 8.162 (29.6% logic, 70.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R3C5A.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.241ns (weighted slack = -8.482ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 7.767ns (31.1% logic, 68.9% route), 6 logic levels. + + Constraint Details: + + 7.767ns physical path delay SLICE_99 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.241ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 SLICE_99 (from PHI2_c) +ROUTE 1 1.026 R2C4C.Q0 to R4C4A.A1 Bank_6 +CTOF_DEL --- 0.371 R4C4A.A1 to R4C4A.F1 SLICE_81 +ROUTE 1 0.696 R4C4A.F1 to R4C4A.B0 n2278 +CTOF_DEL --- 0.371 R4C4A.B0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 1.225 R4C4D.F1 to R5C5B.D0 n1326 +CTOF_DEL --- 0.371 R5C5B.D0 to R5C5B.F0 SLICE_89 +ROUTE 1 0.700 R5C5B.F0 to R6C5C.D0 n1280 +CTOF_DEL --- 0.371 R6C5C.D0 to R6C5C.F0 SLICE_79 +ROUTE 2 1.079 R6C5C.F0 to R5C5D.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 7.767 (31.1% logic, 68.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R5C5D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.241ns (weighted slack = -8.482ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 7.767ns (31.1% logic, 68.9% route), 6 logic levels. + + Constraint Details: + + 7.767ns physical path delay SLICE_99 to SLICE_9 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.241ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C4C.CLK to R2C4C.Q0 SLICE_99 (from PHI2_c) +ROUTE 1 1.026 R2C4C.Q0 to R4C4A.A1 Bank_6 +CTOF_DEL --- 0.371 R4C4A.A1 to R4C4A.F1 SLICE_81 +ROUTE 1 0.696 R4C4A.F1 to R4C4A.B0 n2278 +CTOF_DEL --- 0.371 R4C4A.B0 to R4C4A.F0 SLICE_81 +ROUTE 1 0.626 R4C4A.F0 to R4C4D.D1 n26 +CTOF_DEL --- 0.371 R4C4D.D1 to R4C4D.F1 SLICE_18 +ROUTE 8 1.225 R4C4D.F1 to R5C5B.D0 n1326 +CTOF_DEL --- 0.371 R5C5B.D0 to R5C5B.F0 SLICE_89 +ROUTE 1 0.700 R5C5B.F0 to R6C5C.D0 n1280 +CTOF_DEL --- 0.371 R6C5C.D0 to R6C5C.F0 SLICE_79 +ROUTE 2 1.079 R6C5C.F0 to R4C5D.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 7.767 (31.1% logic, 68.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R2C4C.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.911 39.PADDI to R4C5D.CLK PHI2_c + -------- + 3.911 (0.0% logic, 100.0% route), 0 logic levels. + +Warning: 54.431MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 283.768 MHz| 129.769 MHz| 5 * + | | | +FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 120.077 MHz| 54.431 MHz| 6 * + | | | +---------------------------------------------------------------------------- + + +2 preferences(marked by "*" above) not met. + +---------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +---------------------------------------------------------------------------- +n1326 | 8| 95| 29.14% + | | | +n26 | 1| 71| 21.78% + | | | +---------------------------------------------------------------------------- + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 326 Score: 913247 +Cumulative negative slack: 638389 + +Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:29 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + 383 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i4 (from RCLK_c +) + Destination: FF Data in IS_FSM__i5 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_100 to SLICE_100 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_100 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R6C2B.CLK to R6C2B.Q0 SLICE_100 (from RCLK_c) +ROUTE 1 0.130 R6C2B.Q0 to R6C2B.M1 n736 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_100: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R6C2B.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_100: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R6C2B.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i8 (from RCLK_c +) + Destination: FF Data in IS_FSM__i9 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_76 to SLICE_76 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_76 to SLICE_76: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R4C4B.CLK to R4C4B.Q0 SLICE_76 (from RCLK_c) +ROUTE 1 0.130 R4C4B.Q0 to R4C4B.M1 n732 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_76: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R4C4B.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_76: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R4C4B.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i12 (from RCLK_c +) + Destination: FF Data in IS_FSM__i13 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_77 to SLICE_77 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_77 to SLICE_77: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R6C3D.CLK to R6C3D.Q0 SLICE_77 (from RCLK_c) +ROUTE 1 0.130 R6C3D.Q0 to R6C3D.M1 n728 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_77: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R6C3D.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_77: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R6C3D.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i14 (from RCLK_c +) + Destination: FF Data in IS_FSM__i15 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_80 to SLICE_80 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_80 to SLICE_80: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R8C4A.CLK to R8C4A.Q0 SLICE_80 (from RCLK_c) +ROUTE 1 0.130 R8C4A.Q0 to R8C4A.M1 n726 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_80: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R8C4A.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_80: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R8C4A.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i10 (from RCLK_c +) + Destination: FF Data in IS_FSM__i11 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_82 to SLICE_82 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_82 to SLICE_82: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R4C3A.CLK to R4C3A.Q0 SLICE_82 (from RCLK_c) +ROUTE 1 0.130 R4C3A.Q0 to R4C3A.M1 n730 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_82: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R4C3A.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_82: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R4C3A.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i2 (from RCLK_c +) + Destination: FF Data in IS_FSM__i3 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_84 to SLICE_84 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_84 to SLICE_84: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R3C4A.CLK to R3C4A.Q0 SLICE_84 (from RCLK_c) +ROUTE 1 0.130 R3C4A.Q0 to R3C4A.M1 n738 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_84: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R3C4A.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_84: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R3C4A.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i6 (from RCLK_c +) + Destination: FF Data in IS_FSM__i7 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_86 to SLICE_86 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_86 to SLICE_86: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R4C3C.CLK to R4C3C.Q0 SLICE_86 (from RCLK_c) +ROUTE 1 0.130 R4C3C.Q0 to R4C3C.M1 n734 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_86: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R4C3C.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_86: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R4C3C.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.281ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i0 (from RCLK_c +) + Destination: FF Data in IS_FSM__i1 (to RCLK_c +) + + Delay: 0.264ns (47.7% logic, 52.3% route), 1 logic levels. + + Constraint Details: + + 0.264ns physical path delay SLICE_87 to SLICE_87 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.281ns + + Physical Path Details: + + Data path SLICE_87 to SLICE_87: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R4C2C.CLK to R4C2C.Q0 SLICE_87 (from RCLK_c) +ROUTE 6 0.138 R4C2C.Q0 to R4C2C.M1 nRCS_N_139 (to RCLK_c) + -------- + 0.264 (47.7% logic, 52.3% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_87: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R4C2C.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_87: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R4C2C.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.288ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2_380 (from RCLK_c +) + Destination: FF Data in RASr3_381 (to RCLK_c +) + + Delay: 0.271ns (46.5% logic, 53.5% route), 1 logic levels. + + Constraint Details: + + 0.271ns physical path delay SLICE_74 to SLICE_74 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.288ns + + Physical Path Details: + + Data path SLICE_74 to SLICE_74: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R8C5C.CLK to R8C5C.Q0 SLICE_74 (from RCLK_c) +ROUTE 14 0.145 R8C5C.Q0 to R8C5C.M1 RASr2 (to RCLK_c) + -------- + 0.271 (46.5% logic, 53.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_74: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R8C5C.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_74: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R8C5C.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.301ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in FS_610_add_4_16 (to RCLK_c +) + FF FS_610__i15 + FF FS_610__i14 + + Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. + + Constraint Details: + + 0.257ns physical path delay SLICE_1 to SLICE_1 meets + -0.044ns LUT_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.044ns) by 0.301ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_1: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R5C4D.CLK to R5C4D.Q1 SLICE_1 (from RCLK_c) +ROUTE 3 0.131 R5C4D.Q1 to R5C4D.A1 FS_15 (to RCLK_c) + -------- + 0.257 (49.0% logic, 51.0% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R5C4D.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.333 86.PADDI to R5C4D.CLK RCLK_c + -------- + 0.333 (0.0% logic, 100.0% route), 0 logic levels. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + 106 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.361ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.342ns (61.7% logic, 38.3% route), 2 logic levels. + + Constraint Details: + + 0.342ns physical path delay SLICE_14 to SLICE_14 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.361ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C5D.CLK to R5C5D.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 0.131 R5C5D.Q0 to R5C5D.A0 C1Submitted +CTOF_DEL --- 0.074 R5C5D.A0 to R5C5D.F0 SLICE_14 +ROUTE 1 0.000 R5C5D.F0 to R5C5D.DI0 n6_adj_3 (to PHI2_c) + -------- + 0.342 (61.7% logic, 38.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R5C5D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R5C5D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.361ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_407 (from PHI2_c -) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 0.342ns (61.7% logic, 38.3% route), 2 logic levels. + + Constraint Details: + + 0.342ns physical path delay SLICE_9 to SLICE_9 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.361ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R4C5D.CLK to R4C5D.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.131 R4C5D.Q0 to R4C5D.A0 ADSubmitted +CTOF_DEL --- 0.074 R4C5D.A0 to R4C5D.F0 SLICE_9 +ROUTE 1 0.000 R4C5D.F0 to R4C5D.DI0 n1413 (to PHI2_c) + -------- + 0.342 (61.7% logic, 38.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C5D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C5D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.587ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in XOR8MEG_408 (to PHI2_c -) + + Delay: 0.564ns (37.4% logic, 62.6% route), 2 logic levels. + + Constraint Details: + + 0.564ns physical path delay SLICE_18 to SLICE_49 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 0.587ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_49: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R4C4D.CLK to R4C4D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.223 R4C4D.Q0 to R3C4A.B1 CmdEnable +CTOF_DEL --- 0.074 R3C4A.B1 to R3C4A.F1 SLICE_84 +ROUTE 1 0.130 R3C4A.F1 to R3C4C.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 0.564 (37.4% logic, 62.6% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C4D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_49: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R3C4C.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.869ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) + FF CmdUFMCLK_413 + + Delay: 0.846ns (33.7% logic, 66.3% route), 3 logic levels. + + Constraint Details: + + 0.846ns physical path delay SLICE_18 to SLICE_81 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 0.869ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R4C4D.CLK to R4C4D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.145 R4C4D.Q0 to R4C5C.D0 CmdEnable +CTOF_DEL --- 0.074 R4C5C.D0 to R4C5C.F0 SLICE_83 +ROUTE 2 0.196 R4C5C.F0 to R4C5C.A1 n10 +CTOF_DEL --- 0.074 R4C5C.A1 to R4C5C.F1 SLICE_83 +ROUTE 2 0.220 R4C5C.F1 to R4C4A.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 0.846 (33.7% logic, 66.3% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C4D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C4A.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.869ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) + + Delay: 0.846ns (33.7% logic, 66.3% route), 3 logic levels. + + Constraint Details: + + 0.846ns physical path delay SLICE_18 to SLICE_93 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 0.869ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R4C4D.CLK to R4C4D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.145 R4C4D.Q0 to R4C5C.D0 CmdEnable +CTOF_DEL --- 0.074 R4C5C.D0 to R4C5C.F0 SLICE_83 +ROUTE 2 0.196 R4C5C.F0 to R4C5C.A1 n10 +CTOF_DEL --- 0.074 R4C5C.A1 to R4C5C.F1 SLICE_83 +ROUTE 2 0.220 R4C5C.F1 to R3C5A.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 0.846 (33.7% logic, 66.3% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C4D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R3C5A.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.057ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in Cmdn8MEGEN_410 (to PHI2_c -) + + Delay: 1.034ns (34.7% logic, 65.3% route), 4 logic levels. + + Constraint Details: + + 1.034ns physical path delay SLICE_18 to SLICE_23 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 1.057ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R4C4D.CLK to R4C4D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.145 R4C4D.Q0 to R4C5C.D0 CmdEnable +CTOF_DEL --- 0.074 R4C5C.D0 to R4C5C.F0 SLICE_83 +ROUTE 2 0.211 R4C5C.F0 to R4C4B.A1 n10 +CTOF_DEL --- 0.074 R4C4B.A1 to R4C4B.F1 SLICE_76 +ROUTE 2 0.103 R4C4B.F1 to R4C4B.C0 n2458 +CTOF_DEL --- 0.074 R4C4B.C0 to R4C4B.F0 SLICE_76 +ROUTE 1 0.216 R4C4B.F0 to R3C4B.CE PHI2_N_120_enable_4 (to PHI2_c) + -------- + 1.034 (34.7% logic, 65.3% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C4D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R3C4B.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.079ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdSubmitted_411 (to PHI2_c -) + + Delay: 1.056ns (34.0% logic, 66.0% route), 4 logic levels. + + Constraint Details: + + 1.056ns physical path delay SLICE_18 to SLICE_19 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 1.079ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R4C4D.CLK to R4C4D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.145 R4C4D.Q0 to R4C5C.D0 CmdEnable +CTOF_DEL --- 0.074 R4C5C.D0 to R4C5C.F0 SLICE_83 +ROUTE 2 0.211 R4C5C.F0 to R4C4B.A1 n10 +CTOF_DEL --- 0.074 R4C4B.A1 to R4C4B.F1 SLICE_76 +ROUTE 2 0.211 R4C4B.F1 to R6C4D.A0 n2458 +CTOF_DEL --- 0.074 R6C4D.A0 to R6C4D.F0 SLICE_91 +ROUTE 1 0.130 R6C4D.F0 to R6C4B.CE PHI2_N_120_enable_5 (to PHI2_c) + -------- + 1.056 (34.0% logic, 66.0% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C4D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R6C4B.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.104ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_407 (from PHI2_c -) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 1.081ns (37.9% logic, 62.1% route), 4 logic levels. + + Constraint Details: + + 1.081ns physical path delay SLICE_9 to SLICE_18 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 1.104ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R4C5D.CLK to R4C5D.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.143 R4C5D.Q0 to R3C5C.D0 ADSubmitted +CTOOFX_DEL --- 0.125 R3C5C.D0 to R3C5C.OFX0 i26/SLICE_71 +ROUTE 1 0.207 R3C5C.OFX0 to R4C5A.A0 n13_adj_2 +CTOF_DEL --- 0.074 R4C5A.A0 to R4C5A.F0 SLICE_105 +ROUTE 1 0.179 R4C5A.F0 to R4C3A.C1 n14 +CTOF_DEL --- 0.074 R4C3A.C1 to R4C3A.F1 SLICE_82 +ROUTE 1 0.142 R4C3A.F1 to R4C4D.CE PHI2_N_120_enable_7 (to PHI2_c) + -------- + 1.081 (37.9% logic, 62.1% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C5D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C4D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.368ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 1.345ns (35.7% logic, 64.3% route), 5 logic levels. + + Constraint Details: + + 1.345ns physical path delay SLICE_14 to SLICE_18 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 1.368ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C5D.CLK to R5C5D.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 0.196 R5C5D.Q0 to R5C5D.A1 C1Submitted +CTOF_DEL --- 0.074 R5C5D.A1 to R5C5D.F1 SLICE_14 +ROUTE 1 0.141 R5C5D.F1 to R3C5C.D1 n2284 +CTOOFX_DEL --- 0.121 R3C5C.D1 to R3C5C.OFX0 i26/SLICE_71 +ROUTE 1 0.207 R3C5C.OFX0 to R4C5A.A0 n13_adj_2 +CTOF_DEL --- 0.074 R4C5A.A0 to R4C5A.F0 SLICE_105 +ROUTE 1 0.179 R4C5A.F0 to R4C3A.C1 n14 +CTOF_DEL --- 0.074 R4C3A.C1 to R4C3A.F1 SLICE_82 +ROUTE 1 0.142 R4C3A.F1 to R4C4D.CE PHI2_N_120_enable_7 (to PHI2_c) + -------- + 1.345 (35.7% logic, 64.3% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R5C5D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R4C4D.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 4.689ns (weighted slack = 9.378ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q XOR8MEG_408 (from PHI2_c -) + Destination: FF Data in RA11_385 (to PHI2_c +) + + Delay: 0.517ns (40.8% logic, 59.2% route), 2 logic levels. + + Constraint Details: + + 0.517ns physical path delay SLICE_49 to SLICE_32 meets + -0.008ns DIN_HLD and + -4.164ns delay constraint less + 0.000ns skew requirement (totaling -4.172ns) by 4.689ns + + Physical Path Details: + + Data path SLICE_49 to SLICE_32: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R3C4C.CLK to R3C4C.Q0 SLICE_49 (from PHI2_c) +ROUTE 1 0.306 R3C4C.Q0 to R2C5A.A0 XOR8MEG +CTOF_DEL --- 0.074 R2C5A.A0 to R2C5A.F0 SLICE_32 +ROUTE 1 0.000 R2C5A.F0 to R2C5A.DI0 RA11_N_184 (to PHI2_c) + -------- + 0.517 (40.8% logic, 59.2% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_49: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R3C4C.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_32: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.965 39.PADDI to R2C5A.CLK PHI2_c + -------- + 0.965 (0.0% logic, 100.0% route), 0 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 0.000 ns| 0.273 ns| 1 + | | | +FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 0.000 ns| 0.361 ns| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 326 (setup), 0 (hold) +Score: 913247 (setup), 0 (hold) +Cumulative negative slack: 638389 (638389+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html new file mode 100644 index 0000000..6117b69 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_bgn.html @@ -0,0 +1,111 @@ + +Bitgen Report + + +
    BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:33 2023
+
+
+Command: bitgen -w -g ES:No -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO256C_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit".
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 44 MB
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html new file mode 100644 index 0000000..e3b9e75 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_iotiming.html @@ -0,0 +1,203 @@ + +I/O Timing Report + + +
    I/O Timing Report
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 4
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo256c_impl1.ncd
+// Version: Diamond (64-bit) 3.12.1.454
+// Written on Tue Aug 15 05:03:30 2023
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 5, 4, 3):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F    -0.006      M       1.907     3
+CROW[1] nCRAS F    -0.006      M       1.907     3
+Din[0]  PHI2  F     5.992      3       2.081     3
+Din[0]  nCCAS F     1.591      3      -0.045     M
+Din[1]  PHI2  F     5.388      3       2.863     3
+Din[1]  nCCAS F     0.231      3       0.973     3
+Din[2]  PHI2  F     4.913      3       2.842     3
+Din[2]  nCCAS F     0.265      3       1.112     3
+Din[3]  PHI2  F     6.776      3       2.065     3
+Din[3]  nCCAS F     0.702      3       0.725     3
+Din[4]  PHI2  F     4.191      3       1.807     3
+Din[4]  nCCAS F     1.107      3       0.235     3
+Din[5]  PHI2  F     7.709      3       0.737     3
+Din[5]  nCCAS F     1.192      3       0.184     3
+Din[6]  PHI2  F     6.617      3       1.159     3
+Din[6]  nCCAS F     0.904      3       0.149     3
+Din[7]  PHI2  F     6.864      3       1.300     3
+Din[7]  nCCAS F     0.531      3       0.451     3
+MAin[0] PHI2  F     4.802      3       1.029     3
+MAin[0] nCRAS F     1.511      3       0.599     3
+MAin[1] PHI2  F     4.513      3       1.653     3
+MAin[1] nCRAS F     0.340      3       1.609     3
+MAin[2] PHI2  F     4.241      3       1.193     3
+MAin[2] nCRAS F     1.248      3       0.814     3
+MAin[3] PHI2  F     6.748      3      -0.221     M
+MAin[3] nCRAS F     0.375      3       1.589     3
+MAin[4] PHI2  F     7.111      3      -0.295     M
+MAin[4] nCRAS F    -0.038      M       2.031     3
+MAin[5] PHI2  F     4.083      3       1.319     3
+MAin[5] nCRAS F    -0.126      M       2.320     3
+MAin[6] PHI2  F     8.738      3      -0.639     M
+MAin[6] nCRAS F     0.505      3       1.464     3
+MAin[7] PHI2  F     7.566      3      -0.400     M
+MAin[7] nCRAS F     0.390      3       1.577     3
+MAin[8] nCRAS F    -0.017      M       1.932     3
+MAin[9] nCRAS F     1.390      3       0.679     3
+PHI2    RCLK  R     4.721      3      -0.539     M
+UFMSDO  RCLK  R     2.307      3      -0.173     M
+nCCAS   RCLK  R     3.513      3      -0.441     M
+nCCAS   nCRAS F     1.800      3       0.388     3
+nCRAS   RCLK  R     1.107      3       0.266     3
+nFWE    PHI2  F     4.160      3       1.763     3
+nFWE    nCRAS F     0.864      3       1.164     3
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R     7.020         3        1.411          M
+LED    nCRAS F    10.053         3        2.020          M
+RA[0]  RCLK  R     8.511         3        1.707          M
+RA[0]  nCRAS F    10.448         3        2.067          M
+RA[10] RCLK  R     7.422         3        1.486          M
+RA[11] PHI2  R     8.233         3        1.633          M
+RA[1]  RCLK  R     8.292         3        1.649          M
+RA[1]  nCRAS F    10.175         3        2.009          M
+RA[2]  RCLK  R     8.708         3        1.746          M
+RA[2]  nCRAS F    10.512         3        2.079          M
+RA[3]  RCLK  R     6.982         3        1.404          M
+RA[3]  nCRAS F     8.753         3        1.739          M
+RA[4]  RCLK  R     6.982         3        1.404          M
+RA[4]  nCRAS F     9.764         3        1.953          M
+RA[5]  RCLK  R     6.982         3        1.404          M
+RA[5]  nCRAS F    10.635         3        2.140          M
+RA[6]  RCLK  R     9.127         3        1.839          M
+RA[6]  nCRAS F    10.861         3        2.160          M
+RA[7]  RCLK  R     8.287         3        1.659          M
+RA[7]  nCRAS F    10.995         3        2.202          M
+RA[8]  RCLK  R     8.834         3        1.776          M
+RA[8]  nCRAS F    10.930         3        2.181          M
+RA[9]  RCLK  R     6.729         3        1.353          M
+RA[9]  nCRAS F    10.423         3        2.088          M
+RBA[0] nCRAS F     7.746         3        1.538          M
+RBA[1] nCRAS F     9.473         3        1.887          M
+RCKE   RCLK  R     8.348         3        1.695          M
+RDQMH  RCLK  R     7.433         3        1.503          M
+RDQML  RCLK  R     9.061         3        1.821          M
+RD[0]  nCCAS F     6.791         3        1.468          M
+RD[1]  nCCAS F     7.502         3        1.596          M
+RD[2]  nCCAS F     9.015         3        1.924          M
+RD[3]  nCCAS F     8.919         3        1.901          M
+RD[4]  nCCAS F     7.500         3        1.596          M
+RD[5]  nCCAS F     6.791         3        1.468          M
+RD[6]  nCCAS F     7.950         3        1.703          M
+RD[7]  nCCAS F     7.871         3        1.681          M
+UFMCLK RCLK  R     7.767         3        1.567          M
+UFMSDI RCLK  R     5.675         3        1.141          M
+nRCAS  RCLK  R     6.518         3        1.300          M
+nRCS   RCLK  R     5.675         3        1.141          M
+nRRAS  RCLK  R     7.469         3        1.503          M
+nRWE   RCLK  R     5.675         3        1.141          M
+nUFMCS RCLK  R     7.873         3        1.593          M
+WARNING: you must also run trce with hold speed: 3
+WARNING: you must also run trce with setup speed: M
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_lattice.synproj b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_lattice.synproj new file mode 100644 index 0000000..1c77aea --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_lattice.synproj @@ -0,0 +1,41 @@ +-a "MachXO" +-d LCMXO256C +-t TQFP100 +-s 3 +-frequency 200 +-optimization_goal Balanced +-bram_utilization 100 +-ramstyle Auto +-romstyle auto +-dsp_utilization 100 +-use_dsp 1 +-use_carry_chain 1 +-carry_chain_length 0 +-force_gsr Auto +-resource_sharing 1 +-propagate_constants 1 +-remove_duplicate_regs 1 +-mux_style Auto +-max_fanout 1000 +-fsm_encoding_style Auto +-twr_paths 3 +-fix_gated_clocks 1 +-loop_limit 1950 + + + +-use_io_insertion 1 +-resolve_mixed_drivers 0 +-use_io_reg auto + + +-lpf 1 +-p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C" +-ver "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v" +-top RAM2GS + + +-p "C:/lscc/diamond/3.12/ispfpga/mj5g00/data" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C" + +-ngd "RAM2GS_LCMXO256C_impl1.ngd" + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.asd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.asd new file mode 100644 index 0000000..a397419 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.asd @@ -0,0 +1,13 @@ +[ActiveSupport MAP] +Device = LCMXO256C; +Package = TQFP100; +Performance = 3; +LUTS_avail = 256; +LUTS_used = 142; +FF_avail = 256; +FF_used = 102; +INPUT_LVCMOS33 = 26; +OUTPUT_LVCMOS33 = 33; +BIDI_LVCMOS33 = 8; +IO_avail = 78; +IO_used = 67; diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam new file mode 100644 index 0000000..91ebb0b --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.cam @@ -0,0 +1,99 @@ +[ START MERGED ] +nCRAS_N_9 nCRAS_c +nCCAS_N_3 nCCAS_c +n2477 Ready +nFWE_N_5 nFWE_c +PHI2_N_120 PHI2_c +n1425 nRowColSel_N_34 +nRWE_N_176 nRWE_N_177 +RASr2_N_63 RASr2 +n1426 nRowColSel_N_35 +[ END MERGED ] +[ START CLIPPED ] +GND_net +VCC_net +FS_610_add_4_18/CO1 +FS_610_add_4_18/CO0 +FS_610_add_4_10/CO0 +FS_610_add_4_4/CO0 +FS_610_add_4_12/CO0 +FS_610_add_4_2/CO0 +FS_610_add_4_14/CO0 +FS_610_add_4_6/CO0 +FS_610_add_4_16/CO0 +FS_610_add_4_8/CO0 +[ END CLIPPED ] +[ START DESIGN PREFS ] +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:20 2023 + +SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ; +LOCATE COMP "RD[7]" SITE "71" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "MAin[9]" SITE "51" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "UFMSDO" SITE "55" ; +SCHEMATIC END ; +[ END DESIGN PREFS ] diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.hrr b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.hrr new file mode 100644 index 0000000..c405991 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.hrr @@ -0,0 +1,10 @@ +--------------------------------------------------- +Report for cell RAM2GS + Instance path: RAM2GS + Cell usage: + cell count Res Usage(%) + SLIC 71.00 100.0 + LUT4 124.00 100.0 + IOBUF 67 100.0 + PFUREG 102 100.0 + RIPPLE 9 100.0 diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.ncd b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.ncd new file mode 100644 index 0000000..0a2beec Binary files /dev/null and b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_map.ncd differ diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.sdf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.sdf new file mode 100644 index 0000000..92c0943 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.sdf @@ -0,0 +1,3036 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Tue Aug 15 05:03:23 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8I) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_14") + (INSTANCE SLICE_14I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_18") + (INSTANCE SLICE_18I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_23") + (INSTANCE SLICE_23I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_25") + (INSTANCE SLICE_25I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_26") + (INSTANCE SLICE_26I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_31") + (INSTANCE SLICE_31I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_34") + (INSTANCE SLICE_34I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_35") + (INSTANCE SLICE_35I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_36") + (INSTANCE SLICE_36I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_43") + (INSTANCE SLICE_43I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_49") + (INSTANCE SLICE_49I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_56") + (INSTANCE SLICE_56I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_58") + (INSTANCE SLICE_58I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_60") + (INSTANCE SLICE_60I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_61") + (INSTANCE SLICE_61I) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_63") + (INSTANCE SLICE_63I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_64") + (INSTANCE SLICE_64I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_65") + (INSTANCE SLICE_65I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_66") + (INSTANCE SLICE_66I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_67") + (INSTANCE SLICE_67I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_68") + (INSTANCE SLICE_68I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_69") + (INSTANCE SLICE_69I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "RCKEEN_I_0_445_SLICE_70") + (INSTANCE RCKEEN_I_0_445_SLICE_70I) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i26_SLICE_71") + (INSTANCE i26_SLICE_71I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i2099_SLICE_72") + (INSTANCE i2099_SLICE_72I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i26_adj_28_SLICE_73") + (INSTANCE i26_adj_28_SLICE_73I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_74") + (INSTANCE SLICE_74I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_75") + (INSTANCE SLICE_75I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_76") + (INSTANCE SLICE_76I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_80") + (INSTANCE SLICE_80I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_81") + (INSTANCE SLICE_81I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_84") + (INSTANCE SLICE_84I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_85") + (INSTANCE SLICE_85I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_102") + (INSTANCE SLICE_102I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_103") + (INSTANCE SLICE_103I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_104") + (INSTANCE SLICE_104I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_105") + (INSTANCE SLICE_105I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "RD_7_B") + (INSTANCE RD_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD7 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD7 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD7) (1250:1250:1250)) + (WIDTH (negedge RD7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_6_B") + (INSTANCE RD_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD6 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD6 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD6) (1250:1250:1250)) + (WIDTH (negedge RD6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_5_B") + (INSTANCE RD_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD5 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD5 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD5) (1250:1250:1250)) + (WIDTH (negedge RD5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_4_B") + (INSTANCE RD_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD4 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD4 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD4) (1250:1250:1250)) + (WIDTH (negedge RD4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_3_B") + (INSTANCE RD_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD3 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD3 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD3) (1250:1250:1250)) + (WIDTH (negedge RD3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_2_B") + (INSTANCE RD_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD2 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD2 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD2) (1250:1250:1250)) + (WIDTH (negedge RD2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_1_B") + (INSTANCE RD_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD1 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD1 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD1) (1250:1250:1250)) + (WIDTH (negedge RD1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_0_B") + (INSTANCE RD_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD0 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD0 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD0) (1250:1250:1250)) + (WIDTH (negedge RD0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Dout_7_B") + (INSTANCE Dout_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout7 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_6_B") + (INSTANCE Dout_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout6 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_5_B") + (INSTANCE Dout_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout5 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_4_B") + (INSTANCE Dout_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout4 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_3_B") + (INSTANCE Dout_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout3 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_2_B") + (INSTANCE Dout_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout2 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1_B") + (INSTANCE Dout_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0_B") + (INSTANCE Dout_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "LEDB") + (INSTANCE LEDI) + (DELAY + (ABSOLUTE + (IOPATH PADDO LEDS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_B") + (INSTANCE RBA_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_0_B") + (INSTANCE RBA_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_11_B") + (INSTANCE RA_11_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA11 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_10_B") + (INSTANCE RA_10_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA10 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_9_B") + (INSTANCE RA_9_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA9 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_8_B") + (INSTANCE RA_8_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA8 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_7_B") + (INSTANCE RA_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA7 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_6_B") + (INSTANCE RA_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA6 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_5_B") + (INSTANCE RA_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA5 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_4_B") + (INSTANCE RA_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA4 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_3_B") + (INSTANCE RA_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA3 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_2_B") + (INSTANCE RA_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA2 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_1_B") + (INSTANCE RA_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_0_B") + (INSTANCE RA_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRCSB") + (INSTANCE nRCSI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCSS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RCKEB") + (INSTANCE RCKEI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RCKES (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRWEB") + (INSTANCE nRWEI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRWES (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRRASB") + (INSTANCE nRRASI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRRASS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRCASB") + (INSTANCE nRCASI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCASS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMHB") + (INSTANCE RDQMHI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMHS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMLB") + (INSTANCE RDQMLI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMLS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nUFMCSB") + (INSTANCE nUFMCSI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nUFMCSS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "UFMCLKB") + (INSTANCE UFMCLKI) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMCLKS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "UFMSDIB") + (INSTANCE UFMSDII) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMSDIS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "PHI2B") + (INSTANCE PHI2I) + (DELAY + (ABSOLUTE + (IOPATH PHI2S PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI2S) (1250:1250:1250)) + (WIDTH (negedge PHI2S) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_9_B") + (INSTANCE MAin_9_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (1250:1250:1250)) + (WIDTH (negedge MAin9) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_8_B") + (INSTANCE MAin_8_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (1250:1250:1250)) + (WIDTH (negedge MAin8) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_7_B") + (INSTANCE MAin_7_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (1250:1250:1250)) + (WIDTH (negedge MAin7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_6_B") + (INSTANCE MAin_6_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (1250:1250:1250)) + (WIDTH (negedge MAin6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_5_B") + (INSTANCE MAin_5_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (1250:1250:1250)) + (WIDTH (negedge MAin5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_4_B") + (INSTANCE MAin_4_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (1250:1250:1250)) + (WIDTH (negedge MAin4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_3_B") + (INSTANCE MAin_3_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (1250:1250:1250)) + (WIDTH (negedge MAin3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_2_B") + (INSTANCE MAin_2_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (1250:1250:1250)) + (WIDTH (negedge MAin2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_1_B") + (INSTANCE MAin_1_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (1250:1250:1250)) + (WIDTH (negedge MAin1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_0_B") + (INSTANCE MAin_0_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (1250:1250:1250)) + (WIDTH (negedge MAin0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "CROW_1_B") + (INSTANCE CROW_1_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (1250:1250:1250)) + (WIDTH (negedge CROW1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "CROW_0_B") + (INSTANCE CROW_0_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (1250:1250:1250)) + (WIDTH (negedge CROW0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_7_B") + (INSTANCE Din_7_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (1250:1250:1250)) + (WIDTH (negedge Din7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_6_B") + (INSTANCE Din_6_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (1250:1250:1250)) + (WIDTH (negedge Din6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_5_B") + (INSTANCE Din_5_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (1250:1250:1250)) + (WIDTH (negedge Din5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_4_B") + (INSTANCE Din_4_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (1250:1250:1250)) + (WIDTH (negedge Din4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_3_B") + (INSTANCE Din_3_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (1250:1250:1250)) + (WIDTH (negedge Din3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_2_B") + (INSTANCE Din_2_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (1250:1250:1250)) + (WIDTH (negedge Din2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_1_B") + (INSTANCE Din_1_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (1250:1250:1250)) + (WIDTH (negedge Din1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_0_B") + (INSTANCE Din_0_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (1250:1250:1250)) + (WIDTH (negedge Din0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nCCASB") + (INSTANCE nCCASI) + (DELAY + (ABSOLUTE + (IOPATH nCCASS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCCASS) (1250:1250:1250)) + (WIDTH (negedge nCCASS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nCRASB") + (INSTANCE nCRASI) + (DELAY + (ABSOLUTE + (IOPATH nCRASS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCRASS) (1250:1250:1250)) + (WIDTH (negedge nCRASS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nFWEB") + (INSTANCE nFWEI) + (DELAY + (ABSOLUTE + (IOPATH nFWES PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nFWES) (1250:1250:1250)) + (WIDTH (negedge nFWES) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RCLKB") + (INSTANCE RCLKI) + (DELAY + (ABSOLUTE + (IOPATH RCLKS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RCLKS) (1250:1250:1250)) + (WIDTH (negedge RCLKS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "UFMSDOB") + (INSTANCE UFMSDOI) + (DELAY + (ABSOLUTE + (IOPATH UFMSDOS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge UFMSDOS) (1250:1250:1250)) + (WIDTH (negedge UFMSDOS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_77I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_88I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_0I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_68I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_88I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_25I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_26I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_31I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_34I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_35I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_36I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_43I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_44I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_56I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_58I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_60I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_61I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_63I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_64I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_65I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_66I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_67I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_68I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_69I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_74I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_76I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_77I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_79I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_80I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_82I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_83I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_84I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_86I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_87I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_91I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_100I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/FCO SLICE_0I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/FCO SLICE_7I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_1I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_94I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_94I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_69I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_78I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_90I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_90I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/FCO SLICE_1I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/FCO SLICE_8I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_77I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_88I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_43I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_77I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/FCO SLICE_2I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_94I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_94I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_68I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_69I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_90I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/FCO SLICE_3I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_43I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_68I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_68I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/FCO SLICE_6I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_44I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_56I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_75I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_75I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_78I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_94I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_95I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_5I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_56I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_75I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_88I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_95I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_95I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/FCO SLICE_5I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_68I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_77I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q1 SLICE_7I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q1 SLICE_77I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q1 SLICE_88I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_87I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_88I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_68I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_69I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_90I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_78I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_90I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_90I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_94I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_9I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_14I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_18I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI i26_SLICE_71I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_82I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_83I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_84I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_89I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_89I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_97I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_99I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_9I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_14I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_18I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_76I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_82I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_84I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_89I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_89I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_9I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI i26_SLICE_71I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI i26_SLICE_71I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI i26_adj_28_SLICE_73I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI i26_adj_28_SLICE_73I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_76I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_82I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_83I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_84I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_89I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_97I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_98I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/F1 SLICE_9I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 SLICE_9I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 i26_SLICE_71I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F1 SLICE_9I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/F1 SLICE_9I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/F0 SLICE_9I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F0 SLICE_9I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F0 SLICE_14I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_9I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_14I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_18I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_19I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_23I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_32I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_49I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_81I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_88I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_91I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_93I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_99I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_101I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_102I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_14I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_23I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_32I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_32I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI i26_adj_28_SLICE_73I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI i26_adj_28_SLICE_73I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_79I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_92I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_92I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_92I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_99I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14I/Q0 SLICE_14I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14I/Q0 SLICE_14I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_14I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_76I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_82I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_85I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_86I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_89I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_98I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_105I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14I/F0 SLICE_14I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14I/F1 i26_SLICE_71I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_18I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_95I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_103I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F0 SLICE_18I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F0 SLICE_18I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_18I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_96I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_101I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT i26_adj_28_SLICE_73I/OFX0 SLICE_18I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F0 SLICE_18I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F0 SLICE_79I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F0 SLICE_18I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F1 SLICE_18I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/Q0 SLICE_83I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/Q0 SLICE_84I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q1 SLICE_19I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q1 SLICE_91I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q1 SLICE_100I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/Q0 SLICE_19I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/Q0 SLICE_100I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q0 SLICE_19I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q0 SLICE_100I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F0 SLICE_19I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F0 SLICE_19I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F1 SLICE_67I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F1 SLICE_87I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_23I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI i26_SLICE_71I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI i26_adj_28_SLICE_73I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_76I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_79I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_85I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_91I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_91I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_101I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_105I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_23I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_32I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_86I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_92I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_99I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F1 SLICE_23I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F1 SLICE_49I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F1 SLICE_84I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_23I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_49I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_76I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_83I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_85I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_86I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_91I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_101I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_105I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_105I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/Q0 SLICE_23I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/Q0 SLICE_32I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_23I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_49I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_86I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_88I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_89I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_93I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F0 SLICE_23I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F0 SLICE_23I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/Q0 SLICE_56I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_25I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_36I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_58I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_60I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_61I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_63I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_67I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 RCKEEN_I_0_445_SLICE_70I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 i2099_SLICE_72I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 i2099_SLICE_72I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_80I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_104I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_25I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_34I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_35I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_35I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_58I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_60I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_63I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_65I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_65I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_66I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_68I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 RCKEEN_I_0_445_SLICE_70I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_74I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_100I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_25I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_34I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_34I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_43I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_44I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_56I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_60I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_63I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_65I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_69I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_75I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_78I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_87I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_95I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_100I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_100I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_102I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_25I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_31I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_31I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_32I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_34I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_34I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_36I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_58I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_58I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_60I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_61I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_63I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 i2099_SLICE_72I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 i2099_SLICE_72I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_78I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_80I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_85I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_90I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_95I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_96I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_97I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_100I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_104I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F0 SLICE_25I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/F1 SLICE_25I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_76I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_77I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_80I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_82I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_84I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_86I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_87I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_100I/CE (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_26I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_78I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_83I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_85I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_90I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_95I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_96I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_97I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_98I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_26I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_58I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 RCKEEN_I_0_445_SLICE_70I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 RCKEEN_I_0_445_SLICE_70I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_74I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_74I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_103I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_26I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_49I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/F0 SLICE_26I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F1 SLICE_26I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/F1 LEDI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_31I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_58I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_66I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_66I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 RCKEEN_I_0_445_SLICE_70I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 i2099_SLICE_72I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_80I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 SLICE_31I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 SLICE_84I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 SLICE_102I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 SLICE_102I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63I/F1 SLICE_31I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63I/F1 SLICE_63I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31I/F0 SLICE_31I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q1 SLICE_31I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q1 SLICE_82I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q1 SLICE_102I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31I/Q0 RA_10_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31I/F1 SLICE_61I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49I/Q0 SLICE_32I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/F0 SLICE_32I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/Q0 RA_11_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/F1 SLICE_83I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT RCKEEN_I_0_445_SLICE_70I/OFX0 SLICE_34I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34I/F0 SLICE_34I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F1 SLICE_34I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F1 SLICE_58I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F1 SLICE_60I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34I/Q0 SLICE_35I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34I/F1 SLICE_60I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q0 SLICE_35I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q0 SLICE_60I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q0 RCKEI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q1 SLICE_35I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/Q0 SLICE_35I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/Q0 SLICE_74I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F0 SLICE_35I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q0 SLICE_35I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F1 SLICE_104I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q1 SLICE_67I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q1 SLICE_68I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q1 SLICE_74I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/F0 SLICE_36I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 SLICE_36I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/F1 SLICE_64I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/F1 SLICE_66I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F1 SLICE_43I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F1 SLICE_44I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F1 SLICE_43I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F1 SLICE_69I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F1 SLICE_95I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43I/F1 SLICE_43I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q0 SLICE_43I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43I/F0 SLICE_43I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F0 SLICE_43I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F0 SLICE_44I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F0 SLICE_43I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F0 SLICE_44I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43I/Q0 UFMCLKI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F0 SLICE_44I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F1 SLICE_44I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F1 SLICE_75I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F1 SLICE_78I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F1 SLICE_44I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F1 SLICE_78I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/Q0 SLICE_44I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F1 SLICE_44I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F0 SLICE_44I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/Q0 UFMSDII/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_49I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_81I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_86I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_88I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_89I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49I/F1 SLICE_49I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_49I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI i26_SLICE_71I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI i26_adj_28_SLICE_73I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI i26_adj_28_SLICE_73I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_79I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_81I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_92I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_102I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_103I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_49I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI i26_adj_28_SLICE_73I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI i26_adj_28_SLICE_73I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_76I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_79I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_91I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_91I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_92I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_92I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_102I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_103I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49I/F0 SLICE_49I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/F1 SLICE_49I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F1 SLICE_56I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F1 SLICE_78I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F1 SLICE_95I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/F1 SLICE_56I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDOI/PADDI SLICE_56I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/F0 SLICE_56I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F0 SLICE_56I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/F0 SLICE_58I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_58I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 i2099_SLICE_72I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58I/OFX0 SLICE_58I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58I/Q0 nRCASI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60I/F1 SLICE_60I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60I/F1 SLICE_61I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT i2099_SLICE_72I/OFX0 SLICE_60I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60I/F0 SLICE_60I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60I/Q0 nRCSI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 SLICE_61I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 SLICE_63I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 i2099_SLICE_72I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 i2099_SLICE_72I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 SLICE_87I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 SLICE_102I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_61I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_64I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_65I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_65I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_66I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_66I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_80I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F1 SLICE_61I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/Q0 SLICE_61I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/Q0 nRRASI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/OFX0 SLICE_61I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F0 SLICE_63I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/F1 SLICE_63I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63I/F0 SLICE_63I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F0 SLICE_63I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63I/Q0 nRWEI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_64I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_64I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_93I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_93I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_96I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_97I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_98I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_98I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_99I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_99I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_101I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_101I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_103I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_64I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_90I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_93I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_93I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/Q1 SLICE_64I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/F0 SLICE_64I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_64I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_80I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_104I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/F0 SLICE_64I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/F1 RA_9_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/Q1 SLICE_65I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/Q1 SLICE_87I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_65I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_66I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_67I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_74I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_80I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_100I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F0 SLICE_65I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F1 SLICE_104I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F0 SLICE_66I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F0 SLICE_67I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q1 SLICE_67I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_67I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 nUFMCSI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/F0 RCKEEN_I_0_445_SLICE_70I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/F1 SLICE_69I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F0 SLICE_77I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q1 SLICE_74I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q1 SLICE_103I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F0 SLICE_69I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F0 SLICE_69I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/F0 SLICE_69I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 RCKEEN_I_0_445_SLICE_70I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 RCKEEN_I_0_445_SLICE_70I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_74I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_74I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_103I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F1 i26_SLICE_71I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F1 SLICE_83I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 i26_SLICE_71I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT i26_SLICE_71I/OFX0 SLICE_105I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F0 SLICE_74I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F0 SLICE_104I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F0 SLICE_75I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F0 SLICE_87I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F1 SLICE_75I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F0 SLICE_76I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F0 SLICE_83I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F1 SLICE_76I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F1 SLICE_91I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q0 SLICE_76I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/Q1 SLICE_76I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F0 SLICE_77I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/Q0 SLICE_77I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/Q1 SLICE_77I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F1 SLICE_87I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/Q1 SLICE_80I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_78I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_96I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_99I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_78I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_97I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_101I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/Q0 SLICE_101I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/Q1 SLICE_99I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_79I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/F0 SLICE_79I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q1 SLICE_79I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_79I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_89I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_92I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_98I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_103I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_105I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_105I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/Q0 SLICE_80I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/Q1 SLICE_81I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/Q0 SLICE_81I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/Q1 SLICE_81I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F1 SLICE_81I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/F0 SLICE_81I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/Q0 SLICE_81I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F1 SLICE_81I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F1 SLICE_93I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F0 SLICE_82I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F0 SLICE_82I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F0 SLICE_83I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/Q0 SLICE_82I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/F0 SLICE_84I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_84I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_85I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/Q0 SLICE_84I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/Q1 SLICE_100I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F0 SLICE_85I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F1 SLICE_85I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F1 SLICE_86I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F1 SLICE_105I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT CROW_1_I/PADDI SLICE_85I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW_0_I/PADDI SLICE_85I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/Q0 RBA_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/Q1 RBA_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/Q0 SLICE_86I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/Q1 SLICE_86I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F1 SLICE_87I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F0 SLICE_88I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/Q0 SLICE_97I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/Q1 SLICE_96I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/Q0 RD_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/Q1 RD_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin_8_I/PADDI SLICE_90I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_8_I/PADDI SLICE_98I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/Q0 SLICE_98I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/Q0 RD_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/Q1 RD_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/F0 RDQMHI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/F1 RDQMLI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_95I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_97I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_97I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/Q0 SLICE_97I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/Q1 SLICE_103I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_96I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_96I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_96I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/Q1 SLICE_96I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/Q0 SLICE_96I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/Q0 SLICE_101I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F1 RA_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/Q1 SLICE_97I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/Q0 SLICE_98I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/F1 RA_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/Q1 SLICE_99I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/F0 RA_8_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/F1 RA_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F0 RA_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F1 RA_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/Q0 SLICE_100I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/F0 RA_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/F1 RA_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/Q0 RD_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/F1 RA_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/Q1 RD_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/Q0 RD_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_7_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_6_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_5_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_4_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_3_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_2_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_1_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_0_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/Q1 RD_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_7_I/PADDI Dout_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_6_I/PADDI Dout_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_5_I/PADDI Dout_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_4_I/PADDI Dout_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_3_I/PADDI Dout_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_2_I/PADDI Dout_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_1_I/PADDI Dout_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_0_I/PADDI Dout_0_I/PADDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.vho b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.vho new file mode 100644 index 0000000..ab79c11 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvho.vho @@ -0,0 +1,26269 @@ + +-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +-- ldbanno -n VHDL -o RAM2GS_LCMXO256C_impl1_mapvho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd +-- Netlist created on Tue Aug 15 05:03:20 2023 +-- Netlist written on Tue Aug 15 05:03:23 2023 +-- Design is for device LCMXO256C +-- Design is for package TQFP100 +-- Design is for performance grade 3 + +-- entity vmuxregsre + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vmuxregsre is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE; + + end vmuxregsre; + + architecture Structure of vmuxregsre is + component FL1P3DX + generic (GSR: String); + port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; + CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; + Q: out Std_logic); + end component; + begin + INST01: FL1P3DX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity vcc + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vcc is + port (PWR1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE; + + end vcc; + + architecture Structure of vcc is + component VHI + port (Z: out Std_logic); + end component; + begin + INST1: VHI + port map (Z=>PWR1); + end Structure; + +-- entity gnd + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity gnd is + port (PWR0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE; + + end gnd; + + architecture Structure of gnd is + component VLO + port (Z: out Std_logic); + end component; + begin + INST1: VLO + port map (Z=>PWR0); + end Structure; + +-- entity ccu2B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity ccu2B is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu2B : ENTITY IS TRUE; + + end ccu2B; + + architecture Structure of ccu2B is + component CCU2 + generic (INIT0: String; INIT1: String; INJECT1_0: String; + INJECT1_1: String); + port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; + C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; + B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; + S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; + COUT1: out Std_logic); + end component; + begin + inst1: CCU2 + generic map (INIT0 => "0xfaaa", INIT1 => "0xfaaa", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1); + end Structure; + +-- entity SLICE_0 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_0 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_0"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE; + + end SLICE_0; + + architecture Structure of SLICE_0 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_0_FS_610_add_4_8_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_0_FS_610_add_4_8_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i7: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_0_FS_610_add_4_8_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i6: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_0_FS_610_add_4_8_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_8: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_0_FS_610_add_4_8_S0, + S1=>SLICE_0_FS_610_add_4_8_S1, CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_1 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_1 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_1"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE; + + end SLICE_1; + + architecture Structure of SLICE_1 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_1_FS_610_add_4_16_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_1_FS_610_add_4_16_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i15: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_1_FS_610_add_4_16_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i14: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_1_FS_610_add_4_16_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_16: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_1_FS_610_add_4_16_S0, S1=>SLICE_1_FS_610_add_4_16_S1, + CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_2 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_2 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_2"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE; + + end SLICE_2; + + architecture Structure of SLICE_2 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_2_FS_610_add_4_6_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_2_FS_610_add_4_6_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i5: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_2_FS_610_add_4_6_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i4: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_2_FS_610_add_4_6_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_6: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_2_FS_610_add_4_6_S0, + S1=>SLICE_2_FS_610_add_4_6_S1, CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_3 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_3 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_3"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE; + + end SLICE_3; + + architecture Structure of SLICE_3 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_3_FS_610_add_4_14_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_3_FS_610_add_4_14_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i13: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_3_FS_610_add_4_14_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i12: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_3_FS_610_add_4_14_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_14: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_3_FS_610_add_4_14_S0, S1=>SLICE_3_FS_610_add_4_14_S1, + CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity ccu20001 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity ccu20001 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE; + + end ccu20001; + + architecture Structure of ccu20001 is + component CCU2 + generic (INIT0: String; INIT1: String; INJECT1_0: String; + INJECT1_1: String); + port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; + C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; + B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; + S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; + COUT1: out Std_logic); + end component; + begin + inst1: CCU2 + generic map (INIT0 => "0x0555", INIT1 => "0xfaaa", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1); + end Structure; + +-- entity SLICE_4 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_4 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_4"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE; + + end SLICE_4; + + architecture Structure of SLICE_4 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_4_FS_610_add_4_2_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_4_FS_610_add_4_2_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20001 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i1: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_4_FS_610_add_4_2_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i0: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_4_FS_610_add_4_2_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_2: ccu20001 + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>SLICE_4_FS_610_add_4_2_S0, + S1=>SLICE_4_FS_610_add_4_2_S1, CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, Q0_out, Q1_out, FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_5 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_5 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_5"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE; + + end SLICE_5; + + architecture Structure of SLICE_5 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_5_FS_610_add_4_12_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_5_FS_610_add_4_12_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i11: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_5_FS_610_add_4_12_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i10: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_5_FS_610_add_4_12_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_12: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_5_FS_610_add_4_12_S0, S1=>SLICE_5_FS_610_add_4_12_S1, + CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_6 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_6 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_6"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE; + + end SLICE_6; + + architecture Structure of SLICE_6 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_6_FS_610_add_4_4_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_6_FS_610_add_4_4_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i3: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_6_FS_610_add_4_4_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i2: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_6_FS_610_add_4_4_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_4: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_6_FS_610_add_4_4_S0, + S1=>SLICE_6_FS_610_add_4_4_S1, CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_7 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_7 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_7"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE; + + end SLICE_7; + + architecture Structure of SLICE_7 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_7_FS_610_add_4_10_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_7_FS_610_add_4_10_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i9: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_7_FS_610_add_4_10_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i8: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_7_FS_610_add_4_10_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_10: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_7_FS_610_add_4_10_S0, S1=>SLICE_7_FS_610_add_4_10_S1, + CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_8 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_8 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_8"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE; + + end SLICE_8; + + architecture Structure of SLICE_8 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_8_FS_610_add_4_18_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_8_FS_610_add_4_18_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i17: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_8_FS_610_add_4_18_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i16: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_8_FS_610_add_4_18_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_18: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_8_FS_610_add_4_18_S0, S1=>SLICE_8_FS_610_add_4_18_S1, + CO0=>open, CO1=>open); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut4 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut4 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE; + + end lut4; + + architecture Structure of lut4 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xDFDF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40002 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40002 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40002 : ENTITY IS TRUE; + + end lut40002; + + architecture Structure of lut40002 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x50DC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0003 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vmuxregsre0003 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0003 : ENTITY IS TRUE; + + end vmuxregsre0003; + + architecture Structure of vmuxregsre0003 is + component FL1P3IY + generic (GSR: String); + port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; + CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; + Q: out Std_logic); + end component; + begin + INST01: FL1P3IY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity inverter + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity inverter is + port (I: in Std_logic; Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE; + + end inverter; + + architecture Structure of inverter is + component INV + port (A: in Std_logic; Z: out Std_logic); + end component; + begin + INST1: INV + port map (A=>I, Z=>Z); + end Structure; + +-- entity SLICE_9 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_9 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_9"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE; + + end SLICE_9; + + architecture Structure of SLICE_9 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40002 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1125_4_lut: lut40002 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + ADSubmitted_407: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40004 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40004 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE; + + end lut40004; + + architecture Structure of lut40004 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xEEEE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40005 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40005 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE; + + end lut40005; + + architecture Structure of lut40005 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xE0F0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0006 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vmuxregsre0006 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0006 : ENTITY IS TRUE; + + end vmuxregsre0006; + + architecture Structure of vmuxregsre0006 is + component FL1P3JY + generic (GSR: String); + port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; + CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; + Q: out Std_logic); + end component; + begin + INST01: FL1P3JY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); + end Structure; + +-- entity SLICE_14 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_14 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_14"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE; + + end SLICE_14; + + architecture Structure of SLICE_14 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + begin + i1988_2_lut: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2062_2_lut_3_lut_4_lut: lut40005 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + C1Submitted_406: vmuxregsre0006 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40007 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40007 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40007 : ENTITY IS TRUE; + + end lut40007; + + architecture Structure of lut40007 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xDFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40008 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40008 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE; + + end lut40008; + + architecture Structure of lut40008 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0800") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_18 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_18 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_18"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_18 : ENTITY IS TRUE; + + end SLICE_18; + + architecture Structure of SLICE_18 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40007 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i13_4_lut: lut40007 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut_adj_21: lut40008 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdEnable_405: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40009 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40009 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE; + + end lut40009; + + architecture Structure of lut40009 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0808") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40010 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40010 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE; + + end lut40010; + + architecture Structure of lut40010 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_19 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_19 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_19"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE; + + end SLICE_19; + + architecture Structure of SLICE_19 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_rep_29: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n2568_001_BUF1_BUF1: lut40010 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + CmdSubmitted_411: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, DI0_dly, CE_dly, CLK_dly, + F0_out, Q0_out, F1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40011 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40011 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE; + + end lut40011; + + architecture Structure of lut40011 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFEFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40012 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40012 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE; + + end lut40012; + + architecture Structure of lut40012 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCC5C") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_23 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_23 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_23"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_23 : ENTITY IS TRUE; + + end SLICE_23; + + architecture Structure of SLICE_23 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut_adj_2: lut40011 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Cmdn8MEGEN_I_93_4_lut: lut40012 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Cmdn8MEGEN_410: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40013 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40013 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE; + + end lut40013; + + architecture Structure of lut40013 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x4000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_25 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_25 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_25"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE; + + end SLICE_25; + + architecture Structure of SLICE_25 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_3_lut_4_lut_4_lut: lut40013 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + n2568_000_BUF1_BUF1: lut40010 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + InitReady_394: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, DI0_dly, CE_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40014 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40014 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE; + + end lut40014; + + architecture Structure of lut40014 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFDFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_26 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_26 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_26"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE; + + end SLICE_26; + + architecture Structure of SLICE_26 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2049_3_lut: lut40014 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + m1_lut: lut40010 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + LEDEN_419: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, DI0_dly, CE_dly, CLK_dly, + F0_out, Q0_out, F1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40015 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40015 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE; + + end lut40015; + + architecture Structure of lut40015 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xDDDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_31 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_31 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_31"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE; + + end SLICE_31; + + architecture Structure of SLICE_31 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_2_lut: lut40015 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_adj_27: lut40011 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RA10_400: vmuxregsre0006 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, + LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40016 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40016 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE; + + end lut40016; + + architecture Structure of lut40016 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xC6C6") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_32 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_32 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_32"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE; + + end SLICE_32; + + architecture Structure of SLICE_32 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Din_7_I_0_462_i6_2_lut_rep_35: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RA11_I_54_3_lut: lut40016 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RA11_385: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, + LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40017 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40017 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE; + + end lut40017; + + architecture Structure of lut40017 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xF8F8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40018 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40018 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE; + + end lut40018; + + architecture Structure of lut40018 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCACA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_34 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_34 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_34"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_34 : ENTITY IS TRUE; + + end SLICE_34; + + architecture Structure of SLICE_34 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40017 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i78_2_lut_rep_24_3_lut: lut40017 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1259_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RCKEEN_401: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40019 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40019 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE; + + end lut40019; + + architecture Structure of lut40019 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xBBBB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40020 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40020 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE; + + end lut40020; + + architecture Structure of lut40020 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCFC8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_35 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_35 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_35"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE; + + end SLICE_35; + + architecture Structure of SLICE_35 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40020 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut: lut40019 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKE_I_0_449_4_lut: lut40020 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CASr2_383: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + RCKE_395: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_36 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_36 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_36"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE; + + end SLICE_36; + + architecture Structure of SLICE_36 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i771_2_lut_rep_26_2_lut: lut40015 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n2568_002_BUF1_BUF1: lut40010 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + Ready_404: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, + Q0_out, F1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40021 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40021 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE; + + end lut40021; + + architecture Structure of lut40021 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x3A0A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40022 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40022 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE; + + end lut40022; + + architecture Structure of lut40022 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xACAC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_43 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_43 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_43"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE; + + end SLICE_43; + + architecture Structure of SLICE_43 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40022 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i919_4_lut: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i886_3_lut: lut40022 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + UFMCLK_416: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40023 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40023 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE; + + end lut40023; + + architecture Structure of lut40023 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFEFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40024 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40024 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE; + + end lut40024; + + architecture Structure of lut40024 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xF202") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_44 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_44 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_44"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE; + + end SLICE_44; + + architecture Structure of SLICE_44 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40023 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_19_4_lut: lut40023 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + n2454_bdd_3_lut_4_lut: lut40024 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + UFMSDI_417: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40025 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40025 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE; + + end lut40025; + + architecture Structure of lut40025 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFEFA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40026 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40026 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE; + + end lut40026; + + architecture Structure of lut40026 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_49 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_49 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_49"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_49 : ENTITY IS TRUE; + + end SLICE_49; + + architecture Structure of SLICE_49 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40025 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2028_4_lut: lut40025 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut_adj_12: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + XOR8MEG_408: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40027 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40027 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE; + + end lut40027; + + architecture Structure of lut40027 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCCC5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_56 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_56 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_56"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE; + + end SLICE_56; + + architecture Structure of SLICE_56 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut_adj_4: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n8MEGEN_I_14_4_lut: lut40027 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + n8MEGEN_418: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40028 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40028 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE; + + end lut40028; + + architecture Structure of lut40028 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x7F2F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40029 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40029 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE; + + end lut40029; + + architecture Structure of lut40029 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xBFBF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0030 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vmuxregsre0030 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0030 : ENTITY IS TRUE; + + end vmuxregsre0030; + + architecture Structure of vmuxregsre0030 is + component FL1P3BX + generic (GSR: String); + port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; + CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; + Q: out Std_logic); + end component; + begin + INST01: FL1P3BX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); + end Structure; + +-- entity selmux2 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity selmux2 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE; + + end selmux2; + + architecture Structure of selmux2 is + component MUX21 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + begin + INST1: MUX21 + port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z); + end Structure; + +-- entity SLICE_58 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_58 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_58"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; + Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE; + + end SLICE_58; + + architecture Structure of SLICE_58 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal SLICE_58_SLICE_58_K1_H1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_58_i2095_GATE_H0: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0030 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + begin + SLICE_58_K1: lut40028 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>SLICE_58_SLICE_58_K1_H1); + i2095_GATE: lut40029 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, + Z=>SLICE_58_i2095_GATE_H0); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRCAS_398: vmuxregsre0030 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + SLICE_58_K0K1MUX: selmux2 + port map (D0=>SLICE_58_i2095_GATE_H0, D1=>SLICE_58_SLICE_58_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + OFX0_zd := OFX0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40031 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40031 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE; + + end lut40031; + + architecture Structure of lut40031 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFA88") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40032 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40032 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE; + + end lut40032; + + architecture Structure of lut40032 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCFDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_60 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_60 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_60"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE; + + end SLICE_60; + + architecture Structure of SLICE_60 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0030 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40031 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40032 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1234_4_lut_4_lut: lut40031 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut_adj_17: lut40032 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRCS_396: vmuxregsre0030 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40033 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40033 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE; + + end lut40033; + + architecture Structure of lut40033 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x7373") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40034 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40034 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE; + + end lut40034; + + architecture Structure of lut40034 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFFFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_61 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_61 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_61"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE; + + end SLICE_61; + + architecture Structure of SLICE_61 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal SLICE_61_SLICE_61_K1_H1: Std_logic; + signal SLICE_61_i16_GATE_H0: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0030 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + SLICE_61_K1: lut40033 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, + Z=>SLICE_61_SLICE_61_K1_H1); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i16_GATE: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>SLICE_61_i16_GATE_H0); + nRRAS_397: vmuxregsre0030 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + SLICE_61_K0K1MUX: selmux2 + port map (D0=>SLICE_61_i16_GATE_H0, D1=>SLICE_61_SLICE_61_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + OFX0_zd := OFX0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40035 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40035 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE; + + end lut40035; + + architecture Structure of lut40035 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFF7F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40036 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40036 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE; + + end lut40036; + + architecture Structure of lut40036 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCFC5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_63 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_63 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_63"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE; + + end SLICE_63; + + architecture Structure of SLICE_63 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0030 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40035 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40036 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_4_lut_adj_8: lut40035 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRWE_I_0_455_4_lut: lut40036 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRWE_399: vmuxregsre0030 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40037 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40037 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE; + + end lut40037; + + architecture Structure of lut40037 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCFEE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_64 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_64 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_64"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE; + + end SLICE_64; + + architecture Structure of SLICE_64 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i10_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_4_lut: lut40037 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRowColSel_402: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40038 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40038 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE; + + end lut40038; + + architecture Structure of lut40038 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_65 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_65 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_65"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE; + + end SLICE_65; + + architecture Structure of SLICE_65 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Ready_bdd_4_lut: lut40038 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_adj_25: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_FSM_i4: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40039 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40039 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE; + + end lut40039; + + architecture Structure of lut40039 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFFFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40040 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40040 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE; + + end lut40040; + + architecture Structure of lut40040 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x4444") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_66 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_66 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_66"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE; + + end SLICE_66; + + architecture Structure of SLICE_66 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_4_lut: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2057_2_lut: lut40040 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_FSM_i3: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40041 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40041 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE; + + end lut40041; + + architecture Structure of lut40041 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x3A3A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_67 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_67 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_67"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE; + + end SLICE_67; + + architecture Structure of SLICE_67 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40041 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1129_3_lut: lut40041 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_adj_23: lut40019 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + S_FSM_i2: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, + LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_68 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_68 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_68"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE; + + end SLICE_68; + + architecture Structure of SLICE_68 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal M0_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2024_2_lut_rep_28: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2026_4_lut: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CASr3_384: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + S_FSM_i1: vmuxregsre + port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + M0_INVERTERIN: inverter + port map (I=>M0_dly, Z=>M0_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40042 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40042 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE; + + end lut40042; + + architecture Structure of lut40042 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_69 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_69 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_69"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE; + + end SLICE_69; + + architecture Structure of SLICE_69 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i6_4_lut: lut40042 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i11_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nUFMCS_415: vmuxregsre0006 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40043 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40043 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE; + + end lut40043; + + architecture Structure of lut40043 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x1F1F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40044 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40044 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE; + + end lut40044; + + architecture Structure of lut40044 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x5540") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity RCKEEN_I_0_445_SLICE_70 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RCKEEN_I_0_445_SLICE_70 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCKEEN_I_0_445_SLICE_70"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RCKEEN_I_0_445_SLICE_70 : ENTITY IS TRUE; + + end RCKEEN_I_0_445_SLICE_70; + + architecture Structure of RCKEEN_I_0_445_SLICE_70 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_SLICE_70_K1_H1: Std_logic; + signal RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_GATE_H0: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40043 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40044 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RCKEEN_I_0_445_SLICE_70_K1: lut40043 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, + Z=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_SLICE_70_K1_H1); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKEEN_I_0_445_GATE: lut40044 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_GATE_H0); + RCKEEN_I_0_445_SLICE_70_K0K1MUX: selmux2 + port map (D0=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_GATE_H0, + D1=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_SLICE_70_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40045 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40045 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE; + + end lut40045; + + architecture Structure of lut40045 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40046 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40046 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE; + + end lut40046; + + architecture Structure of lut40046 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity i26_SLICE_71 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity i26_SLICE_71 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "i26_SLICE_71"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF i26_SLICE_71 : ENTITY IS TRUE; + + end i26_SLICE_71; + + architecture Structure of i26_SLICE_71 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal i26_SLICE_71_i26_SLICE_71_K1_H1: Std_logic; + signal i26_SLICE_71_i26_GATE_H0: Std_logic; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40045 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40046 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i26_SLICE_71_K1: lut40045 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>i26_SLICE_71_i26_SLICE_71_K1_H1); + i26_GATE: lut40046 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>i26_SLICE_71_i26_GATE_H0); + i26_SLICE_71_K0K1MUX: selmux2 + port map (D0=>i26_SLICE_71_i26_GATE_H0, + D1=>i26_SLICE_71_i26_SLICE_71_K1_H1, SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 8 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40047 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40047 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE; + + end lut40047; + + architecture Structure of lut40047 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2F23") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40048 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40048 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE; + + end lut40048; + + architecture Structure of lut40048 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2F2F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity i2099_SLICE_72 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity i2099_SLICE_72 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "i2099_SLICE_72"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF i2099_SLICE_72 : ENTITY IS TRUE; + + end i2099_SLICE_72; + + architecture Structure of i2099_SLICE_72 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal i2099_SLICE_72_i2099_SLICE_72_K1_H1: Std_logic; + signal GNDI: Std_logic; + signal i2099_SLICE_72_i2099_GATE_H0: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40047 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2099_SLICE_72_K1: lut40047 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>i2099_SLICE_72_i2099_SLICE_72_K1_H1); + i2099_GATE: lut40048 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, + Z=>i2099_SLICE_72_i2099_GATE_H0); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2099_SLICE_72_K0K1MUX: selmux2 + port map (D0=>i2099_SLICE_72_i2099_GATE_H0, + D1=>i2099_SLICE_72_i2099_SLICE_72_K1_H1, SD=>M0_ipd, + Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40049 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40049 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE; + + end lut40049; + + architecture Structure of lut40049 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x4000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40050 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40050 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE; + + end lut40050; + + architecture Structure of lut40050 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0002") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity i26_adj_28_SLICE_73 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity i26_adj_28_SLICE_73 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "i26_adj_28_SLICE_73"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF i26_adj_28_SLICE_73 : ENTITY IS TRUE; + + end i26_adj_28_SLICE_73; + + architecture Structure of i26_adj_28_SLICE_73 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal i26_adj_28_SLICE_73_i26_adj_28_SLICE_73_K1_H1: Std_logic; + signal i26_adj_28_SLICE_73_i26_adj_28_GATE_H0: Std_logic; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40049 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40050 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i26_adj_28_SLICE_73_K1: lut40049 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>i26_adj_28_SLICE_73_i26_adj_28_SLICE_73_K1_H1); + i26_adj_28_GATE: lut40050 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>i26_adj_28_SLICE_73_i26_adj_28_GATE_H0); + i26_adj_28_SLICE_73_K0K1MUX: selmux2 + port map (D0=>i26_adj_28_SLICE_73_i26_adj_28_GATE_H0, + D1=>i26_adj_28_SLICE_73_i26_adj_28_SLICE_73_K1_H1, SD=>M0_ipd, + Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 8 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40051 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40051 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE; + + end lut40051; + + architecture Structure of lut40051 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x1F10") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40052 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40052 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE; + + end lut40052; + + architecture Structure of lut40052 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0040") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_74 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_74 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_74"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE; + + end SLICE_74; + + architecture Structure of SLICE_74 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40051 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i35_3_lut_4_lut: lut40051 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut: lut40052 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RASr3_381: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RASr2_380: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40053 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40053 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE; + + end lut40053; + + architecture Structure of lut40053 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0200") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_75 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_75 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_75"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE; + + end SLICE_75; + + architecture Structure of SLICE_75 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40053 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i7_4_lut: lut40053 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40054 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40054 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE; + + end lut40054; + + architecture Structure of lut40054 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x1000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40055 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40055 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE; + + end lut40055; + + architecture Structure of lut40055 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xB300") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_76 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_76 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_76"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE; + + end SLICE_76; + + architecture Structure of SLICE_76 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40054 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40055 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i5_3_lut_rep_15_4_lut: lut40054 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut_4_lut: lut40055 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i9: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i8: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40056 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40056 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE; + + end lut40056; + + architecture Structure of lut40056 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_77 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_77 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_77"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE; + + end SLICE_77; + + architecture Structure of SLICE_77 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40056 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_4_lut_adj_18: lut40056 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1994_3_lut: lut40011 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i13: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i12: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40057 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40057 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE; + + end lut40057; + + architecture Structure of lut40057 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0101") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_78 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_78 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_78"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE; + + end SLICE_78; + + architecture Structure of SLICE_78 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40057 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i5_3_lut_rep_21_4_lut: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2065_2_lut_3_lut: lut40057 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowA_i7: vmuxregsre0003 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i6: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40058 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40058 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE; + + end lut40058; + + architecture Structure of lut40058 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0202") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40059 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40059 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE; + + end lut40059; + + architecture Structure of lut40059 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0400") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_79 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_79 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_79"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE; + + end SLICE_79; + + architecture Structure of SLICE_79 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal M0_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40058 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40059 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_25_3_lut: lut40058 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_4_lut: lut40059 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + PHI2r2_377: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CASr_382: vmuxregsre + port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + M0_INVERTERIN: inverter + port map (I=>M0_dly, Z=>M0_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40060 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40060 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE; + + end lut40060; + + architecture Structure of lut40060 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFFFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_80 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_80 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_80"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE; + + end SLICE_80; + + architecture Structure of SLICE_80 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40060 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_16: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_3_lut_4_lut_4_lut: lut40060 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i15: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i14: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40061 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40061 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE; + + end lut40061; + + architecture Structure of lut40061 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x8888") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40062 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40062 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE; + + end lut40062; + + architecture Structure of lut40062 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xBFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_81 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_81 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_81"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE; + + end SLICE_81; + + architecture Structure of SLICE_81 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40062 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1982_2_lut: lut40061 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i12_4_lut: lut40062 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdUFMCS_412: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + CmdUFMCLK_413: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40063 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40063 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE; + + end lut40063; + + architecture Structure of lut40063 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0302") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_82 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_82 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_82"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE; + + end SLICE_82; + + architecture Structure of SLICE_82 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40063 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2052_4_lut: lut40063 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1990_2_lut_rep_17: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i11: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i10: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_83 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_83 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_83"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE; + + end SLICE_83; + + architecture Structure of SLICE_83 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal M0_NOTIN: Std_logic; + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_4_lut: lut40008 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i4_4_lut: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RASr_379: vmuxregsre + port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + M0_INVERTERIN: inverter + port map (I=>M0_dly, Z=>M0_NOTIN); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_84 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_84 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_84"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE; + + end SLICE_84; + + architecture Structure of SLICE_84 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40056 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_4_lut_adj_11: lut40056 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_3_lut_adj_5: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_85 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_85 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_85"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE; + + end SLICE_85; + + architecture Structure of SLICE_85 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_4_lut_adj_15: lut40013 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2004_2_lut_rep_30: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RBA_i2: vmuxregsre0003 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RBA_i1: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40064 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40064 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE; + + end lut40064; + + architecture Structure of lut40064 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x1010") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_86 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_86 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_86"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE; + + end SLICE_86; + + architecture Structure of SLICE_86 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40064 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_adj_10: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_rep_20_3_lut: lut40064 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + IS_FSM_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40065 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40065 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE; + + end lut40065; + + architecture Structure of lut40065 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCAC0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_87 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_87 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_87"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE; + + end SLICE_87; + + architecture Structure of SLICE_87 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40065 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_2_lut: lut40040 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i17_4_lut: lut40065 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40066 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40066 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE; + + end lut40066; + + architecture Structure of lut40066 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0062") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_88 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_88 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_88"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE; + + end SLICE_88; + + architecture Structure of SLICE_88 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40066 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2452_bdd_2_lut_rep_18_3_lut: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_6_bdd_4_lut: lut40066 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Bank_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_89 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_89 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_89"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE; + + end SLICE_89; + + architecture Structure of SLICE_89 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40064 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_16_3_lut: lut40064 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_adj_1: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + WRD_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_90 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_90 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_90"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE; + + end SLICE_90; + + architecture Structure of SLICE_90 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2032_2_lut_3_lut_4_lut: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_2_lut_rep_27: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowA_i9: vmuxregsre0006 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i8: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40067 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40067 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE; + + end lut40067; + + architecture Structure of lut40067 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x8C00") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_91 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_91 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_91"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE; + + end SLICE_91; + + architecture Structure of SLICE_91 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40067 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_33: lut40061 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_4_lut_adj_3: lut40067 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + PHI2r_376: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + PHI2r3_378: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40068 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40068 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE; + + end lut40068; + + architecture Structure of lut40068 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2222") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40069 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40069 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE; + + end lut40069; + + architecture Structure of lut40069 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x4040") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_92 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_92 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_92"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE; + + end SLICE_92; + + architecture Structure of SLICE_92 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40068 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40069 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_32: lut40068 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_rep_31: lut40069 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + WRD_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40070 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40070 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE; + + end lut40070; + + architecture Structure of lut40070 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x7777") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_93 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_93 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_93"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE; + + end SLICE_93; + + architecture Structure of SLICE_93 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40070 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2060_2_lut: lut40070 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1512_2_lut: lut40019 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + CmdUFMSDI_414: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, CE_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_94 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_94 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_94"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE; + + end SLICE_94; + + architecture Structure of SLICE_94 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1976_2_lut: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i5_4_lut: lut40042 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40071 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40071 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE; + + end lut40071; + + architecture Structure of lut40071 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0001") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_95 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_95 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_95"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_95 : ENTITY IS TRUE; + + end SLICE_95; + + architecture Structure of SLICE_95 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40071 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_22: lut40061 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2055_3_lut_4_lut: lut40071 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i5: vmuxregsre0006 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i4: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_96 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_96 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_96"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_96 : ENTITY IS TRUE; + + end SLICE_96; + + architecture Structure of SLICE_96 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i4_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2020_4_lut: lut40042 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i3: vmuxregsre0003 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i2: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_97 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_97 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_97"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_97 : ENTITY IS TRUE; + + end SLICE_97; + + architecture Structure of SLICE_97 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i5_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2018_4_lut: lut40042 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i1: vmuxregsre0003 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i0: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_98 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_98 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_98"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_98 : ENTITY IS TRUE; + + end SLICE_98; + + architecture Structure of SLICE_98 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal M1_NOTIN: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal M0_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i1_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i9_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + FWEr_389: vmuxregsre + port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + M1_INVERTERIN: inverter + port map (I=>M1_dly, Z=>M1_NOTIN); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + CBR_390: vmuxregsre + port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + M0_INVERTERIN: inverter + port map (I=>M0_dly, Z=>M0_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_99 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_99 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_99"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_99 : ENTITY IS TRUE; + + end SLICE_99; + + architecture Structure of SLICE_99 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i2_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i8_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40072 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40072 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE; + + end lut40072; + + architecture Structure of lut40072 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xF0F7") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40073 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40073 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE; + + end lut40073; + + architecture Structure of lut40073 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x08FF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_100 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_100 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_100"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_100 : ENTITY IS TRUE; + + end SLICE_100; + + architecture Structure of SLICE_100 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40072 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40073 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_2_lut_3_lut_4_lut: lut40072 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_4_lut_adj_7: lut40073 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_101 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_101 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_101"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_101 : ENTITY IS TRUE; + + end SLICE_101; + + architecture Structure of SLICE_101 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i3_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i7_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_102 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_102 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_102"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_102 : ENTITY IS TRUE; + + end SLICE_102; + + architecture Structure of SLICE_102 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_26: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + InitReady_bdd_3_lut: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_103 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_103 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_103"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_103 : ENTITY IS TRUE; + + end SLICE_103; + + architecture Structure of SLICE_103 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i6_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_adj_14: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + WRD_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40074 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40074 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE; + + end lut40074; + + architecture Structure of lut40074 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xF0DD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_104 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_104 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_104"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_104 : ENTITY IS TRUE; + + end SLICE_104; + + architecture Structure of SLICE_104 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40074 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2414_bdd_2_lut: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n1_bdd_4_lut: lut40074 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40075 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40075 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE; + + end lut40075; + + architecture Structure of lut40075 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_105 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_105 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_105"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_105 : ENTITY IS TRUE; + + end SLICE_105; + + architecture Structure of SLICE_105 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40075 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1513_2_lut: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_adj_20: lut40075 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + WRD_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mjiobuf + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity mjiobuf is + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + + ATTRIBUTE Vital_Level0 OF mjiobuf : ENTITY IS TRUE; + + end mjiobuf; + + architecture Structure of mjiobuf is + component IBPU + port (I: in Std_logic; O: out Std_logic); + end component; + component OBZPU + port (I: in Std_logic; T: in Std_logic; O: out Std_logic); + end component; + begin + INST1: IBPU + port map (I=>PADI, O=>Z); + INST2: OBZPU + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity RD_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_7_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD7 : VitalDelayType := 0 ns; + tpw_RD7_posedge : VitalDelayType := 0 ns; + tpw_RD7_negedge : VitalDelayType := 0 ns; + tpd_RD7_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD7: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE; + + end RD_7_B; + + architecture Structure of RD_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD7_ipd : std_logic := 'X'; + signal RD7_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_7_713: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, + PADI=>RD7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD7_ipd, RD7, tipd_RD7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD7_zd : std_logic := 'X'; + VARIABLE RD7_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD7_RD7 : x01 := '0'; + VARIABLE periodcheckinfo_RD7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD7_ipd, + TestSignalName => "RD7", + Period => tperiod_RD7, + PulseWidthHigh => tpw_RD7_posedge, + PulseWidthLow => tpw_RD7_negedge, + PeriodData => periodcheckinfo_RD7, + Violation => tviol_RD7_RD7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD7_zd := RD7_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD7_ipd'last_event, + PathDelay => tpd_RD7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD7, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD7, + PathCondition => TRUE)), + GlitchData => RD7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_6_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD6 : VitalDelayType := 0 ns; + tpw_RD6_posedge : VitalDelayType := 0 ns; + tpw_RD6_negedge : VitalDelayType := 0 ns; + tpd_RD6_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD6: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE; + + end RD_6_B; + + architecture Structure of RD_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD6_ipd : std_logic := 'X'; + signal RD6_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_6_714: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, + PADI=>RD6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD6_ipd, RD6, tipd_RD6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD6_zd : std_logic := 'X'; + VARIABLE RD6_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD6_RD6 : x01 := '0'; + VARIABLE periodcheckinfo_RD6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD6_ipd, + TestSignalName => "RD6", + Period => tperiod_RD6, + PulseWidthHigh => tpw_RD6_posedge, + PulseWidthLow => tpw_RD6_negedge, + PeriodData => periodcheckinfo_RD6, + Violation => tviol_RD6_RD6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD6_zd := RD6_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD6_ipd'last_event, + PathDelay => tpd_RD6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD6, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD6, + PathCondition => TRUE)), + GlitchData => RD6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_5_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD5 : VitalDelayType := 0 ns; + tpw_RD5_posedge : VitalDelayType := 0 ns; + tpw_RD5_negedge : VitalDelayType := 0 ns; + tpd_RD5_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD5: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE; + + end RD_5_B; + + architecture Structure of RD_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD5_ipd : std_logic := 'X'; + signal RD5_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_5_715: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, + PADI=>RD5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD5_ipd, RD5, tipd_RD5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD5_zd : std_logic := 'X'; + VARIABLE RD5_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD5_RD5 : x01 := '0'; + VARIABLE periodcheckinfo_RD5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD5_ipd, + TestSignalName => "RD5", + Period => tperiod_RD5, + PulseWidthHigh => tpw_RD5_posedge, + PulseWidthLow => tpw_RD5_negedge, + PeriodData => periodcheckinfo_RD5, + Violation => tviol_RD5_RD5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD5_zd := RD5_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD5_ipd'last_event, + PathDelay => tpd_RD5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD5, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD5, + PathCondition => TRUE)), + GlitchData => RD5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_4_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD4 : VitalDelayType := 0 ns; + tpw_RD4_posedge : VitalDelayType := 0 ns; + tpw_RD4_negedge : VitalDelayType := 0 ns; + tpd_RD4_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD4: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE; + + end RD_4_B; + + architecture Structure of RD_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD4_ipd : std_logic := 'X'; + signal RD4_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_4_716: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, + PADI=>RD4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD4_ipd, RD4, tipd_RD4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD4_zd : std_logic := 'X'; + VARIABLE RD4_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD4_RD4 : x01 := '0'; + VARIABLE periodcheckinfo_RD4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD4_ipd, + TestSignalName => "RD4", + Period => tperiod_RD4, + PulseWidthHigh => tpw_RD4_posedge, + PulseWidthLow => tpw_RD4_negedge, + PeriodData => periodcheckinfo_RD4, + Violation => tviol_RD4_RD4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD4_zd := RD4_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD4_ipd'last_event, + PathDelay => tpd_RD4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD4, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD4, + PathCondition => TRUE)), + GlitchData => RD4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_3_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD3 : VitalDelayType := 0 ns; + tpw_RD3_posedge : VitalDelayType := 0 ns; + tpw_RD3_negedge : VitalDelayType := 0 ns; + tpd_RD3_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD3: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE; + + end RD_3_B; + + architecture Structure of RD_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD3_ipd : std_logic := 'X'; + signal RD3_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_3_717: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, + PADI=>RD3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD3_ipd, RD3, tipd_RD3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD3_zd : std_logic := 'X'; + VARIABLE RD3_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD3_RD3 : x01 := '0'; + VARIABLE periodcheckinfo_RD3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD3_ipd, + TestSignalName => "RD3", + Period => tperiod_RD3, + PulseWidthHigh => tpw_RD3_posedge, + PulseWidthLow => tpw_RD3_negedge, + PeriodData => periodcheckinfo_RD3, + Violation => tviol_RD3_RD3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD3_zd := RD3_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD3_ipd'last_event, + PathDelay => tpd_RD3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD3, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD3, + PathCondition => TRUE)), + GlitchData => RD3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_2_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD2 : VitalDelayType := 0 ns; + tpw_RD2_posedge : VitalDelayType := 0 ns; + tpw_RD2_negedge : VitalDelayType := 0 ns; + tpd_RD2_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD2: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE; + + end RD_2_B; + + architecture Structure of RD_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD2_ipd : std_logic := 'X'; + signal RD2_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_2_718: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, + PADI=>RD2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD2_ipd, RD2, tipd_RD2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD2_zd : std_logic := 'X'; + VARIABLE RD2_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD2_RD2 : x01 := '0'; + VARIABLE periodcheckinfo_RD2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD2_ipd, + TestSignalName => "RD2", + Period => tperiod_RD2, + PulseWidthHigh => tpw_RD2_posedge, + PulseWidthLow => tpw_RD2_negedge, + PeriodData => periodcheckinfo_RD2, + Violation => tviol_RD2_RD2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD2_zd := RD2_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD2_ipd'last_event, + PathDelay => tpd_RD2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD2, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD2, + PathCondition => TRUE)), + GlitchData => RD2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_1_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD1 : VitalDelayType := 0 ns; + tpw_RD1_posedge : VitalDelayType := 0 ns; + tpw_RD1_negedge : VitalDelayType := 0 ns; + tpd_RD1_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD1: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE; + + end RD_1_B; + + architecture Structure of RD_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD1_ipd : std_logic := 'X'; + signal RD1_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_1_719: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, + PADI=>RD1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD1_ipd, RD1, tipd_RD1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD1_zd : std_logic := 'X'; + VARIABLE RD1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD1_RD1 : x01 := '0'; + VARIABLE periodcheckinfo_RD1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD1_ipd, + TestSignalName => "RD1", + Period => tperiod_RD1, + PulseWidthHigh => tpw_RD1_posedge, + PulseWidthLow => tpw_RD1_negedge, + PeriodData => periodcheckinfo_RD1, + Violation => tviol_RD1_RD1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD1_zd := RD1_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD1_ipd'last_event, + PathDelay => tpd_RD1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD1, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD1, + PathCondition => TRUE)), + GlitchData => RD1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_0_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD0 : VitalDelayType := 0 ns; + tpw_RD0_posedge : VitalDelayType := 0 ns; + tpw_RD0_negedge : VitalDelayType := 0 ns; + tpd_RD0_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD0: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE; + + end RD_0_B; + + architecture Structure of RD_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD0_ipd : std_logic := 'X'; + signal RD0_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_0_720: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, + PADI=>RD0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD0_ipd, RD0, tipd_RD0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD0_zd : std_logic := 'X'; + VARIABLE RD0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD0_RD0 : x01 := '0'; + VARIABLE periodcheckinfo_RD0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD0_ipd, + TestSignalName => "RD0", + Period => tperiod_RD0, + PulseWidthHigh => tpw_RD0_posedge, + PulseWidthLow => tpw_RD0_negedge, + PeriodData => periodcheckinfo_RD0, + Violation => tviol_RD0_RD0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD0_zd := RD0_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD0_ipd'last_event, + PathDelay => tpd_RD0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD0, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD0, + PathCondition => TRUE)), + GlitchData => RD0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mjiobuf0076 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity mjiobuf0076 is + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + + ATTRIBUTE Vital_Level0 OF mjiobuf0076 : ENTITY IS TRUE; + + end mjiobuf0076; + + architecture Structure of mjiobuf0076 is + component OBZPU + port (I: in Std_logic; T: in Std_logic; O: out Std_logic); + end component; + begin + INST5: OBZPU + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity Dout_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE; + + end Dout_7_B; + + architecture Structure of Dout_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout7_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_7: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout7_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout7_out) + VARIABLE Dout7_zd : std_logic := 'X'; + VARIABLE Dout7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout7_zd := Dout7_out; + + VitalPathDelay01Z ( + OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout7, + PathCondition => TRUE)), + GlitchData => Dout7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE; + + end Dout_6_B; + + architecture Structure of Dout_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout6_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_6: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout6_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout6_out) + VARIABLE Dout6_zd : std_logic := 'X'; + VARIABLE Dout6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout6_zd := Dout6_out; + + VitalPathDelay01Z ( + OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout6, + PathCondition => TRUE)), + GlitchData => Dout6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE; + + end Dout_5_B; + + architecture Structure of Dout_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout5_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_5: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout5_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout5_out) + VARIABLE Dout5_zd : std_logic := 'X'; + VARIABLE Dout5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout5_zd := Dout5_out; + + VitalPathDelay01Z ( + OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout5, + PathCondition => TRUE)), + GlitchData => Dout5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE; + + end Dout_4_B; + + architecture Structure of Dout_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout4_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_4: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout4_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout4_out) + VARIABLE Dout4_zd : std_logic := 'X'; + VARIABLE Dout4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout4_zd := Dout4_out; + + VitalPathDelay01Z ( + OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout4, + PathCondition => TRUE)), + GlitchData => Dout4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE; + + end Dout_3_B; + + architecture Structure of Dout_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout3_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_3: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout3_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout3_out) + VARIABLE Dout3_zd : std_logic := 'X'; + VARIABLE Dout3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout3_zd := Dout3_out; + + VitalPathDelay01Z ( + OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout3, + PathCondition => TRUE)), + GlitchData => Dout3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE; + + end Dout_2_B; + + architecture Structure of Dout_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout2_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_2: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout2_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout2_out) + VARIABLE Dout2_zd : std_logic := 'X'; + VARIABLE Dout2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout2_zd := Dout2_out; + + VitalPathDelay01Z ( + OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout2, + PathCondition => TRUE)), + GlitchData => Dout2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE; + + end Dout_1_B; + + architecture Structure of Dout_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_1: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout1_out) + VARIABLE Dout1_zd : std_logic := 'X'; + VARIABLE Dout1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout1_zd := Dout1_out; + + VitalPathDelay01Z ( + OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout1, + PathCondition => TRUE)), + GlitchData => Dout1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE; + + end Dout_0_B; + + architecture Structure of Dout_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_0: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout0_out) + VARIABLE Dout0_zd : std_logic := 'X'; + VARIABLE Dout0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout0_zd := Dout0_out; + + VitalPathDelay01Z ( + OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout0, + PathCondition => TRUE)), + GlitchData => Dout0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity LEDB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity LEDB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "LEDB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_LEDS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; LEDS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE; + + end LEDB; + + architecture Structure of LEDB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal LEDS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + LED_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>LEDS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, LEDS_out) + VARIABLE LEDS_zd : std_logic := 'X'; + VARIABLE LEDS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + LEDS_zd := LEDS_out; + + VitalPathDelay01Z ( + OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_LEDS, + PathCondition => TRUE)), + GlitchData => LEDS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RBA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RBA1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RBA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE; + + end RBA_1_B; + + architecture Structure of RBA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RBA1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_1: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RBA1_out) + VARIABLE RBA1_zd : std_logic := 'X'; + VARIABLE RBA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA1_zd := RBA1_out; + + VitalPathDelay01Z ( + OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RBA1, + PathCondition => TRUE)), + GlitchData => RBA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RBA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RBA0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RBA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE; + + end RBA_0_B; + + architecture Structure of RBA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RBA0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_0: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RBA0_out) + VARIABLE RBA0_zd : std_logic := 'X'; + VARIABLE RBA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA0_zd := RBA0_out; + + VitalPathDelay01Z ( + OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RBA0, + PathCondition => TRUE)), + GlitchData => RBA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_11_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_11_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_11_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA11 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RA11: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE; + + end RA_11_B; + + architecture Structure of RA_11_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA11_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_11: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA11_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA11_out) + VARIABLE RA11_zd : std_logic := 'X'; + VARIABLE RA11_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA11_zd := RA11_out; + + VitalPathDelay01Z ( + OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA11, + PathCondition => TRUE)), + GlitchData => RA11_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_10_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_10_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_10_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA10 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RA10: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE; + + end RA_10_B; + + architecture Structure of RA_10_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA10_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_10: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA10_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA10_out) + VARIABLE RA10_zd : std_logic := 'X'; + VARIABLE RA10_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA10_zd := RA10_out; + + VitalPathDelay01Z ( + OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA10, + PathCondition => TRUE)), + GlitchData => RA10_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_9_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_9_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA9 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA9: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE; + + end RA_9_B; + + architecture Structure of RA_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA9_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_9: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA9_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA9_out) + VARIABLE RA9_zd : std_logic := 'X'; + VARIABLE RA9_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA9_zd := RA9_out; + + VitalPathDelay01Z ( + OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA9, + PathCondition => TRUE)), + GlitchData => RA9_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_8_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_8_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA8 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA8: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE; + + end RA_8_B; + + architecture Structure of RA_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA8_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_8: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA8_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA8_out) + VARIABLE RA8_zd : std_logic := 'X'; + VARIABLE RA8_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA8_zd := RA8_out; + + VitalPathDelay01Z ( + OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA8, + PathCondition => TRUE)), + GlitchData => RA8_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE; + + end RA_7_B; + + architecture Structure of RA_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA7_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_7: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA7_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA7_out) + VARIABLE RA7_zd : std_logic := 'X'; + VARIABLE RA7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA7_zd := RA7_out; + + VitalPathDelay01Z ( + OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA7, + PathCondition => TRUE)), + GlitchData => RA7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE; + + end RA_6_B; + + architecture Structure of RA_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA6_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_6: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA6_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA6_out) + VARIABLE RA6_zd : std_logic := 'X'; + VARIABLE RA6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA6_zd := RA6_out; + + VitalPathDelay01Z ( + OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA6, + PathCondition => TRUE)), + GlitchData => RA6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE; + + end RA_5_B; + + architecture Structure of RA_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA5_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_5: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA5_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA5_out) + VARIABLE RA5_zd : std_logic := 'X'; + VARIABLE RA5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA5_zd := RA5_out; + + VitalPathDelay01Z ( + OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA5, + PathCondition => TRUE)), + GlitchData => RA5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE; + + end RA_4_B; + + architecture Structure of RA_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA4_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_4: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA4_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA4_out) + VARIABLE RA4_zd : std_logic := 'X'; + VARIABLE RA4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA4_zd := RA4_out; + + VitalPathDelay01Z ( + OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA4, + PathCondition => TRUE)), + GlitchData => RA4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE; + + end RA_3_B; + + architecture Structure of RA_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA3_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_3: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA3_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA3_out) + VARIABLE RA3_zd : std_logic := 'X'; + VARIABLE RA3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA3_zd := RA3_out; + + VitalPathDelay01Z ( + OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA3, + PathCondition => TRUE)), + GlitchData => RA3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE; + + end RA_2_B; + + architecture Structure of RA_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA2_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_2: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA2_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA2_out) + VARIABLE RA2_zd : std_logic := 'X'; + VARIABLE RA2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA2_zd := RA2_out; + + VitalPathDelay01Z ( + OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA2, + PathCondition => TRUE)), + GlitchData => RA2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE; + + end RA_1_B; + + architecture Structure of RA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_1: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA1_out) + VARIABLE RA1_zd : std_logic := 'X'; + VARIABLE RA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA1_zd := RA1_out; + + VitalPathDelay01Z ( + OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA1, + PathCondition => TRUE)), + GlitchData => RA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE; + + end RA_0_B; + + architecture Structure of RA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_0: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA0_out) + VARIABLE RA0_zd : std_logic := 'X'; + VARIABLE RA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA0_zd := RA0_out; + + VitalPathDelay01Z ( + OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA0, + PathCondition => TRUE)), + GlitchData => RA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCSB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nRCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCSB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRCSS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nRCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE; + + end nRCSB; + + architecture Structure of nRCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRCSS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCS_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCSS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out) + VARIABLE nRCSS_zd : std_logic := 'X'; + VARIABLE nRCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCSS_zd := nRCSS_out; + + VitalPathDelay01Z ( + OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRCSS, + PathCondition => TRUE)), + GlitchData => nRCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCKEB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RCKEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCKEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RCKES : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RCKES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE; + + end RCKEB; + + architecture Structure of RCKEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RCKES_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RCKE_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RCKES_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RCKES_out) + VARIABLE RCKES_zd : std_logic := 'X'; + VARIABLE RCKES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RCKES_zd := RCKES_out; + + VitalPathDelay01Z ( + OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RCKES, + PathCondition => TRUE)), + GlitchData => RCKES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRWEB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nRWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRWEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRWES : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nRWES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE; + + end nRWEB; + + architecture Structure of nRWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRWES_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRWE_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRWES_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRWES_out) + VARIABLE nRWES_zd : std_logic := 'X'; + VARIABLE nRWES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRWES_zd := nRWES_out; + + VitalPathDelay01Z ( + OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRWES, + PathCondition => TRUE)), + GlitchData => nRWES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRRASB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nRRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRRASB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRRASS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nRRASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE; + + end nRRASB; + + architecture Structure of nRRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRRASS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRRAS_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRRASS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out) + VARIABLE nRRASS_zd : std_logic := 'X'; + VARIABLE nRRASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRRASS_zd := nRRASS_out; + + VitalPathDelay01Z ( + OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRRASS, + PathCondition => TRUE)), + GlitchData => nRRASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCASB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nRCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCASB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRCASS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nRCASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE; + + end nRCASB; + + architecture Structure of nRCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRCASS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCAS_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCASS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out) + VARIABLE nRCASS_zd : std_logic := 'X'; + VARIABLE nRCASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCASS_zd := nRCASS_out; + + VitalPathDelay01Z ( + OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRCASS, + PathCondition => TRUE)), + GlitchData => nRCASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMHB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RDQMHB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMHB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMHS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE; + + end RDQMHB; + + architecture Structure of RDQMHB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMHS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQMH_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMHS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out) + VARIABLE RDQMHS_zd : std_logic := 'X'; + VARIABLE RDQMHS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMHS_zd := RDQMHS_out; + + VitalPathDelay01Z ( + OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMHS, + PathCondition => TRUE)), + GlitchData => RDQMHS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMLB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RDQMLB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMLB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMLS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE; + + end RDQMLB; + + architecture Structure of RDQMLB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMLS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQML_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMLS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out) + VARIABLE RDQMLS_zd : std_logic := 'X'; + VARIABLE RDQMLS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMLS_zd := RDQMLS_out; + + VitalPathDelay01Z ( + OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMLS, + PathCondition => TRUE)), + GlitchData => RDQMLS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nUFMCSB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nUFMCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nUFMCSB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + + tpd_PADDO_nUFMCSS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE; + + end nUFMCSB; + + architecture Structure of nUFMCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nUFMCSS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nUFMCS_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nUFMCSS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out) + VARIABLE nUFMCSS_zd : std_logic := 'X'; + VARIABLE nUFMCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nUFMCSS_zd := nUFMCSS_out; + + VitalPathDelay01Z ( + OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nUFMCSS, + PathCondition => TRUE)), + GlitchData => nUFMCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMCLKB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity UFMCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMCLKB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + + tpd_PADDO_UFMCLKS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE; + + end UFMCLKB; + + architecture Structure of UFMCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal UFMCLKS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMCLK_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMCLKS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out) + VARIABLE UFMCLKS_zd : std_logic := 'X'; + VARIABLE UFMCLKS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMCLKS_zd := UFMCLKS_out; + + VitalPathDelay01Z ( + OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_UFMCLKS, + PathCondition => TRUE)), + GlitchData => UFMCLKS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDIB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity UFMSDIB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDIB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + + tpd_PADDO_UFMSDIS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE; + + end UFMSDIB; + + architecture Structure of UFMSDIB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal UFMSDIS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMSDI_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMSDIS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out) + VARIABLE UFMSDIS_zd : std_logic := 'X'; + VARIABLE UFMSDIS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMSDIS_zd := UFMSDIS_out; + + VitalPathDelay01Z ( + OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_UFMSDIS, + PathCondition => TRUE)), + GlitchData => UFMSDIS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mjiobuf0077 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity mjiobuf0077 is + port (Z: out Std_logic; PAD: in Std_logic); + + ATTRIBUTE Vital_Level0 OF mjiobuf0077 : ENTITY IS TRUE; + + end mjiobuf0077; + + architecture Structure of mjiobuf0077 is + component IBPU + port (I: in Std_logic; O: out Std_logic); + end component; + begin + INST1: IBPU + port map (I=>PAD, O=>Z); + end Structure; + +-- entity PHI2B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity PHI2B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "PHI2B"; + + tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns); + tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_PHI2S : VitalDelayType := 0 ns; + tpw_PHI2S_posedge : VitalDelayType := 0 ns; + tpw_PHI2S_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; PHI2S: in Std_logic); + + ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE; + + end PHI2B; + + architecture Structure of PHI2B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PHI2S_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + PHI2_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>PHI2S_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_PHI2S_PHI2S : x01 := '0'; + VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => PHI2S_ipd, + TestSignalName => "PHI2S", + Period => tperiod_PHI2S, + PulseWidthHigh => tpw_PHI2S_posedge, + PulseWidthLow => tpw_PHI2S_negedge, + PeriodData => periodcheckinfo_PHI2S, + Violation => tviol_PHI2S_PHI2S, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event, + PathDelay => tpd_PHI2S_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_9_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_9_B"; + + tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin9 : VitalDelayType := 0 ns; + tpw_MAin9_posedge : VitalDelayType := 0 ns; + tpw_MAin9_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin9: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE; + + end MAin_9_B; + + architecture Structure of MAin_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin9_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_9: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin9_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin9_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin9_MAin9 : x01 := '0'; + VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin9_ipd, + TestSignalName => "MAin9", + Period => tperiod_MAin9, + PulseWidthHigh => tpw_MAin9_posedge, + PulseWidthLow => tpw_MAin9_negedge, + PeriodData => periodcheckinfo_MAin9, + Violation => tviol_MAin9_MAin9, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin9_ipd'last_event, + PathDelay => tpd_MAin9_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_8_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_8_B"; + + tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin8 : VitalDelayType := 0 ns; + tpw_MAin8_posedge : VitalDelayType := 0 ns; + tpw_MAin8_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin8: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE; + + end MAin_8_B; + + architecture Structure of MAin_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin8_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_8: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin8_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin8_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin8_MAin8 : x01 := '0'; + VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin8_ipd, + TestSignalName => "MAin8", + Period => tperiod_MAin8, + PulseWidthHigh => tpw_MAin8_posedge, + PulseWidthLow => tpw_MAin8_negedge, + PeriodData => periodcheckinfo_MAin8, + Violation => tviol_MAin8_MAin8, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin8_ipd'last_event, + PathDelay => tpd_MAin8_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_7_B"; + + tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin7 : VitalDelayType := 0 ns; + tpw_MAin7_posedge : VitalDelayType := 0 ns; + tpw_MAin7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE; + + end MAin_7_B; + + architecture Structure of MAin_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin7_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_7: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin7_MAin7 : x01 := '0'; + VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin7_ipd, + TestSignalName => "MAin7", + Period => tperiod_MAin7, + PulseWidthHigh => tpw_MAin7_posedge, + PulseWidthLow => tpw_MAin7_negedge, + PeriodData => periodcheckinfo_MAin7, + Violation => tviol_MAin7_MAin7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin7_ipd'last_event, + PathDelay => tpd_MAin7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_6_B"; + + tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin6 : VitalDelayType := 0 ns; + tpw_MAin6_posedge : VitalDelayType := 0 ns; + tpw_MAin6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE; + + end MAin_6_B; + + architecture Structure of MAin_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin6_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_6: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin6_MAin6 : x01 := '0'; + VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin6_ipd, + TestSignalName => "MAin6", + Period => tperiod_MAin6, + PulseWidthHigh => tpw_MAin6_posedge, + PulseWidthLow => tpw_MAin6_negedge, + PeriodData => periodcheckinfo_MAin6, + Violation => tviol_MAin6_MAin6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin6_ipd'last_event, + PathDelay => tpd_MAin6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_5_B"; + + tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin5 : VitalDelayType := 0 ns; + tpw_MAin5_posedge : VitalDelayType := 0 ns; + tpw_MAin5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE; + + end MAin_5_B; + + architecture Structure of MAin_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin5_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_5: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin5_MAin5 : x01 := '0'; + VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin5_ipd, + TestSignalName => "MAin5", + Period => tperiod_MAin5, + PulseWidthHigh => tpw_MAin5_posedge, + PulseWidthLow => tpw_MAin5_negedge, + PeriodData => periodcheckinfo_MAin5, + Violation => tviol_MAin5_MAin5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin5_ipd'last_event, + PathDelay => tpd_MAin5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_4_B"; + + tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin4 : VitalDelayType := 0 ns; + tpw_MAin4_posedge : VitalDelayType := 0 ns; + tpw_MAin4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE; + + end MAin_4_B; + + architecture Structure of MAin_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin4_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_4: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin4_MAin4 : x01 := '0'; + VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin4_ipd, + TestSignalName => "MAin4", + Period => tperiod_MAin4, + PulseWidthHigh => tpw_MAin4_posedge, + PulseWidthLow => tpw_MAin4_negedge, + PeriodData => periodcheckinfo_MAin4, + Violation => tviol_MAin4_MAin4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin4_ipd'last_event, + PathDelay => tpd_MAin4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_3_B"; + + tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin3 : VitalDelayType := 0 ns; + tpw_MAin3_posedge : VitalDelayType := 0 ns; + tpw_MAin3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE; + + end MAin_3_B; + + architecture Structure of MAin_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin3_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_3: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin3_MAin3 : x01 := '0'; + VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin3_ipd, + TestSignalName => "MAin3", + Period => tperiod_MAin3, + PulseWidthHigh => tpw_MAin3_posedge, + PulseWidthLow => tpw_MAin3_negedge, + PeriodData => periodcheckinfo_MAin3, + Violation => tviol_MAin3_MAin3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin3_ipd'last_event, + PathDelay => tpd_MAin3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_2_B"; + + tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin2 : VitalDelayType := 0 ns; + tpw_MAin2_posedge : VitalDelayType := 0 ns; + tpw_MAin2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE; + + end MAin_2_B; + + architecture Structure of MAin_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin2_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_2: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin2_MAin2 : x01 := '0'; + VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin2_ipd, + TestSignalName => "MAin2", + Period => tperiod_MAin2, + PulseWidthHigh => tpw_MAin2_posedge, + PulseWidthLow => tpw_MAin2_negedge, + PeriodData => periodcheckinfo_MAin2, + Violation => tviol_MAin2_MAin2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin2_ipd'last_event, + PathDelay => tpd_MAin2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_1_B"; + + tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin1 : VitalDelayType := 0 ns; + tpw_MAin1_posedge : VitalDelayType := 0 ns; + tpw_MAin1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE; + + end MAin_1_B; + + architecture Structure of MAin_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin1_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_1: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin1_MAin1 : x01 := '0'; + VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin1_ipd, + TestSignalName => "MAin1", + Period => tperiod_MAin1, + PulseWidthHigh => tpw_MAin1_posedge, + PulseWidthLow => tpw_MAin1_negedge, + PeriodData => periodcheckinfo_MAin1, + Violation => tviol_MAin1_MAin1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin1_ipd'last_event, + PathDelay => tpd_MAin1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_0_B"; + + tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin0 : VitalDelayType := 0 ns; + tpw_MAin0_posedge : VitalDelayType := 0 ns; + tpw_MAin0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE; + + end MAin_0_B; + + architecture Structure of MAin_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin0_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_0: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin0_MAin0 : x01 := '0'; + VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin0_ipd, + TestSignalName => "MAin0", + Period => tperiod_MAin0, + PulseWidthHigh => tpw_MAin0_posedge, + PulseWidthLow => tpw_MAin0_negedge, + PeriodData => periodcheckinfo_MAin0, + Violation => tviol_MAin0_MAin0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin0_ipd'last_event, + PathDelay => tpd_MAin0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity CROW_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_1_B"; + + tipd_CROW1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW1 : VitalDelayType := 0 ns; + tpw_CROW1_posedge : VitalDelayType := 0 ns; + tpw_CROW1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE; + + end CROW_1_B; + + architecture Structure of CROW_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW1_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_1: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>CROW1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW1_CROW1 : x01 := '0'; + VARIABLE periodcheckinfo_CROW1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW1_ipd, + TestSignalName => "CROW1", + Period => tperiod_CROW1, + PulseWidthHigh => tpw_CROW1_posedge, + PulseWidthLow => tpw_CROW1_negedge, + PeriodData => periodcheckinfo_CROW1, + Violation => tviol_CROW1_CROW1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW1_ipd'last_event, + PathDelay => tpd_CROW1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity CROW_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_0_B"; + + tipd_CROW0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW0 : VitalDelayType := 0 ns; + tpw_CROW0_posedge : VitalDelayType := 0 ns; + tpw_CROW0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE; + + end CROW_0_B; + + architecture Structure of CROW_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW0_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_0: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>CROW0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW0_CROW0 : x01 := '0'; + VARIABLE periodcheckinfo_CROW0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW0_ipd, + TestSignalName => "CROW0", + Period => tperiod_CROW0, + PulseWidthHigh => tpw_CROW0_posedge, + PulseWidthLow => tpw_CROW0_negedge, + PeriodData => periodcheckinfo_CROW0, + Violation => tviol_CROW0_CROW0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW0_ipd'last_event, + PathDelay => tpd_CROW0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_7_B"; + + tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din7 : VitalDelayType := 0 ns; + tpw_Din7_posedge : VitalDelayType := 0 ns; + tpw_Din7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE; + + end Din_7_B; + + architecture Structure of Din_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din7_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_7: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din7_ipd, Din7, tipd_Din7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din7_Din7 : x01 := '0'; + VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din7_ipd, + TestSignalName => "Din7", + Period => tperiod_Din7, + PulseWidthHigh => tpw_Din7_posedge, + PulseWidthLow => tpw_Din7_negedge, + PeriodData => periodcheckinfo_Din7, + Violation => tviol_Din7_Din7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din7_ipd'last_event, + PathDelay => tpd_Din7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_6_B"; + + tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din6 : VitalDelayType := 0 ns; + tpw_Din6_posedge : VitalDelayType := 0 ns; + tpw_Din6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE; + + end Din_6_B; + + architecture Structure of Din_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din6_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_6: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din6_ipd, Din6, tipd_Din6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din6_Din6 : x01 := '0'; + VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din6_ipd, + TestSignalName => "Din6", + Period => tperiod_Din6, + PulseWidthHigh => tpw_Din6_posedge, + PulseWidthLow => tpw_Din6_negedge, + PeriodData => periodcheckinfo_Din6, + Violation => tviol_Din6_Din6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din6_ipd'last_event, + PathDelay => tpd_Din6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_5_B"; + + tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din5 : VitalDelayType := 0 ns; + tpw_Din5_posedge : VitalDelayType := 0 ns; + tpw_Din5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE; + + end Din_5_B; + + architecture Structure of Din_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din5_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_5: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din5_ipd, Din5, tipd_Din5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din5_Din5 : x01 := '0'; + VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din5_ipd, + TestSignalName => "Din5", + Period => tperiod_Din5, + PulseWidthHigh => tpw_Din5_posedge, + PulseWidthLow => tpw_Din5_negedge, + PeriodData => periodcheckinfo_Din5, + Violation => tviol_Din5_Din5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din5_ipd'last_event, + PathDelay => tpd_Din5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_4_B"; + + tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din4 : VitalDelayType := 0 ns; + tpw_Din4_posedge : VitalDelayType := 0 ns; + tpw_Din4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE; + + end Din_4_B; + + architecture Structure of Din_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din4_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_4: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din4_ipd, Din4, tipd_Din4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din4_Din4 : x01 := '0'; + VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din4_ipd, + TestSignalName => "Din4", + Period => tperiod_Din4, + PulseWidthHigh => tpw_Din4_posedge, + PulseWidthLow => tpw_Din4_negedge, + PeriodData => periodcheckinfo_Din4, + Violation => tviol_Din4_Din4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din4_ipd'last_event, + PathDelay => tpd_Din4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_3_B"; + + tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din3 : VitalDelayType := 0 ns; + tpw_Din3_posedge : VitalDelayType := 0 ns; + tpw_Din3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE; + + end Din_3_B; + + architecture Structure of Din_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din3_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_3: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din3_ipd, Din3, tipd_Din3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din3_Din3 : x01 := '0'; + VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din3_ipd, + TestSignalName => "Din3", + Period => tperiod_Din3, + PulseWidthHigh => tpw_Din3_posedge, + PulseWidthLow => tpw_Din3_negedge, + PeriodData => periodcheckinfo_Din3, + Violation => tviol_Din3_Din3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din3_ipd'last_event, + PathDelay => tpd_Din3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_2_B"; + + tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din2 : VitalDelayType := 0 ns; + tpw_Din2_posedge : VitalDelayType := 0 ns; + tpw_Din2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE; + + end Din_2_B; + + architecture Structure of Din_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din2_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_2: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din2_ipd, Din2, tipd_Din2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din2_Din2 : x01 := '0'; + VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din2_ipd, + TestSignalName => "Din2", + Period => tperiod_Din2, + PulseWidthHigh => tpw_Din2_posedge, + PulseWidthLow => tpw_Din2_negedge, + PeriodData => periodcheckinfo_Din2, + Violation => tviol_Din2_Din2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din2_ipd'last_event, + PathDelay => tpd_Din2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_1_B"; + + tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din1 : VitalDelayType := 0 ns; + tpw_Din1_posedge : VitalDelayType := 0 ns; + tpw_Din1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE; + + end Din_1_B; + + architecture Structure of Din_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din1_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_1: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din1_ipd, Din1, tipd_Din1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din1_Din1 : x01 := '0'; + VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din1_ipd, + TestSignalName => "Din1", + Period => tperiod_Din1, + PulseWidthHigh => tpw_Din1_posedge, + PulseWidthLow => tpw_Din1_negedge, + PeriodData => periodcheckinfo_Din1, + Violation => tviol_Din1_Din1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din1_ipd'last_event, + PathDelay => tpd_Din1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_0_B"; + + tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din0 : VitalDelayType := 0 ns; + tpw_Din0_posedge : VitalDelayType := 0 ns; + tpw_Din0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE; + + end Din_0_B; + + architecture Structure of Din_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din0_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_0: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din0_ipd, Din0, tipd_Din0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din0_Din0 : x01 := '0'; + VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din0_ipd, + TestSignalName => "Din0", + Period => tperiod_Din0, + PulseWidthHigh => tpw_Din0_posedge, + PulseWidthLow => tpw_Din0_negedge, + PeriodData => periodcheckinfo_Din0, + Violation => tviol_Din0_Din0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din0_ipd'last_event, + PathDelay => tpd_Din0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCCASB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nCCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCCASB"; + + tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCCASS : VitalDelayType := 0 ns; + tpw_nCCASS_posedge : VitalDelayType := 0 ns; + tpw_nCCASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCCASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE; + + end nCCASB; + + architecture Structure of nCCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCCASS_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCCAS_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>nCCASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCCASS_nCCASS : x01 := '0'; + VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCCASS_ipd, + TestSignalName => "nCCASS", + Period => tperiod_nCCASS, + PulseWidthHigh => tpw_nCCASS_posedge, + PulseWidthLow => tpw_nCCASS_negedge, + PeriodData => periodcheckinfo_nCCASS, + Violation => tviol_nCCASS_nCCASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event, + PathDelay => tpd_nCCASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCRASB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nCRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCRASB"; + + tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCRASS : VitalDelayType := 0 ns; + tpw_nCRASS_posedge : VitalDelayType := 0 ns; + tpw_nCRASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCRASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE; + + end nCRASB; + + architecture Structure of nCRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCRASS_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCRAS_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>nCRASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCRASS_nCRASS : x01 := '0'; + VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCRASS_ipd, + TestSignalName => "nCRASS", + Period => tperiod_nCRASS, + PulseWidthHigh => tpw_nCRASS_posedge, + PulseWidthLow => tpw_nCRASS_negedge, + PeriodData => periodcheckinfo_nCRASS, + Violation => tviol_nCRASS_nCRASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event, + PathDelay => tpd_nCRASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nFWEB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nFWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nFWEB"; + + tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns); + tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nFWES : VitalDelayType := 0 ns; + tpw_nFWES_posedge : VitalDelayType := 0 ns; + tpw_nFWES_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nFWES: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE; + + end nFWEB; + + architecture Structure of nFWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nFWES_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nFWE_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>nFWES_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nFWES_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nFWES_nFWES : x01 := '0'; + VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nFWES_ipd, + TestSignalName => "nFWES", + Period => tperiod_nFWES, + PulseWidthHigh => tpw_nFWES_posedge, + PulseWidthLow => tpw_nFWES_negedge, + PeriodData => periodcheckinfo_nFWES, + Violation => tviol_nFWES_nFWES, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nFWES_ipd'last_event, + PathDelay => tpd_nFWES_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCLKB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCLKB"; + + tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns); + tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RCLKS : VitalDelayType := 0 ns; + tpw_RCLKS_posedge : VitalDelayType := 0 ns; + tpw_RCLKS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; RCLKS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE; + + end RCLKB; + + architecture Structure of RCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal RCLKS_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + RCLK_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>RCLKS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RCLKS_RCLKS : x01 := '0'; + VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RCLKS_ipd, + TestSignalName => "RCLKS", + Period => tperiod_RCLKS, + PulseWidthHigh => tpw_RCLKS_posedge, + PulseWidthLow => tpw_RCLKS_negedge, + PeriodData => periodcheckinfo_RCLKS, + Violation => tviol_RCLKS_RCLKS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event, + PathDelay => tpd_RCLKS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDOB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity UFMSDOB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDOB"; + + tipd_UFMSDOS : VitalDelayType01 := (0 ns, 0 ns); + tpd_UFMSDOS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_UFMSDOS : VitalDelayType := 0 ns; + tpw_UFMSDOS_posedge : VitalDelayType := 0 ns; + tpw_UFMSDOS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE; + + end UFMSDOB; + + architecture Structure of UFMSDOB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal UFMSDOS_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + UFMSDO_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_UFMSDOS_UFMSDOS : x01 := '0'; + VARIABLE periodcheckinfo_UFMSDOS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => UFMSDOS_ipd, + TestSignalName => "UFMSDOS", + Period => tperiod_UFMSDOS, + PulseWidthHigh => tpw_UFMSDOS_posedge, + PulseWidthLow => tpw_UFMSDOS_negedge, + PeriodData => periodcheckinfo_UFMSDOS, + Violation => tviol_UFMSDOS_UFMSDOS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => UFMSDOS_ipd'last_event, + PathDelay => tpd_UFMSDOS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RAM2GS + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RAM2GS is + port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); + CROW: in Std_logic_vector (1 downto 0); + Din: in Std_logic_vector (7 downto 0); + Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; + nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; + RBA: out Std_logic_vector (1 downto 0); + RA: out Std_logic_vector (11 downto 0); + RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; + RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; + nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; + RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; + UFMSDI: out Std_logic; UFMSDO: in Std_logic); + + + + end RAM2GS; + + architecture Structure of RAM2GS is + signal FS_7: Std_logic; + signal FS_6: Std_logic; + signal RCLK_c: Std_logic; + signal n2010: Std_logic; + signal n2011: Std_logic; + signal FS_15: Std_logic; + signal FS_14: Std_logic; + signal n2014: Std_logic; + signal n2015: Std_logic; + signal FS_5: Std_logic; + signal FS_4: Std_logic; + signal n2009: Std_logic; + signal FS_13: Std_logic; + signal FS_12: Std_logic; + signal n2013: Std_logic; + signal FS_1: Std_logic; + signal FS_0: Std_logic; + signal n2008: Std_logic; + signal FS_11: Std_logic; + signal FS_10: Std_logic; + signal n2012: Std_logic; + signal FS_3: Std_logic; + signal FS_2: Std_logic; + signal FS_9: Std_logic; + signal FS_8: Std_logic; + signal FS_17: Std_logic; + signal FS_16: Std_logic; + signal MAin_c_1: Std_logic; + signal n1326: Std_logic; + signal MAin_c_0: Std_logic; + signal n2263: Std_logic; + signal ADSubmitted: Std_logic; + signal n2242: Std_logic; + signal n2459: Std_logic; + signal n1413: Std_logic; + signal C1Submitted_N_237: Std_logic; + signal PHI2_c: Std_logic; + signal Din_c_6: Std_logic; + signal C1Submitted: Std_logic; + signal nFWE_c: Std_logic; + signal n6_adj_3: Std_logic; + signal n2284: Std_logic; + signal MAin_c_5: Std_logic; + signal n2316: Std_logic; + signal n26: Std_logic; + signal MAin_c_2: Std_logic; + signal n15: Std_logic; + signal n2463: Std_logic; + signal CmdEnable_N_248: Std_logic; + signal PHI2_N_120_enable_7: Std_logic; + signal CmdEnable: Std_logic; + signal PHI2r2: Std_logic; + signal CmdSubmitted: Std_logic; + signal PHI2r3: Std_logic; + signal n2568_001_BUF1: Std_logic; + signal PHI2_N_120_enable_5: Std_logic; + signal n2472: Std_logic; + signal Din_c_5: Std_logic; + signal Din_c_7: Std_logic; + signal n1314: Std_logic; + signal Din_c_4: Std_logic; + signal n8MEGEN: Std_logic; + signal Din_c_0: Std_logic; + signal Cmdn8MEGEN_N_264: Std_logic; + signal PHI2_N_120_enable_4: Std_logic; + signal Cmdn8MEGEN: Std_logic; + signal nRowColSel_N_35: Std_logic; + signal RASr2: Std_logic; + signal InitReady: Std_logic; + signal Ready: Std_logic; + signal n2568_000_BUF1: Std_logic; + signal RCLK_c_enable_25: Std_logic; + signal RCLK_c_enable_23: Std_logic; + signal nCRAS_c: Std_logic; + signal CBR: Std_logic; + signal LEDEN: Std_logic; + signal n2568: Std_logic; + signal RCLK_c_enable_12: Std_logic; + signal LED_N_84: Std_logic; + signal nRowColSel_N_34: Std_logic; + signal nRCAS_N_165: Std_logic; + signal n2208: Std_logic; + signal n2209: Std_logic; + signal nRWE_N_177: Std_logic; + signal RA_0S: Std_logic; + signal n56: Std_logic; + signal XOR8MEG: Std_logic; + signal RA11_N_184: Std_logic; + signal RA_c: Std_logic; + signal n2478: Std_logic; + signal RCKEEN_N_122: Std_logic; + signal RCKEEN_N_121: Std_logic; + signal RCLK_c_enable_4: Std_logic; + signal RCKEEN: Std_logic; + signal n2467: Std_logic; + signal RCKE_c: Std_logic; + signal RASr3: Std_logic; + signal RASr: Std_logic; + signal RCKE_N_132: Std_logic; + signal CASr: Std_logic; + signal nRWE_N_182: Std_logic; + signal CASr2: Std_logic; + signal n2568_002_BUF1: Std_logic; + signal Ready_N_292: Std_logic; + signal n2469: Std_logic; + signal n2462: Std_logic; + signal n62: Std_logic; + signal n1160: Std_logic; + signal CmdUFMCLK: Std_logic; + signal UFMCLK_N_224: Std_logic; + signal RCLK_c_enable_24: Std_logic; + signal n1846: Std_logic; + signal UFMCLK_c: Std_logic; + signal n2470: Std_logic; + signal n2272: Std_logic; + signal n2471: Std_logic; + signal CmdUFMSDI: Std_logic; + signal n2461: Std_logic; + signal UFMSDI_N_231: Std_logic; + signal UFMSDI_c: Std_logic; + signal Din_c_1: Std_logic; + signal n2324: Std_logic; + signal Din_c_2: Std_logic; + signal Din_c_3: Std_logic; + signal XOR8MEG_N_110: Std_logic; + signal PHI2_N_120_enable_1: Std_logic; + signal n2464: Std_logic; + signal n1325: Std_logic; + signal UFMSDO_c: Std_logic; + signal n8MEGEN_N_91: Std_logic; + signal RCLK_c_enable_11: Std_logic; + signal n2427: Std_logic; + signal n15_adj_1: Std_logic; + signal nRCAS_N_161: Std_logic; + signal nRCAS_c: Std_logic; + signal n13: Std_logic; + signal n2481: Std_logic; + signal nRCS_N_136: Std_logic; + signal nRCS_c: Std_logic; + signal nRCS_N_139: Std_logic; + signal nRowColSel_N_32: Std_logic; + signal n6: Std_logic; + signal nRRAS_c: Std_logic; + signal n2138: Std_logic; + signal nRWE_N_178: Std_logic; + signal n33: Std_logic; + signal nRWE_N_171: Std_logic; + signal RCLK_c_enable_3: Std_logic; + signal nRWE_c: Std_logic; + signal nRowColSel: Std_logic; + signal MAin_c_9: Std_logic; + signal RowA_9: Std_logic; + signal nRowColSel_N_28: Std_logic; + signal n1502: Std_logic; + signal n1410: Std_logic; + signal RA_1_9: Std_logic; + signal Ready_N_296: Std_logic; + signal nRowColSel_N_33: Std_logic; + signal n1503: Std_logic; + signal n2414: Std_logic; + signal n1093: Std_logic; + signal CmdUFMCS: Std_logic; + signal nUFMCS_c: Std_logic; + signal n11: Std_logic; + signal n1417: Std_logic; + signal n2322: Std_logic; + signal CASr3: Std_logic; + signal n12: Std_logic; + signal n2164: Std_logic; + signal LEDEN_N_82: Std_logic; + signal FWEr: Std_logic; + signal n2476: Std_logic; + signal n2475: Std_logic; + signal n13_adj_2: Std_logic; + signal n1: Std_logic; + signal n2214: Std_logic; + signal n2328: Std_logic; + signal n10: Std_logic; + signal n2458: Std_logic; + signal n732: Std_logic; + signal n733: Std_logic; + signal n2290: Std_logic; + signal n728: Std_logic; + signal n729: Std_logic; + signal n8: Std_logic; + signal n727: Std_logic; + signal MAin_c_7: Std_logic; + signal MAin_c_6: Std_logic; + signal RowA_6: Std_logic; + signal RowA_7: Std_logic; + signal n2468: Std_logic; + signal n1280: Std_logic; + signal PHI2r: Std_logic; + signal nCCAS_c: Std_logic; + signal n726: Std_logic; + signal Bank_3: Std_logic; + signal Bank_6: Std_logic; + signal Bank_5: Std_logic; + signal n2278: Std_logic; + signal n2314: Std_logic; + signal Bank_2: Std_logic; + signal PHI2_N_120_enable_6: Std_logic; + signal n14: Std_logic; + signal n2460: Std_logic; + signal n730: Std_logic; + signal n2262: Std_logic; + signal n2473: Std_logic; + signal n738: Std_logic; + signal n737: Std_logic; + signal n2474: Std_logic; + signal n2253: Std_logic; + signal CROW_c_1: Std_logic; + signal CROW_c_0: Std_logic; + signal RBA_c_0: Std_logic; + signal RBA_c_1: Std_logic; + signal n734: Std_logic; + signal n735: Std_logic; + signal n7: Std_logic; + signal n2451: Std_logic; + signal Bank_0: Std_logic; + signal Bank_1: Std_logic; + signal WRD_0: Std_logic; + signal WRD_1: Std_logic; + signal MAin_c_8: Std_logic; + signal RowA_8: Std_logic; + signal WRD_6: Std_logic; + signal WRD_7: Std_logic; + signal RDQMH_c: Std_logic; + signal RDQML_c: Std_logic; + signal MAin_c_4: Std_logic; + signal RowA_4: Std_logic; + signal RowA_5: Std_logic; + signal MAin_c_3: Std_logic; + signal RowA_3: Std_logic; + signal Bank_4: Std_logic; + signal RowA_2: Std_logic; + signal RA_1_3: Std_logic; + signal Bank_7: Std_logic; + signal RowA_0: Std_logic; + signal RA_1_4: Std_logic; + signal RowA_1: Std_logic; + signal RA_1_8: Std_logic; + signal RA_1_0: Std_logic; + signal RA_1_7: Std_logic; + signal RA_1_1: Std_logic; + signal n736: Std_logic; + signal RA_1_6: Std_logic; + signal RA_1_2: Std_logic; + signal WRD_2: Std_logic; + signal RA_1_5: Std_logic; + signal WRD_3: Std_logic; + signal WRD_4: Std_logic; + signal n984: Std_logic; + signal WRD_5: Std_logic; + signal Dout_c: Std_logic; + signal Dout_0S: Std_logic; + signal Dout_1S: Std_logic; + signal Dout_2S: Std_logic; + signal Dout_3S: Std_logic; + signal Dout_4S: Std_logic; + signal Dout_5S: Std_logic; + signal Dout_6S: Std_logic; + signal VCCI: Std_logic; + signal GNDI_TSALL: Std_logic; + component VHI + port (Z: out Std_logic); + end component; + component VLO + port (Z: out Std_logic); + end component; + component PUR + port (PUR: in Std_logic); + end component; + component GSR + port (GSR: in Std_logic); + end component; + component TSALL + port (TSALL: in Std_logic); + end component; + component SLICE_0 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_1 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_2 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_3 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_4 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_5 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_6 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_7 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_8 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_9 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_14 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_18 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_19 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_23 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_25 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_26 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_31 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_32 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_34 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_35 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_36 + port (B1: in Std_logic; A1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_43 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_44 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_49 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_56 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_58 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; + Q0: out Std_logic); + end component; + component SLICE_60 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_61 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_63 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_64 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_65 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_66 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_67 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_68 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_69 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component RCKEEN_I_0_445_SLICE_70 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + end component; + component i26_SLICE_71 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + OFX0: out Std_logic); + end component; + component i2099_SLICE_72 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + end component; + component i26_adj_28_SLICE_73 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + OFX0: out Std_logic); + end component; + component SLICE_74 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_75 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_76 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_77 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_78 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_79 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_80 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_81 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_82 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_83 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_84 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_85 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_86 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_87 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_88 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_89 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_90 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_91 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_92 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_93 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_94 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_95 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_96 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_97 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_98 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_99 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_100 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_101 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_102 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_103 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_104 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_105 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component RD_7_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD7: inout Std_logic); + end component; + component RD_6_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD6: inout Std_logic); + end component; + component RD_5_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD5: inout Std_logic); + end component; + component RD_4_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD4: inout Std_logic); + end component; + component RD_3_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD3: inout Std_logic); + end component; + component RD_2_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD2: inout Std_logic); + end component; + component RD_1_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD1: inout Std_logic); + end component; + component RD_0_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD0: inout Std_logic); + end component; + component Dout_7_B + port (PADDO: in Std_logic; Dout7: out Std_logic); + end component; + component Dout_6_B + port (PADDO: in Std_logic; Dout6: out Std_logic); + end component; + component Dout_5_B + port (PADDO: in Std_logic; Dout5: out Std_logic); + end component; + component Dout_4_B + port (PADDO: in Std_logic; Dout4: out Std_logic); + end component; + component Dout_3_B + port (PADDO: in Std_logic; Dout3: out Std_logic); + end component; + component Dout_2_B + port (PADDO: in Std_logic; Dout2: out Std_logic); + end component; + component Dout_1_B + port (PADDO: in Std_logic; Dout1: out Std_logic); + end component; + component Dout_0_B + port (PADDO: in Std_logic; Dout0: out Std_logic); + end component; + component LEDB + port (PADDO: in Std_logic; LEDS: out Std_logic); + end component; + component RBA_1_B + port (PADDO: in Std_logic; RBA1: out Std_logic); + end component; + component RBA_0_B + port (PADDO: in Std_logic; RBA0: out Std_logic); + end component; + component RA_11_B + port (PADDO: in Std_logic; RA11: out Std_logic); + end component; + component RA_10_B + port (PADDO: in Std_logic; RA10: out Std_logic); + end component; + component RA_9_B + port (PADDO: in Std_logic; RA9: out Std_logic); + end component; + component RA_8_B + port (PADDO: in Std_logic; RA8: out Std_logic); + end component; + component RA_7_B + port (PADDO: in Std_logic; RA7: out Std_logic); + end component; + component RA_6_B + port (PADDO: in Std_logic; RA6: out Std_logic); + end component; + component RA_5_B + port (PADDO: in Std_logic; RA5: out Std_logic); + end component; + component RA_4_B + port (PADDO: in Std_logic; RA4: out Std_logic); + end component; + component RA_3_B + port (PADDO: in Std_logic; RA3: out Std_logic); + end component; + component RA_2_B + port (PADDO: in Std_logic; RA2: out Std_logic); + end component; + component RA_1_B + port (PADDO: in Std_logic; RA1: out Std_logic); + end component; + component RA_0_B + port (PADDO: in Std_logic; RA0: out Std_logic); + end component; + component nRCSB + port (PADDO: in Std_logic; nRCSS: out Std_logic); + end component; + component RCKEB + port (PADDO: in Std_logic; RCKES: out Std_logic); + end component; + component nRWEB + port (PADDO: in Std_logic; nRWES: out Std_logic); + end component; + component nRRASB + port (PADDO: in Std_logic; nRRASS: out Std_logic); + end component; + component nRCASB + port (PADDO: in Std_logic; nRCASS: out Std_logic); + end component; + component RDQMHB + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + end component; + component RDQMLB + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + end component; + component nUFMCSB + port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + end component; + component UFMCLKB + port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + end component; + component UFMSDIB + port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + end component; + component PHI2B + port (PADDI: out Std_logic; PHI2S: in Std_logic); + end component; + component MAin_9_B + port (PADDI: out Std_logic; MAin9: in Std_logic); + end component; + component MAin_8_B + port (PADDI: out Std_logic; MAin8: in Std_logic); + end component; + component MAin_7_B + port (PADDI: out Std_logic; MAin7: in Std_logic); + end component; + component MAin_6_B + port (PADDI: out Std_logic; MAin6: in Std_logic); + end component; + component MAin_5_B + port (PADDI: out Std_logic; MAin5: in Std_logic); + end component; + component MAin_4_B + port (PADDI: out Std_logic; MAin4: in Std_logic); + end component; + component MAin_3_B + port (PADDI: out Std_logic; MAin3: in Std_logic); + end component; + component MAin_2_B + port (PADDI: out Std_logic; MAin2: in Std_logic); + end component; + component MAin_1_B + port (PADDI: out Std_logic; MAin1: in Std_logic); + end component; + component MAin_0_B + port (PADDI: out Std_logic; MAin0: in Std_logic); + end component; + component CROW_1_B + port (PADDI: out Std_logic; CROW1: in Std_logic); + end component; + component CROW_0_B + port (PADDI: out Std_logic; CROW0: in Std_logic); + end component; + component Din_7_B + port (PADDI: out Std_logic; Din7: in Std_logic); + end component; + component Din_6_B + port (PADDI: out Std_logic; Din6: in Std_logic); + end component; + component Din_5_B + port (PADDI: out Std_logic; Din5: in Std_logic); + end component; + component Din_4_B + port (PADDI: out Std_logic; Din4: in Std_logic); + end component; + component Din_3_B + port (PADDI: out Std_logic; Din3: in Std_logic); + end component; + component Din_2_B + port (PADDI: out Std_logic; Din2: in Std_logic); + end component; + component Din_1_B + port (PADDI: out Std_logic; Din1: in Std_logic); + end component; + component Din_0_B + port (PADDI: out Std_logic; Din0: in Std_logic); + end component; + component nCCASB + port (PADDI: out Std_logic; nCCASS: in Std_logic); + end component; + component nCRASB + port (PADDI: out Std_logic; nCRASS: in Std_logic); + end component; + component nFWEB + port (PADDI: out Std_logic; nFWES: in Std_logic); + end component; + component RCLKB + port (PADDI: out Std_logic; RCLKS: in Std_logic); + end component; + component UFMSDOB + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + end component; + begin + SLICE_0I: SLICE_0 + port map (A1=>FS_7, A0=>FS_6, CLK=>RCLK_c, FCI=>n2010, Q0=>FS_6, + Q1=>FS_7, FCO=>n2011); + SLICE_1I: SLICE_1 + port map (A1=>FS_15, A0=>FS_14, CLK=>RCLK_c, FCI=>n2014, Q0=>FS_14, + Q1=>FS_15, FCO=>n2015); + SLICE_2I: SLICE_2 + port map (A1=>FS_5, A0=>FS_4, CLK=>RCLK_c, FCI=>n2009, Q0=>FS_4, + Q1=>FS_5, FCO=>n2010); + SLICE_3I: SLICE_3 + port map (A1=>FS_13, A0=>FS_12, CLK=>RCLK_c, FCI=>n2013, Q0=>FS_12, + Q1=>FS_13, FCO=>n2014); + SLICE_4I: SLICE_4 + port map (A1=>FS_1, A0=>FS_0, CLK=>RCLK_c, Q0=>FS_0, Q1=>FS_1, + FCO=>n2008); + SLICE_5I: SLICE_5 + port map (A1=>FS_11, A0=>FS_10, CLK=>RCLK_c, FCI=>n2012, Q0=>FS_10, + Q1=>FS_11, FCO=>n2013); + SLICE_6I: SLICE_6 + port map (A1=>FS_3, A0=>FS_2, CLK=>RCLK_c, FCI=>n2008, Q0=>FS_2, + Q1=>FS_3, FCO=>n2009); + SLICE_7I: SLICE_7 + port map (A1=>FS_9, A0=>FS_8, CLK=>RCLK_c, FCI=>n2011, Q0=>FS_8, + Q1=>FS_9, FCO=>n2012); + SLICE_8I: SLICE_8 + port map (A1=>FS_17, A0=>FS_16, CLK=>RCLK_c, FCI=>n2015, Q0=>FS_16, + Q1=>FS_17); + SLICE_9I: SLICE_9 + port map (C1=>MAin_c_1, B1=>n1326, A1=>MAin_c_0, D0=>n2263, + C0=>ADSubmitted, B0=>n2242, A0=>n2459, DI0=>n1413, + LSR=>C1Submitted_N_237, CLK=>PHI2_c, F0=>n1413, + Q0=>ADSubmitted, F1=>n2263); + SLICE_14I: SLICE_14 + port map (B1=>Din_c_6, A1=>C1Submitted, D0=>MAin_c_1, C0=>C1Submitted, + B0=>n1326, A0=>nFWE_c, DI0=>n6_adj_3, LSR=>C1Submitted_N_237, + CLK=>PHI2_c, F0=>n6_adj_3, Q0=>C1Submitted, F1=>n2284); + SLICE_18I: SLICE_18 + port map (D1=>MAin_c_5, C1=>n2316, B1=>n26, A1=>MAin_c_2, D0=>n15, + C0=>n1326, B0=>n2463, A0=>MAin_c_1, DI0=>CmdEnable_N_248, + CE=>PHI2_N_120_enable_7, CLK=>PHI2_c, F0=>CmdEnable_N_248, + Q0=>CmdEnable, F1=>n1326); + SLICE_19I: SLICE_19 + port map (C1=>PHI2r2, B1=>CmdSubmitted, A1=>PHI2r3, DI0=>n2568_001_BUF1, + CE=>PHI2_N_120_enable_5, CLK=>PHI2_c, F0=>n2568_001_BUF1, + Q0=>CmdSubmitted, F1=>n2472); + SLICE_23I: SLICE_23 + port map (C1=>Din_c_5, B1=>Din_c_7, A1=>Din_c_6, D0=>n1314, C0=>Din_c_4, + B0=>n8MEGEN, A0=>Din_c_0, DI0=>Cmdn8MEGEN_N_264, + CE=>PHI2_N_120_enable_4, CLK=>PHI2_c, F0=>Cmdn8MEGEN_N_264, + Q0=>Cmdn8MEGEN, F1=>n1314); + SLICE_25I: SLICE_25 + port map (D1=>nRowColSel_N_35, C1=>RASr2, B1=>InitReady, A1=>Ready, + DI0=>n2568_000_BUF1, CE=>RCLK_c_enable_25, CLK=>RCLK_c, + F0=>n2568_000_BUF1, Q0=>InitReady, F1=>RCLK_c_enable_23); + SLICE_26I: SLICE_26 + port map (C1=>nCRAS_c, B1=>CBR, A1=>LEDEN, DI0=>n2568, + CE=>RCLK_c_enable_12, CLK=>RCLK_c, F0=>n2568, Q0=>LEDEN, + F1=>LED_N_84); + SLICE_31I: SLICE_31 + port map (B1=>nRowColSel_N_34, A1=>Ready, C0=>nRCAS_N_165, B0=>Ready, + A0=>n2208, DI0=>n2209, LSR=>nRWE_N_177, CLK=>RCLK_c, F0=>n2209, + Q0=>RA_0S, F1=>n56); + SLICE_32I: SLICE_32 + port map (B1=>Din_c_7, A1=>Din_c_6, C0=>n8MEGEN, B0=>XOR8MEG, + A0=>Din_c_6, DI0=>RA11_N_184, LSR=>Ready, CLK=>PHI2_c, + F0=>RA11_N_184, Q0=>RA_c, F1=>n2478); + SLICE_34I: SLICE_34 + port map (C1=>Ready, B1=>InitReady, A1=>RASr2, C0=>Ready, + B0=>RCKEEN_N_122, A0=>InitReady, DI0=>RCKEEN_N_121, + CE=>RCLK_c_enable_4, CLK=>RCLK_c, F0=>RCKEEN_N_121, Q0=>RCKEEN, + F1=>n2467); + SLICE_35I: SLICE_35 + port map (B1=>RCKE_c, A1=>RASr2, D0=>RASr3, C0=>RASr2, B0=>RCKEEN, + A0=>RASr, DI0=>RCKE_N_132, M1=>CASr, CLK=>RCLK_c, + F0=>RCKE_N_132, Q0=>RCKE_c, F1=>nRWE_N_182, Q1=>CASr2); + SLICE_36I: SLICE_36 + port map (B1=>nRowColSel_N_35, A1=>Ready, DI0=>n2568_002_BUF1, + CE=>Ready_N_292, CLK=>RCLK_c, F0=>n2568_002_BUF1, Q0=>Ready, + F1=>n2469); + SLICE_43I: SLICE_43 + port map (D1=>FS_1, C1=>n2462, B1=>n62, A1=>FS_4, C0=>InitReady, + B0=>n1160, A0=>CmdUFMCLK, DI0=>UFMCLK_N_224, + CE=>RCLK_c_enable_24, LSR=>n1846, CLK=>RCLK_c, + F0=>UFMCLK_N_224, Q0=>UFMCLK_c, F1=>n1160); + SLICE_44I: SLICE_44 + port map (D1=>FS_11, C1=>n2470, B1=>n2272, A1=>n2471, D0=>CmdUFMSDI, + C0=>InitReady, B0=>n2462, A0=>n2461, DI0=>UFMSDI_N_231, + CE=>RCLK_c_enable_24, LSR=>n1846, CLK=>RCLK_c, + F0=>UFMSDI_N_231, Q0=>UFMSDI_c, F1=>n2462); + SLICE_49I: SLICE_49 + port map (D1=>Din_c_1, C1=>n1314, B1=>LEDEN, A1=>Din_c_4, D0=>n2324, + C0=>Din_c_2, B0=>Din_c_3, A0=>Din_c_0, DI0=>XOR8MEG_N_110, + CE=>PHI2_N_120_enable_1, CLK=>PHI2_c, F0=>XOR8MEG_N_110, + Q0=>XOR8MEG, F1=>n2324); + SLICE_56I: SLICE_56 + port map (C1=>FS_10, B1=>n2464, A1=>FS_11, D0=>n1325, C0=>InitReady, + B0=>Cmdn8MEGEN, A0=>UFMSDO_c, DI0=>n8MEGEN_N_91, + CE=>RCLK_c_enable_11, CLK=>RCLK_c, F0=>n8MEGEN_N_91, + Q0=>n8MEGEN, F1=>n1325); + SLICE_58I: SLICE_58 + port map (D1=>n2427, C1=>RASr2, B1=>CBR, A1=>Ready, C0=>Ready, + B0=>n15_adj_1, A0=>nRowColSel_N_34, DI0=>nRCAS_N_161, + M0=>nRowColSel_N_35, CE=>RCLK_c_enable_4, CLK=>RCLK_c, + OFX0=>nRCAS_N_161, Q0=>nRCAS_c); + SLICE_60I: SLICE_60 + port map (D1=>Ready, C1=>RCKE_c, B1=>InitReady, A1=>RASr2, + D0=>nRowColSel_N_35, C0=>n13, B0=>n2481, A0=>n2467, + DI0=>nRCS_N_136, CE=>RCLK_c_enable_4, CLK=>RCLK_c, + F0=>nRCS_N_136, Q0=>nRCS_c, F1=>n13); + SLICE_61I: SLICE_61 + port map (C1=>nRCS_N_139, B1=>n13, A1=>Ready, D0=>nRowColSel_N_32, + C0=>n6, B0=>nRRAS_c, A0=>n56, DI0=>n2138, M0=>nRowColSel_N_35, + CLK=>RCLK_c, OFX0=>n2138, Q0=>nRRAS_c); + SLICE_63I: SLICE_63 + port map (D1=>nRCS_N_139, C1=>InitReady, B1=>RASr2, A1=>nRowColSel_N_35, + D0=>n2208, C0=>Ready, B0=>nRWE_N_178, A0=>n33, DI0=>nRWE_N_171, + CE=>RCLK_c_enable_3, CLK=>RCLK_c, F0=>nRWE_N_171, Q0=>nRWE_c, + F1=>n2208); + SLICE_64I: SLICE_64 + port map (C1=>nRowColSel, B1=>MAin_c_9, A1=>RowA_9, D0=>nRowColSel_N_32, + C0=>nRowColSel_N_28, B0=>n1502, A0=>nRowColSel, DI0=>n1410, + LSR=>n2469, CLK=>RCLK_c, F0=>n1410, Q0=>nRowColSel, F1=>RA_1_9); + SLICE_65I: SLICE_65 + port map (D1=>InitReady, C1=>Ready_N_296, B1=>RASr2, A1=>nRowColSel_N_32, + B0=>nRowColSel_N_33, A0=>nRowColSel_N_32, DI0=>n1503, + LSR=>RASr2, CLK=>RCLK_c, F0=>n1503, Q0=>nRowColSel_N_32, + F1=>n2414); + SLICE_66I: SLICE_66 + port map (D1=>nRowColSel_N_33, C1=>nRowColSel_N_34, B1=>n2469, + A1=>nRowColSel_N_32, B0=>RASr2, A0=>nRowColSel_N_32, + DI0=>n1093, LSR=>nRowColSel_N_34, CLK=>RCLK_c, F0=>n1093, + Q0=>nRowColSel_N_33, F1=>RCLK_c_enable_4); + SLICE_67I: SLICE_67 + port map (C1=>n2472, B1=>CmdUFMCS, A1=>nUFMCS_c, B0=>CASr2, + A0=>nRowColSel_N_33, M0=>n1093, LSR=>nRowColSel_N_35, + CLK=>RCLK_c, F0=>n11, Q0=>nRowColSel_N_34, F1=>n1417); + SLICE_68I: SLICE_68 + port map (B1=>FS_12, A1=>FS_17, D0=>FS_3, C0=>FS_6, B0=>FS_1, A0=>FS_0, + M1=>CASr2, M0=>RASr2, CLK=>RCLK_c, F0=>n2322, + Q0=>nRowColSel_N_35, F1=>n2471, Q1=>CASr3); + SLICE_69I: SLICE_69 + port map (D1=>FS_14, C1=>FS_12, B1=>n12, A1=>FS_17, C0=>InitReady, + B0=>n1417, A0=>n62, DI0=>n2164, LSR=>LEDEN_N_82, CLK=>RCLK_c, + F0=>n2164, Q0=>nUFMCS_c, F1=>n62); + RCKEEN_I_0_445_SLICE_70I: RCKEEN_I_0_445_SLICE_70 + port map (C1=>RASr2, B1=>FWEr, A1=>CBR, D0=>nRowColSel_N_34, C0=>FWEr, + B0=>n11, A0=>CBR, M0=>nRowColSel_N_35, OFX0=>RCKEEN_N_122); + i26_SLICE_71I: i26_SLICE_71 + port map (D1=>n2284, C1=>n2476, B1=>MAin_c_1, A1=>MAin_c_0, + D0=>ADSubmitted, C0=>MAin_c_0, B0=>n2475, A0=>Din_c_5, + M0=>Din_c_2, OFX0=>n13_adj_2); + i2099_SLICE_72I: i2099_SLICE_72 + port map (D1=>nRowColSel_N_34, C1=>nRowColSel_N_35, B1=>Ready, + A1=>nRCS_N_139, C0=>nRowColSel_N_35, B0=>Ready, A0=>nRCS_N_139, + M0=>n15_adj_1, OFX0=>n2481); + i26_adj_28_SLICE_73I: i26_adj_28_SLICE_73 + port map (D1=>MAin_c_0, C1=>Din_c_2, B1=>Din_c_3, A1=>Din_c_6, + D0=>MAin_c_0, C0=>Din_c_2, B0=>Din_c_3, A0=>Din_c_6, + M0=>Din_c_5, OFX0=>n15); + SLICE_74I: SLICE_74 + port map (D1=>n1, C1=>nRowColSel_N_33, B1=>CBR, A1=>FWEr, D0=>CASr3, + C0=>CASr2, B0=>FWEr, A0=>CBR, M1=>RASr2, M0=>RASr, CLK=>RCLK_c, + F0=>n1, Q0=>RASr2, F1=>n15_adj_1, Q1=>RASr3); + SLICE_75I: SLICE_75 + port map (C1=>InitReady, B1=>FS_11, A1=>n2214, D0=>FS_11, C0=>n2272, + B0=>n2328, A0=>FS_10, F0=>n2214, F1=>RCLK_c_enable_12); + SLICE_76I: SLICE_76 + port map (D1=>MAin_c_0, C1=>n10, B1=>n1326, A1=>nFWE_c, D0=>n2458, + C0=>Din_c_4, B0=>Din_c_5, A0=>Din_c_3, M1=>n732, M0=>n733, + CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>PHI2_N_120_enable_4, + Q0=>n732, F1=>n2458, Q1=>nRWE_N_177); + SLICE_77I: SLICE_77 + port map (D1=>FS_7, C1=>n2322, B1=>FS_4, A1=>n2290, C0=>FS_9, B0=>FS_5, + A0=>FS_2, M1=>n728, M0=>n729, CE=>RCLK_c_enable_23, + CLK=>RCLK_c, F0=>n2290, Q0=>n728, F1=>n8, Q1=>n727); + SLICE_78I: SLICE_78 + port map (D1=>n2471, C1=>n2272, B1=>FS_14, A1=>FS_16, C0=>InitReady, + B0=>n2464, A0=>FS_11, M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready, + CLK=>nCRAS_c, F0=>n1846, Q0=>RowA_6, F1=>n2464, Q1=>RowA_7); + SLICE_79I: SLICE_79 + port map (C1=>Din_c_5, B1=>Din_c_3, A1=>Din_c_6, D0=>n2468, C0=>n1280, + B0=>n2463, A0=>Din_c_2, M1=>PHI2r, M0=>nCCAS_c, CLK=>RCLK_c, + F0=>C1Submitted_N_237, Q0=>CASr, F1=>n2468, Q1=>PHI2r2); + SLICE_80I: SLICE_80 + port map (B1=>nRowColSel_N_33, A1=>nRowColSel_N_34, D0=>nRowColSel_N_35, + C0=>n1502, B0=>nRowColSel_N_32, A0=>Ready, M1=>n726, M0=>n727, + CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>RCLK_c_enable_3, + Q0=>n726, F1=>n1502, Q1=>Ready_N_296); + SLICE_81I: SLICE_81 + port map (B1=>Bank_3, A1=>Bank_6, D0=>Bank_5, C0=>n2278, B0=>n2314, + A0=>Bank_2, M1=>Din_c_2, M0=>Din_c_1, CE=>PHI2_N_120_enable_6, + CLK=>PHI2_c, F0=>n26, Q0=>CmdUFMCLK, F1=>n2278, Q1=>CmdUFMCS); + SLICE_82I: SLICE_82 + port map (D1=>MAin_c_1, C1=>n14, B1=>n2460, A1=>MAin_c_0, B0=>n1326, + A0=>nFWE_c, M1=>n730, M0=>nRWE_N_177, CE=>RCLK_c_enable_23, + CLK=>RCLK_c, F0=>n2460, Q0=>n730, F1=>PHI2_N_120_enable_7, + Q1=>n729); + SLICE_83I: SLICE_83 + port map (D1=>n2476, C1=>n2460, B1=>n10, A1=>MAin_c_0, D0=>MAin_c_1, + C0=>CmdEnable, B0=>n2478, A0=>Din_c_4, M0=>nCRAS_c, + CLK=>RCLK_c, F0=>n10, Q0=>RASr, F1=>PHI2_N_120_enable_6); + SLICE_84I: SLICE_84 + port map (D1=>n1314, C1=>n2262, B1=>CmdEnable, A1=>n2473, C0=>MAin_c_1, + B0=>n1326, A0=>MAin_c_0, M1=>n738, M0=>nRCAS_N_165, + CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>n2262, Q0=>n738, + F1=>PHI2_N_120_enable_1, Q1=>n737); + SLICE_85I: SLICE_85 + port map (D1=>n2474, C1=>Din_c_5, B1=>n2253, A1=>n2473, B0=>nFWE_c, + A0=>Din_c_4, M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready, + CLK=>nCRAS_c, F0=>n2473, Q0=>RBA_c_0, F1=>n2242, Q1=>RBA_c_1); + SLICE_86I: SLICE_86 + port map (C1=>Din_c_1, B1=>Din_c_0, A1=>Din_c_7, C0=>n2253, B0=>nFWE_c, + A0=>Din_c_4, M1=>n734, M0=>n735, CE=>RCLK_c_enable_23, + CLK=>RCLK_c, F0=>n2463, Q0=>n734, F1=>n2253, Q1=>n733); + SLICE_87I: SLICE_87 + port map (B1=>n2214, A1=>FS_8, D0=>n8, C0=>InitReady, B0=>n2472, A0=>n7, + M1=>nRCS_N_139, M0=>Ready_N_296, CE=>RCLK_c_enable_23, + CLK=>RCLK_c, F0=>RCLK_c_enable_11, Q0=>nRCS_N_139, F1=>n7, + Q1=>nRCAS_N_165); + SLICE_88I: SLICE_88 + port map (C1=>FS_10, B1=>FS_6, A1=>n2451, D0=>FS_8, C0=>FS_5, B0=>FS_9, + A0=>FS_7, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, F0=>n2451, + Q0=>Bank_0, F1=>n2461, Q1=>Bank_1); + SLICE_89I: SLICE_89 + port map (C1=>MAin_c_1, B1=>n1326, A1=>nFWE_c, C0=>MAin_c_0, B0=>n1326, + A0=>MAin_c_1, M1=>Din_c_1, M0=>Din_c_0, CLK=>nCCAS_c, + F0=>n1280, Q0=>WRD_0, F1=>n2459, Q1=>WRD_1); + SLICE_90I: SLICE_90 + port map (D1=>FS_16, C1=>FS_14, B1=>FS_12, A1=>FS_17, B0=>FS_14, + A0=>FS_16, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready, + CLK=>nCRAS_c, F0=>n2470, Q0=>RowA_8, F1=>n2328, Q1=>RowA_9); + SLICE_91I: SLICE_91 + port map (B1=>Din_c_5, A1=>Din_c_3, D0=>n2458, C0=>Din_c_5, B0=>Din_c_4, + A0=>Din_c_3, M1=>PHI2_c, M0=>PHI2r2, CLK=>RCLK_c, + F0=>PHI2_N_120_enable_5, Q0=>PHI2r3, F1=>n2476, Q1=>PHI2r); + SLICE_92I: SLICE_92 + port map (B1=>Din_c_3, A1=>Din_c_6, C0=>Din_c_3, B0=>Din_c_2, + A0=>Din_c_6, M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, F0=>n2474, + Q0=>WRD_6, F1=>n2475, Q1=>WRD_7); + SLICE_93I: SLICE_93 + port map (B1=>nRowColSel, A1=>MAin_c_9, B0=>nRowColSel, A0=>MAin_c_9, + M0=>Din_c_0, CE=>PHI2_N_120_enable_6, CLK=>PHI2_c, F0=>RDQMH_c, + Q0=>CmdUFMSDI, F1=>RDQML_c); + SLICE_94I: SLICE_94 + port map (B1=>FS_15, A1=>FS_13, D0=>FS_11, C0=>FS_16, B0=>FS_13, + A0=>FS_15, F0=>n12, F1=>n2272); + SLICE_95I: SLICE_95 + port map (B1=>FS_10, A1=>n62, D0=>InitReady, C0=>FS_10, B0=>n2464, + A0=>FS_11, M1=>MAin_c_5, M0=>MAin_c_4, LSR=>Ready, + CLK=>nCRAS_c, F0=>LEDEN_N_82, Q0=>RowA_4, F1=>RCLK_c_enable_25, + Q1=>RowA_5); + SLICE_96I: SLICE_96 + port map (C1=>nRowColSel, B1=>MAin_c_3, A1=>RowA_3, D0=>Bank_1, + C0=>Bank_4, B0=>MAin_c_3, A0=>MAin_c_7, M1=>MAin_c_3, + M0=>MAin_c_2, LSR=>Ready, CLK=>nCRAS_c, F0=>n2316, Q0=>RowA_2, + F1=>RA_1_3, Q1=>RowA_3); + SLICE_97I: SLICE_97 + port map (C1=>nRowColSel, B1=>MAin_c_4, A1=>RowA_4, D0=>Bank_0, + C0=>Bank_7, B0=>MAin_c_4, A0=>MAin_c_6, M1=>MAin_c_1, + M0=>MAin_c_0, LSR=>Ready, CLK=>nCRAS_c, F0=>n2314, Q0=>RowA_0, + F1=>RA_1_4, Q1=>RowA_1); + SLICE_98I: SLICE_98 + port map (C1=>nRowColSel, B1=>MAin_c_0, A1=>RowA_0, C0=>nRowColSel, + B0=>MAin_c_8, A0=>RowA_8, M1=>nFWE_c, M0=>nCCAS_c, + CLK=>nCRAS_c, F0=>RA_1_8, Q0=>CBR, F1=>RA_1_0, Q1=>FWEr); + SLICE_99I: SLICE_99 + port map (C1=>nRowColSel, B1=>MAin_c_1, A1=>RowA_1, C0=>nRowColSel, + B0=>MAin_c_7, A0=>RowA_7, M1=>Din_c_7, M0=>Din_c_6, + CLK=>PHI2_c, F0=>RA_1_7, Q0=>Bank_6, F1=>RA_1_1, Q1=>Bank_7); + SLICE_100I: SLICE_100 + port map (D1=>Ready, C1=>nRowColSel_N_33, B1=>InitReady, A1=>RASr2, + D0=>InitReady, C0=>PHI2r2, B0=>CmdSubmitted, A0=>PHI2r3, + M1=>n736, M0=>n737, CE=>RCLK_c_enable_23, CLK=>RCLK_c, + F0=>RCLK_c_enable_24, Q0=>n736, F1=>n6, Q1=>n735); + SLICE_101I: SLICE_101 + port map (C1=>nRowColSel, B1=>MAin_c_2, A1=>RowA_2, C0=>nRowColSel, + B0=>MAin_c_6, A0=>RowA_6, M1=>Din_c_5, M0=>Din_c_4, + CLK=>PHI2_c, F0=>RA_1_6, Q0=>Bank_4, F1=>RA_1_2, Q1=>Bank_5); + SLICE_102I: SLICE_102 + port map (B1=>nRWE_N_177, A1=>nRCAS_N_165, C0=>nRCAS_N_165, + B0=>nRCS_N_139, A0=>InitReady, M1=>Din_c_3, M0=>Din_c_2, + CLK=>PHI2_c, F0=>n2427, Q0=>Bank_2, F1=>n33, Q1=>Bank_3); + SLICE_103I: SLICE_103 + port map (C1=>nRowColSel, B1=>MAin_c_5, A1=>RowA_5, C0=>CBR, B0=>CASr3, + A0=>FWEr, M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, + F0=>nRowColSel_N_28, Q0=>WRD_2, F1=>RA_1_5, Q1=>WRD_3); + SLICE_104I: SLICE_104 + port map (B1=>Ready, A1=>n2414, D0=>nRowColSel_N_35, C0=>nRWE_N_182, + B0=>n1502, A0=>n1, F0=>nRWE_N_178, F1=>Ready_N_292); + SLICE_105I: SLICE_105 + port map (B1=>nFWE_c, A1=>nCCAS_c, C0=>n13_adj_2, B0=>Din_c_4, A0=>n2253, + M1=>Din_c_5, M0=>Din_c_4, CLK=>nCCAS_c, F0=>n14, Q0=>WRD_4, + F1=>n984, Q1=>WRD_5); + RD_7_I: RD_7_B + port map (PADDI=>Dout_c, PADDT=>n984, PADDO=>WRD_7, RD7=>RD(7)); + RD_6_I: RD_6_B + port map (PADDI=>Dout_0S, PADDT=>n984, PADDO=>WRD_6, RD6=>RD(6)); + RD_5_I: RD_5_B + port map (PADDI=>Dout_1S, PADDT=>n984, PADDO=>WRD_5, RD5=>RD(5)); + RD_4_I: RD_4_B + port map (PADDI=>Dout_2S, PADDT=>n984, PADDO=>WRD_4, RD4=>RD(4)); + RD_3_I: RD_3_B + port map (PADDI=>Dout_3S, PADDT=>n984, PADDO=>WRD_3, RD3=>RD(3)); + RD_2_I: RD_2_B + port map (PADDI=>Dout_4S, PADDT=>n984, PADDO=>WRD_2, RD2=>RD(2)); + RD_1_I: RD_1_B + port map (PADDI=>Dout_5S, PADDT=>n984, PADDO=>WRD_1, RD1=>RD(1)); + RD_0_I: RD_0_B + port map (PADDI=>Dout_6S, PADDT=>n984, PADDO=>WRD_0, RD0=>RD(0)); + Dout_7_I: Dout_7_B + port map (PADDO=>Dout_c, Dout7=>Dout(7)); + Dout_6_I: Dout_6_B + port map (PADDO=>Dout_0S, Dout6=>Dout(6)); + Dout_5_I: Dout_5_B + port map (PADDO=>Dout_1S, Dout5=>Dout(5)); + Dout_4_I: Dout_4_B + port map (PADDO=>Dout_2S, Dout4=>Dout(4)); + Dout_3_I: Dout_3_B + port map (PADDO=>Dout_3S, Dout3=>Dout(3)); + Dout_2_I: Dout_2_B + port map (PADDO=>Dout_4S, Dout2=>Dout(2)); + Dout_1_I: Dout_1_B + port map (PADDO=>Dout_5S, Dout1=>Dout(1)); + Dout_0_I: Dout_0_B + port map (PADDO=>Dout_6S, Dout0=>Dout(0)); + LEDI: LEDB + port map (PADDO=>LED_N_84, LEDS=>LED); + RBA_1_I: RBA_1_B + port map (PADDO=>RBA_c_1, RBA1=>RBA(1)); + RBA_0_I: RBA_0_B + port map (PADDO=>RBA_c_0, RBA0=>RBA(0)); + RA_11_I: RA_11_B + port map (PADDO=>RA_c, RA11=>RA(11)); + RA_10_I: RA_10_B + port map (PADDO=>RA_0S, RA10=>RA(10)); + RA_9_I: RA_9_B + port map (PADDO=>RA_1_9, RA9=>RA(9)); + RA_8_I: RA_8_B + port map (PADDO=>RA_1_8, RA8=>RA(8)); + RA_7_I: RA_7_B + port map (PADDO=>RA_1_7, RA7=>RA(7)); + RA_6_I: RA_6_B + port map (PADDO=>RA_1_6, RA6=>RA(6)); + RA_5_I: RA_5_B + port map (PADDO=>RA_1_5, RA5=>RA(5)); + RA_4_I: RA_4_B + port map (PADDO=>RA_1_4, RA4=>RA(4)); + RA_3_I: RA_3_B + port map (PADDO=>RA_1_3, RA3=>RA(3)); + RA_2_I: RA_2_B + port map (PADDO=>RA_1_2, RA2=>RA(2)); + RA_1_I: RA_1_B + port map (PADDO=>RA_1_1, RA1=>RA(1)); + RA_0_I: RA_0_B + port map (PADDO=>RA_1_0, RA0=>RA(0)); + nRCSI: nRCSB + port map (PADDO=>nRCS_c, nRCSS=>nRCS); + RCKEI: RCKEB + port map (PADDO=>RCKE_c, RCKES=>RCKE); + nRWEI: nRWEB + port map (PADDO=>nRWE_c, nRWES=>nRWE); + nRRASI: nRRASB + port map (PADDO=>nRRAS_c, nRRASS=>nRRAS); + nRCASI: nRCASB + port map (PADDO=>nRCAS_c, nRCASS=>nRCAS); + RDQMHI: RDQMHB + port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH); + RDQMLI: RDQMLB + port map (PADDO=>RDQML_c, RDQMLS=>RDQML); + nUFMCSI: nUFMCSB + port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS); + UFMCLKI: UFMCLKB + port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK); + UFMSDII: UFMSDIB + port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI); + PHI2I: PHI2B + port map (PADDI=>PHI2_c, PHI2S=>PHI2); + MAin_9_I: MAin_9_B + port map (PADDI=>MAin_c_9, MAin9=>MAin(9)); + MAin_8_I: MAin_8_B + port map (PADDI=>MAin_c_8, MAin8=>MAin(8)); + MAin_7_I: MAin_7_B + port map (PADDI=>MAin_c_7, MAin7=>MAin(7)); + MAin_6_I: MAin_6_B + port map (PADDI=>MAin_c_6, MAin6=>MAin(6)); + MAin_5_I: MAin_5_B + port map (PADDI=>MAin_c_5, MAin5=>MAin(5)); + MAin_4_I: MAin_4_B + port map (PADDI=>MAin_c_4, MAin4=>MAin(4)); + MAin_3_I: MAin_3_B + port map (PADDI=>MAin_c_3, MAin3=>MAin(3)); + MAin_2_I: MAin_2_B + port map (PADDI=>MAin_c_2, MAin2=>MAin(2)); + MAin_1_I: MAin_1_B + port map (PADDI=>MAin_c_1, MAin1=>MAin(1)); + MAin_0_I: MAin_0_B + port map (PADDI=>MAin_c_0, MAin0=>MAin(0)); + CROW_1_I: CROW_1_B + port map (PADDI=>CROW_c_1, CROW1=>CROW(1)); + CROW_0_I: CROW_0_B + port map (PADDI=>CROW_c_0, CROW0=>CROW(0)); + Din_7_I: Din_7_B + port map (PADDI=>Din_c_7, Din7=>Din(7)); + Din_6_I: Din_6_B + port map (PADDI=>Din_c_6, Din6=>Din(6)); + Din_5_I: Din_5_B + port map (PADDI=>Din_c_5, Din5=>Din(5)); + Din_4_I: Din_4_B + port map (PADDI=>Din_c_4, Din4=>Din(4)); + Din_3_I: Din_3_B + port map (PADDI=>Din_c_3, Din3=>Din(3)); + Din_2_I: Din_2_B + port map (PADDI=>Din_c_2, Din2=>Din(2)); + Din_1_I: Din_1_B + port map (PADDI=>Din_c_1, Din1=>Din(1)); + Din_0_I: Din_0_B + port map (PADDI=>Din_c_0, Din0=>Din(0)); + nCCASI: nCCASB + port map (PADDI=>nCCAS_c, nCCASS=>nCCAS); + nCRASI: nCRASB + port map (PADDI=>nCRAS_c, nCRASS=>nCRAS); + nFWEI: nFWEB + port map (PADDI=>nFWE_c, nFWES=>nFWE); + RCLKI: RCLKB + port map (PADDI=>RCLK_c, RCLKS=>RCLK); + UFMSDOI: UFMSDOB + port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO); + VHI_INST: VHI + port map (Z=>VCCI); + PUR_INST: PUR + port map (PUR=>VCCI); + GSR_INST: GSR + port map (GSR=>VCCI); + VLO_INST: VLO + port map (Z=>GNDI_TSALL); + TSALL_INST: TSALL + port map (TSALL=>GNDI_TSALL); + end Structure; + + + + library IEEE, vital2000, MACHXO; + configuration Structure_CON of RAM2GS is + for Structure + end for; + end Structure_CON; + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf new file mode 100644 index 0000000..834db9e --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.sdf @@ -0,0 +1,3036 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Tue Aug 15 05:03:22 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_14") + (INSTANCE SLICE_14) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_18") + (INSTANCE SLICE_18) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_23") + (INSTANCE SLICE_23) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_25") + (INSTANCE SLICE_25) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_26") + (INSTANCE SLICE_26) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_31") + (INSTANCE SLICE_31) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_34") + (INSTANCE SLICE_34) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_35") + (INSTANCE SLICE_35) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_36") + (INSTANCE SLICE_36) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_43") + (INSTANCE SLICE_43) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_49") + (INSTANCE SLICE_49) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_56") + (INSTANCE SLICE_56) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_58") + (INSTANCE SLICE_58) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_60") + (INSTANCE SLICE_60) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_61") + (INSTANCE SLICE_61) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_63") + (INSTANCE SLICE_63) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_64") + (INSTANCE SLICE_64) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_65") + (INSTANCE SLICE_65) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_66") + (INSTANCE SLICE_66) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_67") + (INSTANCE SLICE_67) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_68") + (INSTANCE SLICE_68) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_69") + (INSTANCE SLICE_69) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "RCKEEN_I_0_445_SLICE_70") + (INSTANCE RCKEEN_I_0_445\/SLICE_70) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i26_SLICE_71") + (INSTANCE i26\/SLICE_71) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i2099_SLICE_72") + (INSTANCE i2099\/SLICE_72) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i26_adj_28_SLICE_73") + (INSTANCE i26_adj_28\/SLICE_73) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_74") + (INSTANCE SLICE_74) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_75") + (INSTANCE SLICE_75) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_76") + (INSTANCE SLICE_76) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_80") + (INSTANCE SLICE_80) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_81") + (INSTANCE SLICE_81) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_84") + (INSTANCE SLICE_84) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_85") + (INSTANCE SLICE_85) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_102") + (INSTANCE SLICE_102) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_103") + (INSTANCE SLICE_103) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_104") + (INSTANCE SLICE_104) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_105") + (INSTANCE SLICE_105) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "RD_7_") + (INSTANCE RD\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD7 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD7 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD7) (1250:1250:1250)) + (WIDTH (negedge RD7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_6_") + (INSTANCE RD\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD6 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD6 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD6) (1250:1250:1250)) + (WIDTH (negedge RD6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_5_") + (INSTANCE RD\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD5 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD5 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD5) (1250:1250:1250)) + (WIDTH (negedge RD5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_4_") + (INSTANCE RD\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD4 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD4 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD4) (1250:1250:1250)) + (WIDTH (negedge RD4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_3_") + (INSTANCE RD\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD3 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD3 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD3) (1250:1250:1250)) + (WIDTH (negedge RD3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_2_") + (INSTANCE RD\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD2 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD2 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD2) (1250:1250:1250)) + (WIDTH (negedge RD2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_1_") + (INSTANCE RD\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD1 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD1 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD1) (1250:1250:1250)) + (WIDTH (negedge RD1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_0_") + (INSTANCE RD\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD0 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD0 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD0) (1250:1250:1250)) + (WIDTH (negedge RD0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Dout_7_") + (INSTANCE Dout\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout7 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_6_") + (INSTANCE Dout\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout6 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_5_") + (INSTANCE Dout\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout5 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_4_") + (INSTANCE Dout\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout4 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_3_") + (INSTANCE Dout\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout3 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_2_") + (INSTANCE Dout\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout2 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1_") + (INSTANCE Dout\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0_") + (INSTANCE Dout\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "LED") + (INSTANCE LED_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO LED (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_") + (INSTANCE RBA\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_0_") + (INSTANCE RBA\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_11_") + (INSTANCE RA\[11\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA11 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_10_") + (INSTANCE RA\[10\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA10 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_9_") + (INSTANCE RA\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA9 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_8_") + (INSTANCE RA\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA8 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_7_") + (INSTANCE RA\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA7 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_6_") + (INSTANCE RA\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA6 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_5_") + (INSTANCE RA\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA5 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_4_") + (INSTANCE RA\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA4 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_3_") + (INSTANCE RA\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA3 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_2_") + (INSTANCE RA\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA2 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_1_") + (INSTANCE RA\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_0_") + (INSTANCE RA\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRCS") + (INSTANCE nRCS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RCKE") + (INSTANCE RCKE_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RCKE (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRWE") + (INSTANCE nRWE_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRWE (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRRAS") + (INSTANCE nRRAS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRRAS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRCAS") + (INSTANCE nRCAS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCAS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMH") + (INSTANCE RDQMH_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMH (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RDQML") + (INSTANCE RDQML_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQML (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nUFMCS") + (INSTANCE nUFMCS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nUFMCS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "UFMCLK") + (INSTANCE UFMCLK_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMCLK (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "UFMSDI") + (INSTANCE UFMSDI_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMSDI (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "PHI2") + (INSTANCE PHI2_I) + (DELAY + (ABSOLUTE + (IOPATH PHI2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI2) (1250:1250:1250)) + (WIDTH (negedge PHI2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_9_") + (INSTANCE MAin\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (1250:1250:1250)) + (WIDTH (negedge MAin9) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_8_") + (INSTANCE MAin\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (1250:1250:1250)) + (WIDTH (negedge MAin8) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_7_") + (INSTANCE MAin\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (1250:1250:1250)) + (WIDTH (negedge MAin7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_6_") + (INSTANCE MAin\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (1250:1250:1250)) + (WIDTH (negedge MAin6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_5_") + (INSTANCE MAin\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (1250:1250:1250)) + (WIDTH (negedge MAin5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_4_") + (INSTANCE MAin\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (1250:1250:1250)) + (WIDTH (negedge MAin4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_3_") + (INSTANCE MAin\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (1250:1250:1250)) + (WIDTH (negedge MAin3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_2_") + (INSTANCE MAin\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (1250:1250:1250)) + (WIDTH (negedge MAin2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_1_") + (INSTANCE MAin\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (1250:1250:1250)) + (WIDTH (negedge MAin1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_0_") + (INSTANCE MAin\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (1250:1250:1250)) + (WIDTH (negedge MAin0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "CROW_1_") + (INSTANCE CROW\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (1250:1250:1250)) + (WIDTH (negedge CROW1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "CROW_0_") + (INSTANCE CROW\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (1250:1250:1250)) + (WIDTH (negedge CROW0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_7_") + (INSTANCE Din\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (1250:1250:1250)) + (WIDTH (negedge Din7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_6_") + (INSTANCE Din\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (1250:1250:1250)) + (WIDTH (negedge Din6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_5_") + (INSTANCE Din\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (1250:1250:1250)) + (WIDTH (negedge Din5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_4_") + (INSTANCE Din\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (1250:1250:1250)) + (WIDTH (negedge Din4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_3_") + (INSTANCE Din\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (1250:1250:1250)) + (WIDTH (negedge Din3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_2_") + (INSTANCE Din\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (1250:1250:1250)) + (WIDTH (negedge Din2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_1_") + (INSTANCE Din\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (1250:1250:1250)) + (WIDTH (negedge Din1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_0_") + (INSTANCE Din\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (1250:1250:1250)) + (WIDTH (negedge Din0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nCCAS") + (INSTANCE nCCAS_I) + (DELAY + (ABSOLUTE + (IOPATH nCCAS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCCAS) (1250:1250:1250)) + (WIDTH (negedge nCCAS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nCRAS") + (INSTANCE nCRAS_I) + (DELAY + (ABSOLUTE + (IOPATH nCRAS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCRAS) (1250:1250:1250)) + (WIDTH (negedge nCRAS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nFWE") + (INSTANCE nFWE_I) + (DELAY + (ABSOLUTE + (IOPATH nFWE PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nFWE) (1250:1250:1250)) + (WIDTH (negedge nFWE) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RCLK") + (INSTANCE RCLK_I) + (DELAY + (ABSOLUTE + (IOPATH RCLK PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RCLK) (1250:1250:1250)) + (WIDTH (negedge RCLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "UFMSDO") + (INSTANCE UFMSDO_I) + (DELAY + (ABSOLUTE + (IOPATH UFMSDO PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge UFMSDO) (1250:1250:1250)) + (WIDTH (negedge UFMSDO) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_77/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_88/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_68/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_88/B1 (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_25/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_34/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_35/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_56/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_60/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_61/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_63/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_65/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_66/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_67/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_68/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_69/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_74/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_76/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_77/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_79/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_80/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_82/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_83/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_84/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_86/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_87/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_91/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_100/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/FCO SLICE_0/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/FCO SLICE_7/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_94/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_94/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_69/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_78/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_90/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_90/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/FCO SLICE_1/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/FCO SLICE_8/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_77/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_88/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_43/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_77/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/FCO SLICE_2/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_94/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_94/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_68/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_69/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_90/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/FCO SLICE_3/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_43/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_68/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_68/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/FCO SLICE_6/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_44/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_56/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_75/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_75/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_78/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_94/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_95/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_56/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_75/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_88/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_95/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_95/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/FCO SLICE_5/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_68/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_77/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q1 SLICE_77/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q1 SLICE_88/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_87/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_88/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_68/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_69/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_90/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_78/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_90/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_90/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_94/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_9/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_14/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_18/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI i26\/SLICE_71/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_82/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_83/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_84/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_89/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_89/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_97/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_99/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_9/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_14/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_18/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_76/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_82/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_84/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_89/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_89/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_9/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI i26\/SLICE_71/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI i26\/SLICE_71/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI i26_adj_28\/SLICE_73/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI i26_adj_28\/SLICE_73/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_76/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_82/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_83/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_84/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_89/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_97/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_98/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F1 SLICE_9/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 SLICE_9/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 i26\/SLICE_71/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F1 SLICE_9/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F1 SLICE_9/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F0 SLICE_9/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F0 SLICE_14/LSR (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_14/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_18/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_23/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_49/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_81/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_88/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_91/M1 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_93/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_99/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_101/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_102/CLK (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_14/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_23/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_32/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_32/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI i26_adj_28\/SLICE_73/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI i26_adj_28\/SLICE_73/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_79/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_92/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_92/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_92/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_99/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14/Q0 SLICE_14/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14/Q0 SLICE_14/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_14/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_76/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_82/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_85/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_86/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_89/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_98/M1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_105/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14/F1 i26\/SLICE_71/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_18/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_95/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_103/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F0 SLICE_18/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_18/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_18/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_96/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_101/B1 (0:0:0)(0:0:0)) + (INTERCONNECT i26_adj_28\/SLICE_73/OFX0 SLICE_18/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F0 SLICE_18/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F0 SLICE_79/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F0 SLICE_18/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_18/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/Q0 SLICE_83/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/Q0 SLICE_84/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_19/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_91/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_100/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_19/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_100/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q0 SLICE_19/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q0 SLICE_100/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F0 SLICE_19/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F1 SLICE_67/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F1 SLICE_87/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_23/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI i26\/SLICE_71/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI i26_adj_28\/SLICE_73/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_79/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_85/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_91/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_91/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_101/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_105/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_23/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_32/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_86/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_92/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_99/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F1 SLICE_23/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F1 SLICE_49/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F1 SLICE_84/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_23/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_49/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_76/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_83/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_85/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_86/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_91/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_101/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_105/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_105/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/Q0 SLICE_23/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/Q0 SLICE_32/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_23/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_49/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_86/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_88/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_89/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_93/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F0 SLICE_23/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F0 SLICE_23/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/Q0 SLICE_56/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_25/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_36/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_58/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_60/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_61/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_63/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_67/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 RCKEEN_I_0_445\/SLICE_70/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 i2099\/SLICE_72/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 i2099\/SLICE_72/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_80/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_104/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_25/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_34/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_35/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_35/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_58/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_60/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_63/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_65/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_65/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_66/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_68/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 RCKEEN_I_0_445\/SLICE_70/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_74/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_100/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_25/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_34/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_34/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_43/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_44/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_56/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_60/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_63/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_65/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_69/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_75/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_78/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_87/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_95/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_100/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_100/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_102/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_25/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_31/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_31/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_32/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_34/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_34/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_36/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_58/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_58/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_60/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_61/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_63/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 i2099\/SLICE_72/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 i2099\/SLICE_72/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_78/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_80/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_85/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_90/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_95/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_96/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_97/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_100/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_104/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F1 SLICE_25/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_76/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_77/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_80/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_82/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_84/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_86/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_87/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_100/CE (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_26/C1 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_78/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_83/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_85/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_90/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_95/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_96/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_97/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_98/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_26/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_58/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 RCKEEN_I_0_445\/SLICE_70/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 RCKEEN_I_0_445\/SLICE_70/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_74/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_74/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_103/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_26/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_49/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F1 SLICE_26/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/F1 LED_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_31/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_58/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_66/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_66/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 RCKEEN_I_0_445\/SLICE_70/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 i2099\/SLICE_72/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_80/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 SLICE_31/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 SLICE_84/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 SLICE_102/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 SLICE_102/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F1 SLICE_31/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F1 SLICE_63/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_31/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_82/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_102/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31/Q0 RA\[10\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31/F1 SLICE_61/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49/Q0 SLICE_32/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/Q0 RA\[11\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/F1 SLICE_83/B0 (0:0:0)(0:0:0)) + (INTERCONNECT RCKEEN_I_0_445\/SLICE_70/OFX0 SLICE_34/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34/F0 SLICE_34/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 SLICE_34/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 SLICE_58/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 SLICE_60/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34/Q0 SLICE_35/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34/F1 SLICE_60/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q0 SLICE_35/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q0 SLICE_60/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q0 RCKE_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q1 SLICE_35/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/Q0 SLICE_35/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/Q0 SLICE_74/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F0 SLICE_35/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q0 SLICE_35/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F1 SLICE_104/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q1 SLICE_67/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q1 SLICE_68/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q1 SLICE_74/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/F0 SLICE_36/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 SLICE_36/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/F1 SLICE_64/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/F1 SLICE_66/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F1 SLICE_43/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F1 SLICE_44/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_43/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_69/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_95/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/F1 SLICE_43/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q0 SLICE_43/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/F0 SLICE_43/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 SLICE_43/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 SLICE_44/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F0 SLICE_43/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F0 SLICE_44/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/Q0 UFMCLK_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F0 SLICE_44/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_44/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_75/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_78/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F1 SLICE_44/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F1 SLICE_78/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/Q0 SLICE_44/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F1 SLICE_44/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 UFMSDI_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_49/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_81/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_86/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_88/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_89/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49/F1 SLICE_49/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_49/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI i26\/SLICE_71/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI i26_adj_28\/SLICE_73/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI i26_adj_28\/SLICE_73/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_79/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_81/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_92/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_102/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_103/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_49/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI i26_adj_28\/SLICE_73/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI i26_adj_28\/SLICE_73/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_76/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_79/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_91/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_91/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_92/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_92/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_102/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_103/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49/F0 SLICE_49/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F1 SLICE_49/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_56/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_78/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_95/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F1 SLICE_56/D0 (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDO_I/PADDI SLICE_56/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F0 SLICE_56/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F0 SLICE_56/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F0 SLICE_58/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_58/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 i2099\/SLICE_72/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58/OFX0 SLICE_58/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58/Q0 nRCAS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/F1 SLICE_60/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/F1 SLICE_61/B1 (0:0:0)(0:0:0)) + (INTERCONNECT i2099\/SLICE_72/OFX0 SLICE_60/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/F0 SLICE_60/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/Q0 nRCS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 SLICE_61/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 SLICE_63/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 i2099\/SLICE_72/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 i2099\/SLICE_72/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 SLICE_87/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 SLICE_102/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_61/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_64/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_65/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_65/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_66/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_66/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_80/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 SLICE_61/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/Q0 SLICE_61/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/Q0 nRRAS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/OFX0 SLICE_61/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F0 SLICE_63/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F1 SLICE_63/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F0 SLICE_63/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F0 SLICE_63/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/Q0 nRWE_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_64/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_64/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_93/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_93/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_96/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_97/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_98/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_98/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_99/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_99/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_101/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_101/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_103/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_64/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_90/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_93/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_93/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q1 SLICE_64/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F0 SLICE_64/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_64/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_80/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_104/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F0 SLICE_64/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F1 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/Q1 SLICE_65/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/Q1 SLICE_87/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_65/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_66/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_67/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_74/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_80/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_100/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F0 SLICE_65/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_104/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F0 SLICE_66/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F0 SLICE_67/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q1 SLICE_67/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_67/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 nUFMCS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F0 RCKEEN_I_0_445\/SLICE_70/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F1 SLICE_69/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F0 SLICE_77/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q1 SLICE_74/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q1 SLICE_103/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F0 SLICE_69/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F0 SLICE_69/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F0 SLICE_69/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 RCKEEN_I_0_445\/SLICE_70/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 RCKEEN_I_0_445\/SLICE_70/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_74/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_74/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_103/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F1 i26\/SLICE_71/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F1 SLICE_83/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 i26\/SLICE_71/B0 (0:0:0)(0:0:0)) + (INTERCONNECT i26\/SLICE_71/OFX0 SLICE_105/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F0 SLICE_74/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F0 SLICE_104/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_75/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_87/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F1 SLICE_75/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F0 SLICE_76/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F0 SLICE_83/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_76/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_91/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q0 SLICE_76/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/Q1 SLICE_76/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F0 SLICE_77/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/Q0 SLICE_77/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q1 SLICE_77/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_87/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/Q1 SLICE_80/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_78/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_96/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_99/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_78/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_97/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_101/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/Q0 SLICE_101/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/Q1 SLICE_99/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_79/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F0 SLICE_79/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q1 SLICE_79/M1 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_79/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_89/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_92/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_98/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_103/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_105/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_105/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/Q0 SLICE_80/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/Q1 SLICE_81/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/Q0 SLICE_81/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/Q1 SLICE_81/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F1 SLICE_81/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F0 SLICE_81/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/Q0 SLICE_81/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F1 SLICE_81/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F1 SLICE_93/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F0 SLICE_82/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F0 SLICE_82/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F0 SLICE_83/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q0 SLICE_82/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F0 SLICE_84/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_84/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_85/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q0 SLICE_84/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q1 SLICE_100/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F0 SLICE_85/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_85/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_86/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_105/A0 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_85/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_85/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/Q0 RBA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/Q1 RBA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/Q0 SLICE_86/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/Q1 SLICE_86/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_87/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_88/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/Q0 SLICE_97/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/Q1 SLICE_96/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q0 RD\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q1 RD\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_90/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_98/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q0 SLICE_98/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/Q0 RD\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/Q1 RD\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F0 RDQMH_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_95/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_97/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_97/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/Q0 SLICE_97/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/Q1 SLICE_103/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_96/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_96/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_96/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/Q1 SLICE_96/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/Q0 SLICE_96/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/Q0 SLICE_101/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F1 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/Q1 SLICE_97/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/Q0 SLICE_98/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F1 RA\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/Q1 SLICE_99/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F1 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F0 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F1 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/Q0 SLICE_100/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F0 RA\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F1 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/Q0 RD\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F1 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/Q1 RD\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/Q0 RD\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[7\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[6\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[5\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[4\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[3\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[2\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[1\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[0\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/Q1 RD\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo new file mode 100644 index 0000000..d68e04c --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mapvo.vo @@ -0,0 +1,3678 @@ + +// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +// ldbanno -n Verilog -o RAM2GS_LCMXO256C_impl1_mapvo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd +// Netlist created on Tue Aug 15 05:03:20 2023 +// Netlist written on Tue Aug 15 05:03:22 2023 +// Design is for device LCMXO256C +// Design is for package TQFP100 +// Design is for performance grade 3 + +`timescale 1 ns / 1 ps + +module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, + RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, + UFMCLK, UFMSDI, UFMSDO ); + input PHI2; + input [9:0] MAin; + input [1:0] CROW; + input [7:0] Din; + input nCCAS, nCRAS, nFWE, RCLK, UFMSDO; + output [7:0] Dout; + output LED; + output [1:0] RBA; + output [11:0] RA; + output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI; + inout [7:0] RD; + wire FS_7, FS_6, RCLK_c, n2010, n2011, FS_15, FS_14, n2014, n2015, FS_5, + FS_4, n2009, FS_13, FS_12, n2013, FS_1, FS_0, n2008, FS_11, FS_10, + n2012, FS_3, FS_2, FS_9, FS_8, FS_17, FS_16, MAin_c_1, n1326, + MAin_c_0, n2263, ADSubmitted, n2242, n2459, n1413, C1Submitted_N_237, + PHI2_c, Din_c_6, C1Submitted, nFWE_c, n6_adj_3, n2284, MAin_c_5, + n2316, n26, MAin_c_2, n15, n2463, CmdEnable_N_248, + PHI2_N_120_enable_7, CmdEnable, PHI2r2, CmdSubmitted, PHI2r3, + \n2568\001/BUF1 , PHI2_N_120_enable_5, n2472, Din_c_5, Din_c_7, n1314, + Din_c_4, n8MEGEN, Din_c_0, Cmdn8MEGEN_N_264, PHI2_N_120_enable_4, + Cmdn8MEGEN, nRowColSel_N_35, RASr2, InitReady, Ready, + \n2568\000/BUF1 , RCLK_c_enable_25, RCLK_c_enable_23, nCRAS_c, CBR, + LEDEN, n2568, RCLK_c_enable_12, LED_N_84, nRowColSel_N_34, + nRCAS_N_165, n2208, n2209, nRWE_N_177, RA_0, n56, XOR8MEG, RA11_N_184, + RA_c, n2478, RCKEEN_N_122, RCKEEN_N_121, RCLK_c_enable_4, RCKEEN, + n2467, RCKE_c, RASr3, RASr, RCKE_N_132, CASr, nRWE_N_182, CASr2, + \n2568\002/BUF1 , Ready_N_292, n2469, n2462, n62, n1160, CmdUFMCLK, + UFMCLK_N_224, RCLK_c_enable_24, n1846, UFMCLK_c, n2470, n2272, n2471, + CmdUFMSDI, n2461, UFMSDI_N_231, UFMSDI_c, Din_c_1, n2324, Din_c_2, + Din_c_3, XOR8MEG_N_110, PHI2_N_120_enable_1, n2464, n1325, UFMSDO_c, + n8MEGEN_N_91, RCLK_c_enable_11, n2427, n15_adj_1, nRCAS_N_161, + nRCAS_c, n13, n2481, nRCS_N_136, nRCS_c, nRCS_N_139, nRowColSel_N_32, + n6, nRRAS_c, n2138, nRWE_N_178, n33, nRWE_N_171, RCLK_c_enable_3, + nRWE_c, nRowColSel, MAin_c_9, RowA_9, nRowColSel_N_28, n1502, n1410, + RA_1_9, Ready_N_296, nRowColSel_N_33, n1503, n2414, n1093, CmdUFMCS, + nUFMCS_c, n11, n1417, n2322, CASr3, n12, n2164, LEDEN_N_82, FWEr, + n2476, n2475, n13_adj_2, n1, n2214, n2328, n10, n2458, n732, n733, + n2290, n728, n729, n8, n727, MAin_c_7, MAin_c_6, RowA_6, RowA_7, + n2468, n1280, PHI2r, nCCAS_c, n726, Bank_3, Bank_6, Bank_5, n2278, + n2314, Bank_2, PHI2_N_120_enable_6, n14, n2460, n730, n2262, n2473, + n738, n737, n2474, n2253, CROW_c_1, CROW_c_0, RBA_c_0, RBA_c_1, n734, + n735, n7, n2451, Bank_0, Bank_1, WRD_0, WRD_1, MAin_c_8, RowA_8, + WRD_6, WRD_7, RDQMH_c, RDQML_c, MAin_c_4, RowA_4, RowA_5, MAin_c_3, + RowA_3, Bank_4, RowA_2, RA_1_3, Bank_7, RowA_0, RA_1_4, RowA_1, + RA_1_8, RA_1_0, RA_1_7, RA_1_1, n736, RA_1_6, RA_1_2, WRD_2, RA_1_5, + WRD_3, WRD_4, n984, WRD_5, Dout_c, Dout_0, Dout_1, Dout_2, Dout_3, + Dout_4, Dout_5, Dout_6, VCCI, GNDI_TSALL; + + SLICE_0 SLICE_0( .A1(FS_7), .A0(FS_6), .CLK(RCLK_c), .FCI(n2010), .Q0(FS_6), + .Q1(FS_7), .FCO(n2011)); + SLICE_1 SLICE_1( .A1(FS_15), .A0(FS_14), .CLK(RCLK_c), .FCI(n2014), + .Q0(FS_14), .Q1(FS_15), .FCO(n2015)); + SLICE_2 SLICE_2( .A1(FS_5), .A0(FS_4), .CLK(RCLK_c), .FCI(n2009), .Q0(FS_4), + .Q1(FS_5), .FCO(n2010)); + SLICE_3 SLICE_3( .A1(FS_13), .A0(FS_12), .CLK(RCLK_c), .FCI(n2013), + .Q0(FS_12), .Q1(FS_13), .FCO(n2014)); + SLICE_4 SLICE_4( .A1(FS_1), .A0(FS_0), .CLK(RCLK_c), .Q0(FS_0), .Q1(FS_1), + .FCO(n2008)); + SLICE_5 SLICE_5( .A1(FS_11), .A0(FS_10), .CLK(RCLK_c), .FCI(n2012), + .Q0(FS_10), .Q1(FS_11), .FCO(n2013)); + SLICE_6 SLICE_6( .A1(FS_3), .A0(FS_2), .CLK(RCLK_c), .FCI(n2008), .Q0(FS_2), + .Q1(FS_3), .FCO(n2009)); + SLICE_7 SLICE_7( .A1(FS_9), .A0(FS_8), .CLK(RCLK_c), .FCI(n2011), .Q0(FS_8), + .Q1(FS_9), .FCO(n2012)); + SLICE_8 SLICE_8( .A1(FS_17), .A0(FS_16), .CLK(RCLK_c), .FCI(n2015), + .Q0(FS_16), .Q1(FS_17)); + SLICE_9 SLICE_9( .C1(MAin_c_1), .B1(n1326), .A1(MAin_c_0), .D0(n2263), + .C0(ADSubmitted), .B0(n2242), .A0(n2459), .DI0(n1413), + .LSR(C1Submitted_N_237), .CLK(PHI2_c), .F0(n1413), .Q0(ADSubmitted), + .F1(n2263)); + SLICE_14 SLICE_14( .B1(Din_c_6), .A1(C1Submitted), .D0(MAin_c_1), + .C0(C1Submitted), .B0(n1326), .A0(nFWE_c), .DI0(n6_adj_3), + .LSR(C1Submitted_N_237), .CLK(PHI2_c), .F0(n6_adj_3), .Q0(C1Submitted), + .F1(n2284)); + SLICE_18 SLICE_18( .D1(MAin_c_5), .C1(n2316), .B1(n26), .A1(MAin_c_2), + .D0(n15), .C0(n1326), .B0(n2463), .A0(MAin_c_1), .DI0(CmdEnable_N_248), + .CE(PHI2_N_120_enable_7), .CLK(PHI2_c), .F0(CmdEnable_N_248), + .Q0(CmdEnable), .F1(n1326)); + SLICE_19 SLICE_19( .C1(PHI2r2), .B1(CmdSubmitted), .A1(PHI2r3), + .DI0(\n2568\001/BUF1 ), .CE(PHI2_N_120_enable_5), .CLK(PHI2_c), + .F0(\n2568\001/BUF1 ), .Q0(CmdSubmitted), .F1(n2472)); + SLICE_23 SLICE_23( .C1(Din_c_5), .B1(Din_c_7), .A1(Din_c_6), .D0(n1314), + .C0(Din_c_4), .B0(n8MEGEN), .A0(Din_c_0), .DI0(Cmdn8MEGEN_N_264), + .CE(PHI2_N_120_enable_4), .CLK(PHI2_c), .F0(Cmdn8MEGEN_N_264), + .Q0(Cmdn8MEGEN), .F1(n1314)); + SLICE_25 SLICE_25( .D1(nRowColSel_N_35), .C1(RASr2), .B1(InitReady), + .A1(Ready), .DI0(\n2568\000/BUF1 ), .CE(RCLK_c_enable_25), .CLK(RCLK_c), + .F0(\n2568\000/BUF1 ), .Q0(InitReady), .F1(RCLK_c_enable_23)); + SLICE_26 SLICE_26( .C1(nCRAS_c), .B1(CBR), .A1(LEDEN), .DI0(n2568), + .CE(RCLK_c_enable_12), .CLK(RCLK_c), .F0(n2568), .Q0(LEDEN), .F1(LED_N_84)); + SLICE_31 SLICE_31( .B1(nRowColSel_N_34), .A1(Ready), .C0(nRCAS_N_165), + .B0(Ready), .A0(n2208), .DI0(n2209), .LSR(nRWE_N_177), .CLK(RCLK_c), + .F0(n2209), .Q0(RA_0), .F1(n56)); + SLICE_32 SLICE_32( .B1(Din_c_7), .A1(Din_c_6), .C0(n8MEGEN), .B0(XOR8MEG), + .A0(Din_c_6), .DI0(RA11_N_184), .LSR(Ready), .CLK(PHI2_c), .F0(RA11_N_184), + .Q0(RA_c), .F1(n2478)); + SLICE_34 SLICE_34( .C1(Ready), .B1(InitReady), .A1(RASr2), .C0(Ready), + .B0(RCKEEN_N_122), .A0(InitReady), .DI0(RCKEEN_N_121), + .CE(RCLK_c_enable_4), .CLK(RCLK_c), .F0(RCKEEN_N_121), .Q0(RCKEEN), + .F1(n2467)); + SLICE_35 SLICE_35( .B1(RCKE_c), .A1(RASr2), .D0(RASr3), .C0(RASr2), + .B0(RCKEEN), .A0(RASr), .DI0(RCKE_N_132), .M1(CASr), .CLK(RCLK_c), + .F0(RCKE_N_132), .Q0(RCKE_c), .F1(nRWE_N_182), .Q1(CASr2)); + SLICE_36 SLICE_36( .B1(nRowColSel_N_35), .A1(Ready), .DI0(\n2568\002/BUF1 ), + .CE(Ready_N_292), .CLK(RCLK_c), .F0(\n2568\002/BUF1 ), .Q0(Ready), + .F1(n2469)); + SLICE_43 SLICE_43( .D1(FS_1), .C1(n2462), .B1(n62), .A1(FS_4), + .C0(InitReady), .B0(n1160), .A0(CmdUFMCLK), .DI0(UFMCLK_N_224), + .CE(RCLK_c_enable_24), .LSR(n1846), .CLK(RCLK_c), .F0(UFMCLK_N_224), + .Q0(UFMCLK_c), .F1(n1160)); + SLICE_44 SLICE_44( .D1(FS_11), .C1(n2470), .B1(n2272), .A1(n2471), + .D0(CmdUFMSDI), .C0(InitReady), .B0(n2462), .A0(n2461), .DI0(UFMSDI_N_231), + .CE(RCLK_c_enable_24), .LSR(n1846), .CLK(RCLK_c), .F0(UFMSDI_N_231), + .Q0(UFMSDI_c), .F1(n2462)); + SLICE_49 SLICE_49( .D1(Din_c_1), .C1(n1314), .B1(LEDEN), .A1(Din_c_4), + .D0(n2324), .C0(Din_c_2), .B0(Din_c_3), .A0(Din_c_0), .DI0(XOR8MEG_N_110), + .CE(PHI2_N_120_enable_1), .CLK(PHI2_c), .F0(XOR8MEG_N_110), .Q0(XOR8MEG), + .F1(n2324)); + SLICE_56 SLICE_56( .C1(FS_10), .B1(n2464), .A1(FS_11), .D0(n1325), + .C0(InitReady), .B0(Cmdn8MEGEN), .A0(UFMSDO_c), .DI0(n8MEGEN_N_91), + .CE(RCLK_c_enable_11), .CLK(RCLK_c), .F0(n8MEGEN_N_91), .Q0(n8MEGEN), + .F1(n1325)); + SLICE_58 SLICE_58( .D1(n2427), .C1(RASr2), .B1(CBR), .A1(Ready), .C0(Ready), + .B0(n15_adj_1), .A0(nRowColSel_N_34), .DI0(nRCAS_N_161), + .M0(nRowColSel_N_35), .CE(RCLK_c_enable_4), .CLK(RCLK_c), + .OFX0(nRCAS_N_161), .Q0(nRCAS_c)); + SLICE_60 SLICE_60( .D1(Ready), .C1(RCKE_c), .B1(InitReady), .A1(RASr2), + .D0(nRowColSel_N_35), .C0(n13), .B0(n2481), .A0(n2467), .DI0(nRCS_N_136), + .CE(RCLK_c_enable_4), .CLK(RCLK_c), .F0(nRCS_N_136), .Q0(nRCS_c), .F1(n13)); + SLICE_61 SLICE_61( .C1(nRCS_N_139), .B1(n13), .A1(Ready), + .D0(nRowColSel_N_32), .C0(n6), .B0(nRRAS_c), .A0(n56), .DI0(n2138), + .M0(nRowColSel_N_35), .CLK(RCLK_c), .OFX0(n2138), .Q0(nRRAS_c)); + SLICE_63 SLICE_63( .D1(nRCS_N_139), .C1(InitReady), .B1(RASr2), + .A1(nRowColSel_N_35), .D0(n2208), .C0(Ready), .B0(nRWE_N_178), .A0(n33), + .DI0(nRWE_N_171), .CE(RCLK_c_enable_3), .CLK(RCLK_c), .F0(nRWE_N_171), + .Q0(nRWE_c), .F1(n2208)); + SLICE_64 SLICE_64( .C1(nRowColSel), .B1(MAin_c_9), .A1(RowA_9), + .D0(nRowColSel_N_32), .C0(nRowColSel_N_28), .B0(n1502), .A0(nRowColSel), + .DI0(n1410), .LSR(n2469), .CLK(RCLK_c), .F0(n1410), .Q0(nRowColSel), + .F1(RA_1_9)); + SLICE_65 SLICE_65( .D1(InitReady), .C1(Ready_N_296), .B1(RASr2), + .A1(nRowColSel_N_32), .B0(nRowColSel_N_33), .A0(nRowColSel_N_32), + .DI0(n1503), .LSR(RASr2), .CLK(RCLK_c), .F0(n1503), .Q0(nRowColSel_N_32), + .F1(n2414)); + SLICE_66 SLICE_66( .D1(nRowColSel_N_33), .C1(nRowColSel_N_34), .B1(n2469), + .A1(nRowColSel_N_32), .B0(RASr2), .A0(nRowColSel_N_32), .DI0(n1093), + .LSR(nRowColSel_N_34), .CLK(RCLK_c), .F0(n1093), .Q0(nRowColSel_N_33), + .F1(RCLK_c_enable_4)); + SLICE_67 SLICE_67( .C1(n2472), .B1(CmdUFMCS), .A1(nUFMCS_c), .B0(CASr2), + .A0(nRowColSel_N_33), .M0(n1093), .LSR(nRowColSel_N_35), .CLK(RCLK_c), + .F0(n11), .Q0(nRowColSel_N_34), .F1(n1417)); + SLICE_68 SLICE_68( .B1(FS_12), .A1(FS_17), .D0(FS_3), .C0(FS_6), .B0(FS_1), + .A0(FS_0), .M1(CASr2), .M0(RASr2), .CLK(RCLK_c), .F0(n2322), + .Q0(nRowColSel_N_35), .F1(n2471), .Q1(CASr3)); + SLICE_69 SLICE_69( .D1(FS_14), .C1(FS_12), .B1(n12), .A1(FS_17), + .C0(InitReady), .B0(n1417), .A0(n62), .DI0(n2164), .LSR(LEDEN_N_82), + .CLK(RCLK_c), .F0(n2164), .Q0(nUFMCS_c), .F1(n62)); + RCKEEN_I_0_445_SLICE_70 \RCKEEN_I_0_445/SLICE_70 ( .C1(RASr2), .B1(FWEr), + .A1(CBR), .D0(nRowColSel_N_34), .C0(FWEr), .B0(n11), .A0(CBR), + .M0(nRowColSel_N_35), .OFX0(RCKEEN_N_122)); + i26_SLICE_71 \i26/SLICE_71 ( .D1(n2284), .C1(n2476), .B1(MAin_c_1), + .A1(MAin_c_0), .D0(ADSubmitted), .C0(MAin_c_0), .B0(n2475), .A0(Din_c_5), + .M0(Din_c_2), .OFX0(n13_adj_2)); + i2099_SLICE_72 \i2099/SLICE_72 ( .D1(nRowColSel_N_34), .C1(nRowColSel_N_35), + .B1(Ready), .A1(nRCS_N_139), .C0(nRowColSel_N_35), .B0(Ready), + .A0(nRCS_N_139), .M0(n15_adj_1), .OFX0(n2481)); + i26_adj_28_SLICE_73 \i26_adj_28/SLICE_73 ( .D1(MAin_c_0), .C1(Din_c_2), + .B1(Din_c_3), .A1(Din_c_6), .D0(MAin_c_0), .C0(Din_c_2), .B0(Din_c_3), + .A0(Din_c_6), .M0(Din_c_5), .OFX0(n15)); + SLICE_74 SLICE_74( .D1(n1), .C1(nRowColSel_N_33), .B1(CBR), .A1(FWEr), + .D0(CASr3), .C0(CASr2), .B0(FWEr), .A0(CBR), .M1(RASr2), .M0(RASr), + .CLK(RCLK_c), .F0(n1), .Q0(RASr2), .F1(n15_adj_1), .Q1(RASr3)); + SLICE_75 SLICE_75( .C1(InitReady), .B1(FS_11), .A1(n2214), .D0(FS_11), + .C0(n2272), .B0(n2328), .A0(FS_10), .F0(n2214), .F1(RCLK_c_enable_12)); + SLICE_76 SLICE_76( .D1(MAin_c_0), .C1(n10), .B1(n1326), .A1(nFWE_c), + .D0(n2458), .C0(Din_c_4), .B0(Din_c_5), .A0(Din_c_3), .M1(n732), .M0(n733), + .CE(RCLK_c_enable_23), .CLK(RCLK_c), .F0(PHI2_N_120_enable_4), .Q0(n732), + .F1(n2458), .Q1(nRWE_N_177)); + SLICE_77 SLICE_77( .D1(FS_7), .C1(n2322), .B1(FS_4), .A1(n2290), .C0(FS_9), + .B0(FS_5), .A0(FS_2), .M1(n728), .M0(n729), .CE(RCLK_c_enable_23), + .CLK(RCLK_c), .F0(n2290), .Q0(n728), .F1(n8), .Q1(n727)); + SLICE_78 SLICE_78( .D1(n2471), .C1(n2272), .B1(FS_14), .A1(FS_16), + .C0(InitReady), .B0(n2464), .A0(FS_11), .M1(MAin_c_7), .M0(MAin_c_6), + .LSR(Ready), .CLK(nCRAS_c), .F0(n1846), .Q0(RowA_6), .F1(n2464), + .Q1(RowA_7)); + SLICE_79 SLICE_79( .C1(Din_c_5), .B1(Din_c_3), .A1(Din_c_6), .D0(n2468), + .C0(n1280), .B0(n2463), .A0(Din_c_2), .M1(PHI2r), .M0(nCCAS_c), + .CLK(RCLK_c), .F0(C1Submitted_N_237), .Q0(CASr), .F1(n2468), .Q1(PHI2r2)); + SLICE_80 SLICE_80( .B1(nRowColSel_N_33), .A1(nRowColSel_N_34), + .D0(nRowColSel_N_35), .C0(n1502), .B0(nRowColSel_N_32), .A0(Ready), + .M1(n726), .M0(n727), .CE(RCLK_c_enable_23), .CLK(RCLK_c), + .F0(RCLK_c_enable_3), .Q0(n726), .F1(n1502), .Q1(Ready_N_296)); + SLICE_81 SLICE_81( .B1(Bank_3), .A1(Bank_6), .D0(Bank_5), .C0(n2278), + .B0(n2314), .A0(Bank_2), .M1(Din_c_2), .M0(Din_c_1), + .CE(PHI2_N_120_enable_6), .CLK(PHI2_c), .F0(n26), .Q0(CmdUFMCLK), + .F1(n2278), .Q1(CmdUFMCS)); + SLICE_82 SLICE_82( .D1(MAin_c_1), .C1(n14), .B1(n2460), .A1(MAin_c_0), + .B0(n1326), .A0(nFWE_c), .M1(n730), .M0(nRWE_N_177), .CE(RCLK_c_enable_23), + .CLK(RCLK_c), .F0(n2460), .Q0(n730), .F1(PHI2_N_120_enable_7), .Q1(n729)); + SLICE_83 SLICE_83( .D1(n2476), .C1(n2460), .B1(n10), .A1(MAin_c_0), + .D0(MAin_c_1), .C0(CmdEnable), .B0(n2478), .A0(Din_c_4), .M0(nCRAS_c), + .CLK(RCLK_c), .F0(n10), .Q0(RASr), .F1(PHI2_N_120_enable_6)); + SLICE_84 SLICE_84( .D1(n1314), .C1(n2262), .B1(CmdEnable), .A1(n2473), + .C0(MAin_c_1), .B0(n1326), .A0(MAin_c_0), .M1(n738), .M0(nRCAS_N_165), + .CE(RCLK_c_enable_23), .CLK(RCLK_c), .F0(n2262), .Q0(n738), + .F1(PHI2_N_120_enable_1), .Q1(n737)); + SLICE_85 SLICE_85( .D1(n2474), .C1(Din_c_5), .B1(n2253), .A1(n2473), + .B0(nFWE_c), .A0(Din_c_4), .M1(CROW_c_1), .M0(CROW_c_0), .LSR(Ready), + .CLK(nCRAS_c), .F0(n2473), .Q0(RBA_c_0), .F1(n2242), .Q1(RBA_c_1)); + SLICE_86 SLICE_86( .C1(Din_c_1), .B1(Din_c_0), .A1(Din_c_7), .C0(n2253), + .B0(nFWE_c), .A0(Din_c_4), .M1(n734), .M0(n735), .CE(RCLK_c_enable_23), + .CLK(RCLK_c), .F0(n2463), .Q0(n734), .F1(n2253), .Q1(n733)); + SLICE_87 SLICE_87( .B1(n2214), .A1(FS_8), .D0(n8), .C0(InitReady), + .B0(n2472), .A0(n7), .M1(nRCS_N_139), .M0(Ready_N_296), + .CE(RCLK_c_enable_23), .CLK(RCLK_c), .F0(RCLK_c_enable_11), + .Q0(nRCS_N_139), .F1(n7), .Q1(nRCAS_N_165)); + SLICE_88 SLICE_88( .C1(FS_10), .B1(FS_6), .A1(n2451), .D0(FS_8), .C0(FS_5), + .B0(FS_9), .A0(FS_7), .M1(Din_c_1), .M0(Din_c_0), .CLK(PHI2_c), .F0(n2451), + .Q0(Bank_0), .F1(n2461), .Q1(Bank_1)); + SLICE_89 SLICE_89( .C1(MAin_c_1), .B1(n1326), .A1(nFWE_c), .C0(MAin_c_0), + .B0(n1326), .A0(MAin_c_1), .M1(Din_c_1), .M0(Din_c_0), .CLK(nCCAS_c), + .F0(n1280), .Q0(WRD_0), .F1(n2459), .Q1(WRD_1)); + SLICE_90 SLICE_90( .D1(FS_16), .C1(FS_14), .B1(FS_12), .A1(FS_17), + .B0(FS_14), .A0(FS_16), .M1(MAin_c_9), .M0(MAin_c_8), .LSR(Ready), + .CLK(nCRAS_c), .F0(n2470), .Q0(RowA_8), .F1(n2328), .Q1(RowA_9)); + SLICE_91 SLICE_91( .B1(Din_c_5), .A1(Din_c_3), .D0(n2458), .C0(Din_c_5), + .B0(Din_c_4), .A0(Din_c_3), .M1(PHI2_c), .M0(PHI2r2), .CLK(RCLK_c), + .F0(PHI2_N_120_enable_5), .Q0(PHI2r3), .F1(n2476), .Q1(PHI2r)); + SLICE_92 SLICE_92( .B1(Din_c_3), .A1(Din_c_6), .C0(Din_c_3), .B0(Din_c_2), + .A0(Din_c_6), .M1(Din_c_7), .M0(Din_c_6), .CLK(nCCAS_c), .F0(n2474), + .Q0(WRD_6), .F1(n2475), .Q1(WRD_7)); + SLICE_93 SLICE_93( .B1(nRowColSel), .A1(MAin_c_9), .B0(nRowColSel), + .A0(MAin_c_9), .M0(Din_c_0), .CE(PHI2_N_120_enable_6), .CLK(PHI2_c), + .F0(RDQMH_c), .Q0(CmdUFMSDI), .F1(RDQML_c)); + SLICE_94 SLICE_94( .B1(FS_15), .A1(FS_13), .D0(FS_11), .C0(FS_16), + .B0(FS_13), .A0(FS_15), .F0(n12), .F1(n2272)); + SLICE_95 SLICE_95( .B1(FS_10), .A1(n62), .D0(InitReady), .C0(FS_10), + .B0(n2464), .A0(FS_11), .M1(MAin_c_5), .M0(MAin_c_4), .LSR(Ready), + .CLK(nCRAS_c), .F0(LEDEN_N_82), .Q0(RowA_4), .F1(RCLK_c_enable_25), + .Q1(RowA_5)); + SLICE_96 SLICE_96( .C1(nRowColSel), .B1(MAin_c_3), .A1(RowA_3), .D0(Bank_1), + .C0(Bank_4), .B0(MAin_c_3), .A0(MAin_c_7), .M1(MAin_c_3), .M0(MAin_c_2), + .LSR(Ready), .CLK(nCRAS_c), .F0(n2316), .Q0(RowA_2), .F1(RA_1_3), + .Q1(RowA_3)); + SLICE_97 SLICE_97( .C1(nRowColSel), .B1(MAin_c_4), .A1(RowA_4), .D0(Bank_0), + .C0(Bank_7), .B0(MAin_c_4), .A0(MAin_c_6), .M1(MAin_c_1), .M0(MAin_c_0), + .LSR(Ready), .CLK(nCRAS_c), .F0(n2314), .Q0(RowA_0), .F1(RA_1_4), + .Q1(RowA_1)); + SLICE_98 SLICE_98( .C1(nRowColSel), .B1(MAin_c_0), .A1(RowA_0), + .C0(nRowColSel), .B0(MAin_c_8), .A0(RowA_8), .M1(nFWE_c), .M0(nCCAS_c), + .CLK(nCRAS_c), .F0(RA_1_8), .Q0(CBR), .F1(RA_1_0), .Q1(FWEr)); + SLICE_99 SLICE_99( .C1(nRowColSel), .B1(MAin_c_1), .A1(RowA_1), + .C0(nRowColSel), .B0(MAin_c_7), .A0(RowA_7), .M1(Din_c_7), .M0(Din_c_6), + .CLK(PHI2_c), .F0(RA_1_7), .Q0(Bank_6), .F1(RA_1_1), .Q1(Bank_7)); + SLICE_100 SLICE_100( .D1(Ready), .C1(nRowColSel_N_33), .B1(InitReady), + .A1(RASr2), .D0(InitReady), .C0(PHI2r2), .B0(CmdSubmitted), .A0(PHI2r3), + .M1(n736), .M0(n737), .CE(RCLK_c_enable_23), .CLK(RCLK_c), + .F0(RCLK_c_enable_24), .Q0(n736), .F1(n6), .Q1(n735)); + SLICE_101 SLICE_101( .C1(nRowColSel), .B1(MAin_c_2), .A1(RowA_2), + .C0(nRowColSel), .B0(MAin_c_6), .A0(RowA_6), .M1(Din_c_5), .M0(Din_c_4), + .CLK(PHI2_c), .F0(RA_1_6), .Q0(Bank_4), .F1(RA_1_2), .Q1(Bank_5)); + SLICE_102 SLICE_102( .B1(nRWE_N_177), .A1(nRCAS_N_165), .C0(nRCAS_N_165), + .B0(nRCS_N_139), .A0(InitReady), .M1(Din_c_3), .M0(Din_c_2), .CLK(PHI2_c), + .F0(n2427), .Q0(Bank_2), .F1(n33), .Q1(Bank_3)); + SLICE_103 SLICE_103( .C1(nRowColSel), .B1(MAin_c_5), .A1(RowA_5), .C0(CBR), + .B0(CASr3), .A0(FWEr), .M1(Din_c_3), .M0(Din_c_2), .CLK(nCCAS_c), + .F0(nRowColSel_N_28), .Q0(WRD_2), .F1(RA_1_5), .Q1(WRD_3)); + SLICE_104 SLICE_104( .B1(Ready), .A1(n2414), .D0(nRowColSel_N_35), + .C0(nRWE_N_182), .B0(n1502), .A0(n1), .F0(nRWE_N_178), .F1(Ready_N_292)); + SLICE_105 SLICE_105( .B1(nFWE_c), .A1(nCCAS_c), .C0(n13_adj_2), .B0(Din_c_4), + .A0(n2253), .M1(Din_c_5), .M0(Din_c_4), .CLK(nCCAS_c), .F0(n14), + .Q0(WRD_4), .F1(n984), .Q1(WRD_5)); + RD_7_ \RD[7]_I ( .PADDI(Dout_c), .PADDT(n984), .PADDO(WRD_7), .RD7(RD[7])); + RD_6_ \RD[6]_I ( .PADDI(Dout_0), .PADDT(n984), .PADDO(WRD_6), .RD6(RD[6])); + RD_5_ \RD[5]_I ( .PADDI(Dout_1), .PADDT(n984), .PADDO(WRD_5), .RD5(RD[5])); + RD_4_ \RD[4]_I ( .PADDI(Dout_2), .PADDT(n984), .PADDO(WRD_4), .RD4(RD[4])); + RD_3_ \RD[3]_I ( .PADDI(Dout_3), .PADDT(n984), .PADDO(WRD_3), .RD3(RD[3])); + RD_2_ \RD[2]_I ( .PADDI(Dout_4), .PADDT(n984), .PADDO(WRD_2), .RD2(RD[2])); + RD_1_ \RD[1]_I ( .PADDI(Dout_5), .PADDT(n984), .PADDO(WRD_1), .RD1(RD[1])); + RD_0_ \RD[0]_I ( .PADDI(Dout_6), .PADDT(n984), .PADDO(WRD_0), .RD0(RD[0])); + Dout_7_ \Dout[7]_I ( .PADDO(Dout_c), .Dout7(Dout[7])); + Dout_6_ \Dout[6]_I ( .PADDO(Dout_0), .Dout6(Dout[6])); + Dout_5_ \Dout[5]_I ( .PADDO(Dout_1), .Dout5(Dout[5])); + Dout_4_ \Dout[4]_I ( .PADDO(Dout_2), .Dout4(Dout[4])); + Dout_3_ \Dout[3]_I ( .PADDO(Dout_3), .Dout3(Dout[3])); + Dout_2_ \Dout[2]_I ( .PADDO(Dout_4), .Dout2(Dout[2])); + Dout_1_ \Dout[1]_I ( .PADDO(Dout_5), .Dout1(Dout[1])); + Dout_0_ \Dout[0]_I ( .PADDO(Dout_6), .Dout0(Dout[0])); + LED LED_I( .PADDO(LED_N_84), .LED(LED)); + RBA_1_ \RBA[1]_I ( .PADDO(RBA_c_1), .RBA1(RBA[1])); + RBA_0_ \RBA[0]_I ( .PADDO(RBA_c_0), .RBA0(RBA[0])); + RA_11_ \RA[11]_I ( .PADDO(RA_c), .RA11(RA[11])); + RA_10_ \RA[10]_I ( .PADDO(RA_0), .RA10(RA[10])); + RA_9_ \RA[9]_I ( .PADDO(RA_1_9), .RA9(RA[9])); + RA_8_ \RA[8]_I ( .PADDO(RA_1_8), .RA8(RA[8])); + RA_7_ \RA[7]_I ( .PADDO(RA_1_7), .RA7(RA[7])); + RA_6_ \RA[6]_I ( .PADDO(RA_1_6), .RA6(RA[6])); + RA_5_ \RA[5]_I ( .PADDO(RA_1_5), .RA5(RA[5])); + RA_4_ \RA[4]_I ( .PADDO(RA_1_4), .RA4(RA[4])); + RA_3_ \RA[3]_I ( .PADDO(RA_1_3), .RA3(RA[3])); + RA_2_ \RA[2]_I ( .PADDO(RA_1_2), .RA2(RA[2])); + RA_1_ \RA[1]_I ( .PADDO(RA_1_1), .RA1(RA[1])); + RA_0_ \RA[0]_I ( .PADDO(RA_1_0), .RA0(RA[0])); + nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS)); + RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE)); + nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE)); + nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS)); + nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS)); + RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH)); + RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML)); + nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS)); + UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK)); + UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI)); + PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2)); + MAin_9_ \MAin[9]_I ( .PADDI(MAin_c_9), .MAin9(MAin[9])); + MAin_8_ \MAin[8]_I ( .PADDI(MAin_c_8), .MAin8(MAin[8])); + MAin_7_ \MAin[7]_I ( .PADDI(MAin_c_7), .MAin7(MAin[7])); + MAin_6_ \MAin[6]_I ( .PADDI(MAin_c_6), .MAin6(MAin[6])); + MAin_5_ \MAin[5]_I ( .PADDI(MAin_c_5), .MAin5(MAin[5])); + MAin_4_ \MAin[4]_I ( .PADDI(MAin_c_4), .MAin4(MAin[4])); + MAin_3_ \MAin[3]_I ( .PADDI(MAin_c_3), .MAin3(MAin[3])); + MAin_2_ \MAin[2]_I ( .PADDI(MAin_c_2), .MAin2(MAin[2])); + MAin_1_ \MAin[1]_I ( .PADDI(MAin_c_1), .MAin1(MAin[1])); + MAin_0_ \MAin[0]_I ( .PADDI(MAin_c_0), .MAin0(MAin[0])); + CROW_1_ \CROW[1]_I ( .PADDI(CROW_c_1), .CROW1(CROW[1])); + CROW_0_ \CROW[0]_I ( .PADDI(CROW_c_0), .CROW0(CROW[0])); + Din_7_ \Din[7]_I ( .PADDI(Din_c_7), .Din7(Din[7])); + Din_6_ \Din[6]_I ( .PADDI(Din_c_6), .Din6(Din[6])); + Din_5_ \Din[5]_I ( .PADDI(Din_c_5), .Din5(Din[5])); + Din_4_ \Din[4]_I ( .PADDI(Din_c_4), .Din4(Din[4])); + Din_3_ \Din[3]_I ( .PADDI(Din_c_3), .Din3(Din[3])); + Din_2_ \Din[2]_I ( .PADDI(Din_c_2), .Din2(Din[2])); + Din_1_ \Din[1]_I ( .PADDI(Din_c_1), .Din1(Din[1])); + Din_0_ \Din[0]_I ( .PADDI(Din_c_0), .Din0(Din[0])); + nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS)); + nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS)); + nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE)); + RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK)); + UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO)); + VHI VHI_INST( .Z(VCCI)); + PUR PUR_INST( .PUR(VCCI)); + GSR GSR_INST( .GSR(VCCI)); + VLO VLO_INST( .Z(GNDI_TSALL)); + TSALL TSALL_INST( .TSALL(GNDI_TSALL)); +endmodule + +module SLICE_0 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_0/FS_610_add_4_8_S1 , GNDI, \SLICE_0/FS_610_add_4_8_S0 , + A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i7( .D0(VCCI), .D1(\SLICE_0/FS_610_add_4_8_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i6( .D0(VCCI), .D1(\SLICE_0/FS_610_add_4_8_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_8( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_0/FS_610_add_4_8_S0 ), .S1(\SLICE_0/FS_610_add_4_8_S1 ), .CO0(), + .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module vcc ( output PWR1 ); + + VHI INST1( .Z(PWR1)); +endmodule + +module gnd ( output PWR0 ); + + VLO INST1( .Z(PWR0)); +endmodule + +module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, + CO1 ); + + CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1)); + defparam inst1.INIT0 = 16'hfaaa; + defparam inst1.INIT1 = 16'hfaaa; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_1 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_1/FS_610_add_4_16_S1 , GNDI, + \SLICE_1/FS_610_add_4_16_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i15( .D0(VCCI), .D1(\SLICE_1/FS_610_add_4_16_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i14( .D0(VCCI), .D1(\SLICE_1/FS_610_add_4_16_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_16( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_1/FS_610_add_4_16_S0 ), .S1(\SLICE_1/FS_610_add_4_16_S1 ), + .CO0(), .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_2 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_2/FS_610_add_4_6_S1 , GNDI, \SLICE_2/FS_610_add_4_6_S0 , + A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i5( .D0(VCCI), .D1(\SLICE_2/FS_610_add_4_6_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i4( .D0(VCCI), .D1(\SLICE_2/FS_610_add_4_6_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_6( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_2/FS_610_add_4_6_S0 ), .S1(\SLICE_2/FS_610_add_4_6_S1 ), .CO0(), + .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_3 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_3/FS_610_add_4_14_S1 , GNDI, + \SLICE_3/FS_610_add_4_14_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i13( .D0(VCCI), .D1(\SLICE_3/FS_610_add_4_14_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i12( .D0(VCCI), .D1(\SLICE_3/FS_610_add_4_14_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_14( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_3/FS_610_add_4_14_S0 ), .S1(\SLICE_3/FS_610_add_4_14_S1 ), + .CO0(), .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_4 ( input A1, A0, CLK, output Q0, Q1, FCO ); + wire VCCI, \SLICE_4/FS_610_add_4_2_S1 , GNDI, \SLICE_4/FS_610_add_4_2_S0 , + A1_dly, CLK_dly, A0_dly; + + vmuxregsre FS_610__i1( .D0(VCCI), .D1(\SLICE_4/FS_610_add_4_2_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i0( .D0(VCCI), .D1(\SLICE_4/FS_610_add_4_2_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 FS_610_add_4_2( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), + .S0(\SLICE_4/FS_610_add_4_2_S0 ), .S1(\SLICE_4/FS_610_add_4_2_S1 ), .CO0(), + .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + endspecify + +endmodule + +module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, + CO1 ); + + CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1)); + defparam inst1.INIT0 = 16'h0555; + defparam inst1.INIT1 = 16'hfaaa; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_5 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_5/FS_610_add_4_12_S1 , GNDI, + \SLICE_5/FS_610_add_4_12_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i11( .D0(VCCI), .D1(\SLICE_5/FS_610_add_4_12_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i10( .D0(VCCI), .D1(\SLICE_5/FS_610_add_4_12_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_12( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_5/FS_610_add_4_12_S0 ), .S1(\SLICE_5/FS_610_add_4_12_S1 ), + .CO0(), .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_6 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_6/FS_610_add_4_4_S1 , GNDI, \SLICE_6/FS_610_add_4_4_S0 , + A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i3( .D0(VCCI), .D1(\SLICE_6/FS_610_add_4_4_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i2( .D0(VCCI), .D1(\SLICE_6/FS_610_add_4_4_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_4( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_6/FS_610_add_4_4_S0 ), .S1(\SLICE_6/FS_610_add_4_4_S1 ), .CO0(), + .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_7 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_7/FS_610_add_4_10_S1 , GNDI, + \SLICE_7/FS_610_add_4_10_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i9( .D0(VCCI), .D1(\SLICE_7/FS_610_add_4_10_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i8( .D0(VCCI), .D1(\SLICE_7/FS_610_add_4_10_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_10( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_7/FS_610_add_4_10_S0 ), .S1(\SLICE_7/FS_610_add_4_10_S1 ), + .CO0(), .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1 ); + wire VCCI, \SLICE_8/FS_610_add_4_18_S1 , GNDI, + \SLICE_8/FS_610_add_4_18_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i17( .D0(VCCI), .D1(\SLICE_8/FS_610_add_4_18_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i16( .D0(VCCI), .D1(\SLICE_8/FS_610_add_4_18_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_18( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_8/FS_610_add_4_18_S0 ), .S1(\SLICE_8/FS_610_add_4_18_S1 ), + .CO0(), .CO1()); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_9 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut4 i1_2_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40002 i1125_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 ADSubmitted_407( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut4 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40002 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h50DC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0003 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + +module SLICE_14 ( input B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40004 i1988_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40005 i2062_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0006 C1Submitted_406( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40004 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40005 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hE0F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0006 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_18 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40007 i13_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40008 i3_4_lut_adj_21( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdEnable_405( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40007 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40008 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_19 ( input C1, B1, A1, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40009 i2_3_lut_rep_29( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 \n2568\001/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre CmdSubmitted_411( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40009 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40010 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_23 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40011 i1_2_lut_3_lut_adj_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 Cmdn8MEGEN_I_93_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Cmdn8MEGEN_410( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40011 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCC5C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_25 ( input D1, C1, B1, A1, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40013 i3_3_lut_4_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 \n2568\000/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre InitReady_394( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40013 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_26 ( input C1, B1, A1, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40014 i2049_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 m1_lut( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre LEDEN_419( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40014 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_31 ( input B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40015 i1_2_lut_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40011 i2_3_lut_adj_27( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0006 RA10_400( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40015 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_32 ( input B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40004 Din_7__I_0_462_i6_2_lut_rep_35( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40016 RA11_I_54_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 RA11_385( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40016 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_34 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40017 i78_2_lut_rep_24_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 i1259_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre RCKEEN_401( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40018 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_35 ( input B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40019 i1_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40020 RCKE_I_0_449_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CASr2_383( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RCKE_395( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_36 ( input B1, A1, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40015 i771_2_lut_rep_26_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 \n2568\002/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre Ready_404( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_43 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40021 i919_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40022 i886_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 UFMCLK_416( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h3A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40022 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40023 i1_2_lut_rep_19_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40024 n2454_bdd_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 UFMSDI_417( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40025 i2028_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40026 i3_4_lut_adj_12( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre XOR8MEG_408( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40026 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_56 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut4 i1_2_lut_3_lut_adj_4( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40027 n8MEGEN_I_14_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre n8MEGEN_418( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCCC5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_58 ( input D1, C1, B1, A1, C0, B0, A0, DI0, M0, CE, CLK, output + OFX0, Q0 ); + wire \SLICE_58/SLICE_58_K1_H1 , GNDI, \SLICE_58/i2095/GATE_H0 , VCCI, + DI0_dly, CLK_dly, CE_dly; + + lut40028 SLICE_58_K1( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\SLICE_58/SLICE_58_K1_H1 )); + lut40029 \i2095/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\SLICE_58/i2095/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0030 nRCAS_398( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 SLICE_58_K0K1MUX( .D0(\SLICE_58/i2095/GATE_H0 ), + .D1(\SLICE_58/SLICE_58_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40028 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h7F2F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hBFBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0030 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40031 i1234_4_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40032 i1_4_lut_adj_17( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0030 nRCS_396( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40031 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFA88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_61 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, + Q0 ); + wire GNDI, \SLICE_61/SLICE_61_K1_H1 , \SLICE_61/i16/GATE_H0 , VCCI, + DI0_dly, CLK_dly; + + lut40033 SLICE_61_K1( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\SLICE_61/SLICE_61_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 \i16/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\SLICE_61/i16/GATE_H0 )); + vmuxregsre0030 nRRAS_397( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 SLICE_61_K0K1MUX( .D0(\SLICE_61/i16/GATE_H0 ), + .D1(\SLICE_61/SLICE_61_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h7373) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40035 i2_3_lut_4_lut_adj_8( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40036 nRWE_I_0_455_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0030 nRWE_399( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40036 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFC5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40018 MAin_9__I_0_427_i10_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40037 i1_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 nRowColSel_402( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_65 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40038 Ready_bdd_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 i1_2_lut_adj_25( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 S_FSM_i4( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40038 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_66 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40039 i2_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 i2057_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 S_FSM_i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input C1, B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; + + lut40041 i1129_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40019 i1_2_lut_adj_23( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 S_FSM_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h3A3A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_68 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40004 i2024_2_lut_rep_28( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 i2026_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CASr3_384( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre S_FSM_i1( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_69 ( input D1, C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40042 i6_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40018 i11_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0006 nUFMCS_415( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40042 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RCKEEN_I_0_445_SLICE_70 ( input C1, B1, A1, D0, C0, B0, A0, M0, output + OFX0 ); + wire GNDI, \RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/SLICE_70_K1_H1 , + \RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/GATE_H0 ; + + lut40043 \RCKEEN_I_0_445/SLICE_70_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/SLICE_70_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40044 \RCKEEN_I_0_445/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/GATE_H0 )); + selmux2 \RCKEEN_I_0_445/SLICE_70_K0K1MUX ( + .D0(\RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/GATE_H0 ), + .D1(\RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/SLICE_70_K1_H1 ), .SD(M0), + .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40043 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1F1F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40044 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h5540) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module i26_SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); + wire \i26/SLICE_71/i26/SLICE_71_K1_H1 , \i26/SLICE_71/i26/GATE_H0 ; + + lut40045 \i26/SLICE_71_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\i26/SLICE_71/i26/SLICE_71_K1_H1 )); + lut40046 \i26/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\i26/SLICE_71/i26/GATE_H0 )); + selmux2 \i26/SLICE_71_K0K1MUX ( .D0(\i26/SLICE_71/i26/GATE_H0 ), + .D1(\i26/SLICE_71/i26/SLICE_71_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40046 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module i2099_SLICE_72 ( input D1, C1, B1, A1, C0, B0, A0, M0, output OFX0 ); + wire \i2099/SLICE_72/i2099/SLICE_72_K1_H1 , GNDI, + \i2099/SLICE_72/i2099/GATE_H0 ; + + lut40047 \i2099/SLICE_72_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\i2099/SLICE_72/i2099/SLICE_72_K1_H1 )); + lut40048 \i2099/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\i2099/SLICE_72/i2099/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + selmux2 \i2099/SLICE_72_K0K1MUX ( .D0(\i2099/SLICE_72/i2099/GATE_H0 ), + .D1(\i2099/SLICE_72/i2099/SLICE_72_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40047 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2F23) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2F2F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module i26_adj_28_SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output + OFX0 ); + wire \i26_adj_28/SLICE_73/i26_adj_28/SLICE_73_K1_H1 , + \i26_adj_28/SLICE_73/i26_adj_28/GATE_H0 ; + + lut40049 \i26_adj_28/SLICE_73_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\i26_adj_28/SLICE_73/i26_adj_28/SLICE_73_K1_H1 )); + lut40050 \i26_adj_28/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\i26_adj_28/SLICE_73/i26_adj_28/GATE_H0 )); + selmux2 \i26_adj_28/SLICE_73_K0K1MUX ( + .D0(\i26_adj_28/SLICE_73/i26_adj_28/GATE_H0 ), + .D1(\i26_adj_28/SLICE_73/i26_adj_28/SLICE_73_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly; + + lut40051 i35_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40052 i3_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr3_381( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre RASr2_380( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1F10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_75 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40009 i2_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40053 i7_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40054 i5_3_lut_rep_15_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40055 i1_4_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hB300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_77 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40056 i3_4_lut_adj_18( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40011 i1994_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i13( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i12( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40039 i5_3_lut_rep_21_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40057 i2065_2_lut_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 RowA_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40058 i1_2_lut_rep_25_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40059 i2_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre PHI2r2_377( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre CASr_382( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_80 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40004 i1_2_lut_adj_16( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40060 i1_2_lut_3_lut_4_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i15( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i14( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40060 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_81 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40061 i1982_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40062 i12_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdUFMCS_412( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CmdUFMCLK_413( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40061 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_82 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40063 i2052_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 i1990_2_lut_rep_17( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i11( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i10( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0302) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, + F1 ); + wire M0_NOTIN, VCCI, GNDI, M0_dly, CLK_dly; + + lut40008 i1_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40026 i4_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr_379( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_84 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40056 i2_4_lut_adj_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40014 i1_2_lut_3_lut_adj_5( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_85 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40013 i2_3_lut_4_lut_adj_15( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 i2004_2_lut_rep_30( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 RBA__i2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RBA__i1( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_86 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40009 i2_3_lut_adj_10( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40064 i1_2_lut_rep_20_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre IS_FSM__i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_87 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40040 i2_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40065 i17_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_88 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40009 n2452_bdd_2_lut_rep_18_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40066 FS_6__bdd_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Bank_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0062) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40064 i1_2_lut_rep_16_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 i2_3_lut_adj_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre WRD_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_90 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40039 i2032_2_lut_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 i2_2_lut_rep_27( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0006 RowA_i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_91 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40061 i1_2_lut_rep_33( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40067 i2_4_lut_adj_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre PHI2r_376( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre PHI2r3_378( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40068 i1_2_lut_rep_32( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40069 i2_3_lut_rep_31( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre WRD_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40068 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40069 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_93 ( input B1, A1, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40070 i2060_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40019 i1512_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre CmdUFMSDI_414( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40004 i1976_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 i5_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_95 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40061 i1_2_lut_adj_22( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 i2055_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0006 RowA_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_96 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40018 MAin_9__I_0_427_i4_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 i2020_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 RowA_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_97 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40018 MAin_9__I_0_427_i5_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 i2018_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 RowA_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_98 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40018 MAin_9__I_0_427_i1_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 MAin_9__I_0_427_i9_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre FWEr_389( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CBR_390( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_99 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40018 MAin_9__I_0_427_i2_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 MAin_9__I_0_427_i8_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40072 i2_2_lut_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40073 i1_2_lut_4_lut_adj_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40072 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF0F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40073 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h08FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_101 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40018 MAin_9__I_0_427_i3_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 MAin_9__I_0_427_i7_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_102 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40004 i1_2_lut_adj_26( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 InitReady_bdd_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_103 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40018 MAin_9__I_0_427_i6_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 i2_3_lut_adj_14( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre WRD_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_104 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40004 n2414_bdd_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40074 n1_bdd_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40074 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF0DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_105 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40004 i1513_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40075 i2_3_lut_adj_20( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre WRD_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40075 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); + + mjiobuf Dout_pad_7__713( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), + .PADI(RD7)); + + specify + (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD7) = (0:0:0,0:0:0); + (RD7 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD7, 0:0:0); + $width (negedge RD7, 0:0:0); + endspecify + +endmodule + +module mjiobuf ( input I, T, output Z, PAD, input PADI ); + + IBPU INST1( .I(PADI), .O(Z)); + OBZPU INST2( .I(I), .T(T), .O(PAD)); +endmodule + +module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); + + mjiobuf Dout_pad_6__714( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), + .PADI(RD6)); + + specify + (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD6) = (0:0:0,0:0:0); + (RD6 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD6, 0:0:0); + $width (negedge RD6, 0:0:0); + endspecify + +endmodule + +module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); + + mjiobuf Dout_pad_5__715( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), + .PADI(RD5)); + + specify + (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD5) = (0:0:0,0:0:0); + (RD5 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD5, 0:0:0); + $width (negedge RD5, 0:0:0); + endspecify + +endmodule + +module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); + + mjiobuf Dout_pad_4__716( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), + .PADI(RD4)); + + specify + (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD4) = (0:0:0,0:0:0); + (RD4 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD4, 0:0:0); + $width (negedge RD4, 0:0:0); + endspecify + +endmodule + +module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); + + mjiobuf Dout_pad_3__717( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), + .PADI(RD3)); + + specify + (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD3) = (0:0:0,0:0:0); + (RD3 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD3, 0:0:0); + $width (negedge RD3, 0:0:0); + endspecify + +endmodule + +module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); + + mjiobuf Dout_pad_2__718( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), + .PADI(RD2)); + + specify + (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD2) = (0:0:0,0:0:0); + (RD2 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD2, 0:0:0); + $width (negedge RD2, 0:0:0); + endspecify + +endmodule + +module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); + + mjiobuf Dout_pad_1__719( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), + .PADI(RD1)); + + specify + (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD1) = (0:0:0,0:0:0); + (RD1 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD1, 0:0:0); + $width (negedge RD1, 0:0:0); + endspecify + +endmodule + +module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); + + mjiobuf Dout_pad_0__720( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), + .PADI(RD0)); + + specify + (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD0) = (0:0:0,0:0:0); + (RD0 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD0, 0:0:0); + $width (negedge RD0, 0:0:0); + endspecify + +endmodule + +module Dout_7_ ( input PADDO, output Dout7 ); + wire GNDI; + + mjiobuf0076 Dout_pad_7( .I(PADDO), .T(GNDI), .PAD(Dout7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module mjiobuf0076 ( input I, T, output PAD ); + + OBZPU INST5( .I(I), .T(T), .O(PAD)); +endmodule + +module Dout_6_ ( input PADDO, output Dout6 ); + wire GNDI; + + mjiobuf0076 Dout_pad_6( .I(PADDO), .T(GNDI), .PAD(Dout6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_5_ ( input PADDO, output Dout5 ); + wire GNDI; + + mjiobuf0076 Dout_pad_5( .I(PADDO), .T(GNDI), .PAD(Dout5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_4_ ( input PADDO, output Dout4 ); + wire GNDI; + + mjiobuf0076 Dout_pad_4( .I(PADDO), .T(GNDI), .PAD(Dout4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_3_ ( input PADDO, output Dout3 ); + wire GNDI; + + mjiobuf0076 Dout_pad_3( .I(PADDO), .T(GNDI), .PAD(Dout3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_2_ ( input PADDO, output Dout2 ); + wire GNDI; + + mjiobuf0076 Dout_pad_2( .I(PADDO), .T(GNDI), .PAD(Dout2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_1_ ( input PADDO, output Dout1 ); + wire GNDI; + + mjiobuf0076 Dout_pad_1( .I(PADDO), .T(GNDI), .PAD(Dout1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_0_ ( input PADDO, output Dout0 ); + wire GNDI; + + mjiobuf0076 Dout_pad_0( .I(PADDO), .T(GNDI), .PAD(Dout0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module LED ( input PADDO, output LED ); + wire GNDI; + + mjiobuf0076 LED_pad( .I(PADDO), .T(GNDI), .PAD(LED)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => LED) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_1_ ( input PADDO, output RBA1 ); + wire GNDI; + + mjiobuf0076 RBA_pad_1( .I(PADDO), .T(GNDI), .PAD(RBA1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RBA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_0_ ( input PADDO, output RBA0 ); + wire GNDI; + + mjiobuf0076 RBA_pad_0( .I(PADDO), .T(GNDI), .PAD(RBA0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RBA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_11_ ( input PADDO, output RA11 ); + wire GNDI; + + mjiobuf0076 RA_pad_11( .I(PADDO), .T(GNDI), .PAD(RA11)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_10_ ( input PADDO, output RA10 ); + wire GNDI; + + mjiobuf0076 RA_pad_10( .I(PADDO), .T(GNDI), .PAD(RA10)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_9_ ( input PADDO, output RA9 ); + wire GNDI; + + mjiobuf0076 RA_pad_9( .I(PADDO), .T(GNDI), .PAD(RA9)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_8_ ( input PADDO, output RA8 ); + wire GNDI; + + mjiobuf0076 RA_pad_8( .I(PADDO), .T(GNDI), .PAD(RA8)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_7_ ( input PADDO, output RA7 ); + wire GNDI; + + mjiobuf0076 RA_pad_7( .I(PADDO), .T(GNDI), .PAD(RA7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_6_ ( input PADDO, output RA6 ); + wire GNDI; + + mjiobuf0076 RA_pad_6( .I(PADDO), .T(GNDI), .PAD(RA6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_5_ ( input PADDO, output RA5 ); + wire GNDI; + + mjiobuf0076 RA_pad_5( .I(PADDO), .T(GNDI), .PAD(RA5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_4_ ( input PADDO, output RA4 ); + wire GNDI; + + mjiobuf0076 RA_pad_4( .I(PADDO), .T(GNDI), .PAD(RA4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_3_ ( input PADDO, output RA3 ); + wire GNDI; + + mjiobuf0076 RA_pad_3( .I(PADDO), .T(GNDI), .PAD(RA3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2_ ( input PADDO, output RA2 ); + wire GNDI; + + mjiobuf0076 RA_pad_2( .I(PADDO), .T(GNDI), .PAD(RA2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_1_ ( input PADDO, output RA1 ); + wire GNDI; + + mjiobuf0076 RA_pad_1( .I(PADDO), .T(GNDI), .PAD(RA1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_0_ ( input PADDO, output RA0 ); + wire GNDI; + + mjiobuf0076 RA_pad_0( .I(PADDO), .T(GNDI), .PAD(RA0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCS ( input PADDO, output nRCS ); + wire GNDI; + + mjiobuf0076 nRCS_pad( .I(PADDO), .T(GNDI), .PAD(nRCS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RCKE ( input PADDO, output RCKE ); + wire GNDI; + + mjiobuf0076 RCKE_pad( .I(PADDO), .T(GNDI), .PAD(RCKE)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RCKE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRWE ( input PADDO, output nRWE ); + wire GNDI; + + mjiobuf0076 nRWE_pad( .I(PADDO), .T(GNDI), .PAD(nRWE)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRWE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRRAS ( input PADDO, output nRRAS ); + wire GNDI; + + mjiobuf0076 nRRAS_pad( .I(PADDO), .T(GNDI), .PAD(nRRAS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRRAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCAS ( input PADDO, output nRCAS ); + wire GNDI; + + mjiobuf0076 nRCAS_pad( .I(PADDO), .T(GNDI), .PAD(nRCAS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRCAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQMH ( input PADDO, output RDQMH ); + wire GNDI; + + mjiobuf0076 RDQMH_pad( .I(PADDO), .T(GNDI), .PAD(RDQMH)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RDQMH) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQML ( input PADDO, output RDQML ); + wire GNDI; + + mjiobuf0076 RDQML_pad( .I(PADDO), .T(GNDI), .PAD(RDQML)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RDQML) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nUFMCS ( input PADDO, output nUFMCS ); + wire GNDI; + + mjiobuf0076 nUFMCS_pad( .I(PADDO), .T(GNDI), .PAD(nUFMCS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nUFMCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module UFMCLK ( input PADDO, output UFMCLK ); + wire GNDI; + + mjiobuf0076 UFMCLK_pad( .I(PADDO), .T(GNDI), .PAD(UFMCLK)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => UFMCLK) = (0:0:0,0:0:0); + endspecify + +endmodule + +module UFMSDI ( input PADDO, output UFMSDI ); + wire GNDI; + + mjiobuf0076 UFMSDI_pad( .I(PADDO), .T(GNDI), .PAD(UFMSDI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => UFMSDI) = (0:0:0,0:0:0); + endspecify + +endmodule + +module PHI2 ( output PADDI, input PHI2 ); + + mjiobuf0077 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + + specify + (PHI2 => PADDI) = (0:0:0,0:0:0); + $width (posedge PHI2, 0:0:0); + $width (negedge PHI2, 0:0:0); + endspecify + +endmodule + +module mjiobuf0077 ( output Z, input PAD ); + + IBPU INST1( .I(PAD), .O(Z)); +endmodule + +module MAin_9_ ( output PADDI, input MAin9 ); + + mjiobuf0077 MAin_pad_9( .Z(PADDI), .PAD(MAin9)); + + specify + (MAin9 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin9, 0:0:0); + $width (negedge MAin9, 0:0:0); + endspecify + +endmodule + +module MAin_8_ ( output PADDI, input MAin8 ); + + mjiobuf0077 MAin_pad_8( .Z(PADDI), .PAD(MAin8)); + + specify + (MAin8 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin8, 0:0:0); + $width (negedge MAin8, 0:0:0); + endspecify + +endmodule + +module MAin_7_ ( output PADDI, input MAin7 ); + + mjiobuf0077 MAin_pad_7( .Z(PADDI), .PAD(MAin7)); + + specify + (MAin7 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin7, 0:0:0); + $width (negedge MAin7, 0:0:0); + endspecify + +endmodule + +module MAin_6_ ( output PADDI, input MAin6 ); + + mjiobuf0077 MAin_pad_6( .Z(PADDI), .PAD(MAin6)); + + specify + (MAin6 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin6, 0:0:0); + $width (negedge MAin6, 0:0:0); + endspecify + +endmodule + +module MAin_5_ ( output PADDI, input MAin5 ); + + mjiobuf0077 MAin_pad_5( .Z(PADDI), .PAD(MAin5)); + + specify + (MAin5 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin5, 0:0:0); + $width (negedge MAin5, 0:0:0); + endspecify + +endmodule + +module MAin_4_ ( output PADDI, input MAin4 ); + + mjiobuf0077 MAin_pad_4( .Z(PADDI), .PAD(MAin4)); + + specify + (MAin4 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin4, 0:0:0); + $width (negedge MAin4, 0:0:0); + endspecify + +endmodule + +module MAin_3_ ( output PADDI, input MAin3 ); + + mjiobuf0077 MAin_pad_3( .Z(PADDI), .PAD(MAin3)); + + specify + (MAin3 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin3, 0:0:0); + $width (negedge MAin3, 0:0:0); + endspecify + +endmodule + +module MAin_2_ ( output PADDI, input MAin2 ); + + mjiobuf0077 MAin_pad_2( .Z(PADDI), .PAD(MAin2)); + + specify + (MAin2 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin2, 0:0:0); + $width (negedge MAin2, 0:0:0); + endspecify + +endmodule + +module MAin_1_ ( output PADDI, input MAin1 ); + + mjiobuf0077 MAin_pad_1( .Z(PADDI), .PAD(MAin1)); + + specify + (MAin1 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin1, 0:0:0); + $width (negedge MAin1, 0:0:0); + endspecify + +endmodule + +module MAin_0_ ( output PADDI, input MAin0 ); + + mjiobuf0077 MAin_pad_0( .Z(PADDI), .PAD(MAin0)); + + specify + (MAin0 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin0, 0:0:0); + $width (negedge MAin0, 0:0:0); + endspecify + +endmodule + +module CROW_1_ ( output PADDI, input CROW1 ); + + mjiobuf0077 CROW_pad_1( .Z(PADDI), .PAD(CROW1)); + + specify + (CROW1 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW1, 0:0:0); + $width (negedge CROW1, 0:0:0); + endspecify + +endmodule + +module CROW_0_ ( output PADDI, input CROW0 ); + + mjiobuf0077 CROW_pad_0( .Z(PADDI), .PAD(CROW0)); + + specify + (CROW0 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW0, 0:0:0); + $width (negedge CROW0, 0:0:0); + endspecify + +endmodule + +module Din_7_ ( output PADDI, input Din7 ); + + mjiobuf0077 Din_pad_7( .Z(PADDI), .PAD(Din7)); + + specify + (Din7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din7, 0:0:0); + $width (negedge Din7, 0:0:0); + endspecify + +endmodule + +module Din_6_ ( output PADDI, input Din6 ); + + mjiobuf0077 Din_pad_6( .Z(PADDI), .PAD(Din6)); + + specify + (Din6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din6, 0:0:0); + $width (negedge Din6, 0:0:0); + endspecify + +endmodule + +module Din_5_ ( output PADDI, input Din5 ); + + mjiobuf0077 Din_pad_5( .Z(PADDI), .PAD(Din5)); + + specify + (Din5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din5, 0:0:0); + $width (negedge Din5, 0:0:0); + endspecify + +endmodule + +module Din_4_ ( output PADDI, input Din4 ); + + mjiobuf0077 Din_pad_4( .Z(PADDI), .PAD(Din4)); + + specify + (Din4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din4, 0:0:0); + $width (negedge Din4, 0:0:0); + endspecify + +endmodule + +module Din_3_ ( output PADDI, input Din3 ); + + mjiobuf0077 Din_pad_3( .Z(PADDI), .PAD(Din3)); + + specify + (Din3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din3, 0:0:0); + $width (negedge Din3, 0:0:0); + endspecify + +endmodule + +module Din_2_ ( output PADDI, input Din2 ); + + mjiobuf0077 Din_pad_2( .Z(PADDI), .PAD(Din2)); + + specify + (Din2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din2, 0:0:0); + $width (negedge Din2, 0:0:0); + endspecify + +endmodule + +module Din_1_ ( output PADDI, input Din1 ); + + mjiobuf0077 Din_pad_1( .Z(PADDI), .PAD(Din1)); + + specify + (Din1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din1, 0:0:0); + $width (negedge Din1, 0:0:0); + endspecify + +endmodule + +module Din_0_ ( output PADDI, input Din0 ); + + mjiobuf0077 Din_pad_0( .Z(PADDI), .PAD(Din0)); + + specify + (Din0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din0, 0:0:0); + $width (negedge Din0, 0:0:0); + endspecify + +endmodule + +module nCCAS ( output PADDI, input nCCAS ); + + mjiobuf0077 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + + specify + (nCCAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCCAS, 0:0:0); + $width (negedge nCCAS, 0:0:0); + endspecify + +endmodule + +module nCRAS ( output PADDI, input nCRAS ); + + mjiobuf0077 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + + specify + (nCRAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCRAS, 0:0:0); + $width (negedge nCRAS, 0:0:0); + endspecify + +endmodule + +module nFWE ( output PADDI, input nFWE ); + + mjiobuf0077 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + + specify + (nFWE => PADDI) = (0:0:0,0:0:0); + $width (posedge nFWE, 0:0:0); + $width (negedge nFWE, 0:0:0); + endspecify + +endmodule + +module RCLK ( output PADDI, input RCLK ); + + mjiobuf0077 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + + specify + (RCLK => PADDI) = (0:0:0,0:0:0); + $width (posedge RCLK, 0:0:0); + $width (negedge RCLK, 0:0:0); + endspecify + +endmodule + +module UFMSDO ( output PADDI, input UFMSDO ); + + mjiobuf0077 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); + + specify + (UFMSDO => PADDI) = (0:0:0,0:0:0); + $width (posedge UFMSDO, 0:0:0); + $width (negedge UFMSDO, 0:0:0); + endspecify + +endmodule diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html new file mode 100644 index 0000000..56f2c31 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_mrp.html @@ -0,0 +1,368 @@ + +Project Summary + + +
    
+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+
+Design Information
+
+Command line:   map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial
+     RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr
+     RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf D:/OneDrive/
+     Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf
+     -lpf
+     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf -c
+     0 -gui -msgset
+     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO256CTQFP100
+Target Performance:   3
+Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.1.454
+Mapped on:  08/15/23  05:03:20
+
+
+Design Summary
+   Number of PFU registers:   102 out of   256 (40%)
+   Number of SLICEs:        71 out of   128 (55%)
+      SLICEs as Logic/ROM:     71 out of   128 (55%)
+      SLICEs as RAM:            0 out of    64 (0%)
+      SLICEs as Carry:          9 out of   128 (7%)
+   Number of LUT4s:        142 out of   256 (55%)
+      Number used as logic LUTs:        124
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       18
+      Number used as shift registers:     0
+   Number of external PIOs: 67 out of 78 (86%)
+   Number of GSRs:  0 out of 1 (0%)
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   Number of TSALL: 0 out of 1 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  4
+     Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+   Number of Clock Enables:  13
+     Net PHI2_N_120_enable_4: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
+     Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
+     Net RCLK_c_enable_12: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_5: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_6: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
+     Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs
+     Net Ready_N_292: 1 loads, 1 LSLICEs
+
+     Net RCLK_c_enable_11: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
+   Number of LSRs:  9
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+     Net C1Submitted_N_237: 2 loads, 2 LSLICEs
+     Net n2469: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net n1846: 2 loads, 2 LSLICEs
+     Net LEDEN_N_82: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+     Net nRWE_N_177: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net Ready: 23 loads
+     Net InitReady: 17 loads
+     Net RASr2: 14 loads
+     Net nRowColSel: 13 loads
+     Net MAin_c_0: 12 loads
+     Net nRowColSel_N_35: 12 loads
+     Net Din_c_3: 11 loads
+     Net Din_c_6: 11 loads
+     Net MAin_c_1: 11 loads
+     Net Din_c_4: 10 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+   No errors or warnings present.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+------------+
+| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
+|                     |           |  IO_TYPE  | Register   |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[7]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[6]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[5]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[4]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[3]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[2]               | BIDIR     | LVCMOS33  |            |            |
+
++---------------------+-----------+-----------+------------+------------+
+| RD[1]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[0]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[7]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[6]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[5]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[4]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[3]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[2]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[1]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[0]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| LED                 | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[1]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[0]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[11]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[10]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[9]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[8]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[7]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[6]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[5]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[4]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[3]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[2]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[1]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[0]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCS                | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCKE                | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRWE                | OUTPUT    | LVCMOS33  |            |            |
+
++---------------------+-----------+-----------+------------+------------+
+| nRRAS               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCAS               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQMH               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQML               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nUFMCS              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMCLK              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDI              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| PHI2                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[9]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[8]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[7]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[6]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[5]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[4]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[3]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[2]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[1]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[0]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[1]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[0]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[7]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[6]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[5]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[4]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[3]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[2]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[1]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[0]              | INPUT     | LVCMOS33  |            |            |
+
++---------------------+-----------+-----------+------------+------------+
+| nCCAS               | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nCRAS               | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nFWE                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCLK                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDO              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+
+
+Removed logic
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal nCRAS_N_9 was merged into signal nCRAS_c
+Signal nCCAS_N_3 was merged into signal nCCAS_c
+Signal PHI2_N_120 was merged into signal PHI2_c
+Signal RASr2_N_63 was merged into signal RASr2
+Signal n1426 was merged into signal nRowColSel_N_35
+Signal nRWE_N_176 was merged into signal nRWE_N_177
+Signal n1425 was merged into signal nRowColSel_N_34
+Signal nFWE_N_5 was merged into signal nFWE_c
+Signal n2477 was merged into signal Ready
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_610_add_4_18/CO1 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_18/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_10/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_4/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_12/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_2/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_14/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_6/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_16/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_8/CO0 undriven or does not drive anything - clipped.
+Block i2135 was optimized away.
+Block i2134 was optimized away.
+Block i2136 was optimized away.
+Block RASr2_I_0_1_lut was optimized away.
+Block i1137_1_lut was optimized away.
+Block nRWE_I_50_1_lut was optimized away.
+Block i1136_1_lut was optimized away.
+Block i1_1_lut was optimized away.
+Block i637_1_lut_rep_34 was optimized away.
+Block i1 was optimized away.
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 29 MB
+        
+
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html new file mode 100644 index 0000000..e31d039 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_pad.html @@ -0,0 +1,336 @@ + +PAD Specification File + + +
    PAD Specification File
+***************************
+
+PART TYPE:        LCMXO256C
+Performance Grade:      3
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.19
+
+Tue Aug 15 05:03:28 2023
+
+Pinout by Port Name:
++-----------+----------+---------------+------+------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site | Properties                   |
++-----------+----------+---------------+------+------------------------------+
+| CROW[0]   | 32/1     | LVCMOS33_IN   | PB2C | SLEW:FAST PULL:UP            |
+| CROW[1]   | 34/1     | LVCMOS33_IN   | PB2D | SLEW:FAST PULL:UP            |
+| Din[0]    | 21/1     | LVCMOS33_IN   | PL8A | SLEW:FAST PULL:UP            |
+| Din[1]    | 15/1     | LVCMOS33_IN   | PL6A | SLEW:FAST PULL:UP            |
+| Din[2]    | 14/1     | LVCMOS33_IN   | PL5D | SLEW:FAST PULL:UP            |
+| Din[3]    | 16/1     | LVCMOS33_IN   | PL6B | SLEW:FAST PULL:UP            |
+| Din[4]    | 18/1     | LVCMOS33_IN   | PL7B | SLEW:FAST PULL:UP            |
+| Din[5]    | 17/1     | LVCMOS33_IN   | PL7A | SLEW:FAST PULL:UP            |
+| Din[6]    | 20/1     | LVCMOS33_IN   | PL7D | SLEW:FAST PULL:UP            |
+| Din[7]    | 19/1     | LVCMOS33_IN   | PL7C | SLEW:FAST PULL:UP            |
+| Dout[0]   | 1/1      | LVCMOS33_OUT  | PL2A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[1]   | 7/1      | LVCMOS33_OUT  | PL4A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[2]   | 8/1      | LVCMOS33_OUT  | PL4B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[3]   | 6/1      | LVCMOS33_OUT  | PL3D | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[4]   | 4/1      | LVCMOS33_OUT  | PL3B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[5]   | 5/1      | LVCMOS33_OUT  | PL3C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[6]   | 2/1      | LVCMOS33_OUT  | PL2B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[7]   | 3/1      | LVCMOS33_OUT  | PL3A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| LED       | 57/0     | LVCMOS33_OUT  | PR7B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| MAin[0]   | 23/1     | LVCMOS33_IN   | PL9A | SLEW:FAST PULL:UP            |
+| MAin[1]   | 38/1     | LVCMOS33_IN   | PB3C | SLEW:FAST PULL:UP            |
+| MAin[2]   | 37/1     | LVCMOS33_IN   | PB3B | SLEW:FAST PULL:UP            |
+| MAin[3]   | 47/1     | LVCMOS33_IN   | PB5A | SLEW:FAST PULL:UP            |
+| MAin[4]   | 46/1     | LVCMOS33_IN   | PB4D | SLEW:FAST PULL:UP            |
+| MAin[5]   | 45/1     | LVCMOS33_IN   | PB4C | SLEW:FAST PULL:UP            |
+| MAin[6]   | 49/1     | LVCMOS33_IN   | PB5C | SLEW:FAST PULL:UP            |
+| MAin[7]   | 44/1     | LVCMOS33_IN   | PB4B | SLEW:FAST PULL:UP            |
+| MAin[8]   | 50/1     | LVCMOS33_IN   | PB5D | SLEW:FAST PULL:UP            |
+| MAin[9]   | 51/0     | LVCMOS33_IN   | PR9B | SLEW:FAST PULL:UP            |
+| PHI2      | 39/1     | LVCMOS33_IN   | PB3D | SLEW:FAST PULL:UP            |
+| RA[0]     | 98/0     | LVCMOS33_OUT  | PT2C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[10]    | 87/0     | LVCMOS33_OUT  | PT3D | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[11]    | 79/0     | LVCMOS33_OUT  | PT5A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[1]     | 89/0     | LVCMOS33_OUT  | PT3C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[2]     | 94/0     | LVCMOS33_OUT  | PT3A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[3]     | 97/0     | LVCMOS33_OUT  | PT2D | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[4]     | 99/0     | LVCMOS33_OUT  | PT2B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[5]     | 95/0     | LVCMOS33_OUT  | PT2F | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[6]     | 91/0     | LVCMOS33_OUT  | PT3B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[7]     | 100/0    | LVCMOS33_OUT  | PT2A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[8]     | 96/0     | LVCMOS33_OUT  | PT2E | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[9]     | 85/0     | LVCMOS33_OUT  | PT4B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RBA[0]    | 63/0     | LVCMOS33_OUT  | PR5D | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RBA[1]    | 83/0     | LVCMOS33_OUT  | PT4C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RCKE      | 82/0     | LVCMOS33_OUT  | PT4D | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RCLK      | 86/0     | LVCMOS33_IN   | PT4A | SLEW:FAST PULL:UP            |
+| RDQMH     | 76/0     | LVCMOS33_OUT  | PR2A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RDQML     | 61/0     | LVCMOS33_OUT  | PR6A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[0]     | 64/0     | LVCMOS33_BIDI | PR5C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[1]     | 65/0     | LVCMOS33_BIDI | PR5B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[2]     | 66/0     | LVCMOS33_BIDI | PR5A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[3]     | 67/0     | LVCMOS33_BIDI | PR4B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[4]     | 68/0     | LVCMOS33_BIDI | PR4A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[5]     | 69/0     | LVCMOS33_BIDI | PR3D | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[6]     | 70/0     | LVCMOS33_BIDI | PR3C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[7]     | 71/0     | LVCMOS33_BIDI | PR3B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| UFMCLK    | 58/0     | LVCMOS33_OUT  | PR7A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| UFMSDI    | 56/0     | LVCMOS33_OUT  | PR7C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| UFMSDO    | 55/0     | LVCMOS33_IN   | PR7D | SLEW:FAST PULL:UP            |
+| nCCAS     | 27/1     | LVCMOS33_IN   | PL9B | SLEW:FAST PULL:UP            |
+| nCRAS     | 43/1     | LVCMOS33_IN   | PB4A | SLEW:FAST PULL:UP            |
+| nFWE      | 22/1     | LVCMOS33_IN   | PL8B | SLEW:FAST PULL:UP            |
+| nRCAS     | 78/0     | LVCMOS33_OUT  | PT5B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| nRCS      | 77/0     | LVCMOS33_OUT  | PT5C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| nRRAS     | 73/0     | LVCMOS33_OUT  | PR2B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| nRWE      | 72/0     | LVCMOS33_OUT  | PR3A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| nUFMCS    | 53/0     | LVCMOS33_OUT  | PR8B | DRIVE:8mA SLEW:FAST PULL:UP  |
++-----------+----------+---------------+------+------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+---------------------+------------+---------------+------+---------------+
+| Pin/Bank | Pin Info            | Preference | Buffer Type   | Site | Dual Function |
++----------+---------------------+------------+---------------+------+---------------+
+| 1/1      | Dout[0]             | LOCATED    | LVCMOS33_OUT  | PL2A |               |
+| 2/1      | Dout[6]             | LOCATED    | LVCMOS33_OUT  | PL2B |               |
+| 3/1      | Dout[7]             | LOCATED    | LVCMOS33_OUT  | PL3A |               |
+| 4/1      | Dout[4]             | LOCATED    | LVCMOS33_OUT  | PL3B |               |
+| 5/1      | Dout[5]             | LOCATED    | LVCMOS33_OUT  | PL3C |               |
+| 6/1      | Dout[3]             | LOCATED    | LVCMOS33_OUT  | PL3D |               |
+| 7/1      | Dout[1]             | LOCATED    | LVCMOS33_OUT  | PL4A |               |
+| 8/1      | Dout[2]             | LOCATED    | LVCMOS33_OUT  | PL4B |               |
+| 9/1      |     unused, PULL:UP |            |               | PL5A |               |
+| 11/1     |     unused, PULL:UP |            |               | PL5B |               |
+| 13/1     |     unused, PULL:UP |            |               | PL5C |               |
+| 14/1     | Din[2]              | LOCATED    | LVCMOS33_IN   | PL5D | GSR_PADN      |
+| 15/1     | Din[1]              | LOCATED    | LVCMOS33_IN   | PL6A |               |
+| 16/1     | Din[3]              | LOCATED    | LVCMOS33_IN   | PL6B | TSALLPAD      |
+| 17/1     | Din[5]              | LOCATED    | LVCMOS33_IN   | PL7A |               |
+| 18/1     | Din[4]              | LOCATED    | LVCMOS33_IN   | PL7B |               |
+| 19/1     | Din[7]              | LOCATED    | LVCMOS33_IN   | PL7C |               |
+| 20/1     | Din[6]              | LOCATED    | LVCMOS33_IN   | PL7D |               |
+| 21/1     | Din[0]              | LOCATED    | LVCMOS33_IN   | PL8A |               |
+| 22/1     | nFWE                | LOCATED    | LVCMOS33_IN   | PL8B |               |
+| 23/1     | MAin[0]             | LOCATED    | LVCMOS33_IN   | PL9A |               |
+| 27/1     | nCCAS               | LOCATED    | LVCMOS33_IN   | PL9B |               |
+| 29/1     |     unused, PULL:UP |            |               | PB2A |               |
+| 30/1     |     unused, PULL:UP |            |               | PB2B |               |
+| 32/1     | CROW[0]             | LOCATED    | LVCMOS33_IN   | PB2C |               |
+| 34/1     | CROW[1]             | LOCATED    | LVCMOS33_IN   | PB2D |               |
+| 36/1     |     unused, PULL:UP |            |               | PB3A | PCLKT1_1      |
+| 37/1     | MAin[2]             | LOCATED    | LVCMOS33_IN   | PB3B |               |
+| 38/1     | MAin[1]             | LOCATED    | LVCMOS33_IN   | PB3C | PCLKT1_0      |
+| 39/1     | PHI2                | LOCATED    | LVCMOS33_IN   | PB3D |               |
+| 43/1     | nCRAS               | LOCATED    | LVCMOS33_IN   | PB4A |               |
+| 44/1     | MAin[7]             | LOCATED    | LVCMOS33_IN   | PB4B |               |
+| 45/1     | MAin[5]             | LOCATED    | LVCMOS33_IN   | PB4C |               |
+| 46/1     | MAin[4]             | LOCATED    | LVCMOS33_IN   | PB4D |               |
+| 47/1     | MAin[3]             | LOCATED    | LVCMOS33_IN   | PB5A |               |
+| 49/1     | MAin[6]             | LOCATED    | LVCMOS33_IN   | PB5C |               |
+| 50/1     | MAin[8]             | LOCATED    | LVCMOS33_IN   | PB5D |               |
+| 51/0     | MAin[9]             | LOCATED    | LVCMOS33_IN   | PR9B |               |
+| 52/0     |     unused, PULL:UP |            |               | PR9A |               |
+| 53/0     | nUFMCS              | LOCATED    | LVCMOS33_OUT  | PR8B |               |
+| 54/0     |     unused, PULL:UP |            |               | PR8A |               |
+| 55/0     | UFMSDO              | LOCATED    | LVCMOS33_IN   | PR7D |               |
+| 56/0     | UFMSDI              | LOCATED    | LVCMOS33_OUT  | PR7C |               |
+| 57/0     | LED                 | LOCATED    | LVCMOS33_OUT  | PR7B |               |
+| 58/0     | UFMCLK              | LOCATED    | LVCMOS33_OUT  | PR7A |               |
+| 59/0     |     unused, PULL:UP |            |               | PR6B |               |
+| 61/0     | RDQML               | LOCATED    | LVCMOS33_OUT  | PR6A |               |
+| 63/0     | RBA[0]              | LOCATED    | LVCMOS33_OUT  | PR5D |               |
+| 64/0     | RD[0]               | LOCATED    | LVCMOS33_BIDI | PR5C |               |
+| 65/0     | RD[1]               | LOCATED    | LVCMOS33_BIDI | PR5B |               |
+| 66/0     | RD[2]               | LOCATED    | LVCMOS33_BIDI | PR5A |               |
+| 67/0     | RD[3]               | LOCATED    | LVCMOS33_BIDI | PR4B |               |
+| 68/0     | RD[4]               | LOCATED    | LVCMOS33_BIDI | PR4A |               |
+| 69/0     | RD[5]               | LOCATED    | LVCMOS33_BIDI | PR3D |               |
+| 70/0     | RD[6]               | LOCATED    | LVCMOS33_BIDI | PR3C |               |
+| 71/0     | RD[7]               | LOCATED    | LVCMOS33_BIDI | PR3B |               |
+| 72/0     | nRWE                | LOCATED    | LVCMOS33_OUT  | PR3A |               |
+| 73/0     | nRRAS               | LOCATED    | LVCMOS33_OUT  | PR2B |               |
+| 76/0     | RDQMH               | LOCATED    | LVCMOS33_OUT  | PR2A |               |
+| 77/0     | nRCS                | LOCATED    | LVCMOS33_OUT  | PT5C |               |
+| 78/0     | nRCAS               | LOCATED    | LVCMOS33_OUT  | PT5B |               |
+| 79/0     | RA[11]              | LOCATED    | LVCMOS33_OUT  | PT5A |               |
+| 80/0     |     unused, PULL:UP |            |               | PT4F |               |
+| 81/0     |     unused, PULL:UP |            |               | PT4E |               |
+| 82/0     | RCKE                | LOCATED    | LVCMOS33_OUT  | PT4D |               |
+| 83/0     | RBA[1]              | LOCATED    | LVCMOS33_OUT  | PT4C |               |
+| 85/0     | RA[9]               | LOCATED    | LVCMOS33_OUT  | PT4B | PCLKT0_1      |
+| 86/0     | RCLK                | LOCATED    | LVCMOS33_IN   | PT4A | PCLKT0_0      |
+| 87/0     | RA[10]              | LOCATED    | LVCMOS33_OUT  | PT3D |               |
+| 89/0     | RA[1]               | LOCATED    | LVCMOS33_OUT  | PT3C |               |
+| 91/0     | RA[6]               | LOCATED    | LVCMOS33_OUT  | PT3B |               |
+| 94/0     | RA[2]               | LOCATED    | LVCMOS33_OUT  | PT3A |               |
+| 95/0     | RA[5]               | LOCATED    | LVCMOS33_OUT  | PT2F |               |
+| 96/0     | RA[8]               | LOCATED    | LVCMOS33_OUT  | PT2E |               |
+| 97/0     | RA[3]               | LOCATED    | LVCMOS33_OUT  | PT2D |               |
+| 98/0     | RA[0]               | LOCATED    | LVCMOS33_OUT  | PT2C |               |
+| 99/0     | RA[4]               | LOCATED    | LVCMOS33_OUT  | PT2B |               |
+| 100/0    | RA[7]               | LOCATED    | LVCMOS33_OUT  | PT2A |               |
+| PB5B/0   |     unused, PULL:UP |            |               | PB5B |               |
+| PT5D/0   |     unused, PULL:UP |            |               | PT5D |               |
+| TCK/1    |                     |            |               | TCK  | TCK           |
+| TDI/1    |                     |            |               | TDI  | TDI           |
+| TDO/1    |                     |            |               | TDO  | TDO           |
+| TMS/1    |                     |            |               | TMS  | TMS           |
++----------+---------------------+------------+---------------+------+---------------+
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "32";
+LOCATE  COMP  "CROW[1]"  SITE  "34";
+LOCATE  COMP  "Din[0]"  SITE  "21";
+LOCATE  COMP  "Din[1]"  SITE  "15";
+LOCATE  COMP  "Din[2]"  SITE  "14";
+LOCATE  COMP  "Din[3]"  SITE  "16";
+LOCATE  COMP  "Din[4]"  SITE  "18";
+LOCATE  COMP  "Din[5]"  SITE  "17";
+LOCATE  COMP  "Din[6]"  SITE  "20";
+LOCATE  COMP  "Din[7]"  SITE  "19";
+LOCATE  COMP  "Dout[0]"  SITE  "1";
+LOCATE  COMP  "Dout[1]"  SITE  "7";
+LOCATE  COMP  "Dout[2]"  SITE  "8";
+LOCATE  COMP  "Dout[3]"  SITE  "6";
+LOCATE  COMP  "Dout[4]"  SITE  "4";
+LOCATE  COMP  "Dout[5]"  SITE  "5";
+LOCATE  COMP  "Dout[6]"  SITE  "2";
+LOCATE  COMP  "Dout[7]"  SITE  "3";
+LOCATE  COMP  "LED"  SITE  "57";
+LOCATE  COMP  "MAin[0]"  SITE  "23";
+LOCATE  COMP  "MAin[1]"  SITE  "38";
+LOCATE  COMP  "MAin[2]"  SITE  "37";
+LOCATE  COMP  "MAin[3]"  SITE  "47";
+LOCATE  COMP  "MAin[4]"  SITE  "46";
+LOCATE  COMP  "MAin[5]"  SITE  "45";
+LOCATE  COMP  "MAin[6]"  SITE  "49";
+LOCATE  COMP  "MAin[7]"  SITE  "44";
+LOCATE  COMP  "MAin[8]"  SITE  "50";
+LOCATE  COMP  "MAin[9]"  SITE  "51";
+LOCATE  COMP  "PHI2"  SITE  "39";
+LOCATE  COMP  "RA[0]"  SITE  "98";
+LOCATE  COMP  "RA[10]"  SITE  "87";
+LOCATE  COMP  "RA[11]"  SITE  "79";
+LOCATE  COMP  "RA[1]"  SITE  "89";
+LOCATE  COMP  "RA[2]"  SITE  "94";
+LOCATE  COMP  "RA[3]"  SITE  "97";
+LOCATE  COMP  "RA[4]"  SITE  "99";
+LOCATE  COMP  "RA[5]"  SITE  "95";
+LOCATE  COMP  "RA[6]"  SITE  "91";
+LOCATE  COMP  "RA[7]"  SITE  "100";
+LOCATE  COMP  "RA[8]"  SITE  "96";
+LOCATE  COMP  "RA[9]"  SITE  "85";
+LOCATE  COMP  "RBA[0]"  SITE  "63";
+LOCATE  COMP  "RBA[1]"  SITE  "83";
+LOCATE  COMP  "RCKE"  SITE  "82";
+LOCATE  COMP  "RCLK"  SITE  "86";
+LOCATE  COMP  "RDQMH"  SITE  "76";
+LOCATE  COMP  "RDQML"  SITE  "61";
+LOCATE  COMP  "RD[0]"  SITE  "64";
+LOCATE  COMP  "RD[1]"  SITE  "65";
+LOCATE  COMP  "RD[2]"  SITE  "66";
+LOCATE  COMP  "RD[3]"  SITE  "67";
+LOCATE  COMP  "RD[4]"  SITE  "68";
+LOCATE  COMP  "RD[5]"  SITE  "69";
+LOCATE  COMP  "RD[6]"  SITE  "70";
+LOCATE  COMP  "RD[7]"  SITE  "71";
+LOCATE  COMP  "UFMCLK"  SITE  "58";
+LOCATE  COMP  "UFMSDI"  SITE  "56";
+LOCATE  COMP  "UFMSDO"  SITE  "55";
+LOCATE  COMP  "nCCAS"  SITE  "27";
+LOCATE  COMP  "nCRAS"  SITE  "43";
+LOCATE  COMP  "nFWE"  SITE  "22";
+LOCATE  COMP  "nRCAS"  SITE  "78";
+LOCATE  COMP  "nRCS"  SITE  "77";
+LOCATE  COMP  "nRRAS"  SITE  "73";
+LOCATE  COMP  "nRWE"  SITE  "72";
+LOCATE  COMP  "nUFMCS"  SITE  "53";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:28 2023
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html new file mode 100644 index 0000000..f78605b --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_par.html @@ -0,0 +1,331 @@ + +Place & Route Report + + +
    PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:23 2023
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
+RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
+RAM2GS_LCMXO256C_impl1.prf -gui -msgset
+D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml
+
+
+Preference file: RAM2GS_LCMXO256C_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            -10.044      913247       0.273        0            06           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
+Tue Aug 15 05:03:23 2023
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
+Preference file: RAM2GS_LCMXO256C_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)      67/79           84% used
+                     67/78           85% bonded
+   SLICE             71/128          55% used
+
+
+
+Number of Signals: 262
+Number of Connections: 662
+
+Pin Constraint Summary:
+   67 out of 67 pins locked (100% locked).
+
+The following 2 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 40)
+    PHI2_c (driver: PHI2, clk load #: 13)
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0)
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+........
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+..............
+Placer score = 831129.
+Finished Placer Phase 1.  REAL time: 5 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  828350
+Finished Placer Phase 2.  REAL time: 5 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 4 (25%)
+  General PIO: 1 out of 80 (1%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 40
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13
+  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7, ce load = 0, sr load = 0
+
+  PRIMARY  : 2 out of 4 (50%)
+  SECONDARY: 1 out of 4 (25%)
+
+
+
+
+I/O Usage Summary (final):
+   67 out of 79 (84.8%) PIO sites used.
+   67 out of 78 (85.9%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 36 / 41 ( 87%) | 3.3V       | -          | -          |
+| 1        | 31 / 37 ( 83%) | 3.3V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 4 secs 
+
+Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
+
+0 connections routed; 662 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks.  This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=7 clock_loads=4
+
+Completed router resource preassignment. Real time: 5 secs 
+
+Start NBR router at 05:03:28 08/15/23
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 05:03:28 08/15/23
+
+Start NBR section for initial routing at 05:03:28 08/15/23
+Level 1, iteration 1
+0(0.00%) conflict; 563(85.05%) untouched conns; 712361 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.968ns/-712.361ns; real time: 5 secs 
+Level 2, iteration 1
+3(0.02%) conflicts; 494(74.62%) untouched conns; 697746 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-697.746ns; real time: 5 secs 
+Level 3, iteration 1
+6(0.05%) conflicts; 255(38.52%) untouched conns; 756550 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-756.550ns; real time: 5 secs 
+Level 4, iteration 1
+17(0.14%) conflicts; 0(0.00%) untouched conn; 761255 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-761.256ns; real time: 5 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 05:03:28 08/15/23
+Level 4, iteration 1
+12(0.10%) conflicts; 0(0.00%) untouched conn; 765605 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-765.606ns; real time: 5 secs 
+Level 4, iteration 2
+6(0.05%) conflicts; 0(0.00%) untouched conn; 766423 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-766.424ns; real time: 5 secs 
+Level 4, iteration 3
+3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-769.149ns; real time: 5 secs 
+Level 4, iteration 4
+3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-769.149ns; real time: 5 secs 
+Level 4, iteration 5
+3(0.02%) conflicts; 0(0.00%) untouched conn; 766523 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-766.524ns; real time: 5 secs 
+Level 4, iteration 6
+1(0.01%) conflict; 0(0.00%) untouched conn; 766523 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-766.524ns; real time: 5 secs 
+Level 4, iteration 7
+1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 6 secs 
+Level 4, iteration 8
+1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 6 secs 
+Level 4, iteration 9
+1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 6 secs 
+Level 4, iteration 10
+0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 6 secs 
+
+Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-772.930ns; real time: 6 secs 
+
+Start NBR section for re-routing at 05:03:29 08/15/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 768048 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -10.044ns/-768.049ns; real time: 6 secs 
+
+Start NBR section for post-routing at 05:03:29 08/15/23
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 256 (38.67%)
+  Estimated worst slack<setup> : -10.044ns
+  Timing score<setup> : 913247
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=7 clock_loads=4
+
+Total CPU time 5 secs 
+Total REAL time: 6 secs 
+Completely routed.
+End of route.  662 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 913247 
+
+Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = -10.044
+PAR_SUMMARY::Timing score<setup/<ns>> = 913.247
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.273
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 5 secs 
+Total REAL time to completion: 6 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html new file mode 100644 index 0000000..3f88aa1 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_summary.html @@ -0,0 +1,83 @@ + +Project Summary + + +
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    RAM2GS_LCMXO256C project summary
    Module Name:RAM2GS_LCMXO256CSynthesis:Lattice LSE
    Implementation Name:impl1Strategy Name:Strategy1
    Last Process:JEDEC FileState:Passed
    Target Device:LCMXO256C-3T100CDevice Family:MachXO
    Device Type:LCMXO256CPackage Type:TQFP100
    Performance grade:3Operating conditions:COM
    Logic preference file:RAM2GS_LCMXO256C.lpf
    Physical Preference file:impl1/RAM2GS_LCMXO256C_impl1.prf
    Product Version:3.12.1.454Patch Version:
    Updated:2023/08/15 05:03:37
    Implementation Location:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1
    Project File:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html new file mode 100644 index 0000000..40eaf8f --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_tw1.html @@ -0,0 +1,434 @@ + +Lattice Map TRACE Report + + +
    Map TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:21 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf 
+Design file:     ram2gs_lcmxo256c_impl1_map.ncd
+Preference file: ram2gs_lcmxo256c_impl1.prf
+Device,speed:    LCMXO256C,3
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 283.768000 MHz (213 errors)
    • 
+                383 items scored, 213 timing errors detected.
+Warning: 116.104MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY NET "PHI2_c" 120.077000 MHz (97 errors)
    • 
+                106 items scored, 97 timing errors detected.
+Warning:  42.739MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+            383 items scored, 213 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 5.089ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i14  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               8.369ns  (24.4% logic, 75.6% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.369ns physical path delay SLICE_1 to SLICE_56 exceeds
+      3.524ns delay constraint less
+      0.244ns CE_SET requirement (totaling 3.280ns) by 5.089ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560    SLICE_1.CLK to     SLICE_1.Q0 SLICE_1 (from RCLK_c)
+ROUTE         5   e 1.441     SLICE_1.Q0 to    SLICE_90.C1 FS_14
+CTOF_DEL    ---     0.371    SLICE_90.C1 to    SLICE_90.F1 SLICE_90
+ROUTE         1   e 1.441    SLICE_90.F1 to    SLICE_75.B0 n2328
+CTOF_DEL    ---     0.371    SLICE_75.B0 to    SLICE_75.F0 SLICE_75
+ROUTE         2   e 1.441    SLICE_75.F0 to    SLICE_87.B1 n2214
+CTOF_DEL    ---     0.371    SLICE_87.B1 to    SLICE_87.F1 SLICE_87
+ROUTE         1   e 0.561    SLICE_87.F1 to    SLICE_87.A0 n7
+CTOF_DEL    ---     0.371    SLICE_87.A0 to    SLICE_87.F0 SLICE_87
+ROUTE         1   e 1.441    SLICE_87.F0 to    SLICE_56.CE RCLK_c_enable_11 (to RCLK_c)
+                  --------
+                    8.369   (24.4% logic, 75.6% route), 5 logic levels.
+
+Warning: 116.104MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+            106 items scored, 97 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 7.535ns (weighted slack = -15.070ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:              11.061ns  (21.8% logic, 78.2% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.061ns physical path delay SLICE_88 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 7.535ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_88.CLK to    SLICE_88.Q0 SLICE_88 (from PHI2_c)
+ROUTE         1   e 1.441    SLICE_88.Q0 to    SLICE_97.D0 Bank_0
+CTOF_DEL    ---     0.371    SLICE_97.D0 to    SLICE_97.F0 SLICE_97
+ROUTE         1   e 1.441    SLICE_97.F0 to    SLICE_81.B0 n2314
+CTOF_DEL    ---     0.371    SLICE_81.B0 to    SLICE_81.F0 SLICE_81
+ROUTE         1   e 1.441    SLICE_81.F0 to    SLICE_18.B1 n26
+CTOF_DEL    ---     0.371    SLICE_18.B1 to    SLICE_18.F1 SLICE_18
+ROUTE         8   e 1.441    SLICE_18.F1 to    SLICE_89.B0 n1326
+CTOF_DEL    ---     0.371    SLICE_89.B0 to    SLICE_89.F0 SLICE_89
+ROUTE         1   e 1.441    SLICE_89.F0 to    SLICE_79.C0 n1280
+CTOF_DEL    ---     0.371    SLICE_79.C0 to    SLICE_79.F0 SLICE_79
+ROUTE         2   e 1.441    SLICE_79.F0 to   SLICE_14.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                   11.061   (21.8% logic, 78.2% route), 6 logic levels.
+
+Warning:  42.739MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 283.768000 MHz ; |  283.768 MHz|  116.104 MHz|   5 *
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 120.077000 MHz ; |  120.077 MHz|   42.739 MHz|   6 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+2 preferences(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+n1326                                   |       8|      96|     30.97%
+                                        |        |        |
+n26                                     |       1|      72|     23.23%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 310  Score: 1346529
+Cumulative negative slack: 874289
+
+Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:21 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf 
+Design file:     ram2gs_lcmxo256c_impl1_map.ncd
+Preference file: ram2gs_lcmxo256c_impl1.prf
+Device,speed:    LCMXO256C,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 283.768000 MHz (0 errors)
    •             383 items scored, 0 timing errors detected.
+
+
  • FREQUENCY NET "PHI2_c" 120.077000 MHz (0 errors)
    •             106 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+            383 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.342ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.325ns  (38.8% logic, 61.2% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.325ns physical path delay SLICE_100 to SLICE_100 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns
+
+ Physical Path Details:
+
+      Data path SLICE_100 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126  SLICE_100.CLK to   SLICE_100.Q0 SLICE_100 (from RCLK_c)
+ROUTE         1   e 0.199   SLICE_100.Q0 to   SLICE_100.M1 n736 (to RCLK_c)
+                  --------
+                    0.325   (38.8% logic, 61.2% route), 1 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+            106 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.430ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.411ns  (51.3% logic, 48.7% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.411ns physical path delay SLICE_14 to SLICE_14 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.019ns) by 0.430ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137   SLICE_14.CLK to    SLICE_14.Q0 SLICE_14 (from PHI2_c)
+ROUTE         2   e 0.199    SLICE_14.Q0 to    SLICE_14.C0 C1Submitted
+CTOF_DEL    ---     0.074    SLICE_14.C0 to    SLICE_14.F0 SLICE_14
+ROUTE         1   e 0.001    SLICE_14.F0 to   SLICE_14.DI0 n6_adj_3 (to PHI2_c)
+                  --------
+                    0.411   (51.3% logic, 48.7% route), 2 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 283.768000 MHz ; |     0.000 ns|     0.342 ns|   1  
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 120.077000 MHz ; |     0.000 ns|     0.430 ns|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 310 (setup), 0 (hold)
+Score: 1346529 (setup), 0 (hold)
+Cumulative negative slack: 874289 (874289+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html new file mode 100644 index 0000000..d7e5a9f --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_twr.html @@ -0,0 +1,2251 @@ + +Lattice TRACE Report + + +
    Place & Route TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo256c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO256C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:29 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
+Design file:     ram2gs_lcmxo256c_impl1.ncd
+Preference file: ram2gs_lcmxo256c_impl1.prf
+Device,speed:    LCMXO256C,3
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 283.768000 MHz (231 errors)
    • 
+                383 items scored, 231 timing errors detected.
+Warning: 129.769MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY NET "PHI2_c" 120.077000 MHz (95 errors)
    • 
+                106 items scored, 95 timing errors detected.
+Warning:  54.431MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+            383 items scored, 231 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 4.182ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i17  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               7.525ns  (27.2% logic, 72.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.525ns physical path delay SLICE_8 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 4.182ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C5A.CLK to       R5C5A.Q1 SLICE_8 (from RCLK_c)
+ROUTE         4     1.509       R5C5A.Q1 to       R6C4C.A1 FS_17
+CTOF_DEL    ---     0.371       R6C4C.A1 to       R6C4C.F1 SLICE_68
+ROUTE         2     1.503       R6C4C.F1 to       R7C5B.A1 n2471
+CTOF_DEL    ---     0.371       R7C5B.A1 to       R7C5B.F1 SLICE_44
+ROUTE         2     1.972       R7C5B.F1 to       R3C2B.C1 n2462
+CTOF_DEL    ---     0.371       R3C2B.C1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    7.525   (27.2% logic, 72.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C5A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.947ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i16  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               7.290ns  (28.0% logic, 72.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.290ns physical path delay SLICE_8 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 3.947ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C5A.CLK to       R5C5A.Q0 SLICE_8 (from RCLK_c)
+ROUTE         5     1.526       R5C5A.Q0 to       R5C2D.A0 FS_16
+CTOF_DEL    ---     0.371       R5C2D.A0 to       R5C2D.F0 SLICE_90
+ROUTE         1     1.251       R5C2D.F0 to       R7C5B.D1 n2470
+CTOF_DEL    ---     0.371       R7C5B.D1 to       R7C5B.F1 SLICE_44
+ROUTE         2     1.972       R7C5B.F1 to       R3C2B.C1 n2462
+CTOF_DEL    ---     0.371       R3C2B.C1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    7.290   (28.0% logic, 72.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C5A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.864ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               7.144ns  (28.6% logic, 71.4% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.144ns physical path delay SLICE_3 to SLICE_56 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 3.280ns) by 3.864ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C4C.CLK to       R5C4C.Q0 SLICE_3 (from RCLK_c)
+ROUTE         4     2.038       R5C4C.Q0 to       R5C2D.B1 FS_12
+CTOF_DEL    ---     0.371       R5C2D.B1 to       R5C2D.F1 SLICE_90
+ROUTE         1     0.887       R5C2D.F1 to       R4C2D.C0 n2328
+CTOF_DEL    ---     0.371       R4C2D.C0 to       R4C2D.F0 SLICE_75
+ROUTE         2     0.513       R4C2D.F0 to       R4C2C.C1 n2214
+CTOF_DEL    ---     0.371       R4C2C.C1 to       R4C2C.F1 SLICE_87
+ROUTE         1     0.497       R4C2C.F1 to       R4C2C.C0 n7
+CTOF_DEL    ---     0.371       R4C2C.C0 to       R4C2C.F0 SLICE_87
+ROUTE         1     1.165       R4C2C.F0 to       R6C2C.CE RCLK_c_enable_11 (to RCLK_c)
+                  --------
+                    7.144   (28.6% logic, 71.4% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R6C2C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.702ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i13  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               7.045ns  (29.0% logic, 71.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.045ns physical path delay SLICE_3 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 3.702ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C4C.CLK to       R5C4C.Q1 SLICE_3 (from RCLK_c)
+ROUTE         3     1.057       R5C4C.Q1 to       R5C2B.A1 FS_13
+CTOF_DEL    ---     0.371       R5C2B.A1 to       R5C2B.F1 SLICE_94
+ROUTE         3     1.475       R5C2B.F1 to       R7C5B.C1 n2272
+CTOF_DEL    ---     0.371       R7C5B.C1 to       R7C5B.F1 SLICE_44
+ROUTE         2     1.972       R7C5B.F1 to       R3C2B.C1 n2462
+CTOF_DEL    ---     0.371       R3C2B.C1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    7.045   (29.0% logic, 71.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.669ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i11  (from RCLK_c +)
+   Destination:    FF         Data in        InitReady_394  (to RCLK_c +)
+
+   Delay:               6.949ns  (24.1% logic, 75.9% route), 4 logic levels.
+
+ Constraint Details:
+
+      6.949ns physical path delay SLICE_5 to SLICE_25 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 3.280ns) by 3.669ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C4B.CLK to       R5C4B.Q1 SLICE_5 (from RCLK_c)
+ROUTE         8     1.895       R5C4B.Q1 to       R5C2B.C0 FS_11
+CTOF_DEL    ---     0.371       R5C2B.C0 to       R5C2B.F0 SLICE_94
+ROUTE         1     0.694       R5C2B.F0 to       R3C2A.D1 n12
+CTOF_DEL    ---     0.371       R3C2A.D1 to       R3C2A.F1 SLICE_69
+ROUTE         3     1.057       R3C2A.F1 to       R5C2C.A1 n62
+CTOF_DEL    ---     0.371       R5C2C.A1 to       R5C2C.F1 SLICE_95
+ROUTE         1     1.630       R5C2C.F1 to       R6C2A.CE RCLK_c_enable_25 (to RCLK_c)
+                  --------
+                    6.949   (24.1% logic, 75.9% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C4B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_25:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R6C2A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.582ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               6.925ns  (29.5% logic, 70.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.925ns physical path delay SLICE_3 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 3.582ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C4C.CLK to       R5C4C.Q0 SLICE_3 (from RCLK_c)
+ROUTE         4     0.909       R5C4C.Q0 to       R6C4C.C1 FS_12
+CTOF_DEL    ---     0.371       R6C4C.C1 to       R6C4C.F1 SLICE_68
+ROUTE         2     1.503       R6C4C.F1 to       R7C5B.A1 n2471
+CTOF_DEL    ---     0.371       R7C5B.A1 to       R7C5B.F1 SLICE_44
+ROUTE         2     1.972       R7C5B.F1 to       R3C2B.C1 n2462
+CTOF_DEL    ---     0.371       R3C2B.C1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    6.925   (29.5% logic, 70.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.567ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CASr3_384  (from RCLK_c +)
+   Destination:    FF         Data in        nRCS_396  (to RCLK_c +)
+
+   Delay:               6.910ns  (31.5% logic, 68.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.910ns physical path delay SLICE_68 to SLICE_60 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 3.567ns
+
+ Physical Path Details:
+
+      Data path SLICE_68 to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R6C4C.CLK to       R6C4C.Q1 SLICE_68 (from RCLK_c)
+ROUTE         2     1.364       R6C4C.Q1 to       R8C5C.C0 CASr3
+CTOF_DEL    ---     0.371       R8C5C.C0 to       R8C5C.F0 SLICE_74
+ROUTE         2     0.513       R8C5C.F0 to       R8C5C.C1 n1
+CTOF_DEL    ---     0.371       R8C5C.C1 to       R8C5C.F1 SLICE_74
+ROUTE         2     1.276       R8C5C.F1 to       R8C4D.M0 n15_adj_1
+MTOOFX_DEL  ---     0.501       R8C4D.M0 to     R8C4D.OFX0 i2099/SLICE_72
+ROUTE         1     1.583     R8C4D.OFX0 to       R2C5B.A0 n2481
+CTOF_DEL    ---     0.371       R2C5B.A0 to       R2C5B.F0 SLICE_60
+ROUTE         1     0.000       R2C5B.F0 to      R2C5B.DI0 nRCS_N_136 (to RCLK_c)
+                  --------
+                    6.910   (31.5% logic, 68.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_68:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R6C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_60:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R2C5B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.552ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_419  (to RCLK_c +)
+
+   Delay:               6.832ns  (24.5% logic, 75.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      6.832ns physical path delay SLICE_3 to SLICE_26 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 3.280ns) by 3.552ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C4C.CLK to       R5C4C.Q0 SLICE_3 (from RCLK_c)
+ROUTE         4     2.038       R5C4C.Q0 to       R5C2D.B1 FS_12
+CTOF_DEL    ---     0.371       R5C2D.B1 to       R5C2D.F1 SLICE_90
+ROUTE         1     0.887       R5C2D.F1 to       R4C2D.C0 n2328
+CTOF_DEL    ---     0.371       R4C2D.C0 to       R4C2D.F0 SLICE_75
+ROUTE         2     0.513       R4C2D.F0 to       R4C2D.C1 n2214
+CTOF_DEL    ---     0.371       R4C2D.C1 to       R4C2D.F1 SLICE_75
+ROUTE         1     1.721       R4C2D.F1 to       R7C5A.CE RCLK_c_enable_12 (to RCLK_c)
+                  --------
+                    6.832   (24.5% logic, 75.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C4C.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R7C5A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.405ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i17  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               6.303ns  (26.5% logic, 73.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      6.303ns physical path delay SLICE_8 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.626ns LSR_SET requirement (totaling 2.898ns) by 3.405ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C5A.CLK to       R5C5A.Q1 SLICE_8 (from RCLK_c)
+ROUTE         4     1.509       R5C5A.Q1 to       R6C4C.A1 FS_17
+CTOF_DEL    ---     0.371       R6C4C.A1 to       R6C4C.F1 SLICE_68
+ROUTE         2     1.042       R6C4C.F1 to       R6C2D.A1 n2471
+CTOF_DEL    ---     0.371       R6C2D.A1 to       R6C2D.F1 SLICE_78
+ROUTE         3     0.528       R6C2D.F1 to       R6C2D.C0 n2464
+CTOF_DEL    ---     0.371       R6C2D.C0 to       R6C2D.F0 SLICE_78
+ROUTE         2     1.551       R6C2D.F0 to      R3C2B.LSR n1846 (to RCLK_c)
+                  --------
+                    6.303   (26.5% logic, 73.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C5A.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 3.361ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               6.704ns  (30.5% logic, 69.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      6.704ns physical path delay SLICE_1 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 3.361ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R5C4D.CLK to       R5C4D.Q1 SLICE_1 (from RCLK_c)
+ROUTE         3     0.716       R5C4D.Q1 to       R5C2B.D1 FS_15
+CTOF_DEL    ---     0.371       R5C2B.D1 to       R5C2B.F1 SLICE_94
+ROUTE         3     1.475       R5C2B.F1 to       R7C5B.C1 n2272
+CTOF_DEL    ---     0.371       R7C5B.C1 to       R7C5B.F1 SLICE_44
+ROUTE         2     1.972       R7C5B.F1 to       R3C2B.C1 n2462
+CTOF_DEL    ---     0.371       R3C2B.C1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    6.704   (30.5% logic, 69.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R5C4D.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.353       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.353   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning: 129.769MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+            106 items scored, 95 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 5.022ns (weighted slack = -10.044ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               8.548ns  (28.3% logic, 71.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.548ns physical path delay SLICE_88 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 5.022ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R4C3D.CLK to       R4C3D.Q0 SLICE_88 (from PHI2_c)
+ROUTE         1     1.155       R4C3D.Q0 to       R2C2A.D0 Bank_0
+CTOF_DEL    ---     0.371       R2C2A.D0 to       R2C2A.F0 SLICE_97
+ROUTE         1     1.348       R2C2A.F0 to       R4C4A.C0 n2314
+CTOF_DEL    ---     0.371       R4C4A.C0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     1.225       R4C4D.F1 to       R5C5B.D0 n1326
+CTOF_DEL    ---     0.371       R5C5B.D0 to       R5C5B.F0 SLICE_89
+ROUTE         1     0.700       R5C5B.F0 to       R6C5C.D0 n1280
+CTOF_DEL    ---     0.371       R6C5C.D0 to       R6C5C.F0 SLICE_79
+ROUTE         2     1.079       R6C5C.F0 to      R5C5D.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    8.548   (28.3% logic, 71.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C3D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C5D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 5.022ns (weighted slack = -10.044ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               8.548ns  (28.3% logic, 71.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.548ns physical path delay SLICE_88 to SLICE_9 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 5.022ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R4C3D.CLK to       R4C3D.Q0 SLICE_88 (from PHI2_c)
+ROUTE         1     1.155       R4C3D.Q0 to       R2C2A.D0 Bank_0
+CTOF_DEL    ---     0.371       R2C2A.D0 to       R2C2A.F0 SLICE_97
+ROUTE         1     1.348       R2C2A.F0 to       R4C4A.C0 n2314
+CTOF_DEL    ---     0.371       R4C4A.C0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     1.225       R4C4D.F1 to       R5C5B.D0 n1326
+CTOF_DEL    ---     0.371       R5C5B.D0 to       R5C5B.F0 SLICE_89
+ROUTE         1     0.700       R5C5B.F0 to       R6C5C.D0 n1280
+CTOF_DEL    ---     0.371       R6C5C.D0 to       R6C5C.F0 SLICE_79
+ROUTE         2     1.079       R6C5C.F0 to      R4C5D.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    8.548   (28.3% logic, 71.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C3D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C5D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.893ns (weighted slack = -9.786ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               8.419ns  (28.7% logic, 71.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.419ns physical path delay SLICE_99 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.893ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     1.026       R2C4C.Q1 to       R2C2A.A0 Bank_7
+CTOF_DEL    ---     0.371       R2C2A.A0 to       R2C2A.F0 SLICE_97
+ROUTE         1     1.348       R2C2A.F0 to       R4C4A.C0 n2314
+CTOF_DEL    ---     0.371       R4C4A.C0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     1.225       R4C4D.F1 to       R5C5B.D0 n1326
+CTOF_DEL    ---     0.371       R5C5B.D0 to       R5C5B.F0 SLICE_89
+ROUTE         1     0.700       R5C5B.F0 to       R6C5C.D0 n1280
+CTOF_DEL    ---     0.371       R6C5C.D0 to       R6C5C.F0 SLICE_79
+ROUTE         2     1.079       R6C5C.F0 to      R5C5D.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    8.419   (28.7% logic, 71.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C4C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C5D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.893ns (weighted slack = -9.786ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               8.419ns  (28.7% logic, 71.3% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.419ns physical path delay SLICE_99 to SLICE_9 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.893ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     1.026       R2C4C.Q1 to       R2C2A.A0 Bank_7
+CTOF_DEL    ---     0.371       R2C2A.A0 to       R2C2A.F0 SLICE_97
+ROUTE         1     1.348       R2C2A.F0 to       R4C4A.C0 n2314
+CTOF_DEL    ---     0.371       R4C4A.C0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     1.225       R4C4D.F1 to       R5C5B.D0 n1326
+CTOF_DEL    ---     0.371       R5C5B.D0 to       R5C5B.F0 SLICE_89
+ROUTE         1     0.700       R5C5B.F0 to       R6C5C.D0 n1280
+CTOF_DEL    ---     0.371       R6C5C.D0 to       R6C5C.F0 SLICE_79
+ROUTE         2     1.079       R6C5C.F0 to      R4C5D.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    8.419   (28.7% logic, 71.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C4C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C5D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.392ns (weighted slack = -8.784ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
+                   FF                        CmdUFMCLK_413
+
+   Delay:               8.291ns  (29.1% logic, 70.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.291ns physical path delay SLICE_88 to SLICE_81 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.392ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R4C3D.CLK to       R4C3D.Q0 SLICE_88 (from PHI2_c)
+ROUTE         1     1.155       R4C3D.Q0 to       R2C2A.D0 Bank_0
+CTOF_DEL    ---     0.371       R2C2A.D0 to       R2C2A.F0 SLICE_97
+ROUTE         1     1.348       R2C2A.F0 to       R4C4A.C0 n2314
+CTOF_DEL    ---     0.371       R4C4A.C0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     0.755       R4C4D.F1 to       R4C3A.D0 n1326
+CTOF_DEL    ---     0.371       R4C3A.D0 to       R4C3A.F0 SLICE_82
+ROUTE         2     0.903       R4C3A.F0 to       R4C5C.C1 n2460
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_83
+ROUTE         2     1.089       R4C5C.F1 to       R4C4A.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    8.291   (29.1% logic, 70.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C3D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C4A.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.392ns (weighted slack = -8.784ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:               8.291ns  (29.1% logic, 70.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.291ns physical path delay SLICE_88 to SLICE_93 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.392ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R4C3D.CLK to       R4C3D.Q0 SLICE_88 (from PHI2_c)
+ROUTE         1     1.155       R4C3D.Q0 to       R2C2A.D0 Bank_0
+CTOF_DEL    ---     0.371       R2C2A.D0 to       R2C2A.F0 SLICE_97
+ROUTE         1     1.348       R2C2A.F0 to       R4C4A.C0 n2314
+CTOF_DEL    ---     0.371       R4C4A.C0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     0.755       R4C4D.F1 to       R4C3A.D0 n1326
+CTOF_DEL    ---     0.371       R4C3A.D0 to       R4C3A.F0 SLICE_82
+ROUTE         2     0.903       R4C3A.F0 to       R4C5C.C1 n2460
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_83
+ROUTE         2     1.089       R4C5C.F1 to       R3C5A.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    8.291   (29.1% logic, 70.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C3D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R3C5A.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.263ns (weighted slack = -8.526ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
+                   FF                        CmdUFMCLK_413
+
+   Delay:               8.162ns  (29.6% logic, 70.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.162ns physical path delay SLICE_99 to SLICE_81 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.263ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     1.026       R2C4C.Q1 to       R2C2A.A0 Bank_7
+CTOF_DEL    ---     0.371       R2C2A.A0 to       R2C2A.F0 SLICE_97
+ROUTE         1     1.348       R2C2A.F0 to       R4C4A.C0 n2314
+CTOF_DEL    ---     0.371       R4C4A.C0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     0.755       R4C4D.F1 to       R4C3A.D0 n1326
+CTOF_DEL    ---     0.371       R4C3A.D0 to       R4C3A.F0 SLICE_82
+ROUTE         2     0.903       R4C3A.F0 to       R4C5C.C1 n2460
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_83
+ROUTE         2     1.089       R4C5C.F1 to       R4C4A.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    8.162   (29.6% logic, 70.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C4C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C4A.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.263ns (weighted slack = -8.526ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:               8.162ns  (29.6% logic, 70.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.162ns physical path delay SLICE_99 to SLICE_93 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.263ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     1.026       R2C4C.Q1 to       R2C2A.A0 Bank_7
+CTOF_DEL    ---     0.371       R2C2A.A0 to       R2C2A.F0 SLICE_97
+ROUTE         1     1.348       R2C2A.F0 to       R4C4A.C0 n2314
+CTOF_DEL    ---     0.371       R4C4A.C0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     0.755       R4C4D.F1 to       R4C3A.D0 n1326
+CTOF_DEL    ---     0.371       R4C3A.D0 to       R4C3A.F0 SLICE_82
+ROUTE         2     0.903       R4C3A.F0 to       R4C5C.C1 n2460
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_83
+ROUTE         2     1.089       R4C5C.F1 to       R3C5A.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    8.162   (29.6% logic, 70.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C4C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R3C5A.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.241ns (weighted slack = -8.482ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               7.767ns  (31.1% logic, 68.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.767ns physical path delay SLICE_99 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.241ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q0 SLICE_99 (from PHI2_c)
+ROUTE         1     1.026       R2C4C.Q0 to       R4C4A.A1 Bank_6
+CTOF_DEL    ---     0.371       R4C4A.A1 to       R4C4A.F1 SLICE_81
+ROUTE         1     0.696       R4C4A.F1 to       R4C4A.B0 n2278
+CTOF_DEL    ---     0.371       R4C4A.B0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     1.225       R4C4D.F1 to       R5C5B.D0 n1326
+CTOF_DEL    ---     0.371       R5C5B.D0 to       R5C5B.F0 SLICE_89
+ROUTE         1     0.700       R5C5B.F0 to       R6C5C.D0 n1280
+CTOF_DEL    ---     0.371       R6C5C.D0 to       R6C5C.F0 SLICE_79
+ROUTE         2     1.079       R6C5C.F0 to      R5C5D.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    7.767   (31.1% logic, 68.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C4C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R5C5D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.241ns (weighted slack = -8.482ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               7.767ns  (31.1% logic, 68.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.767ns physical path delay SLICE_99 to SLICE_9 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.241ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C4C.CLK to       R2C4C.Q0 SLICE_99 (from PHI2_c)
+ROUTE         1     1.026       R2C4C.Q0 to       R4C4A.A1 Bank_6
+CTOF_DEL    ---     0.371       R4C4A.A1 to       R4C4A.F1 SLICE_81
+ROUTE         1     0.696       R4C4A.F1 to       R4C4A.B0 n2278
+CTOF_DEL    ---     0.371       R4C4A.B0 to       R4C4A.F0 SLICE_81
+ROUTE         1     0.626       R4C4A.F0 to       R4C4D.D1 n26
+CTOF_DEL    ---     0.371       R4C4D.D1 to       R4C4D.F1 SLICE_18
+ROUTE         8     1.225       R4C4D.F1 to       R5C5B.D0 n1326
+CTOF_DEL    ---     0.371       R5C5B.D0 to       R5C5B.F0 SLICE_89
+ROUTE         1     0.700       R5C5B.F0 to       R6C5C.D0 n1280
+CTOF_DEL    ---     0.371       R6C5C.D0 to       R6C5C.F0 SLICE_79
+ROUTE         2     1.079       R6C5C.F0 to      R4C5D.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    7.767   (31.1% logic, 68.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R2C4C.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.911       39.PADDI to      R4C5D.CLK PHI2_c
+                  --------
+                    3.911   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning:  54.431MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 283.768000 MHz ; |  283.768 MHz|  129.769 MHz|   5 *
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 120.077000 MHz ; |  120.077 MHz|   54.431 MHz|   6 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+2 preferences(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+n1326                                   |       8|      95|     29.14%
+                                        |        |        |
+n26                                     |       1|      71|     21.78%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 326  Score: 913247
+Cumulative negative slack: 638389
+
+Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:29 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf 
+Design file:     ram2gs_lcmxo256c_impl1.ncd
+Preference file: ram2gs_lcmxo256c_impl1.prf
+Device,speed:    LCMXO256C,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 283.768000 MHz (0 errors)
    •             383 items scored, 0 timing errors detected.
+
+
  • FREQUENCY NET "PHI2_c" 120.077000 MHz (0 errors)
    •             106 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+            383 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_100 to SLICE_100 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_100 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R6C2B.CLK to       R6C2B.Q0 SLICE_100 (from RCLK_c)
+ROUTE         1     0.130       R6C2B.Q0 to       R6C2B.M1 n736 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R6C2B.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R6C2B.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i8  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i9  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_76 to SLICE_76 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_76 to SLICE_76:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R4C4B.CLK to       R4C4B.Q0 SLICE_76 (from RCLK_c)
+ROUTE         1     0.130       R4C4B.Q0 to       R4C4B.M1 n732 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_76:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R4C4B.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_76:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R4C4B.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_77 to SLICE_77 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_77 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R6C3D.CLK to       R6C3D.Q0 SLICE_77 (from RCLK_c)
+ROUTE         1     0.130       R6C3D.Q0 to       R6C3D.M1 n728 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R6C3D.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R6C3D.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_80 to SLICE_80 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_80 to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R8C4A.CLK to       R8C4A.Q0 SLICE_80 (from RCLK_c)
+ROUTE         1     0.130       R8C4A.Q0 to       R8C4A.M1 n726 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R8C4A.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R8C4A.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_82 to SLICE_82 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_82 to SLICE_82:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R4C3A.CLK to       R4C3A.Q0 SLICE_82 (from RCLK_c)
+ROUTE         1     0.130       R4C3A.Q0 to       R4C3A.M1 n730 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_82:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R4C3A.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_82:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R4C3A.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_84 to SLICE_84 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_84 to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R3C4A.CLK to       R3C4A.Q0 SLICE_84 (from RCLK_c)
+ROUTE         1     0.130       R3C4A.Q0 to       R3C4A.M1 n738 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R3C4A.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R3C4A.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_86 to SLICE_86 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_86 to SLICE_86:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R4C3C.CLK to       R4C3C.Q0 SLICE_86 (from RCLK_c)
+ROUTE         1     0.130       R4C3C.Q0 to       R4C3C.M1 n734 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_86:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R4C3C.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_86:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R4C3C.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.281ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
+
+   Delay:               0.264ns  (47.7% logic, 52.3% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.264ns physical path delay SLICE_87 to SLICE_87 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.281ns
+
+ Physical Path Details:
+
+      Data path SLICE_87 to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R4C2C.CLK to       R4C2C.Q0 SLICE_87 (from RCLK_c)
+ROUTE         6     0.138       R4C2C.Q0 to       R4C2C.M1 nRCS_N_139 (to RCLK_c)
+                  --------
+                    0.264   (47.7% logic, 52.3% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R4C2C.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R4C2C.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.288ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr2_380  (from RCLK_c +)
+   Destination:    FF         Data in        RASr3_381  (to RCLK_c +)
+
+   Delay:               0.271ns  (46.5% logic, 53.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.271ns physical path delay SLICE_74 to SLICE_74 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.288ns
+
+ Physical Path Details:
+
+      Data path SLICE_74 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R8C5C.CLK to       R8C5C.Q0 SLICE_74 (from RCLK_c)
+ROUTE        14     0.145       R8C5C.Q0 to       R8C5C.M1 RASr2 (to RCLK_c)
+                  --------
+                    0.271   (46.5% logic, 53.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R8C5C.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R8C5C.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.301ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        FS_610_add_4_16  (to RCLK_c +)
+                   FF                        FS_610__i15
+                   FF                        FS_610__i14
+
+   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.257ns physical path delay SLICE_1 to SLICE_1 meets
+     -0.044ns LUT_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.044ns) by 0.301ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R5C4D.CLK to       R5C4D.Q1 SLICE_1 (from RCLK_c)
+ROUTE         3     0.131       R5C4D.Q1 to       R5C4D.A1 FS_15 (to RCLK_c)
+                  --------
+                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R5C4D.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.333       86.PADDI to      R5C4D.CLK RCLK_c
+                  --------
+                    0.333   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+            106 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.361ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.342ns  (61.7% logic, 38.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.342ns physical path delay SLICE_14 to SLICE_14 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.361ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R5C5D.CLK to       R5C5D.Q0 SLICE_14 (from PHI2_c)
+ROUTE         2     0.131       R5C5D.Q0 to       R5C5D.A0 C1Submitted
+CTOF_DEL    ---     0.074       R5C5D.A0 to       R5C5D.F0 SLICE_14
+ROUTE         1     0.000       R5C5D.F0 to      R5C5D.DI0 n6_adj_3 (to PHI2_c)
+                  --------
+                    0.342   (61.7% logic, 38.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R5C5D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R5C5D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.361ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_407  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               0.342ns  (61.7% logic, 38.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.342ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.361ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R4C5D.CLK to       R4C5D.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.131       R4C5D.Q0 to       R4C5D.A0 ADSubmitted
+CTOF_DEL    ---     0.074       R4C5D.A0 to       R4C5D.F0 SLICE_9
+ROUTE         1     0.000       R4C5D.F0 to      R4C5D.DI0 n1413 (to PHI2_c)
+                  --------
+                    0.342   (61.7% logic, 38.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C5D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C5D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.587ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_408  (to PHI2_c -)
+
+   Delay:               0.564ns  (37.4% logic, 62.6% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.564ns physical path delay SLICE_18 to SLICE_49 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.587ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_49:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R4C4D.CLK to       R4C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.223       R4C4D.Q0 to       R3C4A.B1 CmdEnable
+CTOF_DEL    ---     0.074       R3C4A.B1 to       R3C4A.F1 SLICE_84
+ROUTE         1     0.130       R3C4A.F1 to       R3C4C.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    0.564   (37.4% logic, 62.6% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C4D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_49:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R3C4C.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.869ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
+                   FF                        CmdUFMCLK_413
+
+   Delay:               0.846ns  (33.7% logic, 66.3% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.846ns physical path delay SLICE_18 to SLICE_81 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.869ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R4C4D.CLK to       R4C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.145       R4C4D.Q0 to       R4C5C.D0 CmdEnable
+CTOF_DEL    ---     0.074       R4C5C.D0 to       R4C5C.F0 SLICE_83
+ROUTE         2     0.196       R4C5C.F0 to       R4C5C.A1 n10
+CTOF_DEL    ---     0.074       R4C5C.A1 to       R4C5C.F1 SLICE_83
+ROUTE         2     0.220       R4C5C.F1 to       R4C4A.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    0.846   (33.7% logic, 66.3% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C4D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C4A.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.869ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:               0.846ns  (33.7% logic, 66.3% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.846ns physical path delay SLICE_18 to SLICE_93 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.869ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R4C4D.CLK to       R4C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.145       R4C4D.Q0 to       R4C5C.D0 CmdEnable
+CTOF_DEL    ---     0.074       R4C5C.D0 to       R4C5C.F0 SLICE_83
+ROUTE         2     0.196       R4C5C.F0 to       R4C5C.A1 n10
+CTOF_DEL    ---     0.074       R4C5C.A1 to       R4C5C.F1 SLICE_83
+ROUTE         2     0.220       R4C5C.F1 to       R3C5A.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    0.846   (33.7% logic, 66.3% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C4D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R3C5A.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.057ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_410  (to PHI2_c -)
+
+   Delay:               1.034ns  (34.7% logic, 65.3% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.034ns physical path delay SLICE_18 to SLICE_23 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 1.057ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R4C4D.CLK to       R4C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.145       R4C4D.Q0 to       R4C5C.D0 CmdEnable
+CTOF_DEL    ---     0.074       R4C5C.D0 to       R4C5C.F0 SLICE_83
+ROUTE         2     0.211       R4C5C.F0 to       R4C4B.A1 n10
+CTOF_DEL    ---     0.074       R4C4B.A1 to       R4C4B.F1 SLICE_76
+ROUTE         2     0.103       R4C4B.F1 to       R4C4B.C0 n2458
+CTOF_DEL    ---     0.074       R4C4B.C0 to       R4C4B.F0 SLICE_76
+ROUTE         1     0.216       R4C4B.F0 to       R3C4B.CE PHI2_N_120_enable_4 (to PHI2_c)
+                  --------
+                    1.034   (34.7% logic, 65.3% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C4D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R3C4B.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.079ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_411  (to PHI2_c -)
+
+   Delay:               1.056ns  (34.0% logic, 66.0% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.056ns physical path delay SLICE_18 to SLICE_19 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 1.079ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R4C4D.CLK to       R4C4D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.145       R4C4D.Q0 to       R4C5C.D0 CmdEnable
+CTOF_DEL    ---     0.074       R4C5C.D0 to       R4C5C.F0 SLICE_83
+ROUTE         2     0.211       R4C5C.F0 to       R4C4B.A1 n10
+CTOF_DEL    ---     0.074       R4C4B.A1 to       R4C4B.F1 SLICE_76
+ROUTE         2     0.211       R4C4B.F1 to       R6C4D.A0 n2458
+CTOF_DEL    ---     0.074       R6C4D.A0 to       R6C4D.F0 SLICE_91
+ROUTE         1     0.130       R6C4D.F0 to       R6C4B.CE PHI2_N_120_enable_5 (to PHI2_c)
+                  --------
+                    1.056   (34.0% logic, 66.0% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C4D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R6C4B.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.104ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_407  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               1.081ns  (37.9% logic, 62.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.081ns physical path delay SLICE_9 to SLICE_18 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 1.104ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R4C5D.CLK to       R4C5D.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.143       R4C5D.Q0 to       R3C5C.D0 ADSubmitted
+CTOOFX_DEL  ---     0.125       R3C5C.D0 to     R3C5C.OFX0 i26/SLICE_71
+ROUTE         1     0.207     R3C5C.OFX0 to       R4C5A.A0 n13_adj_2
+CTOF_DEL    ---     0.074       R4C5A.A0 to       R4C5A.F0 SLICE_105
+ROUTE         1     0.179       R4C5A.F0 to       R4C3A.C1 n14
+CTOF_DEL    ---     0.074       R4C3A.C1 to       R4C3A.F1 SLICE_82
+ROUTE         1     0.142       R4C3A.F1 to       R4C4D.CE PHI2_N_120_enable_7 (to PHI2_c)
+                  --------
+                    1.081   (37.9% logic, 62.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C5D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C4D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.368ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               1.345ns  (35.7% logic, 64.3% route), 5 logic levels.
+
+ Constraint Details:
+
+      1.345ns physical path delay SLICE_14 to SLICE_18 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 1.368ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R5C5D.CLK to       R5C5D.Q0 SLICE_14 (from PHI2_c)
+ROUTE         2     0.196       R5C5D.Q0 to       R5C5D.A1 C1Submitted
+CTOF_DEL    ---     0.074       R5C5D.A1 to       R5C5D.F1 SLICE_14
+ROUTE         1     0.141       R5C5D.F1 to       R3C5C.D1 n2284
+CTOOFX_DEL  ---     0.121       R3C5C.D1 to     R3C5C.OFX0 i26/SLICE_71
+ROUTE         1     0.207     R3C5C.OFX0 to       R4C5A.A0 n13_adj_2
+CTOF_DEL    ---     0.074       R4C5A.A0 to       R4C5A.F0 SLICE_105
+ROUTE         1     0.179       R4C5A.F0 to       R4C3A.C1 n14
+CTOF_DEL    ---     0.074       R4C3A.C1 to       R4C3A.F1 SLICE_82
+ROUTE         1     0.142       R4C3A.F1 to       R4C4D.CE PHI2_N_120_enable_7 (to PHI2_c)
+                  --------
+                    1.345   (35.7% logic, 64.3% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R5C5D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R4C4D.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.689ns (weighted slack = 9.378ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_408  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_385  (to PHI2_c +)
+
+   Delay:               0.517ns  (40.8% logic, 59.2% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.517ns physical path delay SLICE_49 to SLICE_32 meets
+     -0.008ns DIN_HLD and
+     -4.164ns delay constraint less
+      0.000ns skew requirement (totaling -4.172ns) by 4.689ns
+
+ Physical Path Details:
+
+      Data path SLICE_49 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R3C4C.CLK to       R3C4C.Q0 SLICE_49 (from PHI2_c)
+ROUTE         1     0.306       R3C4C.Q0 to       R2C5A.A0 XOR8MEG
+CTOF_DEL    ---     0.074       R2C5A.A0 to       R2C5A.F0 SLICE_32
+ROUTE         1     0.000       R2C5A.F0 to      R2C5A.DI0 RA11_N_184 (to PHI2_c)
+                  --------
+                    0.517   (40.8% logic, 59.2% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_49:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R3C4C.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.965       39.PADDI to      R2C5A.CLK PHI2_c
+                  --------
+                    0.965   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 283.768000 MHz ; |     0.000 ns|     0.273 ns|   1  
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 120.077000 MHz ; |     0.000 ns|     0.361 ns|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 326 (setup), 0 (hold)
+Score: 913247 (setup), 0 (hold)
+Cumulative negative slack: 638389 (638389+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_drc.log b/CPLD/LCMXO256C/impl1/RAM2GS_drc.log new file mode 100644 index 0000000..7293e09 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_drc.log @@ -0,0 +1,15 @@ +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 318 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO256C_impl1.ngd. diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_lse.twr b/CPLD/LCMXO256C/impl1/RAM2GS_lse.twr new file mode 100644 index 0000000..02e97ea --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_lse.twr @@ -0,0 +1,291 @@ +-------------------------------------------------------------------------------- +Lattice Synthesis Timing Report, Version +Tue Aug 15 05:03:20 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Design: RAM2GS +Constraint file: +Report level: verbose report, limited to 3 items per constraint +-------------------------------------------------------------------------------- + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c] + 115 items scored, 112 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 8.575ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i3 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMCS_412 (to PHI2_c -) + + Delay: 10.811ns (23.7% logic, 76.3% route), 6 logic levels. + + Constraint Details: + + 10.811ns data_path Bank_i3 to CmdUFMCS_412 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns + + Path Details: Bank_i3 to CmdUFMCS_412 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i3 (from PHI2_c) +Route 1 e 1.220 Bank[3] +LUT4 --- 0.390 B to Z i1982_2_lut +Route 1 e 1.220 n2278 +LUT4 --- 0.390 C to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 8 e 1.719 n1326 +LUT4 --- 0.390 B to Z i1990_2_lut_rep_17 +Route 2 e 1.386 n2460 +LUT4 --- 0.390 C to Z i1_2_lut_4_lut +Route 3 e 1.483 PHI2_N_120_enable_6 + -------- + 10.811 (23.7% logic, 76.3% route), 6 logic levels. + + +Error: The following path violates requirements by 8.575ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i3 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMSDI_414 (to PHI2_c -) + + Delay: 10.811ns (23.7% logic, 76.3% route), 6 logic levels. + + Constraint Details: + + 10.811ns data_path Bank_i3 to CmdUFMSDI_414 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns + + Path Details: Bank_i3 to CmdUFMSDI_414 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i3 (from PHI2_c) +Route 1 e 1.220 Bank[3] +LUT4 --- 0.390 B to Z i1982_2_lut +Route 1 e 1.220 n2278 +LUT4 --- 0.390 C to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 8 e 1.719 n1326 +LUT4 --- 0.390 B to Z i1990_2_lut_rep_17 +Route 2 e 1.386 n2460 +LUT4 --- 0.390 C to Z i1_2_lut_4_lut +Route 3 e 1.483 PHI2_N_120_enable_6 + -------- + 10.811 (23.7% logic, 76.3% route), 6 logic levels. + + +Error: The following path violates requirements by 8.575ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i3 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMCLK_413 (to PHI2_c -) + + Delay: 10.811ns (23.7% logic, 76.3% route), 6 logic levels. + + Constraint Details: + + 10.811ns data_path Bank_i3 to CmdUFMCLK_413 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns + + Path Details: Bank_i3 to CmdUFMCLK_413 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i3 (from PHI2_c) +Route 1 e 1.220 Bank[3] +LUT4 --- 0.390 B to Z i1982_2_lut +Route 1 e 1.220 n2278 +LUT4 --- 0.390 C to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 8 e 1.719 n1326 +LUT4 --- 0.390 B to Z i1990_2_lut_rep_17 +Route 2 e 1.386 n2460 +LUT4 --- 0.390 C to Z i1_2_lut_4_lut +Route 3 e 1.483 PHI2_N_120_enable_6 + -------- + 10.811 (23.7% logic, 76.3% route), 6 logic levels. + +Warning: 11.075 ns is the maximum delay for this constraint. + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c] + 357 items scored, 234 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 4.364ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i13 (from RCLK_c +) + Destination: FD1P3AX D n8MEGEN_418 (to RCLK_c +) + + Delay: 9.182ns (23.7% logic, 76.3% route), 5 logic levels. + + Constraint Details: + + 9.182ns data_path FS_610__i13 to n8MEGEN_418 violates + 5.000ns delay constraint less + 0.182ns L_S requirement (totaling 4.818ns) by 4.364ns + + Path Details: FS_610__i13 to n8MEGEN_418 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_610__i13 (from RCLK_c) +Route 3 e 1.603 FS[13] +LUT4 --- 0.390 A to Z i1976_2_lut +Route 3 e 1.483 n2272 +LUT4 --- 0.390 C to Z i5_3_lut_rep_21_4_lut +Route 3 e 1.483 n2464 +LUT4 --- 0.390 B to Z i1_2_lut_3_lut_adj_4 +Route 1 e 1.220 n1325 +LUT4 --- 0.390 D to Z n8MEGEN_I_14_4_lut +Route 1 e 1.220 n8MEGEN_N_91 + -------- + 9.182 (23.7% logic, 76.3% route), 5 logic levels. + + +Error: The following path violates requirements by 4.364ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i15 (from RCLK_c +) + Destination: FD1P3AX D n8MEGEN_418 (to RCLK_c +) + + Delay: 9.182ns (23.7% logic, 76.3% route), 5 logic levels. + + Constraint Details: + + 9.182ns data_path FS_610__i15 to n8MEGEN_418 violates + 5.000ns delay constraint less + 0.182ns L_S requirement (totaling 4.818ns) by 4.364ns + + Path Details: FS_610__i15 to n8MEGEN_418 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_610__i15 (from RCLK_c) +Route 3 e 1.603 FS[15] +LUT4 --- 0.390 B to Z i1976_2_lut +Route 3 e 1.483 n2272 +LUT4 --- 0.390 C to Z i5_3_lut_rep_21_4_lut +Route 3 e 1.483 n2464 +LUT4 --- 0.390 B to Z i1_2_lut_3_lut_adj_4 +Route 1 e 1.220 n1325 +LUT4 --- 0.390 D to Z n8MEGEN_I_14_4_lut +Route 1 e 1.220 n8MEGEN_N_91 + -------- + 9.182 (23.7% logic, 76.3% route), 5 logic levels. + + +Error: The following path violates requirements by 4.349ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i13 (from RCLK_c +) + Destination: FD1P3AX SP n8MEGEN_418 (to RCLK_c +) + + Delay: 9.085ns (23.9% logic, 76.1% route), 5 logic levels. + + Constraint Details: + + 9.085ns data_path FS_610__i13 to n8MEGEN_418 violates + 5.000ns delay constraint less + 0.264ns LCE_S requirement (totaling 4.736ns) by 4.349ns + + Path Details: FS_610__i13 to n8MEGEN_418 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_610__i13 (from RCLK_c) +Route 3 e 1.603 FS[13] +LUT4 --- 0.390 A to Z i1976_2_lut +Route 3 e 1.483 n2272 +LUT4 --- 0.390 C to Z i7_4_lut +Route 2 e 1.386 n2214 +LUT4 --- 0.390 B to Z i2_2_lut +Route 1 e 1.220 n7 +LUT4 --- 0.390 A to Z i17_4_lut +Route 1 e 1.220 RCLK_c_enable_11 + -------- + 9.085 (23.9% logic, 76.1% route), 5 logic levels. + +Warning: 9.364 ns is the maximum delay for this constraint. + + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 5.000 ns| 22.150 ns| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 5.000 ns| 9.364 ns| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + +-------------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +-------------------------------------------------------------------------------- +n1326 | 8| 104| 30.06% + | | | +n26 | 1| 78| 22.54% + | | | +RCLK_c_enable_23 | 16| 64| 18.50% + | | | +-------------------------------------------------------------------------------- + + +Timing summary: +--------------- + +Timing errors: 346 Score: 1874657 + +Constraints cover 476 paths, 187 nets, and 480 connections (64.3% coverage) + + +Peak memory: 52895744 bytes, TRCE: 1204224 bytes, DLYMAN: 163840 bytes +CPU_TIME_REPORT: 0 secs diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html new file mode 100644 index 0000000..2c994f7 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_lse_lsetwr.html @@ -0,0 +1,356 @@ + +Lattice Synthesis Timing Report + + +
    Lattice Synthesis Timing Report
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Tue Aug 15 05:03:20 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
+            115 items scored, 112 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 8.575ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCS_412  (to PHI2_c -)
+
+   Delay:                  10.811ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.811ns data_path Bank_i3 to CmdUFMCS_412 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns
+
+ Path Details: Bank_i3 to CmdUFMCS_412
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 1.220                                  Bank[3]
+LUT4        ---     0.390              B to Z              i1982_2_lut
+Route         1   e 1.220                                  n2278
+LUT4        ---     0.390              C to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         8   e 1.719                                  n1326
+LUT4        ---     0.390              B to Z              i1990_2_lut_rep_17
+Route         2   e 1.386                                  n2460
+LUT4        ---     0.390              C to Z              i1_2_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_120_enable_6
+                  --------
+                   10.811  (23.7% logic, 76.3% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 8.575ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:                  10.811ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.811ns data_path Bank_i3 to CmdUFMSDI_414 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns
+
+ Path Details: Bank_i3 to CmdUFMSDI_414
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 1.220                                  Bank[3]
+LUT4        ---     0.390              B to Z              i1982_2_lut
+Route         1   e 1.220                                  n2278
+LUT4        ---     0.390              C to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         8   e 1.719                                  n1326
+LUT4        ---     0.390              B to Z              i1990_2_lut_rep_17
+Route         2   e 1.386                                  n2460
+LUT4        ---     0.390              C to Z              i1_2_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_120_enable_6
+                  --------
+                   10.811  (23.7% logic, 76.3% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 8.575ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCLK_413  (to PHI2_c -)
+
+   Delay:                  10.811ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.811ns data_path Bank_i3 to CmdUFMCLK_413 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns
+
+ Path Details: Bank_i3 to CmdUFMCLK_413
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 1.220                                  Bank[3]
+LUT4        ---     0.390              B to Z              i1982_2_lut
+Route         1   e 1.220                                  n2278
+LUT4        ---     0.390              C to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         8   e 1.719                                  n1326
+LUT4        ---     0.390              B to Z              i1990_2_lut_rep_17
+Route         2   e 1.386                                  n2460
+LUT4        ---     0.390              C to Z              i1_2_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_120_enable_6
+                  --------
+                   10.811  (23.7% logic, 76.3% route), 6 logic levels.
+
+Warning: 11.075 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            357 items scored, 234 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 4.364ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i13  (from RCLK_c +)
+   Destination:    FD1P3AX    D              n8MEGEN_418  (to RCLK_c +)
+
+   Delay:                   9.182ns  (23.7% logic, 76.3% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.182ns data_path FS_610__i13 to n8MEGEN_418 violates
+      5.000ns delay constraint less
+      0.182ns L_S requirement (totaling 4.818ns) by 4.364ns
+
+ Path Details: FS_610__i13 to n8MEGEN_418
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_610__i13 (from RCLK_c)
+Route         3   e 1.603                                  FS[13]
+LUT4        ---     0.390              A to Z              i1976_2_lut
+Route         3   e 1.483                                  n2272
+LUT4        ---     0.390              C to Z              i5_3_lut_rep_21_4_lut
+Route         3   e 1.483                                  n2464
+LUT4        ---     0.390              B to Z              i1_2_lut_3_lut_adj_4
+Route         1   e 1.220                                  n1325
+LUT4        ---     0.390              D to Z              n8MEGEN_I_14_4_lut
+Route         1   e 1.220                                  n8MEGEN_N_91
+                  --------
+                    9.182  (23.7% logic, 76.3% route), 5 logic levels.
+
+
+Error:  The following path violates requirements by 4.364ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i15  (from RCLK_c +)
+   Destination:    FD1P3AX    D              n8MEGEN_418  (to RCLK_c +)
+
+   Delay:                   9.182ns  (23.7% logic, 76.3% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.182ns data_path FS_610__i15 to n8MEGEN_418 violates
+      5.000ns delay constraint less
+      0.182ns L_S requirement (totaling 4.818ns) by 4.364ns
+
+ Path Details: FS_610__i15 to n8MEGEN_418
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_610__i15 (from RCLK_c)
+Route         3   e 1.603                                  FS[15]
+LUT4        ---     0.390              B to Z              i1976_2_lut
+Route         3   e 1.483                                  n2272
+LUT4        ---     0.390              C to Z              i5_3_lut_rep_21_4_lut
+Route         3   e 1.483                                  n2464
+LUT4        ---     0.390              B to Z              i1_2_lut_3_lut_adj_4
+Route         1   e 1.220                                  n1325
+LUT4        ---     0.390              D to Z              n8MEGEN_I_14_4_lut
+Route         1   e 1.220                                  n8MEGEN_N_91
+                  --------
+                    9.182  (23.7% logic, 76.3% route), 5 logic levels.
+
+
+Error:  The following path violates requirements by 4.349ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i13  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             n8MEGEN_418  (to RCLK_c +)
+
+   Delay:                   9.085ns  (23.9% logic, 76.1% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.085ns data_path FS_610__i13 to n8MEGEN_418 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 4.349ns
+
+ Path Details: FS_610__i13 to n8MEGEN_418
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_610__i13 (from RCLK_c)
+Route         3   e 1.603                                  FS[13]
+LUT4        ---     0.390              A to Z              i1976_2_lut
+Route         3   e 1.483                                  n2272
+LUT4        ---     0.390              C to Z              i7_4_lut
+Route         2   e 1.386                                  n2214
+LUT4        ---     0.390              B to Z              i2_2_lut
+Route         1   e 1.220                                  n7
+LUT4        ---     0.390              A to Z              i17_4_lut
+Route         1   e 1.220                                  RCLK_c_enable_11
+                  --------
+                    9.085  (23.9% logic, 76.1% route), 5 logic levels.
+
+Warning: 9.364 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |     5.000 ns|    22.150 ns|     6 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|     9.364 ns|     5 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n1326                                   |       8|     104|     30.06%
+                                        |        |        |
+n26                                     |       1|      78|     22.54%
+                                        |        |        |
+RCLK_c_enable_23                        |      16|      64|     18.50%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 346  Score: 1874657
+
+Constraints cover  476 paths, 187 nets, and 480 connections (64.3% coverage)
+
+
+Peak memory: 52895744 bytes, TRCE: 1204224 bytes, DLYMAN: 163840 bytes
+CPU_TIME_REPORT: 0 secs 
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/RAM2GS_prim.v b/CPLD/LCMXO256C/impl1/RAM2GS_prim.v new file mode 100644 index 0000000..ef9726d --- /dev/null +++ b/CPLD/LCMXO256C/impl1/RAM2GS_prim.v @@ -0,0 +1,819 @@ +// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.12.1.454 +// Netlist written on Tue Aug 15 05:03:20 2023 +// +// Verilog Description of module RAM2GS +// + +module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, + LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, + nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1[8:14]) + input PHI2; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + input [9:0]MAin; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + input [1:0]CROW; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + input [7:0]Din; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + output [7:0]Dout; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + input nCCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + input nCRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + input nFWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) + output LED; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) + output [1:0]RBA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + output [11:0]RA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + inout [7:0]RD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + output nRCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) + input RCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + output RCKE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) + output nRWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) + output nRRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) + output nRCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) + output RDQMH; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) + output RDQML; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) + output nUFMCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) + output UFMCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) + output UFMSDI; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) + input UFMSDO; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) + + wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + wire nCCAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + wire nCRAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + wire nCRAS_N_9 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + wire PHI2_N_120 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(38[6:13]) + + wire GND_net, VCC_net, PHI2r, PHI2r2, PHI2r3, RASr, RASr2, + RASr3, CASr, CASr2, CASr3, FWEr, CBR, LEDEN, Din_c_7, + Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, Din_c_0; + wire [7:0]Bank; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(31[12:16]) + + wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, + MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, + nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, + nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, RA_0; + wire [9:0]RowA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(51[12:16]) + + wire RA_1_9, RA_1_8, RA_1_7, RA_1_6, RA_1_5, RA_1_4, RA_1_3, + RA_1_2, RA_1_1, RA_1_0, RDQML_c, RDQMH_c; + wire [7:0]WRD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(59[12:15]) + + wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted, + CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI, + CmdUFMCS, InitReady, Ready; + wire [17:0]FS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15]) + + wire LED_N_84, nFWE_N_5, n2414, RA11_N_184, n15, n2262, PHI2_N_120_enable_6, + n2257, n7, RASr2_N_63, RCKE_N_132, nRowColSel_N_35, n2011, + nRWE_N_182, RCKEEN_N_130, nRowColSel_N_34, nRowColSel_N_33, + n2015, nRowColSel_N_32, nRowColSel_N_28, n1426, n6, n2328, + n2457, n1425, RCKEEN_N_123, nRWE_N_178, RCKEEN_N_122, n2324, + nRCS_N_139, nRCAS_N_165, nRWE_N_177, nRWE_N_176, n2322, Ready_N_296, + n2316, n2314, Ready_N_292, nRCS_N_136, nRCAS_N_161, nRWE_N_171, + RCKEEN_N_121, n2336, PHI2_N_120_enable_5, n2209, CmdEnable_N_248, + C1Submitted_N_237, n2478, n2477, n2138, n1410, n2290, Cmdn8MEGEN_N_264, + XOR8MEG_N_110, n2208, LEDEN_N_82, n2243, RCLK_c_enable_24, + n2476, n2475, n8MEGEN_N_91, UFMCLK_N_224, UFMSDI_N_231, n2460, + n2227, n2253, n726, n727, n728, n729, n730, n1502, n732, + n733, n734, n735, n736, n737, n738, n2284, n2463, n2164, + PHI2_N_120_enable_4, n1325, n2278, n1503, n2214, n1417, + n2010, n2474, n2009, n1280, n33, n2473, n2263, n56, + PHI2_N_120_enable_1, n12, n10, n13, n2272, Dout_c, n78, + n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, + n89, n90, n91, n92, n93, n94, n95, n15_adj_1, n1, + n2462, n2472, n2471, n1093, RCLK_c_enable_11, n62, RCLK_c_enable_25, + n2470, n2242, n2461, RCLK_c_enable_23, RCLK_c_enable_12, n2451, + n2014, n14, n13_adj_2, n2568, n2245, PHI2_N_120_enable_7, + RCLK_c_enable_4, n2469, n1413, n1846, Dout_0, Dout_1, n984, + Dout_2, Dout_3, Dout_4, n1314, Dout_5, Dout_6, n2468, + n1160, n2337, n2008, n2013, n6_adj_3, RCLK_c_enable_3, n2467, + n2012, n2479, n1326, n2464, n8, n2481, n2430, n2459, + n2458, n2427, n2480, n11, n26; + + VHI i2 (.Z(VCC_net)); + INV i2136 (.A(PHI2_c), .Z(PHI2_N_120)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + ORCALUT4 i6_4_lut (.A(FS[17]), .B(n12), .C(FS[12]), .D(FS[14]), + .Z(n62)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i6_4_lut.init = 16'h8000; + ORCALUT4 i1_4_lut_4_lut (.A(Din_c_3), .B(Din_c_5), .C(Din_c_4), .D(n2458), + .Z(PHI2_N_120_enable_4)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A !(B+!(D))) */ ; + defparam i1_4_lut_4_lut.init = 16'hb300; + FD1S3AX PHI2r2_377 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r2_377.GSR = "ENABLED"; + ORCALUT4 i1994_3_lut (.A(FS[2]), .B(FS[5]), .C(FS[9]), .Z(n2290)) /* synthesis lut_function=(A+(B+(C))) */ ; + defparam i1994_3_lut.init = 16'hfefe; + ORCALUT4 i1_2_lut_3_lut (.A(MAin_c_0), .B(n1326), .C(MAin_c_1), .Z(n2263)) /* synthesis lut_function=((B+!(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(80[15:31]) + defparam i1_2_lut_3_lut.init = 16'hdfdf; + FD1S3AX PHI2r3_378 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r3_378.GSR = "ENABLED"; + FD1S3AX RASr_379 (.D(nCRAS_N_9), .CK(RCLK_c), .Q(RASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr_379.GSR = "ENABLED"; + FD1S3AX RASr2_380 (.D(RASr), .CK(RCLK_c), .Q(RASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr2_380.GSR = "ENABLED"; + FD1S3AX RASr3_381 (.D(RASr2), .CK(RCLK_c), .Q(RASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr3_381.GSR = "ENABLED"; + FD1S3AX CASr_382 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr_382.GSR = "ENABLED"; + FD1S3AX CASr2_383 (.D(CASr), .CK(RCLK_c), .Q(CASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr2_383.GSR = "ENABLED"; + FD1S3AX CASr3_384 (.D(CASr2), .CK(RCLK_c), .Q(CASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr3_384.GSR = "ENABLED"; + FD1S3IX RA11_385 (.D(RA11_N_184), .CK(PHI2_c), .CD(n2477), .Q(RA_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam RA11_385.GSR = "ENABLED"; + FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i0.GSR = "ENABLED"; + ORCALUT4 i637_1_lut_rep_34 (.A(Ready), .Z(n2477)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i637_1_lut_rep_34.init = 16'h5555; + FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i0.GSR = "ENABLED"; + FD1S3AX FWEr_389 (.D(nFWE_N_5), .CK(nCRAS_N_9), .Q(FWEr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam FWEr_389.GSR = "ENABLED"; + FD1S3AX CBR_390 (.D(nCCAS_N_3), .CK(nCRAS_N_9), .Q(CBR)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam CBR_390.GSR = "ENABLED"; + FD1S3IX ADSubmitted_407 (.D(n1413), .CK(PHI2_N_120), .CD(C1Submitted_N_237), + .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam ADSubmitted_407.GSR = "ENABLED"; + ORCALUT4 i2026_4_lut (.A(FS[0]), .B(FS[1]), .C(FS[6]), .D(FS[3]), + .Z(n2322)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i2026_4_lut.init = 16'hfffe; + FD1S3AX RCKE_395 (.D(RCKE_N_132), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(141[9] 144[5]) + defparam RCKE_395.GSR = "ENABLED"; + FD1P3AY nRCS_396 (.D(nRCS_N_136), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRCS_396.GSR = "ENABLED"; + FD1S3IX nRowColSel_402 (.D(n1410), .CK(RCLK_c), .CD(n2469), .Q(nRowColSel)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRowColSel_402.GSR = "ENABLED"; + ORCALUT4 n8MEGEN_I_14_4_lut (.A(UFMSDO_c), .B(Cmdn8MEGEN), .C(InitReady), + .D(n1325), .Z(n8MEGEN_N_91)) /* synthesis lut_function=(A (B (C+(D)))+!A (B+!(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(394[12] 409[6]) + defparam n8MEGEN_I_14_4_lut.init = 16'hccc5; + ORCALUT4 i771_2_lut_rep_26_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2469)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i771_2_lut_rep_26_2_lut.init = 16'hdddd; + ORCALUT4 i7_4_lut (.A(FS[10]), .B(n2328), .C(n2272), .D(FS[11]), + .Z(n2214)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i7_4_lut.init = 16'h0200; + ORCALUT4 i2062_2_lut_3_lut_4_lut (.A(nFWE_c), .B(n1326), .C(C1Submitted), + .D(MAin_c_1), .Z(n6_adj_3)) /* synthesis lut_function=(A (C)+!A (B (C)+!B !((D)+!C))) */ ; + defparam i2062_2_lut_3_lut_4_lut.init = 16'he0f0; + ORCALUT4 i2046_1_lut_2_lut_3_lut_3_lut (.A(Ready), .B(n13), .C(nRCS_N_139), + .Z(n2337)) /* synthesis lut_function=(!(A (B)+!A !((C)+!B))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i2046_1_lut_2_lut_3_lut_3_lut.init = 16'h7373; + ORCALUT4 i3_3_lut_4_lut_4_lut (.A(Ready), .B(InitReady), .C(RASr2), + .D(nRowColSel_N_35), .Z(RCLK_c_enable_23)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i3_3_lut_4_lut_4_lut.init = 16'h4000; + ORCALUT4 i2065_2_lut_3_lut (.A(FS[11]), .B(n2464), .C(InitReady), + .Z(n1846)) /* synthesis lut_function=(!(A+(B+(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i2065_2_lut_3_lut.init = 16'h0101; + ORCALUT4 i2055_3_lut_4_lut (.A(FS[11]), .B(n2464), .C(FS[10]), .D(InitReady), + .Z(LEDEN_N_82)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i2055_3_lut_4_lut.init = 16'h0001; + ORCALUT4 i2_3_lut (.A(n2214), .B(FS[11]), .C(InitReady), .Z(RCLK_c_enable_12)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam i2_3_lut.init = 16'h0808; + CCU2 FS_610_add_4_8 (.A0(FS[6]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[7]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2010), + .COUT1(n2011), .S0(n89), .S1(n88)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_8.INIT0 = 16'hfaaa; + defparam FS_610_add_4_8.INIT1 = 16'hfaaa; + defparam FS_610_add_4_8.INJECT1_0 = "NO"; + defparam FS_610_add_4_8.INJECT1_1 = "NO"; + FD1S3IX S_FSM_i3 (.D(n1093), .CK(RCLK_c), .CD(n1425), .Q(nRowColSel_N_33)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i3.GSR = "ENABLED"; + ORCALUT4 Ready_bdd_4_lut (.A(nRowColSel_N_32), .B(RASr2), .C(Ready_N_296), + .D(InitReady), .Z(n2414)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; + defparam Ready_bdd_4_lut.init = 16'h2000; + FD1S3AY nRRAS_397 (.D(n2138), .CK(RCLK_c), .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRRAS_397.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_2_lut (.A(Ready), .B(nRowColSel_N_34), .Z(n56)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i1_2_lut_2_lut.init = 16'hdddd; + ORCALUT4 i2_4_lut (.A(Din_c_2), .B(n2463), .C(n1280), .D(n2468), + .Z(C1Submitted_N_237)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ; + defparam i2_4_lut.init = 16'h0400; + ORCALUT4 i1_2_lut_3_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_32), + .C(n1502), .D(nRowColSel_N_35), .Z(RCLK_c_enable_3)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i1_2_lut_3_lut_4_lut_4_lut.init = 16'hfffd; + ORCALUT4 Din_7__I_0_462_i6_2_lut_rep_35 (.A(Din_c_6), .B(Din_c_7), .Z(n2478)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) + defparam Din_7__I_0_462_i6_2_lut_rep_35.init = 16'heeee; + BB Dout_pad_7__713 (.I(WRD[7]), .T(n984), .B(RD[7]), .O(Dout_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + FD1P3AY nRCAS_398 (.D(nRCAS_N_161), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRCAS_398.GSR = "ENABLED"; + FD1P3AY nRWE_399 (.D(nRWE_N_171), .SP(RCLK_c_enable_3), .CK(RCLK_c), + .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRWE_399.GSR = "ENABLED"; + FD1S3JX RA10_400 (.D(n2209), .CK(RCLK_c), .PD(nRWE_N_176), .Q(RA_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam RA10_400.GSR = "ENABLED"; + FD1P3AX RCKEEN_401 (.D(RCKEEN_N_121), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(RCKEEN)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam RCKEEN_401.GSR = "ENABLED"; + FD1S3AX FS_610__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i0.GSR = "ENABLED"; + ORCALUT4 i13_4_lut (.A(MAin_c_2), .B(n26), .C(n2316), .D(MAin_c_5), + .Z(n1326)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; + defparam i13_4_lut.init = 16'hdfff; + ORCALUT4 i12_4_lut (.A(Bank[2]), .B(n2314), .C(n2278), .D(Bank[5]), + .Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; + defparam i12_4_lut.init = 16'hbfff; + ORCALUT4 i2_3_lut_adj_1 (.A(MAin_c_1), .B(n1326), .C(MAin_c_0), .Z(n1280)) /* synthesis lut_function=((B+(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(80[15:31]) + defparam i2_3_lut_adj_1.init = 16'hfdfd; + FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_N_9), .CD(n2477), .Q(RBA_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RBA__i1.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_3_lut_adj_2 (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), + .Z(n1314)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) + defparam i1_2_lut_3_lut_adj_2.init = 16'hfefe; + ORCALUT4 i2020_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]), + .Z(n2316)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i2020_4_lut.init = 16'h8000; + ORCALUT4 i1990_2_lut_rep_17 (.A(nFWE_c), .B(n1326), .Z(n2460)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1990_2_lut_rep_17.init = 16'heeee; + ORCALUT4 i1125_4_lut (.A(n2459), .B(n2242), .C(ADSubmitted), .D(n2263), + .Z(n1413)) /* synthesis lut_function=(!(A ((D)+!B)+!A !(B (C+!(D))+!B (C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam i1125_4_lut.init = 16'h50dc; + ORCALUT4 i2018_4_lut (.A(MAin_c_6), .B(MAin_c_4), .C(Bank[7]), .D(Bank[0]), + .Z(n2314)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i2018_4_lut.init = 16'h8000; + ORCALUT4 i4_4_lut (.A(Din_c_4), .B(n2478), .C(CmdEnable), .D(MAin_c_1), + .Z(n10)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; + defparam i4_4_lut.init = 16'h0020; + ORCALUT4 i2_2_lut_rep_27 (.A(FS[16]), .B(FS[14]), .Z(n2470)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i2_2_lut_rep_27.init = 16'heeee; + ORCALUT4 i2_3_lut_4_lut (.A(nRowColSel_N_32), .B(n2469), .C(nRowColSel_N_34), + .D(nRowColSel_N_33), .Z(RCLK_c_enable_4)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i2_3_lut_4_lut.init = 16'hfffe; + ORCALUT4 Cmdn8MEGEN_I_93_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_4), + .D(n1314), .Z(Cmdn8MEGEN_N_264)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(321[13] 335[7]) + defparam Cmdn8MEGEN_I_93_4_lut.init = 16'hcc5c; + ORCALUT4 i1982_2_lut (.A(Bank[6]), .B(Bank[3]), .Z(n2278)) /* synthesis lut_function=(A (B)) */ ; + defparam i1982_2_lut.init = 16'h8888; + ORCALUT4 i2_4_lut_adj_3 (.A(Din_c_3), .B(Din_c_4), .C(Din_c_5), .D(n2458), + .Z(PHI2_N_120_enable_5)) /* synthesis lut_function=(A (B (D))+!A !((C+!(D))+!B)) */ ; + defparam i2_4_lut_adj_3.init = 16'h8c00; + FD1P3AX IS_FSM__i0 (.D(Ready_N_296), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRCS_N_139)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i0.GSR = "ENABLED"; + FD1S3JX C1Submitted_406 (.D(n6_adj_3), .CK(PHI2_N_120), .PD(C1Submitted_N_237), + .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam C1Submitted_406.GSR = "ENABLED"; + FD1S3JX nUFMCS_415 (.D(n2164), .CK(RCLK_c), .PD(LEDEN_N_82), .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam nUFMCS_415.GSR = "ENABLED"; + ORCALUT4 i2049_3_lut (.A(LEDEN), .B(CBR), .C(nCRAS_c), .Z(LED_N_84)) /* synthesis lut_function=((B+(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[15:41]) + defparam i2049_3_lut.init = 16'hfdfd; + ORCALUT4 MAin_9__I_0_427_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), + .Z(RA_1_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i10_3_lut.init = 16'hcaca; + FD1S3AX S_FSM_i1 (.D(RASr2_N_63), .CK(RCLK_c), .Q(nRowColSel_N_35)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i1.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_3_lut_adj_4 (.A(FS[11]), .B(n2464), .C(FS[10]), + .Z(n1325)) /* synthesis lut_function=((B+!(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_3_lut_adj_4.init = 16'hdfdf; + ORCALUT4 MAin_9__I_0_427_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), + .Z(RA_1_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i9_3_lut.init = 16'hcaca; + ORCALUT4 MAin_9__I_0_427_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), + .Z(RA_1_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i8_3_lut.init = 16'hcaca; + ORCALUT4 i1209_4_lut_else_4_lut (.A(nRCS_N_139), .B(Ready), .C(nRowColSel_N_35), + .Z(n2479)) /* synthesis lut_function=(!(A (B (C))+!A (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(48[6:16]) + defparam i1209_4_lut_else_4_lut.init = 16'h2f2f; + ORCALUT4 i1_2_lut_3_lut_adj_5 (.A(MAin_c_0), .B(n1326), .C(MAin_c_1), + .Z(n2262)) /* synthesis lut_function=((B+(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(80[15:31]) + defparam i1_2_lut_3_lut_adj_5.init = 16'hfdfd; + ORCALUT4 i2045_1_lut_4_lut (.A(n56), .B(nRRAS_c), .C(n6), .D(nRowColSel_N_32), + .Z(n2336)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i2045_1_lut_4_lut.init = 16'hfffe; + FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i0.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_4_lut (.A(MAin_c_0), .B(n10), .C(n2460), .D(n2476), + .Z(PHI2_N_120_enable_6)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i1_2_lut_4_lut.init = 16'h0800; + ORCALUT4 i2_3_lut_rep_29 (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), + .Z(n2472)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) + defparam i2_3_lut_rep_29.init = 16'h0808; + ORCALUT4 nRowColSel_N_34_bdd_3_lut_2115 (.A(nRowColSel_N_34), .B(n15_adj_1), + .C(Ready), .Z(n2430)) /* synthesis lut_function=(A+!(B (C))) */ ; + defparam nRowColSel_N_34_bdd_3_lut_2115.init = 16'hbfbf; + ORCALUT4 i4_4_lut_adj_6 (.A(MAin_c_1), .B(n2476), .C(MAin_c_0), .D(n2284), + .Z(n2257)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ; + defparam i4_4_lut_adj_6.init = 16'h0080; + FD1S3AX PHI2r_376 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r_376.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_4_lut_adj_7 (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), + .D(InitReady), .Z(RCLK_c_enable_24)) /* synthesis lut_function=(!(A (B (C (D))+!B (D))+!A (D))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) + defparam i1_2_lut_4_lut_adj_7.init = 16'h08ff; + ORCALUT4 i2024_2_lut_rep_28 (.A(FS[17]), .B(FS[12]), .Z(n2471)) /* synthesis lut_function=(A+(B)) */ ; + defparam i2024_2_lut_rep_28.init = 16'heeee; + FD1S3IX S_FSM_i4 (.D(n1503), .CK(RCLK_c), .CD(RASr2_N_63), .Q(nRowColSel_N_32)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i4.GSR = "ENABLED"; + CCU2 FS_610_add_4_16 (.A0(FS[14]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[15]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2014), + .COUT1(n2015), .S0(n81), .S1(n80)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_16.INIT0 = 16'hfaaa; + defparam FS_610_add_4_16.INIT1 = 16'hfaaa; + defparam FS_610_add_4_16.INJECT1_0 = "NO"; + defparam FS_610_add_4_16.INJECT1_1 = "NO"; + ORCALUT4 i2_3_lut_4_lut_adj_8 (.A(nRowColSel_N_35), .B(RASr2), .C(InitReady), + .D(nRCS_N_139), .Z(n2208)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i2_3_lut_4_lut_adj_8.init = 16'hff7f; + ORCALUT4 i1_4_lut_4_lut_adj_9 (.A(CBR), .B(n11), .C(FWEr), .D(nRowColSel_N_34), + .Z(RCKEEN_N_123)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[27:31]) + defparam i1_4_lut_4_lut_adj_9.init = 16'h5540; + ORCALUT4 i3_4_lut (.A(CBR), .B(FWEr), .C(CASr2), .D(CASr3), .Z(n1)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ; + defparam i3_4_lut.init = 16'h0040; + PFUMX i2095 (.BLUT(n2430), .ALUT(n2457), .C0(nRowColSel_N_35), .Z(nRCAS_N_161)); + ORCALUT4 MAin_9__I_0_427_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), + .Z(RA_1_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i7_3_lut.init = 16'hcaca; + ORCALUT4 i1_4_lut (.A(nRowColSel), .B(n1502), .C(nRowColSel_N_28), + .D(nRowColSel_N_32), .Z(n1410)) /* synthesis lut_function=(A (B+!(C (D)))+!A (B+!(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1_4_lut.init = 16'hcfee; + ORCALUT4 i1_2_lut (.A(RASr2), .B(RCKE_c), .Z(nRWE_N_182)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam i1_2_lut.init = 16'hbbbb; + ORCALUT4 i2004_2_lut_rep_30 (.A(Din_c_4), .B(nFWE_c), .Z(n2473)) /* synthesis lut_function=(A+(B)) */ ; + defparam i2004_2_lut_rep_30.init = 16'heeee; + ORCALUT4 i1_2_lut_rep_20_3_lut (.A(Din_c_4), .B(nFWE_c), .C(n2253), + .Z(n2463)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; + defparam i1_2_lut_rep_20_3_lut.init = 16'h1010; + ORCALUT4 i2_3_lut_adj_10 (.A(Din_c_7), .B(Din_c_0), .C(Din_c_1), .Z(n2253)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; + defparam i2_3_lut_adj_10.init = 16'h0808; + CCU2 FS_610_add_4_6 (.A0(FS[4]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[5]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2009), + .COUT1(n2010), .S0(n91), .S1(n90)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_6.INIT0 = 16'hfaaa; + defparam FS_610_add_4_6.INIT1 = 16'hfaaa; + defparam FS_610_add_4_6.INJECT1_0 = "NO"; + defparam FS_610_add_4_6.INJECT1_1 = "NO"; + ORCALUT4 i2_4_lut_adj_11 (.A(n2473), .B(CmdEnable), .C(n2262), .D(n1314), + .Z(PHI2_N_120_enable_1)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; + defparam i2_4_lut_adj_11.init = 16'h0004; + ORCALUT4 MAin_9__I_0_427_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), + .Z(RA_1_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i6_3_lut.init = 16'hcaca; + ORCALUT4 i3_4_lut_adj_12 (.A(Din_c_0), .B(Din_c_3), .C(Din_c_2), .D(n2324), + .Z(XOR8MEG_N_110)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; + defparam i3_4_lut_adj_12.init = 16'h0020; + ORCALUT4 MAin_9__I_0_427_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), + .Z(RA_1_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i5_3_lut.init = 16'hcaca; + ORCALUT4 i2028_4_lut (.A(Din_c_4), .B(LEDEN), .C(n1314), .D(Din_c_1), + .Z(n2324)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ; + defparam i2028_4_lut.init = 16'hfefa; + ORCALUT4 MAin_9__I_0_427_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), + .Z(RA_1_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i4_3_lut.init = 16'hcaca; + ORCALUT4 i2_3_lut_rep_31 (.A(Din_c_6), .B(Din_c_2), .C(Din_c_3), .Z(n2474)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i2_3_lut_rep_31.init = 16'h4040; + FD1P3IX UFMSDI_417 (.D(UFMSDI_N_231), .SP(RCLK_c_enable_24), .CD(n1846), + .CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam UFMSDI_417.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_4_lut_adj_13 (.A(Din_c_6), .B(Din_c_2), .C(Din_c_3), + .D(MAin_c_0), .Z(n2243)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i1_2_lut_4_lut_adj_13.init = 16'h4000; + ORCALUT4 MAin_9__I_0_427_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), + .Z(RA_1_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i3_3_lut.init = 16'hcaca; + ORCALUT4 n2427_bdd_4_lut_4_lut (.A(CBR), .B(RASr2), .C(Ready), .D(n2427), + .Z(n2457)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A !((C+(D))+!B))) */ ; + defparam n2427_bdd_4_lut_4_lut.init = 16'h7f73; + GSR GSR_INST (.GSR(VCC_net)); + ORCALUT4 i2_3_lut_adj_14 (.A(FWEr), .B(CASr3), .C(CBR), .Z(nRowColSel_N_28)) /* synthesis lut_function=((B+(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(230[16:37]) + defparam i2_3_lut_adj_14.init = 16'hfdfd; + ORCALUT4 InitReady_bdd_3_lut (.A(InitReady), .B(nRCS_N_139), .C(nRCAS_N_165), + .Z(n2427)) /* synthesis lut_function=((B+(C))+!A) */ ; + defparam InitReady_bdd_3_lut.init = 16'hfdfd; + ORCALUT4 i35_3_lut_4_lut (.A(FWEr), .B(CBR), .C(nRowColSel_N_33), + .D(n1), .Z(n15_adj_1)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C+(D))))) */ ; + defparam i35_3_lut_4_lut.init = 16'h1f10; + ORCALUT4 MAin_9__I_0_427_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), + .Z(RA_1_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i2_3_lut.init = 16'hcaca; + CCU2 FS_610_add_4_14 (.A0(FS[12]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[13]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2013), + .COUT1(n2014), .S0(n83), .S1(n82)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_14.INIT0 = 16'hfaaa; + defparam FS_610_add_4_14.INIT1 = 16'hfaaa; + defparam FS_610_add_4_14.INJECT1_0 = "NO"; + defparam FS_610_add_4_14.INJECT1_1 = "NO"; + ORCALUT4 i2_3_lut_4_lut_adj_15 (.A(n2473), .B(n2253), .C(Din_c_5), + .D(n2474), .Z(n2242)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; + defparam i2_3_lut_4_lut_adj_15.init = 16'h4000; + ORCALUT4 n2414_bdd_2_lut (.A(n2414), .B(Ready), .Z(Ready_N_292)) /* synthesis lut_function=(A+(B)) */ ; + defparam n2414_bdd_2_lut.init = 16'heeee; + ORCALUT4 i1_2_lut_adj_16 (.A(nRowColSel_N_34), .B(nRowColSel_N_33), + .Z(n1502)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1_2_lut_adj_16.init = 16'heeee; + ORCALUT4 RCKE_I_0_449_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), + .Z(RCKE_N_132)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[11:55]) + defparam RCKE_I_0_449_4_lut.init = 16'hcfc8; + ORCALUT4 i1_4_lut_adj_17 (.A(n2467), .B(n2481), .C(n13), .D(nRowColSel_N_35), + .Z(nRCS_N_136)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B+!(C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(48[6:16]) + defparam i1_4_lut_adj_17.init = 16'hcfdd; + FD1P3AX IS_FSM__i15 (.D(n726), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(Ready_N_296)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i15.GSR = "ENABLED"; + ORCALUT4 MAin_9__I_0_427_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), + .Z(RA_1_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i1_3_lut.init = 16'hcaca; + ORCALUT4 i1558_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(RCKEEN_N_130)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ; + defparam i1558_2_lut_3_lut.init = 16'h1f1f; + ORCALUT4 RA11_I_54_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_184)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(99[22:51]) + defparam RA11_I_54_3_lut.init = 16'hc6c6; + ORCALUT4 i17_4_lut (.A(n7), .B(n2472), .C(InitReady), .D(n8), .Z(RCLK_c_enable_11)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ; + defparam i17_4_lut.init = 16'hcac0; + ORCALUT4 i1234_4_lut_4_lut (.A(RASr2), .B(InitReady), .C(RCKE_c), + .D(Ready), .Z(n13)) /* synthesis lut_function=(A (B+(D))+!A (C (D))) */ ; + defparam i1234_4_lut_4_lut.init = 16'hfa88; + ORCALUT4 i2_2_lut (.A(FS[8]), .B(n2214), .Z(n7)) /* synthesis lut_function=(!(A+!(B))) */ ; + defparam i2_2_lut.init = 16'h4444; + ORCALUT4 i78_2_lut_rep_24_3_lut (.A(RASr2), .B(InitReady), .C(Ready), + .Z(n2467)) /* synthesis lut_function=(A (B+(C))+!A (C)) */ ; + defparam i78_2_lut_rep_24_3_lut.init = 16'hf8f8; + FD1P3AX IS_FSM__i14 (.D(n727), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n726)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i14.GSR = "ENABLED"; + FD1P3AX IS_FSM__i13 (.D(n728), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n727)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i13.GSR = "ENABLED"; + ORCALUT4 i2_2_lut_3_lut_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_33), + .D(Ready), .Z(n6)) /* synthesis lut_function=(A (B (C)+!B (C+!(D)))+!A (C+!(D))) */ ; + defparam i2_2_lut_3_lut_4_lut.init = 16'hf0f7; + ORCALUT4 i1512_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(58[17:46]) + defparam i1512_2_lut.init = 16'hbbbb; + ORCALUT4 i1_1_lut (.A(nFWE_c), .Z(nFWE_N_5)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam i1_1_lut.init = 16'h5555; + FD1P3AX IS_FSM__i12 (.D(n729), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n728)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i12.GSR = "ENABLED"; + FD1P3AX XOR8MEG_408 (.D(XOR8MEG_N_110), .SP(PHI2_N_120_enable_1), .CK(PHI2_N_120), + .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam XOR8MEG_408.GSR = "ENABLED"; + FD1P3AX n8MEGEN_418 (.D(n8MEGEN_N_91), .SP(RCLK_c_enable_11), .CK(RCLK_c), + .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam n8MEGEN_418.GSR = "ENABLED"; + FD1P3AX LEDEN_419 (.D(n2568), .SP(RCLK_c_enable_12), .CK(RCLK_c), + .Q(LEDEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam LEDEN_419.GSR = "ENABLED"; + PFUMX i16 (.BLUT(n2336), .ALUT(n2337), .C0(nRowColSel_N_35), .Z(n2138)); + FD1P3AX Ready_404 (.D(n2568), .SP(Ready_N_292), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam Ready_404.GSR = "ENABLED"; + FD1P3AX CmdUFMCLK_413 (.D(Din_c_1), .SP(PHI2_N_120_enable_6), .CK(PHI2_N_120), + .Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMCLK_413.GSR = "ENABLED"; + FD1P3AX CmdUFMSDI_414 (.D(Din_c_0), .SP(PHI2_N_120_enable_6), .CK(PHI2_N_120), + .Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMSDI_414.GSR = "ENABLED"; + FD1P3AX Cmdn8MEGEN_410 (.D(Cmdn8MEGEN_N_264), .SP(PHI2_N_120_enable_4), + .CK(PHI2_N_120), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam Cmdn8MEGEN_410.GSR = "ENABLED"; + FD1P3AX CmdSubmitted_411 (.D(n2568), .SP(PHI2_N_120_enable_5), .CK(PHI2_N_120), + .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdSubmitted_411.GSR = "ENABLED"; + FD1P3AX CmdUFMCS_412 (.D(Din_c_2), .SP(PHI2_N_120_enable_6), .CK(PHI2_N_120), + .Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMCS_412.GSR = "ENABLED"; + FD1P3AX IS_FSM__i11 (.D(n730), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n729)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i11.GSR = "ENABLED"; + ORCALUT4 i2060_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ; + defparam i2060_2_lut.init = 16'h7777; + ORCALUT4 i1_2_lut_rep_32 (.A(Din_c_6), .B(Din_c_3), .Z(n2475)) /* synthesis lut_function=(!((B)+!A)) */ ; + defparam i1_2_lut_rep_32.init = 16'h2222; + FD1P3AX IS_FSM__i10 (.D(nRWE_N_177), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n730)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i10.GSR = "ENABLED"; + ORCALUT4 i3_4_lut_adj_18 (.A(n2290), .B(FS[4]), .C(n2322), .D(FS[7]), + .Z(n8)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; + defparam i3_4_lut_adj_18.init = 16'h0004; + ORCALUT4 i886_3_lut (.A(CmdUFMCLK), .B(n1160), .C(InitReady), .Z(UFMCLK_N_224)) /* synthesis lut_function=(A (B+(C))+!A !((C)+!B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(386[12] 409[6]) + defparam i886_3_lut.init = 16'hacac; + FD1P3AX IS_FSM__i9 (.D(n732), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRWE_N_177)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i9.GSR = "ENABLED"; + ORCALUT4 i2_3_lut_4_lut_adj_19 (.A(Din_c_6), .B(Din_c_3), .C(Din_c_2), + .D(MAin_c_0), .Z(n2245)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; + defparam i2_3_lut_4_lut_adj_19.init = 16'h0002; + ORCALUT4 i919_4_lut (.A(FS[4]), .B(n62), .C(n2462), .D(FS[1]), .Z(n1160)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(386[12] 409[6]) + defparam i919_4_lut.init = 16'h3a0a; + ORCALUT4 i2052_4_lut (.A(MAin_c_0), .B(n2460), .C(n14), .D(MAin_c_1), + .Z(PHI2_N_120_enable_7)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C+!(D))))) */ ; + defparam i2052_4_lut.init = 16'h0302; + ORCALUT4 i2_3_lut_adj_20 (.A(n2253), .B(Din_c_4), .C(n13_adj_2), .Z(n14)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; + defparam i2_3_lut_adj_20.init = 16'h2020; + ORCALUT4 i1136_1_lut (.A(nRowColSel_N_34), .Z(n1425)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1136_1_lut.init = 16'h5555; + FD1P3AX IS_FSM__i8 (.D(n733), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n732)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i8.GSR = "ENABLED"; + FD1P3AX IS_FSM__i7 (.D(n734), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n733)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i7.GSR = "ENABLED"; + FD1P3AX IS_FSM__i6 (.D(n735), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n734)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i6.GSR = "ENABLED"; + FD1P3AX IS_FSM__i5 (.D(n736), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n735)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i5.GSR = "ENABLED"; + FD1P3AX IS_FSM__i4 (.D(n737), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n736)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i4.GSR = "ENABLED"; + FD1P3AX IS_FSM__i3 (.D(n738), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n737)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i3.GSR = "ENABLED"; + FD1P3AX IS_FSM__i2 (.D(nRCAS_N_165), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n738)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i2.GSR = "ENABLED"; + FD1P3AX IS_FSM__i1 (.D(nRCS_N_139), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRCAS_N_165)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i1.GSR = "ENABLED"; + FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_N_9), .CD(n2477), .Q(RBA_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RBA__i2.GSR = "ENABLED"; + FD1S3AX FS_610__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i17.GSR = "ENABLED"; + FD1S3AX FS_610__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i16.GSR = "ENABLED"; + FD1S3AX FS_610__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i15.GSR = "ENABLED"; + FD1S3AX FS_610__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i14.GSR = "ENABLED"; + FD1S3AX FS_610__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i13.GSR = "ENABLED"; + FD1S3AX FS_610__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i12.GSR = "ENABLED"; + FD1S3AX FS_610__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i11.GSR = "ENABLED"; + FD1S3AX FS_610__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i10.GSR = "ENABLED"; + FD1S3AX FS_610__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i9.GSR = "ENABLED"; + FD1S3AX FS_610__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i8.GSR = "ENABLED"; + FD1S3AX FS_610__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i7.GSR = "ENABLED"; + FD1S3AX FS_610__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i6.GSR = "ENABLED"; + FD1S3AX FS_610__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i5.GSR = "ENABLED"; + FD1S3AX FS_610__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i4.GSR = "ENABLED"; + FD1S3AX FS_610__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i3.GSR = "ENABLED"; + FD1S3AX FS_610__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i2.GSR = "ENABLED"; + FD1S3AX FS_610__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i1.GSR = "ENABLED"; + FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i7.GSR = "ENABLED"; + ORCALUT4 i3_4_lut_adj_21 (.A(MAin_c_1), .B(n2463), .C(n1326), .D(n15), + .Z(CmdEnable_N_248)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i3_4_lut_adj_21.init = 16'h0800; + FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i6.GSR = "ENABLED"; + FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i5.GSR = "ENABLED"; + FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i4.GSR = "ENABLED"; + FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i3.GSR = "ENABLED"; + FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i2.GSR = "ENABLED"; + FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i1.GSR = "ENABLED"; + FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_N_9), .PD(n2477), .Q(RowA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i9.GSR = "ENABLED"; + FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i8.GSR = "ENABLED"; + FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i7.GSR = "ENABLED"; + FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i6.GSR = "ENABLED"; + FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_N_9), .PD(n2477), .Q(RowA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i5.GSR = "ENABLED"; + FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i4.GSR = "ENABLED"; + FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i3.GSR = "ENABLED"; + FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i2.GSR = "ENABLED"; + FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i1.GSR = "ENABLED"; + FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i7.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_rep_25_3_lut (.A(Din_c_6), .B(Din_c_3), .C(Din_c_5), + .Z(n2468)) /* synthesis lut_function=(!((B+(C))+!A)) */ ; + defparam i1_2_lut_rep_25_3_lut.init = 16'h0202; + ORCALUT4 i5_3_lut_rep_15_4_lut (.A(nFWE_c), .B(n1326), .C(n10), .D(MAin_c_0), + .Z(n2458)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; + defparam i5_3_lut_rep_15_4_lut.init = 16'h1000; + FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i6.GSR = "ENABLED"; + FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i5.GSR = "ENABLED"; + FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i4.GSR = "ENABLED"; + FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i3.GSR = "ENABLED"; + FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i2.GSR = "ENABLED"; + FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i1.GSR = "ENABLED"; + ORCALUT4 FS_6__bdd_4_lut (.A(FS[7]), .B(FS[9]), .C(FS[5]), .D(FS[8]), + .Z(n2451)) /* synthesis lut_function=(!(A (B+(D))+!A (((D)+!C)+!B))) */ ; + defparam FS_6__bdd_4_lut.init = 16'h0062; + BB Dout_pad_6__714 (.I(WRD[6]), .T(n984), .B(RD[6]), .O(Dout_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_5__715 (.I(WRD[5]), .T(n984), .B(RD[5]), .O(Dout_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + ORCALUT4 i1_2_lut_rep_16_3_lut (.A(nFWE_c), .B(n1326), .C(MAin_c_1), + .Z(n2459)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; + defparam i1_2_lut_rep_16_3_lut.init = 16'h1010; + BB Dout_pad_4__716 (.I(WRD[4]), .T(n984), .B(RD[4]), .O(Dout_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_3__717 (.I(WRD[3]), .T(n984), .B(RD[3]), .O(Dout_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_2__718 (.I(WRD[2]), .T(n984), .B(RD[2]), .O(Dout_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + ORCALUT4 i1_2_lut_rep_33 (.A(Din_c_3), .B(Din_c_5), .Z(n2476)) /* synthesis lut_function=(A (B)) */ ; + defparam i1_2_lut_rep_33.init = 16'h8888; + BB Dout_pad_1__719 (.I(WRD[1]), .T(n984), .B(RD[1]), .O(Dout_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_0__720 (.I(WRD[0]), .T(n984), .B(RD[0]), .O(Dout_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + OB Dout_pad_7 (.I(Dout_c), .O(Dout[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_6 (.I(Dout_0), .O(Dout[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_5 (.I(Dout_1), .O(Dout[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_4 (.I(Dout_2), .O(Dout[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_3 (.I(Dout_3), .O(Dout[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_2 (.I(Dout_4), .O(Dout[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_1 (.I(Dout_5), .O(Dout[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_0 (.I(Dout_6), .O(Dout[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB LED_pad (.I(LED_N_84), .O(LED)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) + OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + OB RA_pad_11 (.I(RA_c), .O(RA[11])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_10 (.I(RA_0), .O(RA[10])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_9 (.I(RA_1_9), .O(RA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_8 (.I(RA_1_8), .O(RA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_7 (.I(RA_1_7), .O(RA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_6 (.I(RA_1_6), .O(RA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_5 (.I(RA_1_5), .O(RA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_4 (.I(RA_1_4), .O(RA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_3 (.I(RA_1_3), .O(RA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_2 (.I(RA_1_2), .O(RA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_1 (.I(RA_1_1), .O(RA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_0 (.I(RA_1_0), .O(RA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB nRCS_pad (.I(nRCS_c), .O(nRCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) + OB RCKE_pad (.I(RCKE_c), .O(RCKE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) + OB nRWE_pad (.I(nRWE_c), .O(nRWE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) + OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) + OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) + OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) + OB RDQML_pad (.I(RDQML_c), .O(RDQML)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) + OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) + OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) + OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) + IB PHI2_pad (.I(PHI2), .O(PHI2_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + IB Din_pad_7 (.I(Din[7]), .O(Din_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_6 (.I(Din[6]), .O(Din_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_5 (.I(Din[5]), .O(Din_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_4 (.I(Din[4]), .O(Din_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_3 (.I(Din[3]), .O(Din_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_2 (.I(Din[2]), .O(Din_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_1 (.I(Din[1]), .O(Din_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_0 (.I(Din[0]), .O(Din_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + IB nFWE_pad (.I(nFWE), .O(nFWE_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) + IB RCLK_pad (.I(RCLK), .O(RCLK_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) + ORCALUT4 i1_2_lut_rep_19_4_lut (.A(n2471), .B(n2272), .C(n2470), .D(FS[11]), + .Z(n2462)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_rep_19_4_lut.init = 16'hfeff; + CCU2 FS_610_add_4_2 (.A0(FS[0]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[1]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(GND_net), + .COUT1(n2008), .S0(n95), .S1(n94)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_2.INIT0 = 16'h0555; + defparam FS_610_add_4_2.INIT1 = 16'hfaaa; + defparam FS_610_add_4_2.INJECT1_0 = "NO"; + defparam FS_610_add_4_2.INJECT1_1 = "NO"; + ORCALUT4 i2057_2_lut (.A(nRowColSel_N_32), .B(RASr2), .Z(n1093)) /* synthesis lut_function=(!(A+!(B))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i2057_2_lut.init = 16'h4444; + ORCALUT4 n2454_bdd_3_lut_4_lut (.A(n2461), .B(n2462), .C(InitReady), + .D(CmdUFMSDI), .Z(UFMSDI_N_231)) /* synthesis lut_function=(A (B (C (D))+!B ((D)+!C))+!A (C (D))) */ ; + defparam n2454_bdd_3_lut_4_lut.init = 16'hf202; + FD1P3IX UFMCLK_416 (.D(UFMCLK_N_224), .SP(RCLK_c_enable_24), .CD(n1846), + .CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam UFMCLK_416.GSR = "ENABLED"; + FD1P3AX CmdEnable_405 (.D(CmdEnable_N_248), .SP(PHI2_N_120_enable_7), + .CK(PHI2_N_120), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdEnable_405.GSR = "ENABLED"; + ORCALUT4 i1513_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n984)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1513_2_lut.init = 16'heeee; + ORCALUT4 n1_bdd_4_lut (.A(n1), .B(n1502), .C(nRWE_N_182), .D(nRowColSel_N_35), + .Z(nRWE_N_178)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ; + defparam n1_bdd_4_lut.init = 16'hf0dd; + CCU2 FS_610_add_4_12 (.A0(FS[10]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[11]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2012), + .COUT1(n2013), .S0(n85), .S1(n84)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_12.INIT0 = 16'hfaaa; + defparam FS_610_add_4_12.INIT1 = 16'hfaaa; + defparam FS_610_add_4_12.INJECT1_0 = "NO"; + defparam FS_610_add_4_12.INJECT1_1 = "NO"; + ORCALUT4 i1_2_lut_adj_22 (.A(n62), .B(FS[10]), .Z(RCLK_c_enable_25)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_adj_22.init = 16'h8888; + ORCALUT4 i1209_4_lut_then_4_lut (.A(nRCS_N_139), .B(Ready), .C(nRowColSel_N_35), + .D(nRowColSel_N_34), .Z(n2480)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A (B (C+!(D))+!B (C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(48[6:16]) + defparam i1209_4_lut_then_4_lut.init = 16'h2f23; + ORCALUT4 nRWE_I_0_455_4_lut (.A(n33), .B(nRWE_N_178), .C(Ready), .D(n2208), + .Z(nRWE_N_171)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRWE_I_0_455_4_lut.init = 16'hcfc5; + ORCALUT4 nRWE_I_50_1_lut (.A(nRWE_N_177), .Z(nRWE_N_176)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(255[14] 262[8]) + defparam nRWE_I_50_1_lut.init = 16'h5555; + CCU2 FS_610_add_4_4 (.A0(FS[2]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[3]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2008), + .COUT1(n2009), .S0(n93), .S1(n92)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_4.INIT0 = 16'hfaaa; + defparam FS_610_add_4_4.INIT1 = 16'hfaaa; + defparam FS_610_add_4_4.INJECT1_0 = "NO"; + defparam FS_610_add_4_4.INJECT1_1 = "NO"; + CCU2 FS_610_add_4_10 (.A0(FS[8]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[9]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2011), + .COUT1(n2012), .S0(n87), .S1(n86)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_10.INIT0 = 16'hfaaa; + defparam FS_610_add_4_10.INIT1 = 16'hfaaa; + defparam FS_610_add_4_10.INJECT1_0 = "NO"; + defparam FS_610_add_4_10.INJECT1_1 = "NO"; + ORCALUT4 i1_2_lut_adj_23 (.A(nRowColSel_N_33), .B(CASr2), .Z(n11)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(48[6:16]) + defparam i1_2_lut_adj_23.init = 16'hbbbb; + CCU2 FS_610_add_4_18 (.A0(FS[16]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[17]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2015), + .S0(n79), .S1(n78)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_18.INIT0 = 16'hfaaa; + defparam FS_610_add_4_18.INIT1 = 16'hfaaa; + defparam FS_610_add_4_18.INJECT1_0 = "NO"; + defparam FS_610_add_4_18.INJECT1_1 = "NO"; + ORCALUT4 i5_3_lut_rep_21_4_lut (.A(FS[16]), .B(FS[14]), .C(n2272), + .D(n2471), .Z(n2464)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i5_3_lut_rep_21_4_lut.init = 16'hfffe; + ORCALUT4 i1137_1_lut (.A(nRowColSel_N_35), .Z(n1426)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1137_1_lut.init = 16'h5555; + ORCALUT4 RASr2_I_0_1_lut (.A(RASr2), .Z(RASr2_N_63)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46]) + defparam RASr2_I_0_1_lut.init = 16'h5555; + ORCALUT4 n2452_bdd_2_lut_rep_18_3_lut (.A(n2451), .B(FS[6]), .C(FS[10]), + .Z(n2461)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; + defparam n2452_bdd_2_lut_rep_18_3_lut.init = 16'h0808; + ORCALUT4 i2_3_lut_4_lut_adj_24 (.A(Din_c_5), .B(n2475), .C(MAin_c_0), + .D(ADSubmitted), .Z(n2227)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i2_3_lut_4_lut_adj_24.init = 16'h0004; + ORCALUT4 i1_2_lut_adj_25 (.A(nRowColSel_N_32), .B(nRowColSel_N_33), + .Z(n1503)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1_2_lut_adj_25.init = 16'heeee; + ORCALUT4 i5_4_lut (.A(FS[15]), .B(FS[13]), .C(FS[16]), .D(FS[11]), + .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i5_4_lut.init = 16'h8000; + ORCALUT4 i1_2_lut_adj_26 (.A(nRCAS_N_165), .B(nRWE_N_177), .Z(n33)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1_2_lut_adj_26.init = 16'heeee; + ORCALUT4 i1259_3_lut (.A(InitReady), .B(RCKEEN_N_122), .C(Ready), + .Z(RCKEEN_N_121)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(84[6:11]) + defparam i1259_3_lut.init = 16'hcaca; + FD1P3AX InitReady_394 (.D(n2568), .SP(RCLK_c_enable_25), .CK(RCLK_c), + .Q(InitReady)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(134[9] 138[5]) + defparam InitReady_394.GSR = "ENABLED"; + ORCALUT4 i11_3_lut (.A(n62), .B(n1417), .C(InitReady), .Z(n2164)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(21[6:11]) + defparam i11_3_lut.init = 16'hcaca; + PFUMX RCKEEN_I_0_445 (.BLUT(RCKEEN_N_123), .ALUT(RCKEEN_N_130), .C0(nRowColSel_N_35), + .Z(RCKEEN_N_122)); + ORCALUT4 i1129_3_lut (.A(nUFMCS_c), .B(CmdUFMCS), .C(n2472), .Z(n1417)) /* synthesis lut_function=(!(A (B (C))+!A (B+!(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam i1129_3_lut.init = 16'h3a3a; + FD1S3IX S_FSM_i2 (.D(n1093), .CK(RCLK_c), .CD(n1426), .Q(nRowColSel_N_34)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i2.GSR = "ENABLED"; + INV i2134 (.A(nCCAS_c), .Z(nCCAS_N_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + ORCALUT4 i1988_2_lut (.A(C1Submitted), .B(Din_c_6), .Z(n2284)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1988_2_lut.init = 16'heeee; + PFUMX i26 (.BLUT(n2227), .ALUT(n2257), .C0(Din_c_2), .Z(n13_adj_2)); + INV i2135 (.A(nCRAS_c), .Z(nCRAS_N_9)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + VLO i1 (.Z(GND_net)); + TSALL TSALL_INST (.TSALL(GND_net)); + ORCALUT4 i2_3_lut_adj_27 (.A(n2208), .B(Ready), .C(nRCAS_N_165), .Z(n2209)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i2_3_lut_adj_27.init = 16'hfefe; + PUR PUR_INST (.PUR(VCC_net)); + defparam PUR_INST.RST_PULSE = 1; + ORCALUT4 i2032_2_lut_3_lut_4_lut (.A(FS[17]), .B(FS[12]), .C(FS[14]), + .D(FS[16]), .Z(n2328)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i2032_2_lut_3_lut_4_lut.init = 16'hfffe; + ORCALUT4 i1976_2_lut (.A(FS[13]), .B(FS[15]), .Z(n2272)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1976_2_lut.init = 16'heeee; + ORCALUT4 m1_lut (.Z(n2568)) /* synthesis lut_function=1, syn_instantiated=1 */ ; + defparam m1_lut.init = 16'hffff; + PFUMX i2099 (.BLUT(n2479), .ALUT(n2480), .C0(n15_adj_1), .Z(n2481)); + PFUMX i26_adj_28 (.BLUT(n2245), .ALUT(n2243), .C0(Din_c_5), .Z(n15)); + +endmodule +// +// Verilog Description of module TSALL +// module not written out since it is a black-box. +// + +// +// Verilog Description of module PUR +// module not written out since it is a black-box. +// + diff --git a/CPLD/LCMXO256C/impl1/automake.log b/CPLD/LCMXO256C/impl1/automake.log new file mode 100644 index 0000000..0229264 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/automake.log @@ -0,0 +1,1026 @@ + +synthesis -f "RAM2GS_LCMXO256C_impl1_lattice.synproj" +synthesis: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:20 2023 + + +Command Line: synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml + + +Synthesis options: +The -a option is MachXO. +The -s option is 3. +The -t option is TQFP100. +The -d option is LCMXO256C. +Using package TQFP100. +Using performance grade 3. + + +########################################################## + +### Lattice Family : MachXO + +### Device : LCMXO256C + +### Package : TQFP100 + +### Speed : 3 + +########################################################## + + + + +Optimization goal = Balanced +Top-level module name = RAM2GS. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added) +-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1 (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added) +Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v +NGD file = RAM2GS_LCMXO256C_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 +Compile design. +Compile Design Begin +Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 +Top module name (Verilog): RAM2GS + + + + +Last elaborated design is RAM2GS() +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Top-level module name = RAM2GS. + +original encoding -> new encoding (one-hot encoding) + + 0000 -> 0000000000000001 + + 0001 -> 0000000000000010 + + 0010 -> 0000000000000100 + + 0011 -> 0000000000001000 + + 0100 -> 0000000000010000 + + 0101 -> 0000000000100000 + + 0110 -> 0000000001000000 + + 0111 -> 0000000010000000 + + 1000 -> 0000000100000000 + + 1001 -> 0000001000000000 + + 1010 -> 0000010000000000 + + 1011 -> 0000100000000000 + + 1100 -> 0001000000000000 + + 1101 -> 0010000000000000 + + 1110 -> 0100000000000000 + + 1111 -> 1000000000000000 + + +original encoding -> new encoding (one-hot encoding) + + 00 -> 0001 + + 01 -> 0010 + + 10 -> 0100 + + 11 -> 1000 + + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. + +Applying 200.000000 MHz constraint to all clocks + + +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 318 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO256C_impl1.ngd. + +################### Begin Area Report (RAM2GS)###################### +Number of register bits => 102 of 490 (20 % ) +BB => 8 +CCU2 => 9 +FD1P3AX => 28 +FD1P3AY => 3 +FD1P3IX => 2 +FD1S3AX => 47 +FD1S3AY => 1 +FD1S3IX => 16 +FD1S3JX => 5 +GSR => 1 +IB => 26 +INV => 3 +OB => 33 +ORCALUT4 => 127 +PFUMX => 6 +################### End Area Report ################## + +################### Begin BlackBox Report ###################### +TSALL => 1 +################### End BlackBox Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 4 + Net : RCLK_c, loads : 62 + Net : PHI2_c, loads : 11 + Net : nCCAS_c, loads : 2 + Net : nCRAS_c, loads : 2 +Clock Enable Nets +Number of Clock Enables: 13 +Top 10 highest fanout Clock Enables: + Net : RCLK_c_enable_23, loads : 16 + Net : RCLK_c_enable_4, loads : 3 + Net : PHI2_N_120_enable_6, loads : 3 + Net : RCLK_c_enable_24, loads : 2 + Net : RCLK_c_enable_12, loads : 1 + Net : PHI2_N_120_enable_1, loads : 1 + Net : PHI2_N_120_enable_4, loads : 1 + Net : RCLK_c_enable_3, loads : 1 + Net : PHI2_N_120_enable_5, loads : 1 + Net : RCLK_c_enable_11, loads : 1 +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : InitReady, loads : 17 + Net : Ready, loads : 17 + Net : RCLK_c_enable_23, loads : 16 + Net : nCRAS_N_9, loads : 15 + Net : RASr2, loads : 13 + Net : nRowColSel, loads : 13 + Net : n2477, loads : 13 + Net : MAin_c_0, loads : 12 + Net : nRowColSel_N_35, loads : 12 + Net : Din_c_6, loads : 11 +################### End Clock Report ################## + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 200.000 MHz| 45.147 MHz| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 200.000 MHz| 106.792 MHz| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + + +Peak Memory Usage: 50.672 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 0.516 secs +-------------------------------------------------------------- + +map -a "MachXO" -p LCMXO256C -t TQFP100 -s 3 -oc Commercial "RAM2GS_LCMXO256C_impl1.ngd" -o "RAM2GS_LCMXO256C_impl1_map.ncd" -pr "RAM2GS_LCMXO256C_impl1.prf" -mp "RAM2GS_LCMXO256C_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.lpf" -c 0 +map: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + Process the file: RAM2GS_LCMXO256C_impl1.ngd + Picdevice="LCMXO256C" + + Pictype="TQFP100" + + Picspeed=3 + + Remove unused logic + + Do not produce over sized NCDs. + +Part used: LCMXO256CTQFP100, Performance used: 3. + +Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Running general design DRC... + +Removing unused logic... + +Optimizing... + + + + +Design Summary: + Number of PFU registers: 102 out of 256 (40%) + Number of SLICEs: 71 out of 128 (55%) + SLICEs as Logic/ROM: 71 out of 128 (55%) + SLICEs as RAM: 0 out of 64 (0%) + SLICEs as Carry: 9 out of 128 (7%) + Number of LUT4s: 142 out of 256 (55%) + Number used as logic LUTs: 124 + Number used as distributed RAM: 0 + Number used as ripple logic: 18 + Number used as shift registers: 0 + Number of external PIOs: 67 out of 78 (86%) + Number of GSRs: 0 out of 1 (0%) + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + Number of TSALL: 0 out of 1 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. + Number of clocks: 4 + Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Number of Clock Enables: 13 + Net PHI2_N_120_enable_4: 1 loads, 1 LSLICEs + Net RCLK_c_enable_4: 3 loads, 3 LSLICEs + Net RCLK_c_enable_23: 8 loads, 8 LSLICEs + Net RCLK_c_enable_12: 1 loads, 1 LSLICEs + Net RCLK_c_enable_3: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_5: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_6: 2 loads, 2 LSLICEs + Net RCLK_c_enable_24: 2 loads, 2 LSLICEs + Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs + Net Ready_N_292: 1 loads, 1 LSLICEs + Net RCLK_c_enable_11: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_25: 1 loads, 1 LSLICEs + Number of LSRs: 9 + Net RASr2: 1 loads, 1 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net C1Submitted_N_237: 2 loads, 2 LSLICEs + Net n2469: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net n1846: 2 loads, 2 LSLICEs + Net LEDEN_N_82: 1 loads, 1 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Net nRWE_N_177: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 23 loads + Net InitReady: 17 loads + Net RASr2: 14 loads + Net nRowColSel: 13 loads + Net MAin_c_0: 12 loads + Net nRowColSel_N_35: 12 loads + Net Din_c_3: 11 loads + Net Din_c_6: 11 loads + Net MAin_c_1: 11 loads + Net Din_c_4: 10 loads + + + Number of warnings: 0 + Number of errors: 0 + + + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 29 MB + +Dumping design to file RAM2GS_LCMXO256C_impl1_map.ncd. + +ncd2vdb "RAM2GS_LCMXO256C_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO256C_impl1_map.vdb" + +Loading device for application ncd2vdb from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. + +ncd2eqn "RAM2GS_LCMXO256C_impl1_map.ncd" +ncd2eqn: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Start loading RAM2GS_LCMXO256C_impl1_map.ncd. + +Loading design for application ncd2eqn from file RAM2GS_LCMXO256C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application ncd2eqn from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Finish loading RAM2GS_LCMXO256C_impl1_map.ncd. +ncd2eqn runs successfully. + +trce -f "RAM2GS_LCMXO256C_impl1.mt" -o "RAM2GS_LCMXO256C_impl1.tw1" "RAM2GS_LCMXO256C_impl1_map.ncd" "RAM2GS_LCMXO256C_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:21 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1_map.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,3 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 310 Score: 1346529 +Cumulative negative slack: 874289 + +Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:21 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1_map.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 310 (setup), 0 (hold) +Score: 1346529 (setup), 0 (hold) +Cumulative negative slack: 874289 (874289+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 32 MB + + +ldbanno "RAM2GS_LCMXO256C_impl1_map.ncd" -n Verilog -o "RAM2GS_LCMXO256C_impl1_mapvo.vo" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a Verilog netlist using the orca library type based on the RAM2GS_LCMXO256C_impl1_map design file. + + +Loading design for application ldbanno from file RAM2GS_LCMXO256C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application ldbanno from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Converting design RAM2GS_LCMXO256C_impl1_map.ncd into .ldb format. +Writing Verilog netlist to file RAM2GS_LCMXO256C_impl1_mapvo.vo +Writing SDF timing to file RAM2GS_LCMXO256C_impl1_mapvo.sdf + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 29 MB + +ldbanno "RAM2GS_LCMXO256C_impl1_map.ncd" -n VHDL -o "RAM2GS_LCMXO256C_impl1_mapvho.vho" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a VHDL netlist using the orca library type based on the RAM2GS_LCMXO256C_impl1_map design file. + + +Loading design for application ldbanno from file RAM2GS_LCMXO256C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application ldbanno from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Converting design RAM2GS_LCMXO256C_impl1_map.ncd into .ldb format. +Writing VHDL netlist to file RAM2GS_LCMXO256C_impl1_mapvho.vho +Writing SDF timing to file RAM2GS_LCMXO256C_impl1_mapvho.sdf + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 29 MB + +mpartrce -p "RAM2GS_LCMXO256C_impl1.p2t" -f "RAM2GS_LCMXO256C_impl1.p3t" -tf "RAM2GS_LCMXO256C_impl1.pt" "RAM2GS_LCMXO256C_impl1_map.ncd" "RAM2GS_LCMXO256C_impl1.ncd" + +---- MParTrce Tool ---- +Removing old design directory at request of -rem command line option to this program. +Running par. Please wait . . . + +Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd" +Tue Aug 15 05:03:23 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf +Preference file: RAM2GS_LCMXO256C_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67/79 84% used + 67/78 85% bonded + SLICE 71/128 55% used + + + +Number of Signals: 262 +Number of Connections: 662 + +Pin Constraint Summary: + 67 out of 67 pins locked (100% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +........ +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +.............. +Placer score = 831129. +Finished Placer Phase 1. REAL time: 5 secs + +Starting Placer Phase 2. +. +Placer score = 828350 +Finished Placer Phase 2. REAL time: 5 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 1 out of 4 (25%) + General PIO: 1 out of 80 (1%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 4 (50%) + SECONDARY: 1 out of 4 (25%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 out of 79 (84.8%) PIO sites used. + 67 out of 78 (85.9%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+------------+------------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | ++----------+----------------+------------+------------+------------+ +| 0 | 36 / 41 ( 87%) | 3.3V | - | - | +| 1 | 31 / 37 ( 83%) | 3.3V | - | - | ++----------+----------------+------------+------------+------------+ + +Total placer CPU time: 4 secs + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + +0 connections routed; 662 unrouted. +Starting router resource preassignment + + + + + +Completed router resource preassignment. Real time: 5 secs + +Start NBR router at 05:03:28 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:28 08/15/23 + +Start NBR section for initial routing at 05:03:28 08/15/23 +Level 1, iteration 1 +0(0.00%) conflict; 563(85.05%) untouched conns; 712361 (nbr) score; +Estimated worst slack/total negative slack: -9.968ns/-712.361ns; real time: 5 secs +Level 2, iteration 1 +3(0.02%) conflicts; 494(74.62%) untouched conns; 697746 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-697.746ns; real time: 5 secs +Level 3, iteration 1 +6(0.05%) conflicts; 255(38.52%) untouched conns; 756550 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-756.550ns; real time: 5 secs +Level 4, iteration 1 +17(0.14%) conflicts; 0(0.00%) untouched conn; 761255 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-761.256ns; real time: 5 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:28 08/15/23 +Level 4, iteration 1 +12(0.10%) conflicts; 0(0.00%) untouched conn; 765605 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-765.606ns; real time: 5 secs +Level 4, iteration 2 +6(0.05%) conflicts; 0(0.00%) untouched conn; 766423 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.424ns; real time: 5 secs +Level 4, iteration 3 +3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs +Level 4, iteration 4 +3(0.02%) conflicts; 0(0.00%) untouched conn; 769148 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-769.149ns; real time: 5 secs +Level 4, iteration 5 +3(0.02%) conflicts; 0(0.00%) untouched conn; 766523 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs +Level 4, iteration 6 +1(0.01%) conflict; 0(0.00%) untouched conn; 766523 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-766.524ns; real time: 5 secs +Level 4, iteration 7 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 8 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 9 +1(0.01%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs +Level 4, iteration 10 +0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 772930 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-772.930ns; real time: 6 secs + +Start NBR section for re-routing at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 768048 (nbr) score; +Estimated worst slack/total negative slack: -10.044ns/-768.049ns; real time: 6 secs + +Start NBR section for post-routing at 05:03:29 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 256 (38.67%) + Estimated worst slack : -10.044ns + Timing score : 913247 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + + + +Total CPU time 5 secs +Total REAL time: 6 secs +Completely routed. +End of route. 662 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 913247 + +Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -10.044 +PAR_SUMMARY::Timing score> = 913.247 +PAR_SUMMARY::Worst slack> = 0.273 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 5 secs +Total REAL time to completion: 6 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Exiting par with exit code 0 +Exiting mpartrce with exit code 0 + +trce -f "RAM2GS_LCMXO256C_impl1.pt" -o "RAM2GS_LCMXO256C_impl1.twr" "RAM2GS_LCMXO256C_impl1.ncd" "RAM2GS_LCMXO256C_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:29 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,3 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 326 Score: 913247 +Cumulative negative slack: 638389 + +Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:29 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO256C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf +Design file: ram2gs_lcmxo256c_impl1.ncd +Preference file: ram2gs_lcmxo256c_impl1.prf +Device,speed: LCMXO256C,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 489 paths, 2 nets, and 414 connections (62.54% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 326 (setup), 0 (hold) +Score: 913247 (setup), 0 (hold) +Cumulative negative slack: 638389 (638389+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 31 MB + + +iotiming "RAM2GS_LCMXO256C_impl1.ncd" "RAM2GS_LCMXO256C_impl1.prf" +I/O Timing Report: +: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application iotiming from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Running Performance Grade: 3 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 4 +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Running Performance Grade: 4 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Running Performance Grade: 5 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: M +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Running Performance Grade: M +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... +Done. + +tmcheck -par "RAM2GS_LCMXO256C_impl1.par" + +bitgen -w "RAM2GS_LCMXO256C_impl1.ncd" -f "RAM2GS_LCMXO256C_impl1.t2b" "RAM2GS_LCMXO256C_impl1.prf" + + +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + + +Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 3 +Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2GS_LCMXO256C_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| ES | No** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... +Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit". +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 44 MB + +ddtcmd -dev LCMXO256C-XXT100 -if "RAM2GS_LCMXO256C_impl1.bit" -oft -jed -of "RAM2GS_LCMXO256C_impl1.jed" -comment "RAM2GS_LCMXO256C_impl1.alt" +Lattice Diamond Deployment Tool 3.12 Command Line + +Loading Programmer Device Database... + +Generating JED..... +Device Name: LCMXO256C-XXT100 +Reading Input File: RAM2GS_LCMXO256C_impl1.bit +Output File: RAM2GS_LCMXO256C_impl1.jed +Comment file RAM2GS_LCMXO256C_impl1.alt. +Generating JEDEC..... +File RAM2GS_LCMXO256C_impl1.jed generated successfully. +Lattice Diamond Deployment Tool has exited successfully. + diff --git a/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html new file mode 100644 index 0000000..df264d3 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html @@ -0,0 +1,9 @@ + 
    Setting log file to 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v'
+(VERI-1482) Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-411,10) (VERI-9000) elaborating module 'RAM2GS'
+Done: design load finished with (0) errors, and (0) warnings
+
+
    \ No newline at end of file diff --git a/CPLD/LCMXO256C/impl1/impl1.xcf b/CPLD/LCMXO256C/impl1/impl1.xcf new file mode 100644 index 0000000..19089d7 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/impl1.xcf @@ -0,0 +1,50 @@ + + + + + + JTAG + + + 1 + Lattice + MachXO + LCMXO256C + 0x01281043 + All + LCMXO256C + + 8 + 11111111 + 1 + 0 + + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.jed + 08/15/23 04:29:43 + 0xF26B + FLASH Erase,Program,Verify + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB + EzUSB-0 + \\?\usb#vid_1134&amp;pid_8001#5&amp;887acb0&amp;0&amp;13# + + diff --git a/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior b/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior new file mode 100644 index 0000000..83e2eca --- /dev/null +++ b/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1.ior @@ -0,0 +1,138 @@ +Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 4 +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO256C +Package: TQFP100 +Performance: M +Package Status: Final Version 1.19. +Performance Hardware Data Status: Version 1.124. +// Design: RAM2GS +// Package: TQFP100 +// ncd File: ram2gs_lcmxo256c_impl1.ncd +// Version: Diamond (64-bit) 3.12.1.454 +// Written on Tue Aug 15 05:03:30 2023 +// M: Minimum Performance Grade +// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml + +I/O Timing Report (All units are in ns) + +Worst Case Results across Performance Grades (M, 5, 4, 3): + +// Input Setup and Hold Times + +Port Clock Edge Setup Performance_Grade Hold Performance_Grade +---------------------------------------------------------------------- +CROW[0] nCRAS F -0.006 M 1.907 3 +CROW[1] nCRAS F -0.006 M 1.907 3 +Din[0] PHI2 F 5.992 3 2.081 3 +Din[0] nCCAS F 1.591 3 -0.045 M +Din[1] PHI2 F 5.388 3 2.863 3 +Din[1] nCCAS F 0.231 3 0.973 3 +Din[2] PHI2 F 4.913 3 2.842 3 +Din[2] nCCAS F 0.265 3 1.112 3 +Din[3] PHI2 F 6.776 3 2.065 3 +Din[3] nCCAS F 0.702 3 0.725 3 +Din[4] PHI2 F 4.191 3 1.807 3 +Din[4] nCCAS F 1.107 3 0.235 3 +Din[5] PHI2 F 7.709 3 0.737 3 +Din[5] nCCAS F 1.192 3 0.184 3 +Din[6] PHI2 F 6.617 3 1.159 3 +Din[6] nCCAS F 0.904 3 0.149 3 +Din[7] PHI2 F 6.864 3 1.300 3 +Din[7] nCCAS F 0.531 3 0.451 3 +MAin[0] PHI2 F 4.802 3 1.029 3 +MAin[0] nCRAS F 1.511 3 0.599 3 +MAin[1] PHI2 F 4.513 3 1.653 3 +MAin[1] nCRAS F 0.340 3 1.609 3 +MAin[2] PHI2 F 4.241 3 1.193 3 +MAin[2] nCRAS F 1.248 3 0.814 3 +MAin[3] PHI2 F 6.748 3 -0.221 M +MAin[3] nCRAS F 0.375 3 1.589 3 +MAin[4] PHI2 F 7.111 3 -0.295 M +MAin[4] nCRAS F -0.038 M 2.031 3 +MAin[5] PHI2 F 4.083 3 1.319 3 +MAin[5] nCRAS F -0.126 M 2.320 3 +MAin[6] PHI2 F 8.738 3 -0.639 M +MAin[6] nCRAS F 0.505 3 1.464 3 +MAin[7] PHI2 F 7.566 3 -0.400 M +MAin[7] nCRAS F 0.390 3 1.577 3 +MAin[8] nCRAS F -0.017 M 1.932 3 +MAin[9] nCRAS F 1.390 3 0.679 3 +PHI2 RCLK R 4.721 3 -0.539 M +UFMSDO RCLK R 2.307 3 -0.173 M +nCCAS RCLK R 3.513 3 -0.441 M +nCCAS nCRAS F 1.800 3 0.388 3 +nCRAS RCLK R 1.107 3 0.266 3 +nFWE PHI2 F 4.160 3 1.763 3 +nFWE nCRAS F 0.864 3 1.164 3 + + +// Clock to Output Delay + +Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade +------------------------------------------------------------------------ +LED RCLK R 7.020 3 1.411 M +LED nCRAS F 10.053 3 2.020 M +RA[0] RCLK R 8.511 3 1.707 M +RA[0] nCRAS F 10.448 3 2.067 M +RA[10] RCLK R 7.422 3 1.486 M +RA[11] PHI2 R 8.233 3 1.633 M +RA[1] RCLK R 8.292 3 1.649 M +RA[1] nCRAS F 10.175 3 2.009 M +RA[2] RCLK R 8.708 3 1.746 M +RA[2] nCRAS F 10.512 3 2.079 M +RA[3] RCLK R 6.982 3 1.404 M +RA[3] nCRAS F 8.753 3 1.739 M +RA[4] RCLK R 6.982 3 1.404 M +RA[4] nCRAS F 9.764 3 1.953 M +RA[5] RCLK R 6.982 3 1.404 M +RA[5] nCRAS F 10.635 3 2.140 M +RA[6] RCLK R 9.127 3 1.839 M +RA[6] nCRAS F 10.861 3 2.160 M +RA[7] RCLK R 8.287 3 1.659 M +RA[7] nCRAS F 10.995 3 2.202 M +RA[8] RCLK R 8.834 3 1.776 M +RA[8] nCRAS F 10.930 3 2.181 M +RA[9] RCLK R 6.729 3 1.353 M +RA[9] nCRAS F 10.423 3 2.088 M +RBA[0] nCRAS F 7.746 3 1.538 M +RBA[1] nCRAS F 9.473 3 1.887 M +RCKE RCLK R 8.348 3 1.695 M +RDQMH RCLK R 7.433 3 1.503 M +RDQML RCLK R 9.061 3 1.821 M +RD[0] nCCAS F 6.791 3 1.468 M +RD[1] nCCAS F 7.502 3 1.596 M +RD[2] nCCAS F 9.015 3 1.924 M +RD[3] nCCAS F 8.919 3 1.901 M +RD[4] nCCAS F 7.500 3 1.596 M +RD[5] nCCAS F 6.791 3 1.468 M +RD[6] nCCAS F 7.950 3 1.703 M +RD[7] nCCAS F 7.871 3 1.681 M +UFMCLK RCLK R 7.767 3 1.567 M +UFMSDI RCLK R 5.675 3 1.141 M +nRCAS RCLK R 6.518 3 1.300 M +nRCS RCLK R 5.675 3 1.141 M +nRRAS RCLK R 7.469 3 1.503 M +nRWE RCLK R 5.675 3 1.141 M +nUFMCS RCLK R 7.873 3 1.593 M +WARNING: you must also run trce with hold speed: 3 +WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd b/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd new file mode 100644 index 0000000..e83757e --- /dev/null +++ b/CPLD/LCMXO256C/impl1/ram2gs_lcmxo256c_impl1_trce.asd @@ -0,0 +1,13 @@ +[ActiveSupport TRCE] +; Setup Analysis +Fmax_0 = 129.769 MHz (283.768 MHz); +Fmax_1 = 54.431 MHz (120.077 MHz); +Failed = 2 (Total 2); +Clock_ports = 4; +Clock_nets = 4; +; Hold Analysis +Fmax_0 = 0.273 ns (0.000 ns); +Fmax_1 = 0.361 ns (0.000 ns); +Failed = 0 (Total 2); +Clock_ports = 4; +Clock_nets = 4; diff --git a/CPLD/LCMXO256C/impl1/synthesis.log b/CPLD/LCMXO256C/impl1/synthesis.log new file mode 100644 index 0000000..0788bf8 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/synthesis.log @@ -0,0 +1,238 @@ +synthesis: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:20 2023 + + +Command Line: synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml + +Synthesis options: +The -a option is MachXO. +The -s option is 3. +The -t option is TQFP100. +The -d option is LCMXO256C. +Using package TQFP100. +Using performance grade 3. + + +########################################################## + +### Lattice Family : MachXO + +### Device : LCMXO256C + +### Package : TQFP100 + +### Speed : 3 + +########################################################## + + + +INFO - synthesis: User-Selected Strategy Settings +Optimization goal = Balanced +Top-level module name = RAM2GS. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added) +-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1 (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added) +Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v +NGD file = RAM2GS_LCMXO256C_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 +Compile design. +Compile Design Begin +Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 +Top module name (Verilog): RAM2GS +INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209 +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.19. +Top-level module name = RAM2GS. +INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding +original encoding -> new encoding (one-hot encoding) + + 0000 -> 0000000000000001 + + 0001 -> 0000000000000010 + + 0010 -> 0000000000000100 + + 0011 -> 0000000000001000 + + 0100 -> 0000000000010000 + + 0101 -> 0000000000100000 + + 0110 -> 0000000001000000 + + 0111 -> 0000000010000000 + + 1000 -> 0000000100000000 + + 1001 -> 0000001000000000 + + 1010 -> 0000010000000000 + + 1011 -> 0000100000000000 + + 1100 -> 0001000000000000 + + 1101 -> 0010000000000000 + + 1110 -> 0100000000000000 + + 1111 -> 1000000000000000 + +INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding +original encoding -> new encoding (one-hot encoding) + + 00 -> 0001 + + 01 -> 0010 + + 10 -> 0100 + + 11 -> 1000 + + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. +WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored. +Applying 200.000000 MHz constraint to all clocks + +WARNING - synthesis: No user .sdc file. +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO256C_impl1.ngd. + +################### Begin Area Report (RAM2GS)###################### +Number of register bits => 102 of 490 (20 % ) +BB => 8 +CCU2 => 9 +FD1P3AX => 28 +FD1P3AY => 3 +FD1P3IX => 2 +FD1S3AX => 47 +FD1S3AY => 1 +FD1S3IX => 16 +FD1S3JX => 5 +GSR => 1 +IB => 26 +INV => 3 +OB => 33 +ORCALUT4 => 127 +PFUMX => 6 +################### End Area Report ################## + +################### Begin BlackBox Report ###################### +TSALL => 1 +################### End BlackBox Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 4 + Net : RCLK_c, loads : 62 + Net : PHI2_c, loads : 11 + Net : nCCAS_c, loads : 2 + Net : nCRAS_c, loads : 2 +Clock Enable Nets +Number of Clock Enables: 13 +Top 10 highest fanout Clock Enables: + Net : RCLK_c_enable_23, loads : 16 + Net : RCLK_c_enable_4, loads : 3 + Net : PHI2_N_120_enable_6, loads : 3 + Net : RCLK_c_enable_24, loads : 2 + Net : RCLK_c_enable_12, loads : 1 + Net : PHI2_N_120_enable_1, loads : 1 + Net : PHI2_N_120_enable_4, loads : 1 + Net : RCLK_c_enable_3, loads : 1 + Net : PHI2_N_120_enable_5, loads : 1 + Net : RCLK_c_enable_11, loads : 1 +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : InitReady, loads : 17 + Net : Ready, loads : 17 + Net : RCLK_c_enable_23, loads : 16 + Net : nCRAS_N_9, loads : 15 + Net : RASr2, loads : 13 + Net : nRowColSel, loads : 13 + Net : n2477, loads : 13 + Net : MAin_c_0, loads : 12 + Net : nRowColSel_N_35, loads : 12 + Net : Din_c_6, loads : 11 +################### End Clock Report ################## + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 200.000 MHz| 45.147 MHz| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 200.000 MHz| 106.792 MHz| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + + +Peak Memory Usage: 50.672 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 0.516 secs +-------------------------------------------------------------- diff --git a/CPLD/LCMXO256C/impl1/synthesis_lse.html b/CPLD/LCMXO256C/impl1/synthesis_lse.html new file mode 100644 index 0000000..110b727 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/synthesis_lse.html @@ -0,0 +1,303 @@ + +Synthesis and Ngdbuild Report + + +
    Synthesis and Ngdbuild  Report
+synthesis:  version Diamond (64-bit) 3.12.1.454
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:20 2023
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/promote.xml 
+
+Synthesis options:
+The -a option is MachXO.
+The -s option is 3.
+The -t option is TQFP100.
+The -d option is LCMXO256C.
+Using package TQFP100.
+Using performance grade 3.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO
+
+### Device  : LCMXO256C
+
+### Package : TQFP100
+
+### Speed   : 3
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C/impl1 (searchpath added)
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO256C (searchpath added)
+Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
+NGD file = RAM2GS_LCMXO256C_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.19.
+Top-level module name = RAM2GS.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO256C_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 102 of 490 (20 % )
+BB => 8
+CCU2 => 9
+FD1P3AX => 28
+FD1P3AY => 3
+FD1P3IX => 2
+FD1S3AX => 47
+FD1S3AY => 1
+FD1S3IX => 16
+FD1S3JX => 5
+GSR => 1
+IB => 26
+INV => 3
+OB => 33
+ORCALUT4 => 127
+PFUMX => 6
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 4
+  Net : RCLK_c, loads : 62
+  Net : PHI2_c, loads : 11
+  Net : nCCAS_c, loads : 2
+  Net : nCRAS_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 13
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RCLK_c_enable_4, loads : 3
+  Net : PHI2_N_120_enable_6, loads : 3
+  Net : RCLK_c_enable_24, loads : 2
+  Net : RCLK_c_enable_12, loads : 1
+  Net : PHI2_N_120_enable_1, loads : 1
+  Net : PHI2_N_120_enable_4, loads : 1
+  Net : RCLK_c_enable_3, loads : 1
+  Net : PHI2_N_120_enable_5, loads : 1
+  Net : RCLK_c_enable_11, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : InitReady, loads : 17
+  Net : Ready, loads : 17
+  Net : RCLK_c_enable_23, loads : 16
+  Net : nCRAS_N_9, loads : 15
+  Net : RASr2, loads : 13
+  Net : nRowColSel, loads : 13
+  Net : n2477, loads : 13
+  Net : MAin_c_0, loads : 12
+  Net : nRowColSel_N_35, loads : 12
+  Net : Din_c_6, loads : 11
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |  200.000 MHz|   45.147 MHz|     6 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|  106.792 MHz|     5 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 50.672  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.516  secs
+--------------------------------------------------------------
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO256C/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO256C/impl1/xxx_lse_cp_file_list new file mode 100644 index 0000000..1c1a02c --- /dev/null +++ b/CPLD/LCMXO256C/impl1/xxx_lse_cp_file_list @@ -0,0 +1,250 @@ +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v diff --git a/CPLD/LCMXO256C/impl1/xxx_lse_sign_file b/CPLD/LCMXO256C/impl1/xxx_lse_sign_file new file mode 100644 index 0000000..15202f1 --- /dev/null +++ b/CPLD/LCMXO256C/impl1/xxx_lse_sign_file @@ -0,0 +1,250 @@ +LSE_CPS_ID_1 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" +LSE_CPS_ID_2 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_3 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_4 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:80[15:31]" +LSE_CPS_ID_5 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_6 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_7 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_8 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_9 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_10 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_11 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_12 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_13 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_14 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_15 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_16 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_17 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_18 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_19 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:141[9] 144[5]" +LSE_CPS_ID_20 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_21 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_22 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:394[12] 409[6]" +LSE_CPS_ID_23 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_24 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_25 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_26 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_27 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_28 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_29 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_30 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_31 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_32 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_33 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_34 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_35 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" +LSE_CPS_ID_36 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_37 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_38 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_39 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_40 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_41 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_42 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:80[15:31]" +LSE_CPS_ID_43 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_44 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" +LSE_CPS_ID_45 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_46 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_47 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_48 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:321[13] 335[7]" +LSE_CPS_ID_49 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_50 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_51 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_52 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[15:41]" +LSE_CPS_ID_53 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_54 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_55 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_56 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_57 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_58 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:48[6:16]" +LSE_CPS_ID_59 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:80[15:31]" +LSE_CPS_ID_60 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_61 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" +LSE_CPS_ID_62 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_63 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" +LSE_CPS_ID_64 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_65 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_66 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_67 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[27:31]" +LSE_CPS_ID_68 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_69 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_70 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_71 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_72 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_73 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_74 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_75 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_76 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_77 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_78 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_79 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:230[16:37]" +LSE_CPS_ID_80 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_81 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_82 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_83 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[11:55]" +LSE_CPS_ID_84 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:48[6:16]" +LSE_CPS_ID_85 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_86 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_87 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:99[22:51]" +LSE_CPS_ID_88 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_89 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_90 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:58[17:46]" +LSE_CPS_ID_91 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_92 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_93 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_94 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_95 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_96 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_97 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_98 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_99 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_100 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_101 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_102 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_103 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_104 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:386[12] 409[6]" +LSE_CPS_ID_105 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_106 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:386[12] 409[6]" +LSE_CPS_ID_107 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_108 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_109 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_110 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_111 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_112 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_113 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_114 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_115 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_116 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_117 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_118 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_119 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_120 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_121 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_122 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_123 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_124 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_125 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_126 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_127 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_128 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_129 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_130 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_131 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_132 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_133 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_134 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_135 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_136 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_137 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_138 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_139 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_140 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_141 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_142 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_143 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_144 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_145 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_146 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_147 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_148 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_149 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_150 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_151 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_152 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_153 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_154 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_155 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_156 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_157 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_158 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_159 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_160 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_161 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_162 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_163 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_164 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_165 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_166 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_167 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_168 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_169 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_170 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_171 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_172 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:22[9:12]" +LSE_CPS_ID_173 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" +LSE_CPS_ID_174 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" +LSE_CPS_ID_175 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_176 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_177 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_178 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_179 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_180 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_181 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_182 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_183 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_184 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_185 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_186 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_187 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[13:17]" +LSE_CPS_ID_188 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:45[13:17]" +LSE_CPS_ID_189 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[45:49]" +LSE_CPS_ID_190 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[23:28]" +LSE_CPS_ID_191 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[34:39]" +LSE_CPS_ID_192 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[16:21]" +LSE_CPS_ID_193 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[9:14]" +LSE_CPS_ID_194 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:63[13:19]" +LSE_CPS_ID_195 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:64[13:19]" +LSE_CPS_ID_196 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:65[13:19]" +LSE_CPS_ID_197 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" +LSE_CPS_ID_198 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_199 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_200 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_201 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_202 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_203 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_204 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_205 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_206 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_207 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_208 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" +LSE_CPS_ID_209 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" +LSE_CPS_ID_210 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_211 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_212 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_213 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_214 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_215 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_216 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_217 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_218 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" +LSE_CPS_ID_219 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" +LSE_CPS_ID_220 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:36[8:12]" +LSE_CPS_ID_221 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:41[8:12]" +LSE_CPS_ID_222 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:66[8:14]" +LSE_CPS_ID_223 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_224 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_225 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_226 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_227 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_228 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_229 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_230 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:48[6:16]" +LSE_CPS_ID_231 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_232 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:255[14] 262[8]" +LSE_CPS_ID_233 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_234 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_235 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:48[6:16]" +LSE_CPS_ID_236 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_237 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_238 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_239 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[40:46]" +LSE_CPS_ID_240 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_241 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_242 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_243 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:84[6:11]" +LSE_CPS_ID_244 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:134[9] 138[5]" +LSE_CPS_ID_245 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:21[6:11]" +LSE_CPS_ID_246 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_247 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_248 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" +LSE_CPS_ID_249 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" +LSE_CPS_ID_250 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" diff --git a/CPLD/LCMXO640C/.run_manager.ini b/CPLD/LCMXO640C/.run_manager.ini new file mode 100644 index 0000000..8c0aa7b --- /dev/null +++ b/CPLD/LCMXO640C/.run_manager.ini @@ -0,0 +1,9 @@ +[Runmanager] +Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0) +windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0) +headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0) + +[impl1%3CStrategy1%3E] +isChecked=false +isHidden=false +isExpanded=false diff --git a/CPLD/LCMXO640C/.setting.ini b/CPLD/LCMXO640C/.setting.ini new file mode 100644 index 0000000..22632d4 --- /dev/null +++ b/CPLD/LCMXO640C/.setting.ini @@ -0,0 +1,4 @@ +[General] +Export.auto_tasks=Bitgen +Map.auto_tasks=MapEqu, MapTrace, MapVerilogSimFile, MapVHDLSimFile +PAR.auto_tasks=PARTrace, IOTiming diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO256C1.sty b/CPLD/LCMXO640C/RAM2GS_LCMXO256C1.sty new file mode 100644 index 0000000..7292d5f --- /dev/null +++ b/CPLD/LCMXO640C/RAM2GS_LCMXO256C1.sty @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf b/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf new file mode 100644 index 0000000..20835a0 --- /dev/null +++ b/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf b/CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf new file mode 100644 index 0000000..64fb54f --- /dev/null +++ b/CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf @@ -0,0 +1,137 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +IOBUF ALLPORTS PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "CROW[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "CROW[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "PHI2" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RCLK" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nCCAS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nCRAS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Din[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[8]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "MAin[9]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "UFMSDO" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nFWE" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "Dout[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "LED" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[8]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[9]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[10]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RA[11]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RBA[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RBA[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RCKE" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RDQMH" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RDQML" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "UFMCLK" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "UFMSDI" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nRCAS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nRCS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nRRAS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nRWE" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "nUFMCS" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "RD[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[9]" SITE "51" ; +LOCATE COMP "UFMSDO" SITE "55" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[7]" SITE "71" ; diff --git a/CPLD/LCMXO640C/impl1/.build_status b/CPLD/LCMXO640C/impl1/.build_status new file mode 100644 index 0000000..a3a7abe --- /dev/null +++ b/CPLD/LCMXO640C/impl1/.build_status @@ -0,0 +1,60 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_LCMXO640C_impl1_map.vdb b/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_LCMXO640C_impl1_map.vdb new file mode 100644 index 0000000..085d429 Binary files /dev/null and b/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_LCMXO640C_impl1_map.vdb differ diff --git a/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_rtl.vdb b/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_rtl.vdb new file mode 100644 index 0000000..b71a278 Binary files /dev/null and b/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_rtl.vdb differ diff --git a/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_tech.vdb b/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_tech.vdb new file mode 100644 index 0000000..f29938d Binary files /dev/null and b/CPLD/LCMXO640C/impl1/.vdbs/RAM2GS_tech.vdb differ diff --git a/CPLD/LCMXO640C/impl1/.vdbs/dbStat.txt b/CPLD/LCMXO640C/impl1/.vdbs/dbStat.txt new file mode 100644 index 0000000..0a575a4 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/.vdbs/dbStat.txt @@ -0,0 +1 @@ +RAM2GS_rtl.vdb diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.alt b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.alt new file mode 100644 index 0000000..4fb4bb4 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.alt @@ -0,0 +1,75 @@ +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Tue Aug 15 05:03:33 2023 * +NOTE DESIGN NAME: RAM2GS * +NOTE DEVICE NAME: LCMXO640C-3TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[7] : 71 : inout * +NOTE PINS RD[6] : 70 : inout * +NOTE PINS RD[5] : 69 : inout * +NOTE PINS RD[4] : 68 : inout * +NOTE PINS RD[3] : 67 : inout * +NOTE PINS RD[2] : 66 : inout * +NOTE PINS RD[1] : 65 : inout * +NOTE PINS RD[0] : 64 : inout * +NOTE PINS Dout[7] : 3 : out * +NOTE PINS Dout[6] : 2 : out * +NOTE PINS Dout[5] : 5 : out * +NOTE PINS Dout[4] : 4 : out * +NOTE PINS Dout[3] : 6 : out * +NOTE PINS Dout[2] : 8 : out * +NOTE PINS Dout[1] : 7 : out * +NOTE PINS Dout[0] : 1 : out * +NOTE PINS LED : 57 : out * +NOTE PINS RBA[1] : 83 : out * +NOTE PINS RBA[0] : 63 : out * +NOTE PINS RA[11] : 79 : out * +NOTE PINS RA[10] : 87 : out * +NOTE PINS RA[9] : 85 : out * +NOTE PINS RA[8] : 96 : out * +NOTE PINS RA[7] : 100 : out * +NOTE PINS RA[6] : 91 : out * +NOTE PINS RA[5] : 95 : out * +NOTE PINS RA[4] : 99 : out * +NOTE PINS RA[3] : 97 : out * +NOTE PINS RA[2] : 94 : out * +NOTE PINS RA[1] : 89 : out * +NOTE PINS RA[0] : 98 : out * +NOTE PINS nRCS : 77 : out * +NOTE PINS RCKE : 82 : out * +NOTE PINS nRWE : 72 : out * +NOTE PINS nRRAS : 73 : out * +NOTE PINS nRCAS : 78 : out * +NOTE PINS RDQMH : 76 : out * +NOTE PINS RDQML : 61 : out * +NOTE PINS nUFMCS : 53 : out * +NOTE PINS UFMCLK : 58 : out * +NOTE PINS UFMSDI : 56 : out * +NOTE PINS PHI2 : 39 : in * +NOTE PINS MAin[9] : 51 : in * +NOTE PINS MAin[8] : 50 : in * +NOTE PINS MAin[7] : 44 : in * +NOTE PINS MAin[6] : 49 : in * +NOTE PINS MAin[5] : 45 : in * +NOTE PINS MAin[4] : 46 : in * +NOTE PINS MAin[3] : 47 : in * +NOTE PINS MAin[2] : 37 : in * +NOTE PINS MAin[1] : 38 : in * +NOTE PINS MAin[0] : 23 : in * +NOTE PINS CROW[1] : 34 : in * +NOTE PINS CROW[0] : 32 : in * +NOTE PINS Din[7] : 19 : in * +NOTE PINS Din[6] : 20 : in * +NOTE PINS Din[5] : 17 : in * +NOTE PINS Din[4] : 18 : in * +NOTE PINS Din[3] : 16 : in * +NOTE PINS Din[2] : 14 : in * +NOTE PINS Din[1] : 15 : in * +NOTE PINS Din[0] : 21 : in * +NOTE PINS nCCAS : 27 : in * +NOTE PINS nCRAS : 43 : in * +NOTE PINS nFWE : 22 : in * +NOTE PINS RCLK : 86 : in * +NOTE PINS UFMSDO : 55 : in * +NOTE CONFIGURATION MODE: NONE * +NOTE COMPRESSION: off * diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.arearep b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.arearep new file mode 100644 index 0000000..9275f37 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.arearep @@ -0,0 +1,23 @@ +---------------------------------------------------------------------- +Report for cell RAM2GS.TECH +Register bits: 102 of 862 (11.833%) +I/O cells: 67 + Cell usage: + cell count Res Usage(%) + BB 8 100.0 + CCU2 9 100.0 + FD1P3AX 28 100.0 + FD1P3AY 3 100.0 + FD1P3IX 2 100.0 + FD1S3AX 47 100.0 + FD1S3AY 1 100.0 + FD1S3IX 16 100.0 + FD1S3JX 5 100.0 + GSR 1 100.0 + IB 26 100.0 + INV 3 100.0 + LUT4 126 100.0 + OB 33 100.0 + ORCALUT4 1 100.0 + PFUMX 6 100.0 + TOTAL 315 diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bgn b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bgn new file mode 100644 index 0000000..ba06e25 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bgn @@ -0,0 +1,45 @@ +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:32 2023 + + +Command: bitgen -w -g ES:No -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf + +Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application Bitgen from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2GS_LCMXO640C_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| ES | No** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... +Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit". +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 46 MB diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bit b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bit new file mode 100644 index 0000000..787f30d Binary files /dev/null and b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.bit differ diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.ncd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.ncd new file mode 100644 index 0000000..405a3aa Binary files /dev/null and b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.ncd differ diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad new file mode 100644 index 0000000..124dd5c --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.pad @@ -0,0 +1,353 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO640C +Performance Grade: 3 +PACKAGE: TQFP100 +Package Status: Final Version 1.17 + +Tue Aug 15 05:03:28 2023 + +Pinout by Port Name: ++-----------+----------+---------------+-------+------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | Properties | ++-----------+----------+---------------+-------+------------------------------+ +| CROW[0] | 32/2 | LVCMOS33_IN | PB4C | SLEW:FAST PULL:UP | +| CROW[1] | 34/2 | LVCMOS33_IN | PB4E | SLEW:FAST PULL:UP | +| Din[0] | 21/3 | LVCMOS33_IN | PL10C | SLEW:FAST PULL:UP | +| Din[1] | 15/3 | LVCMOS33_IN | PL7B | SLEW:FAST PULL:UP | +| Din[2] | 14/3 | LVCMOS33_IN | PL5B | SLEW:FAST PULL:UP | +| Din[3] | 16/3 | LVCMOS33_IN | PL8C | SLEW:FAST PULL:UP | +| Din[4] | 18/3 | LVCMOS33_IN | PL9A | SLEW:FAST PULL:UP | +| Din[5] | 17/3 | LVCMOS33_IN | PL8D | SLEW:FAST PULL:UP | +| Din[6] | 20/3 | LVCMOS33_IN | PL10A | SLEW:FAST PULL:UP | +| Din[7] | 19/3 | LVCMOS33_IN | PL9C | SLEW:FAST PULL:UP | +| Dout[0] | 1/3 | LVCMOS33_OUT | PL2A | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[1] | 7/3 | LVCMOS33_OUT | PL3C | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[2] | 8/3 | LVCMOS33_OUT | PL3D | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[3] | 6/3 | LVCMOS33_OUT | PL3B | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[4] | 4/3 | LVCMOS33_OUT | PL2D | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[5] | 5/3 | LVCMOS33_OUT | PL3A | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[6] | 2/3 | LVCMOS33_OUT | PL2C | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[7] | 3/3 | LVCMOS33_OUT | PL2B | DRIVE:8mA SLEW:FAST PULL:UP | +| LED | 57/1 | LVCMOS33_OUT | PR10B | DRIVE:8mA SLEW:FAST PULL:UP | +| MAin[0] | 23/3 | LVCMOS33_IN | PL11C | SLEW:FAST PULL:UP | +| MAin[1] | 38/2 | LVCMOS33_IN | PB6B | SLEW:FAST PULL:UP | +| MAin[2] | 37/2 | LVCMOS33_IN | PB5D | SLEW:FAST PULL:UP | +| MAin[3] | 47/2 | LVCMOS33_IN | PB9C | SLEW:FAST PULL:UP | +| MAin[4] | 46/2 | LVCMOS33_IN | PB9A | SLEW:FAST PULL:UP | +| MAin[5] | 45/2 | LVCMOS33_IN | PB8D | SLEW:FAST PULL:UP | +| MAin[6] | 49/2 | LVCMOS33_IN | PB9D | SLEW:FAST PULL:UP | +| MAin[7] | 44/2 | LVCMOS33_IN | PB8C | SLEW:FAST PULL:UP | +| MAin[8] | 50/2 | LVCMOS33_IN | PB9F | SLEW:FAST PULL:UP | +| MAin[9] | 51/1 | LVCMOS33_IN | PR11D | SLEW:FAST PULL:UP | +| PHI2 | 39/2 | LVCMOS33_IN | PB6C | SLEW:FAST PULL:UP | +| RA[0] | 98/0 | LVCMOS33_OUT | PT2B | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[10] | 87/0 | LVCMOS33_OUT | PT5A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[11] | 79/0 | LVCMOS33_OUT | PT9A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[1] | 89/0 | LVCMOS33_OUT | PT4F | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[2] | 94/0 | LVCMOS33_OUT | PT3B | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[3] | 97/0 | LVCMOS33_OUT | PT2E | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[4] | 99/0 | LVCMOS33_OUT | PT2C | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[5] | 95/0 | LVCMOS33_OUT | PT3A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[6] | 91/0 | LVCMOS33_OUT | PT3F | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[7] | 100/0 | LVCMOS33_OUT | PT2A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[8] | 96/0 | LVCMOS33_OUT | PT2F | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[9] | 85/0 | LVCMOS33_OUT | PT6B | DRIVE:8mA SLEW:FAST PULL:UP | +| RBA[0] | 63/1 | LVCMOS33_OUT | PR7B | DRIVE:8mA SLEW:FAST PULL:UP | +| RBA[1] | 83/0 | LVCMOS33_OUT | PT7A | DRIVE:8mA SLEW:FAST PULL:UP | +| RCKE | 82/0 | LVCMOS33_OUT | PT7E | DRIVE:8mA SLEW:FAST PULL:UP | +| RCLK | 86/0 | LVCMOS33_IN | PT5B | SLEW:FAST PULL:UP | +| RDQMH | 76/0 | LVCMOS33_OUT | PT9F | DRIVE:8mA SLEW:FAST PULL:UP | +| RDQML | 61/1 | LVCMOS33_OUT | PR9B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[0] | 64/1 | LVCMOS33_BIDI | PR6C | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[1] | 65/1 | LVCMOS33_BIDI | PR6B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[2] | 66/1 | LVCMOS33_BIDI | PR5D | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[3] | 67/1 | LVCMOS33_BIDI | PR5B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[4] | 68/1 | LVCMOS33_BIDI | PR4D | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[5] | 69/1 | LVCMOS33_BIDI | PR4B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[6] | 70/1 | LVCMOS33_BIDI | PR3D | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[7] | 71/1 | LVCMOS33_BIDI | PR3B | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMCLK | 58/1 | LVCMOS33_OUT | PR10A | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMSDI | 56/1 | LVCMOS33_OUT | PR10C | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMSDO | 55/1 | LVCMOS33_IN | PR10D | SLEW:FAST PULL:UP | +| nCCAS | 27/2 | LVCMOS33_IN | PB2C | SLEW:FAST PULL:UP | +| nCRAS | 43/2 | LVCMOS33_IN | PB8B | SLEW:FAST PULL:UP | +| nFWE | 22/3 | LVCMOS33_IN | PL11A | SLEW:FAST PULL:UP | +| nRCAS | 78/0 | LVCMOS33_OUT | PT9C | DRIVE:8mA SLEW:FAST PULL:UP | +| nRCS | 77/0 | LVCMOS33_OUT | PT9E | DRIVE:8mA SLEW:FAST PULL:UP | +| nRRAS | 73/1 | LVCMOS33_OUT | PR2B | DRIVE:8mA SLEW:FAST PULL:UP | +| nRWE | 72/1 | LVCMOS33_OUT | PR2D | DRIVE:8mA SLEW:FAST PULL:UP | +| nUFMCS | 53/1 | LVCMOS33_OUT | PR11C | DRIVE:8mA SLEW:FAST PULL:UP | ++-----------+----------+---------------+-------+------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 3.3V | +| 1 | 3.3V | +| 2 | | +| 3 | 3.3V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+---------------------+------------+---------------+-------+---------------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | ++----------+---------------------+------------+---------------+-------+---------------+ +| 1/3 | Dout[0] | LOCATED | LVCMOS33_OUT | PL2A | | +| 2/3 | Dout[6] | LOCATED | LVCMOS33_OUT | PL2C | | +| 3/3 | Dout[7] | LOCATED | LVCMOS33_OUT | PL2B | | +| 4/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL2D | | +| 5/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL3A | | +| 6/3 | Dout[3] | LOCATED | LVCMOS33_OUT | PL3B | | +| 7/3 | Dout[1] | LOCATED | LVCMOS33_OUT | PL3C | | +| 8/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL3D | | +| 9/3 | unused, PULL:UP | | | PL4A | | +| 11/3 | unused, PULL:UP | | | PL4C | | +| 13/3 | unused, PULL:UP | | | PL4D | | +| 14/3 | Din[2] | LOCATED | LVCMOS33_IN | PL5B | GSR_PADN | +| 15/3 | Din[1] | LOCATED | LVCMOS33_IN | PL7B | | +| 16/3 | Din[3] | LOCATED | LVCMOS33_IN | PL8C | TSALLPAD | +| 17/3 | Din[5] | LOCATED | LVCMOS33_IN | PL8D | | +| 18/3 | Din[4] | LOCATED | LVCMOS33_IN | PL9A | | +| 19/3 | Din[7] | LOCATED | LVCMOS33_IN | PL9C | | +| 20/3 | Din[6] | LOCATED | LVCMOS33_IN | PL10A | | +| 21/3 | Din[0] | LOCATED | LVCMOS33_IN | PL10C | | +| 22/3 | nFWE | LOCATED | LVCMOS33_IN | PL11A | | +| 23/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL11C | | +| 27/2 | nCCAS | LOCATED | LVCMOS33_IN | PB2C | | +| 32/2 | CROW[0] | LOCATED | LVCMOS33_IN | PB4C | | +| 34/2 | CROW[1] | LOCATED | LVCMOS33_IN | PB4E | | +| 36/2 | unused, PULL:UP | | | PB5B | PCLKT2_1 | +| 37/2 | MAin[2] | LOCATED | LVCMOS33_IN | PB5D | | +| 38/2 | MAin[1] | LOCATED | LVCMOS33_IN | PB6B | PCLKT2_0 | +| 39/2 | PHI2 | LOCATED | LVCMOS33_IN | PB6C | | +| 43/2 | nCRAS | LOCATED | LVCMOS33_IN | PB8B | | +| 44/2 | MAin[7] | LOCATED | LVCMOS33_IN | PB8C | | +| 45/2 | MAin[5] | LOCATED | LVCMOS33_IN | PB8D | | +| 46/2 | MAin[4] | LOCATED | LVCMOS33_IN | PB9A | | +| 47/2 | MAin[3] | LOCATED | LVCMOS33_IN | PB9C | | +| 49/2 | MAin[6] | LOCATED | LVCMOS33_IN | PB9D | | +| 50/2 | MAin[8] | LOCATED | LVCMOS33_IN | PB9F | | +| 51/1 | MAin[9] | LOCATED | LVCMOS33_IN | PR11D | | +| 52/1 | unused, PULL:UP | | | PR11B | | +| 53/1 | nUFMCS | LOCATED | LVCMOS33_OUT | PR11C | | +| 54/1 | unused, PULL:UP | | | PR11A | | +| 55/1 | UFMSDO | LOCATED | LVCMOS33_IN | PR10D | | +| 56/1 | UFMSDI | LOCATED | LVCMOS33_OUT | PR10C | | +| 57/1 | LED | LOCATED | LVCMOS33_OUT | PR10B | | +| 58/1 | UFMCLK | LOCATED | LVCMOS33_OUT | PR10A | | +| 59/1 | unused, PULL:UP | | | PR9D | | +| 61/1 | RDQML | LOCATED | LVCMOS33_OUT | PR9B | | +| 63/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR7B | | +| 64/1 | RD[0] | LOCATED | LVCMOS33_BIDI | PR6C | | +| 65/1 | RD[1] | LOCATED | LVCMOS33_BIDI | PR6B | | +| 66/1 | RD[2] | LOCATED | LVCMOS33_BIDI | PR5D | | +| 67/1 | RD[3] | LOCATED | LVCMOS33_BIDI | PR5B | | +| 68/1 | RD[4] | LOCATED | LVCMOS33_BIDI | PR4D | | +| 69/1 | RD[5] | LOCATED | LVCMOS33_BIDI | PR4B | | +| 70/1 | RD[6] | LOCATED | LVCMOS33_BIDI | PR3D | | +| 71/1 | RD[7] | LOCATED | LVCMOS33_BIDI | PR3B | | +| 72/1 | nRWE | LOCATED | LVCMOS33_OUT | PR2D | | +| 73/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR2B | | +| 76/0 | RDQMH | LOCATED | LVCMOS33_OUT | PT9F | | +| 77/0 | nRCS | LOCATED | LVCMOS33_OUT | PT9E | | +| 78/0 | nRCAS | LOCATED | LVCMOS33_OUT | PT9C | | +| 79/0 | RA[11] | LOCATED | LVCMOS33_OUT | PT9A | | +| 82/0 | RCKE | LOCATED | LVCMOS33_OUT | PT7E | D7 | +| 83/0 | RBA[1] | LOCATED | LVCMOS33_OUT | PT7A | D6 | +| 85/0 | RA[9] | LOCATED | LVCMOS33_OUT | PT6B | PCLKT0_1 | +| 86/0 | RCLK | LOCATED | LVCMOS33_IN | PT5B | PCLKT0_0 | +| 87/0 | RA[10] | LOCATED | LVCMOS33_OUT | PT5A | | +| 89/0 | RA[1] | LOCATED | LVCMOS33_OUT | PT4F | | +| 91/0 | RA[6] | LOCATED | LVCMOS33_OUT | PT3F | D3 | +| 94/0 | RA[2] | LOCATED | LVCMOS33_OUT | PT3B | | +| 95/0 | RA[5] | LOCATED | LVCMOS33_OUT | PT3A | | +| 96/0 | RA[8] | LOCATED | LVCMOS33_OUT | PT2F | D2 | +| 97/0 | RA[3] | LOCATED | LVCMOS33_OUT | PT2E | | +| 98/0 | RA[0] | LOCATED | LVCMOS33_OUT | PT2B | D1 | +| 99/0 | RA[4] | LOCATED | LVCMOS33_OUT | PT2C | | +| 100/0 | RA[7] | LOCATED | LVCMOS33_OUT | PT2A | | +| PB2A/2 | unused, PULL:UP | | | PB2A | | +| PB2B/2 | unused, PULL:UP | | | PB2B | | +| PB2D/2 | unused, PULL:UP | | | PB2D | | +| PB3A/2 | unused, PULL:UP | | | PB3A | | +| PB3B/2 | unused, PULL:UP | | | PB3B | | +| PB3C/2 | unused, PULL:UP | | | PB3C | | +| PB3D/2 | unused, PULL:UP | | | PB3D | | +| PB4A/2 | unused, PULL:UP | | | PB4A | | +| PB4B/2 | unused, PULL:UP | | | PB4B | | +| PB4D/2 | unused, PULL:UP | | | PB4D | | +| PB4F/2 | unused, PULL:UP | | | PB4F | | +| PB5A/2 | unused, PULL:UP | | | PB5A | | +| PB5C/2 | unused, PULL:UP | | | PB5C | | +| PB6A/2 | unused, PULL:UP | | | PB6A | | +| PB6D/2 | unused, PULL:UP | | | PB6D | | +| PB7A/2 | unused, PULL:UP | | | PB7A | | +| PB7B/2 | unused, PULL:UP | | | PB7B | | +| PB7C/2 | unused, PULL:UP | | | PB7C | | +| PB7D/2 | unused, PULL:UP | | | PB7D | | +| PB7E/2 | unused, PULL:UP | | | PB7E | | +| PB7F/2 | unused, PULL:UP | | | PB7F | | +| PB8A/2 | unused, PULL:UP | | | PB8A | | +| PB9B/2 | unused, PULL:UP | | | PB9B | | +| PB9E/0 | unused, PULL:UP | | | PB9E | | +| PL4B/3 | unused, PULL:UP | | | PL4B | | +| PL5A/3 | unused, PULL:UP | | | PL5A | | +| PL5C/3 | unused, PULL:UP | | | PL5C | | +| PL5D/3 | unused, PULL:UP | | | PL5D | | +| PL6A/3 | unused, PULL:UP | | | PL6A | | +| PL6B/3 | unused, PULL:UP | | | PL6B | | +| PL6C/3 | unused, PULL:UP | | | PL6C | | +| PL6D/3 | unused, PULL:UP | | | PL6D | | +| PL7A/3 | unused, PULL:UP | | | PL7A | | +| PL7C/3 | unused, PULL:UP | | | PL7C | | +| PL7D/3 | unused, PULL:UP | | | PL7D | | +| PL8A/3 | unused, PULL:UP | | | PL8A | | +| PL8B/3 | unused, PULL:UP | | | PL8B | | +| PL9B/3 | unused, PULL:UP | | | PL9B | | +| PL9D/3 | unused, PULL:UP | | | PL9D | | +| PL10B/3 | unused, PULL:UP | | | PL10B | | +| PL10D/3 | unused, PULL:UP | | | PL10D | | +| PL11B/3 | unused, PULL:UP | | | PL11B | | +| PL11D/3 | unused, PULL:UP | | | PL11D | | +| PR2A/1 | unused, PULL:UP | | | PR2A | | +| PR2C/1 | unused, PULL:UP | | | PR2C | | +| PR3A/1 | unused, PULL:UP | | | PR3A | | +| PR3C/1 | unused, PULL:UP | | | PR3C | | +| PR4A/1 | unused, PULL:UP | | | PR4A | | +| PR4C/1 | unused, PULL:UP | | | PR4C | | +| PR5A/1 | unused, PULL:UP | | | PR5A | | +| PR5C/1 | unused, PULL:UP | | | PR5C | | +| PR6A/1 | unused, PULL:UP | | | PR6A | | +| PR6D/1 | unused, PULL:UP | | | PR6D | | +| PR7A/1 | unused, PULL:UP | | | PR7A | | +| PR7C/1 | unused, PULL:UP | | | PR7C | | +| PR7D/1 | unused, PULL:UP | | | PR7D | | +| PR8A/1 | unused, PULL:UP | | | PR8A | | +| PR8B/1 | unused, PULL:UP | | | PR8B | | +| PR8C/1 | unused, PULL:UP | | | PR8C | | +| PR8D/1 | unused, PULL:UP | | | PR8D | | +| PR9A/1 | unused, PULL:UP | | | PR9A | | +| PR9C/1 | unused, PULL:UP | | | PR9C | | +| PT2D/0 | unused, PULL:UP | | | PT2D | | +| PT3C/0 | unused, PULL:UP | | | PT3C | | +| PT3D/0 | unused, PULL:UP | | | PT3D | | +| PT3E/0 | unused, PULL:UP | | | PT3E | | +| PT4A/0 | unused, PULL:UP | | | PT4A | | +| PT4B/0 | unused, PULL:UP | | | PT4B | | +| PT4C/0 | unused, PULL:UP | | | PT4C | | +| PT4D/0 | unused, PULL:UP | | | PT4D | | +| PT4E/0 | unused, PULL:UP | | | PT4E | | +| PT5C/0 | unused, PULL:UP | | | PT5C | | +| PT5D/0 | unused, PULL:UP | | | PT5D | | +| PT6A/0 | unused, PULL:UP | | | PT6A | | +| PT6C/0 | unused, PULL:UP | | | PT6C | | +| PT6D/0 | unused, PULL:UP | | | PT6D | | +| PT7B/0 | unused, PULL:UP | | | PT7B | | +| PT7C/0 | unused, PULL:UP | | | PT7C | | +| PT7D/0 | unused, PULL:UP | | | PT7D | | +| PT7F/0 | unused, PULL:UP | | | PT7F | | +| PT8A/0 | unused, PULL:UP | | | PT8A | | +| PT8B/0 | unused, PULL:UP | | | PT8B | | +| PT8C/0 | unused, PULL:UP | | | PT8C | | +| PT8D/0 | unused, PULL:UP | | | PT8D | | +| PT9B/0 | unused, PULL:UP | | | PT9B | | +| PT9D/0 | unused, PULL:UP | | | PT9D | | +| TCK/2 | | | | TCK | TCK | +| TDI/2 | | | | TDI | TDID0 | +| TDO/2 | | | | TDO | TDO | +| TMS/2 | | | | TMS | TMS | ++----------+---------------------+------------+---------------+-------+---------------+ + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "32"; +LOCATE COMP "CROW[1]" SITE "34"; +LOCATE COMP "Din[0]" SITE "21"; +LOCATE COMP "Din[1]" SITE "15"; +LOCATE COMP "Din[2]" SITE "14"; +LOCATE COMP "Din[3]" SITE "16"; +LOCATE COMP "Din[4]" SITE "18"; +LOCATE COMP "Din[5]" SITE "17"; +LOCATE COMP "Din[6]" SITE "20"; +LOCATE COMP "Din[7]" SITE "19"; +LOCATE COMP "Dout[0]" SITE "1"; +LOCATE COMP "Dout[1]" SITE "7"; +LOCATE COMP "Dout[2]" SITE "8"; +LOCATE COMP "Dout[3]" SITE "6"; +LOCATE COMP "Dout[4]" SITE "4"; +LOCATE COMP "Dout[5]" SITE "5"; +LOCATE COMP "Dout[6]" SITE "2"; +LOCATE COMP "Dout[7]" SITE "3"; +LOCATE COMP "LED" SITE "57"; +LOCATE COMP "MAin[0]" SITE "23"; +LOCATE COMP "MAin[1]" SITE "38"; +LOCATE COMP "MAin[2]" SITE "37"; +LOCATE COMP "MAin[3]" SITE "47"; +LOCATE COMP "MAin[4]" SITE "46"; +LOCATE COMP "MAin[5]" SITE "45"; +LOCATE COMP "MAin[6]" SITE "49"; +LOCATE COMP "MAin[7]" SITE "44"; +LOCATE COMP "MAin[8]" SITE "50"; +LOCATE COMP "MAin[9]" SITE "51"; +LOCATE COMP "PHI2" SITE "39"; +LOCATE COMP "RA[0]" SITE "98"; +LOCATE COMP "RA[10]" SITE "87"; +LOCATE COMP "RA[11]" SITE "79"; +LOCATE COMP "RA[1]" SITE "89"; +LOCATE COMP "RA[2]" SITE "94"; +LOCATE COMP "RA[3]" SITE "97"; +LOCATE COMP "RA[4]" SITE "99"; +LOCATE COMP "RA[5]" SITE "95"; +LOCATE COMP "RA[6]" SITE "91"; +LOCATE COMP "RA[7]" SITE "100"; +LOCATE COMP "RA[8]" SITE "96"; +LOCATE COMP "RA[9]" SITE "85"; +LOCATE COMP "RBA[0]" SITE "63"; +LOCATE COMP "RBA[1]" SITE "83"; +LOCATE COMP "RCKE" SITE "82"; +LOCATE COMP "RCLK" SITE "86"; +LOCATE COMP "RDQMH" SITE "76"; +LOCATE COMP "RDQML" SITE "61"; +LOCATE COMP "RD[0]" SITE "64"; +LOCATE COMP "RD[1]" SITE "65"; +LOCATE COMP "RD[2]" SITE "66"; +LOCATE COMP "RD[3]" SITE "67"; +LOCATE COMP "RD[4]" SITE "68"; +LOCATE COMP "RD[5]" SITE "69"; +LOCATE COMP "RD[6]" SITE "70"; +LOCATE COMP "RD[7]" SITE "71"; +LOCATE COMP "UFMCLK" SITE "58"; +LOCATE COMP "UFMSDI" SITE "56"; +LOCATE COMP "UFMSDO" SITE "55"; +LOCATE COMP "nCCAS" SITE "27"; +LOCATE COMP "nCRAS" SITE "43"; +LOCATE COMP "nFWE" SITE "22"; +LOCATE COMP "nRCAS" SITE "78"; +LOCATE COMP "nRCS" SITE "77"; +LOCATE COMP "nRRAS" SITE "73"; +LOCATE COMP "nRWE" SITE "72"; +LOCATE COMP "nUFMCS" SITE "53"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:28 2023 + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par new file mode 100644 index 0000000..ac4e203 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1.par @@ -0,0 +1,225 @@ + +Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd" +Tue Aug 15 05:03:25 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf +Preference file: RAM2GS_LCMXO640C_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67/159 42% used + 67/74 90% bonded + SLICE 71/320 22% used + + + +Number of Signals: 262 +Number of Connections: 662 + +Pin Constraint Summary: + 67 out of 67 pins locked (100% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +......... +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +......... +Placer score = 1223575. +Finished Placer Phase 1. REAL time: 3 secs + +Starting Placer Phase 2. +. +Placer score = 1220793 +Finished Placer Phase 2. REAL time: 3 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 1 out of 4 (25%) + General PIO: 1 out of 160 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 4 (50%) + SECONDARY: 1 out of 4 (25%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 out of 159 (42.1%) PIO sites used. + 67 out of 74 (90.5%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+------------+------------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | ++----------+----------------+------------+------------+------------+ +| 0 | 18 / 18 (100%) | 3.3V | - | - | +| 1 | 18 / 21 ( 85%) | 3.3V | - | - | +| 2 | 13 / 14 ( 92%) | - | - | - | +| 3 | 18 / 21 ( 85%) | 3.3V | - | - | ++----------+----------------+------------+------------+------------+ + +Total placer CPU time: 3 secs + +Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd. + +0 connections routed; 662 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. +WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks. This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew. + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=7 clock_loads=4 + +Completed router resource preassignment. Real time: 3 secs + +Start NBR router at 05:03:28 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:28 08/15/23 + +Start NBR section for initial routing at 05:03:28 08/15/23 +Level 1, iteration 1 +0(0.00%) conflict; 559(84.44%) untouched conns; 717961 (nbr) score; +Estimated worst slack/total negative slack: -9.776ns/-717.961ns; real time: 3 secs +Level 2, iteration 1 +7(0.03%) conflicts; 496(74.92%) untouched conns; 699022 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-699.022ns; real time: 3 secs +Level 3, iteration 1 +9(0.03%) conflicts; 252(38.07%) untouched conns; 765745 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-765.746ns; real time: 3 secs +Level 4, iteration 1 +9(0.03%) conflicts; 0(0.00%) untouched conn; 781820 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-781.821ns; real time: 4 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:29 08/15/23 +Level 4, iteration 1 +5(0.02%) conflicts; 0(0.00%) untouched conn; 781048 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-781.049ns; real time: 4 secs +Level 4, iteration 2 +4(0.01%) conflicts; 0(0.00%) untouched conn; 780690 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.691ns; real time: 4 secs +Level 4, iteration 3 +4(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs +Level 4, iteration 4 +2(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs +Level 4, iteration 5 +2(0.01%) conflicts; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs +Level 4, iteration 6 +0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs + +Start NBR section for re-routing at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 776978 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-776.979ns; real time: 4 secs + +Start NBR section for post-routing at 05:03:29 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 260 (39.27%) + Estimated worst slack : -9.822ns + Timing score : 909228 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=7 clock_loads=4 + +Total CPU time 4 secs +Total REAL time: 4 secs +Completely routed. +End of route. 662 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 909228 + +Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -9.822 +PAR_SUMMARY::Timing score> = 909.228 +PAR_SUMMARY::Worst slack> = 0.273 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 4 secs +Total REAL time to completion: 4 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd new file mode 100644 index 0000000..676f553 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/5_1_par.asd @@ -0,0 +1,42 @@ +[ActiveSupport PAR] +; Global primary clocks +GLOBAL_PRIMARY_USED = 2; +; Global primary clock #0 +GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c; +GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN; +GLOBAL_PRIMARY_0_LOADNUM = 40; +; Global primary clock #1 +GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c; +GLOBAL_PRIMARY_1_DRIVERTYPE = PIO; +GLOBAL_PRIMARY_1_LOADNUM = 13; +; # of global secondary clocks +GLOBAL_SECONDARY_USED = 1; +; Global secondary clock #0 +GLOBAL_SECONDARY_0_SIGNALNAME = nCRAS_c; +GLOBAL_SECONDARY_0_DRIVERTYPE = PIO; +GLOBAL_SECONDARY_0_LOADNUM = 9; +GLOBAL_SECONDARY_0_SIGTYPE = CLK; +; I/O Bank 0 Usage +BANK_0_USED = 18; +BANK_0_AVAIL = 18; +BANK_0_VCCIO = 3.3V; +BANK_0_VREF1 = NA; +BANK_0_VREF2 = NA; +; I/O Bank 1 Usage +BANK_1_USED = 18; +BANK_1_AVAIL = 21; +BANK_1_VCCIO = 3.3V; +BANK_1_VREF1 = NA; +BANK_1_VREF2 = NA; +; I/O Bank 2 Usage +BANK_2_USED = 13; +BANK_2_AVAIL = 14; +BANK_2_VCCIO = NA; +BANK_2_VREF1 = NA; +BANK_2_VREF2 = NA; +; I/O Bank 3 Usage +BANK_3_USED = 18; +BANK_3_AVAIL = 21; +BANK_3_VCCIO = 3.3V; +BANK_3_VREF1 = NA; +BANK_3_VREF2 = NA; diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par new file mode 100644 index 0000000..cce2773 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.dir/RAM2GS_LCMXO640C_impl1.par @@ -0,0 +1,28 @@ +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:25 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t +RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir +RAM2GS_LCMXO640C_impl1.prf -gui -msgset +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml + + +Preference file: RAM2GS_LCMXO640C_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 -9.822 909228 0.273 0 04 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 4 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc new file mode 100644 index 0000000..ec074a2 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.drc @@ -0,0 +1 @@ +DRC detected 0 errors and 0 warnings. diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed new file mode 100644 index 0000000..b2ff5f6 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed @@ -0,0 +1,1745 @@ + +* +NOTE JEDEC CREATED BY: Lattice Semiconductor Diamond Deployment Tool 3.12* +NOTE Version: Diamond (64-bit) 3.12.1.454* +NOTE Readback: Off* +NOTE Security: Off* +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Tue Aug 15 05:03:33 2023 * +NOTE DESIGN NAME: RAM2GS * +NOTE DEVICE NAME: LCMXO640C-3TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[7] : 71 : inout * +NOTE PINS RD[6] : 70 : inout * +NOTE PINS RD[5] : 69 : inout * +NOTE PINS RD[4] : 68 : inout * +NOTE PINS RD[3] : 67 : inout * +NOTE PINS RD[2] : 66 : inout * +NOTE PINS RD[1] : 65 : inout * +NOTE PINS RD[0] : 64 : inout * +NOTE PINS Dout[7] : 3 : out * +NOTE PINS Dout[6] : 2 : out * +NOTE PINS Dout[5] : 5 : out * +NOTE PINS Dout[4] : 4 : out * +NOTE PINS Dout[3] : 6 : out * +NOTE PINS Dout[2] : 8 : out * +NOTE PINS Dout[1] : 7 : out * +NOTE PINS Dout[0] : 1 : out * +NOTE PINS LED : 57 : out * +NOTE PINS RBA[1] : 83 : out * +NOTE PINS RBA[0] : 63 : out * +NOTE PINS RA[11] : 79 : out * +NOTE PINS RA[10] : 87 : out * +NOTE PINS RA[9] : 85 : out * +NOTE PINS RA[8] : 96 : out * +NOTE PINS RA[7] : 100 : out * +NOTE PINS RA[6] : 91 : out * +NOTE PINS RA[5] : 95 : out * +NOTE PINS RA[4] : 99 : out * +NOTE PINS RA[3] : 97 : out * +NOTE PINS RA[2] : 94 : out * +NOTE PINS RA[1] : 89 : out * +NOTE PINS RA[0] : 98 : out * +NOTE PINS nRCS : 77 : out * +NOTE PINS RCKE : 82 : out * +NOTE PINS nRWE : 72 : out * +NOTE PINS nRRAS : 73 : out * +NOTE PINS nRCAS : 78 : out * +NOTE PINS RDQMH : 76 : out * +NOTE PINS RDQML : 61 : out * +NOTE PINS nUFMCS : 53 : out * +NOTE PINS UFMCLK : 58 : out * +NOTE PINS UFMSDI : 56 : out * +NOTE PINS PHI2 : 39 : in * +NOTE PINS MAin[9] : 51 : in * +NOTE PINS MAin[8] : 50 : in * +NOTE PINS MAin[7] : 44 : in * +NOTE PINS MAin[6] : 49 : in * +NOTE PINS MAin[5] : 45 : in * +NOTE PINS MAin[4] : 46 : in * +NOTE PINS MAin[3] : 47 : in * +NOTE PINS MAin[2] : 37 : in * +NOTE PINS MAin[1] : 38 : in * +NOTE PINS MAin[0] : 23 : in * +NOTE PINS CROW[1] : 34 : in * +NOTE PINS CROW[0] : 32 : in * +NOTE PINS Din[7] : 19 : in * +NOTE PINS Din[6] : 20 : in * +NOTE PINS Din[5] : 17 : in * +NOTE PINS Din[4] : 18 : in * +NOTE PINS Din[3] : 16 : in * +NOTE PINS Din[2] : 14 : in * +NOTE PINS Din[1] : 15 : in * +NOTE PINS Din[0] : 21 : in * +NOTE PINS nCCAS : 27 : in * +NOTE PINS nCRAS : 43 : in * +NOTE PINS nFWE : 22 : in * +NOTE PINS RCLK : 86 : in * +NOTE PINS UFMSDO : 55 : in * +NOTE CONFIGURATION MODE: NONE * +NOTE COMPRESSION: off * + + +QF130036* +G0* +F0* +L000000 +11111111001111111111011110111100111111111101111011110011111111110111101111111111 +11111111111011111111111111111111101111111111111111111110111111111111111111111011 +1111111111111111111011110011111111110101111011001111111111010111011111111111 +11111111111111111111111110111111111111111111111011111111111111111111101111111111 +11111111111011110011111111110111101111111111111111111110111100111111111101111011 +1111111111111111111011110011111111110101110111001111111111010111011111111111 +11111111001111111111011110111100111111111101111011110011111111110111101111001111 +11111101111011111111111111111111101111111111111111111110111111111111111111111011 +1111111111111111111011110011111111110101110111001111111111010111011111111111 +11111111111111111111111110111111111111111111111011111111111111111111101111001111 +11111101111011111111111111111111101111111111111111111110111111111111111111111011 +1111111111111111111011110011111111110101110111001111111111010111011111111111 +11111111111111111111110111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111100111111111100111111111111111110 +11111111111111111111111111111111111011111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111110 +11111111111111111111111111111111111011111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111110111111111111111101111111111111111111111111111111111111111 +11111111111111111111111110111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111110111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111110001111111111110111111111110111111111011111111111111 +11111111111111111111111111111111111111101111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111100011111110111111111110011111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111001111111111111111111100111111111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111111111111 +1111111111111111111111111111110111111111011111111111011111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111110111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111101111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111001111111111111111111111111111111111111111111111111111111011111111111011111 +1111111111111111111111111111111111111111111111111111101111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111011111 +1111111111111111111111111111111111111110111111111111111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111110101111111111111111111010111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111011111111111110111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +1111111111111011111111111111111100111111101111111111111111111111111111111011 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111101101111111111111111 +1101111111111101101111111111100111011111111111011111111111111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +1111111111111110110111111111111101111111110101111011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110101111111111111111 +1110111111111110111111111111111111111111101111101011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111001111111101110111 +1111111011101010100011111111111111111110111100110111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111000001111111110111 +1110011011011101100111101111111111111111111101100100100111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111001111011011111111 +1111011011011101110101011111111111111111011011110011010111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110001011011111110111 +1110111100010101110111111111111111111111111111110001110111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110101111111111101111 +1110111111111111011011111111111111111111111111100011111111111101111110111011 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110111111111111111101111111111001111111111111100011111111111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111011111011111111111111111111011111111111111111101111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +1110111111111111111011111111111101111111111111101011111111111111111110011110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +1111101111111011111010111111111111101111011111110111111011111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111100000011101111111111111100101110111111111110111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111101111111111011111111 +1101100111011111111111011111111011111111011111011111111101011111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111101111011111111101111111011101111111111111111111111111011111111111111111 +01111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111101111111111111111111111111111 +1101101111011111110110001111111110111011111111111111111010011111111111111011 +01011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +1101101001111111101111010110111111011011111111111111111100011111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111101101111111111110111111111111 +1111111111011111110111110110111111110111011111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111110111111111111111111111111111 +1110111111111111110111111100111111110101111111111111111111111111111111111111 +10111111111111111111111111111111111111111111010111111111111111111001011111111111 +11111111111111111111111111111111111111111111111101111111111111111111111011111111 +0011101111011101011111110111111111101101011111111111111111111111110111111101 +11111111111111111111111111111111111111111111110111111111111111111111011111111111 +11111111111111111111111111111111111111111111111111011111111111111111111101111111 +0110101001111111110111111110111101110111011111111111111111111110110111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111001111011011111111111110111011111111111111111111111111111111111111111101 +11111111111111111111111111111111111111111111101111111111111111111100011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111110 +1110001111111111111111111100111111111110111111111111111111111111101111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110111111111111111001111010111110111111111111111111111011111111111111111111 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110001111111111111111001011001111011111111111111111111101111111111101111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111101111111111111111111111110101110111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110101111111111111111111110111111110111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111110111111111111111111011100111 +1111111111111011111111011110111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111101111111111111111101110111 +1111001111111101111011011100101001111111111111111111111111111111111111011111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111101111 +1101101111111111111111110111110111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1101101111111111111110111110111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111101111111111111111111111111 +1111111110111111111111111111101110111001111111111111111111011111110111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111011111111111110111101001111111011111111111111110111111110111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111011111111111111110100011101010101111111111111111111111110111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111011111111111111111111111111 +1111111111011111111111110100110101110111111111111111111111111111101111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111010101111111 +1111111111011111111111010111111111110111111111111111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011011101111111 +1111111011011111111011011100111111111111111111111100000111011111111110111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110100011011111111 +1111111100011111111111111100111111101111111111111101110111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +1111110111011111111110111111111111111111111111111111110011111111111110111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111101111111111111111111111111111111111111110101111011 +1111111111111111111111111011101111111111111100111111111011111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111011111111111111111111111111111111111111001111101 +1111111111111111111111111010101101111111111001111111111101111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +0111111111111111111111111111111001111111111111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111011 +1111111111111111111111111111010101111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111100101111111111111111111101110101111111111111111111111111111111101 +11111100111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111110001111111111111001101110111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101101111111110111010001111111111111111111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111101111111110111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111011111011 +1111111111111111111111111111011111111111110111111111111110011111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +0111111111111111111111110111111101111111100111111111111110011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111011 +1111111111111111111111111111111001111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111110 +1111111111111111111111111111011101111111101111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111111111111 +1111111111101100111111111111010111111111111111111111111111101011111110111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111110110111 +1111110010011100111111111111101101110111111111111111111111101101111101111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111111111111111110100111 +1111110101011011011111111010111001111111101111111111111111110111111110011111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111011111 +1111111111000110111111111111011100111111111101111111111111101111111101111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111110111111100111111110111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111100111111100001101110111110111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100010001111110011101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111110111111111100111100101111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111001111111111111111011110111 +1111111111110101101111111100111111111111111111111110111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011101111111111111011101101111 +1111111111111101110111111100111111111111111111111110100111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111011111111110111111111111111 +1111111111111011111111110111111111111111111111111101110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111110011111111111 +1111111111111111111111111111111111111111111111111111010111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101111111111111111101110111111111111110011111011111111111111111011 +11011111111111111111111111111111111111111111111111111111111111111011011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111101101111111111111010011111111111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111110111111111111111101000010111111111111011111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111000111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111110101111111111111101011111111111111111101111110 +11111111111111111111111111111111111111111001111111111111111111111101111111111111 +11111111111111111111111110111111111111111111111110111111111111111111111111111111 +1111111111111101111111111111111111111111111111110001111111111101111111111101 +11111111111111111111111111111111111111111001111111111111111111111111111111111111 +11111111111111111111111111011111111111111111111111011111111111111111111111111111 +1111111111111011111111111111111111111111111111100010100111111101111110111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +11111111111111111111111111110111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111110010110111111011111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111100011010111111101111101011111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101111111111 +1111111111101111111111111111111110111111111111101011111111111111111111111011 +11011111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111100111111111111111111111011111111111100011111111111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +1111111111111101111111111111111110110111111111110011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111110101111111 +1111111111111111111111111111111111111101111111101011111111111111111111111110 +11111111111111111111111111111111111111111011111111111111101111111111111111111111 +11111101111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111111111110111111111111111011111110111111111111111101 +11111111111111111111111111111111111111111101111111111111100101111111111111111111 +11111001111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111011111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111001111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111011111111111111111111010111111111011111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11101111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111110010111111111011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111101111111111111111111111111 +1111111111111111111111111111111110111111111111111111101111111111111111111111 +11011111111111111111111111111111111111111111111111110101111111111111111111111111 +11111111111111111111111111111111111111111111111111111001111111111111111111111111 +1111111111111111111111111111111111111111111111111111110111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111110111111111111110111111111111111111111111 +11111111111111111111111111111111111111111111111111111011111111111111111111111111 +11111111111111111111111111111111111111111111111111101111111111111111111111111111 +1111111111111111111111111111111111010111111111111111110111111111111111111111 +11111111111111111111111111111111111111111111111111111110111111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111110111 +1111111111111111111111111111111111110011111111111111111111111101111111111111 +11111111111111111111111111111111111111111111111111111001000101111111011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111100111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111011001111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111101111 +1111111111111111111111111111111111111101011111111111111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111110111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111001111111111111100111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111111111101111111111111111111111111111111111111111111 +11011111111111111111111111111111111111111111111111111001111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111101001111111111111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111110101111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111011111111111111111101111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111011111111111111011101111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111110111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111100111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101111111111 +1111111111111111111111111111111111111111111111111111111111111111110011111111 +11111111111111111111111101111111111111111111110111111111001111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111110111111111 +1111111111111111111111111111111111111111111111111111111111111111100111111110 +11111111111111111111111111111111111111111111101111111111110101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101101111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111101111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111101111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111111111110010111011111111110101111111110111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111001111111111111111111110001011111111110110111111111011010111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111100001111111111110110111111111110111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101111111111111111111111010010111111111111010111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111110111111 +1111111111101111111111111111111110111011111011111111111011111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111101111111111111011011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111110110111 +1111111111111111111111111111111110010101011101111111111011011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111011111 +1111111111110111111111111111111111111111011111111111111111111111111110111110 +11111111111111111111111111111111111111111111111111111111111111111011111111111111 +11111111100111111111111111111111111111111111111111111111111111111111111101111111 +1111111111111111110111111111100111100110111111111111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111011111111111111 +11111111110111111111111111111111111111111111111111111111111111111111111011111111 +1111111111111111111111111111101111110111011111111111111111111111110111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111101111111111111101111111111111111111111111111110111111111101 +11111111111111111111111111111111111111111111111111111111111111111101111111111111 +11111111101111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111101111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111111111111111111111111111111111111111111111 +1111111111101111111111111101111110111111111111111111111011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111110111111111110111111111111111111111111111111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111110111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011111111010111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111100101111111 +1111111111111011111111111111111111111111110111111111111111100011111111111111 +11111111111111111111111111111111111111111111111111111111100101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111110101111111 +1111111111111101111111111111111111111111101110111111111111101101111111111111 +11111111111111111111111111111111111111111111111111111111111001111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111011111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111011101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011111111111111101111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111101111111111111111111111111111111111111111111101111 +1111111111111111111111111011011110111111111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111011111111111111111111111111111111111111111110111 +1111111111111111111111111110111111111111111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111110111100010111111111111111111111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111110011111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111100111 +1111111111111111111111111111111111110111111111111110011111011101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111110111 +1111111111111111111111111110111111101111111111111110111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111110110111111111111111111111111110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111101111 +1111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101111111111 +1111111111111111111111111000111111101111111111111111111011111111111111111111 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011100001110111111111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111100101111111 +1111111111111111111111111111111111111111111111111111111001011111111111111111 +11111110111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111111111111111111111111111111111111111111 +11111101111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111110111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011111111111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101111111111 +1111111111101111111111111000111110101111111111111111111011111111111111111111 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101111111111 +1111111111101111111111111000111111110111111111111111111101111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +1111111111111101111111111100111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111110111111111 +1111111111110111111111111111111111011111111111111111111111011111111111111111 +11111100111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111110111111111111111111111111111011111111111111111111111111111111111 +11111010111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111100111111111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011111111111110111111111111111111111111111111111111 +01111111111111111111110101111111111111111111010111111111111111111101011111111111 +11111111111111111111111111111111111111111111111111111111111111111111101111111111 +1111111111101111111111111111111110111111111111111111111111111111111111111111 +01011111111111111111111101111111111111111111110111111111111111111111011111111111 +11111111111111111111111111111111111111111111111111111111111111111111110111111111 +1111111111110111111111111000100001011111111111111111111111111111111111111110 +11111111111111111111111011111111111111111111101111111111111111111110111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101101111111 +1111111111111111111111111100111110110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +10111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111001111111 +1111111111111111111111111111111111111111101101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +1111111111111111111111111000111111111111110000111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111101101111111111111111011111111 +1111111111111111111111111100111111111111111100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111110101111111111000111110101111111111111111111111111111111111111111 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111000111111010111111111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111110110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111110110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111011111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111101111 +1111111111111111111111111111111111111011101101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111110111 +1111111111111111111111111100111111111101111100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111111111110100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011111111111111111011111111111111111111111111111111 +01111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101111111111111111111110101111111111111111111011111111111111111111 +01011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000100001110111111111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111110110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111100101111111111100111110010111111111111111111101011111111111111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111011111111111111111 +10111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111011111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111101011111111111111111111111111111111111011 +11011111111111111111111111111111111111111111110111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111110101111111111111111111111111111110111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111110110111111111111111111111111111111101111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111110011110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111110111111111111111111111111111111111111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111011111111100111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111110110111111000111111111111111111111111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111011111111111111111111101111111111 +1111111111101111111111111111111111111111111111111111111011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111011111111111111111111101111111111 +1111111111111111111111111000100001111111111111111111111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111101111111 +1111111111101101111111111100111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111101111111111111111111110111111111 +1111111111110111111111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111000111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101111111111111100111111111111111111111111111111111111111111111111 +11111111111111111111111101111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111101111111111111111111111111111111111111111 +11111111111111111111111101111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111110111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111110111111111111111111111111111111111111111 +11111111111111111111101011111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111110011111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111110011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111111111111111111111110011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101111111111 +1111111010111111001011011111111111010111111111111011111111111111111111111011 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111101111111110111111111 +1101111011011110110111111000100001100111111111011011111111111111111111111011 +11111111111111111111111111111111111111111111111111111111111110110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101101111111 +1111110101011110110111011100111111110111111111010011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +1110101111011111111000111111111111110111111111010011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +1111111111011110101001101111111110111110111111010011111011111111110111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111000011101111111 +1110001010011111110111011000111111111111011111110010111111111101110111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111011111111111 +1111001101011111110111011100111111110111011111110011111101111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111001111111111 +1111101111111111110101111100111111010111011111110011011111111101100111111101 +11111111111111111111111111111111111111111101111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110111111111111011111111000111111111111111111100111111011111111111111111011 +11011111111111111111111111111111111111111101111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110110011111111111111111000111111110111111111110011111101111111111111111010 +11111111111111111111111111111111111111111111111111111111111110110111111111111111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +1111001111011111111111111100111111110111111111110011111111011111111111111111 +11111111111111111111111111111111111111101011111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110001101111111111111111111111110110111111111110111111111011111111111111111 +11111101111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111001111111111111111110111111011111110111111111111111111111111101 +11111011111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111001011101110111111100111110011111011111110011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111101111111111111111111 +1101111011111111111111111000111111110111011111010011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111110011011101111111011111111111110111111110111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111110111 +1111010111111110111111111111111111101011100101111111101111011111111111111111 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111000011111110111 +1101011011111110111111111000100001110011111100111111110110011111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111101111 +1111111101011111110111111100111111111111011001111110111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111011110111111 +1110111111111111011111111111111111111101111110111111110011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111110111111111111111111111111110111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111110011011111111111111000111111111110111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111110101011111111111111100111111101111111111111111111111101101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110111111011111111111111100111111111111111111111111111111111111111111111111 +01111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110001111011111111111111000111111111111100111111111111111111111111111111111 +01011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111001001111111111111111000111111110111111111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111001111011111111111111100111111110111111100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110000111011111111111111111111110110111111111111111111111111111111111111111 +10111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111001101111111111111011111111110111111101111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111000011011111111111001100111111111111110111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1101001110011111111111111000111111010111111100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111101111111111111110111011111111110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111101111111111111111101111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1101111111011111110111111000100001110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111110110111 +1111110110111111111111111100111111110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111011111111111111111111111110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +1111111111111111111111111111111111111111111111111111110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111011001111111111111111000111111111111111111111110000111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +1110111111111111111111111100111111111111111111111111110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011011111111111 +1111111111111111111111111100111111111111111111111101110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111001111011111111111111000111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111100111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111011111111111111100111111110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111110111011111111111111111111111110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111011 +1111111111111111011011011111111111111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111010011111110101001100111111111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1101111101111111111111011000111111111110111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111101 +1111111111111111111110011011111111111011111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111100111111111111111 +11111111111111111111111111111111111111111111111101011111111111111111110111111111 +1111001111011111111111111111111111111111111111111111111111111110111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111101111111 +1101111111011111111111101000100001111111111111111111111111111111110111111111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1101101110011111111111111100111111111111111111111111111111111110101111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111111111111111111111111 +1111101011011111111011111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111110111111 +1101101111011111101111111111111110111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111110111 +1110101110011111110111111000111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111101111 +1111100111011110110111111100111111110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111110111111 +1111101111011111111111111100111111010111111111111111111111111111111111111111 +11111111111111111111110111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110001111111111111111011000111111101011111111111111111110011101111111111111 +11111111111111111111111101111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1110000011111111111111011000111111110101111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111011101011111111010111100111111111111111111111111111110111011111111111111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111001111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111101011111111111111111011111111111 +1111001111111001110111111111111111111111111111111111111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111011111111111111111011111111111111011011111111111 +1111000001011101101001111100111111111011111111111100111111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111111111100011111111111 +1101010111011111111111011000111111111111011111111111010111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111011111111111111111111111111111111110111011111111111 +1111001110011011111101111011111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111011111111111111111111111111111111 +1111111111101111111111111111011111111111000111111011111110011111110011111111 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111011111111111111111111111111111111 +1111111111111111111111111000101111111111011111011011111111011111110111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111111111111 +1111111111101101111111111100100101111011111101011111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111101111111111111111111111111111111 +1111111111110111111111111111111101111010010111110011111110111111101111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111111111111111010110110010011101111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111000111111111111011101110000010111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111011111111111100111111111111011101110010110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101111111111111100111111111111011111110011110111111101111111111111 +01111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111101011111111111111111111001111111 +1111111111111111111111111000011111111101111111100011111111111111111111111011 +01011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111101111111 +1111111111111111111111111000101111111111111111100011111111111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111011111111 +1111111111111111111111111100110101111111111111110111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111111111111111111111111 +1111111111111111111111111111111111111111111111110111111111111111111111111111 +10111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111100111011111111011111111111111111111111101 +11111100111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100101101110111011111111011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111111111111011111011111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111011110011101110111111111111111111111111111111111101 +01111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111001111111 +1111111111101111111111111111111111111011101111111110111110011111111111111111 +01011111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +1111111111111111111111110111100001111111111111111110011110011111111111111110 +11111110111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111011111111 +1111111111111101111111111100111111111111110101111111110111111111111111111111 +11111110111111111111111111111111111111111111111111111111111110101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111110101111111111000111111111101111101111111111111111111111111111111 +10111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111100101111111111111111111111111111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111100100001111011111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100101101111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101011111111111000111101111111111111111111111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101001111111111000011111101111011111111111111111111111111111111111 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111100101111111111100100101110101011111111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111100101001111011111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111011111111110000111101111010111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111010111111111111111111111111111111111111111111111110111 +1111111111111111111111111100011110111011111101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111111111111111111111111111111111111111100111 +1111111111111111111111111100101101111111111000111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111111111111111111111111111111111111 +1111111111111111111111110100110101111111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111110111111 +1111111111111111111111111110111011011101011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101001111111 +1111111111101111111111110110111110111001111111111111111011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +1111111111110111111111110100111001111101011111111111111011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111110001111111 +1111111111111101111111111100101111110111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +1111111111111101111111111000111101010111111111111111111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111111111111111111111111 +1111111111111111111111111100111111111011101111111111111111111110011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111111111111 +1111111111111111111111111000111111111101011111111110110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111011111111111111111011011111110111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111010110111111111001111111111011111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111101111111111111000011111101111101111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111000100111110111111100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111100111101111111101101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111100101111111111011111111111111110111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100101111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100101101111111111101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111110100110001111111101111111111111111101101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101101111111 +1111111111111111111111111110101111111111111111111111111111111111110111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111110100101001111111101111111111111111111111110111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101101111111 +1111111111101101111111111100100101110111110101111111111111111110101111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111110011111111 +1111111111111111111111111000111101110111101111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111110111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111000111101111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111111111111111111111111111111111111111101111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111100111011111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110110111111111111111 +11111111111111111111111111111111111111111111111101011111111111111111111001111111 +1111111111101111111111111011111111111101011111111111111011101111111111111111 +11111111111111111111111111111111111111111111111111111111111111010111111111111111 +11111111111111111111111111111111111111111111111111011111111111111111111101111111 +1111111111111111111111111011111101111111011111111111111101101101111111111111 +11111111111111111111111111111111111111111111111111111111111110110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111011111111 +1111111111100101111111111111111011110111111111111111111111011101111111111111 +11111111111111111111111111111111111111111111111111111111111110101111111111111111 +11111111111111111111111111111111111111111111111110111111111111111111111111111111 +1111111111111111111111111011101101110110111111111111111111000111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111010111111111111111111111111111111111111111111111111111111111111110111111 +1111111111111011111111111111111111111111111111111111110011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111110111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111111111111111111111110111110110101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111110111 +1111111111111111111111110111111111111111111101111110000111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111101111111111111111111111111111111111111111111111111111111111111111010111 +1111111111111111111111111110111111111111111111111111110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111101001111111 +1111111111101101111111111111111110111111111111111111111011111111111111111011 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111010111111111111111111101111111110001111111 +1101111111111011111111111111111111011111111111111111111101111111111111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111010011111111111111111111111111111101111111 +1111111111111101111111111111111110110111111111111111111011011111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111011111111111111111111111011111111101111111 +1110111111110101111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111011111110111111111111111110110111101111111 +1111101101111111111111101111111111111111111111111111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111110010111111111101111011111111011001111111 +1110110010011111110111001111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111110011010111111111110110111011011111111111 +1111110111011111111111011111111111111111111111111111111111111111111111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111110111111111111101111111111111111111111111111001111111111 +1111111111011111110111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111100111111111111111 +11111111111111111111111111111111111111100011111110011101111111110101110101111111 +1110111110111001111111111111111111111111111111111110111110011111111111111111 +11011111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111100011111111011111111111111011111101111111 +1110111111011101111111111111111111111111111111111110011110011111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111110011111110111111111111101111011111111111 +1111011111111111111111111111111111111111111111111111110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111011111111 +1110011111111011111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111110011111111011111111111111111111111110111 +1111111111110111110111111111111110111111111111111111111111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111110011111110111111111111111111111111110111 +1111001111111101111111111111111110011111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111010011111111111111111101111111111111110111 +1101001111111111110111111111111111110111111111111111111111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111011111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111101101011111111111111001101101111111 +1111111111111111111111111111111110100111111111111111111110111111111111111111 +11011111111111111111111111111111111111111111111111111111111111100111111111111111 +11111111111111111111111111111111111111111110010110011111111111111011111001111111 +1111110011011101111111111111111111010111111111111111111111011111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011000101111111 +1111111110011111111111111111111110110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111001111111111 +1111111101101111111111111111111111101111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111111111111111011111111111111111111111100111 +0111111111111101111111011111111111110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111110110 +0011111111111111111110001111111111100111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111110111111111111111111111111101111 +1111111111111011111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111110111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111101111111111111111111110111111111111111 +11111111111111111111111111110111111111111111111111111111111111111111111010111111 +0011111111111101111111111111111111100111111111111111111111111111111111111111 +11011111111111111111111111111111111111111111111111111111111111100111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111100111111 +0111111111111111111111111111111111110111111111111111111111110111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011111110111111 +1111111111111011111111111111111111111111111111111111111111101111111100111111 +11111111111111111111111111111111111111111011111111111111111110111111111111111111 +11111111111111111111111111101111111111111111111111111111111111111111011110010110 +1111111111111111111111111111111111101111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011111110111111 +1111111111111111111011001111111110111111111111111101111011111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011111111111111 +1111111111111111111110011111111111011111111111111110111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111101011111110111 +1111111011111111111111001111111111111111111111111110110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111010111 +1111111111011111111101111111111111111111111111111111010101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11110101111111111111111111100111111111111111111101011111111111111111101100111011 +0111111111101001111111001111111110100111111111111111111011111111110011111011 +11011111111111111111111111111111111111111111111111111111111111111111111111111111 +11111101111111111111111111100111111111111111111110011111111101111111111111011111 +1001001111100101111111011111111111000111111111010011111101111111100111111011 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111011111111111111111111111111111111111111111111111111111111111111111110110111 +0101001111111101111111111111111111110111111111010011111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111110011111100 +1111111111111011111110111111111111110111111111111011111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111110111111111111111111100111101111111001 +1101001011111011111111111111111110111111111111011011111111111111111011111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111110111111111111111110101111110101111111 +0111001011011101111111111111111111111111111111101011111111111111110111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111010111111111111111101111011111111111 +0111000110011111111111111111111110110111111111111011111111111111110111111101 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011001111111101 +0111001101011111111111111111111111011111111111111011111111111110111111111101 +11111111111111111111111111111111111111111101111111111111111111110111111111111111 +11111111111111111111111111100111111111111111111111111111111110111011111111010111 +0110111110101101111111111111111111111111111111100010111011111111110111111111 +11011111111111111111111111111111111111111001111111111111111111110111111111111111 +11111111111111111111111111110111111111111111111111111111111110001111111111110110 +0011010001010111111111111111111111110111111111100011111101111110100111111110 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +11111111111111111111111111101111111111111111111111111111111111001111011111111011 +0111110111011011111111111111111111111111111111111111110011011111111111111111 +11111111111111111111111111111111111111101111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111011011111101111 +1111111111011111111111111111111110111111111111100011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111110101111111111111101100001 +1011111111111111111111011111111111111111111111110011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111110101 +0111111111111111111111011111111111111111111111110011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111110101111111111111101111 +0101111111111111111111111111111111111111111111011111111011011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111011111111011011011111111 +1111111111111111111110011111111111111111111111110011111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111001011111101111111 +1111111111111111111111111111111111111111111111111101111110011111111111111111 +11111111111111111111111111111111111111111111111111111111111111100111111111111111 +11111111111111111111111111111111111111111111111111111111111101001000011011111111 +1111111001011111111111111111111111111111111111111110111110011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111110111101001011011111111111 +1111111010111111111111111111111111111111111111111110110111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111110111001111011111111111 +1111111111011111111111111111111111111111111111111111010111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110011111111101001111110101110111 +1111111111101001101111101111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110011111111110001111111001110111 +1111111111100101110111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111001111111111101111 +1111111111111100110011111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110001111111110111111 +1111111111111011111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111111111111111011111111110111111100101111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111110000001111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111110111111111111111111111101111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111011111111111 +1111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111001111011111111111101110111111111111 +1111111111111001011111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111100110111111111111111100011001111111110 +1111110011001101110111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111110111111111111101111011011101111111 +0111110100011101111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111101110110111111111111111101011111111111 +1111111111011011111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111101111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111101011111111111111111110101111001 +0011111010110101010011111111100111101111111100111111111111111111111111111111 +11011111111111111111111111111111111111111011111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111101111111011001111110 +0111111011011100111101101111101101110111111101111111111111111111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111101111011111111111101 +0111110101011010111111011111101001111111111011111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111110011111111111 +1111111111011110110111111111111101111111111111111111111111111111111111111111 +11111111111111111101011111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111101011111111101111011111101011111 +0011111111101101101011111111111110111110100111111111111011111111111111111111 +11111111111111111111011111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110011111111110111001111101110111 +0111111111111101111111111111111111111111111111111111111111111111111111111111 +11111111111111111110111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011011111110111 +1111111111110101110101011111111111110111010101111111111101011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110011111001011111110 +1111111111101001111011111111111111010111111111111111111111011111111111111111 +01111111111111111111111111111111111111110101111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111101011111111110001001111101110011 +1111111100101101111111111111100110110111111111111111111010011111111111111111 +01011111111111111111111111111111111111111001111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111110011111111110001011111001111111 +1011110011000101111111111111101111111111111111111111111100011111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111001111011111111101 +0111110111011001111111111111111101111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111000111001111111111 +1111111111001111111111111111101101001111111111111111111111111111111111111111 +10111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111111101110111111110111 +1111111011101101111111111111111111110111011111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111111001001011101110111 +0111111011011001111111101111111111111111011110111111111111111111111111111111 +11111100111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111101101011111101110111 +1111110111011101111111011111111111111111011101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111101111001101101111 +0111111100000101111111111111111111101110111111111111111111111111111111111111 +01111111111111111111011111111111111111111111111111111111111111111110011111111111 +11111111111111111111111111010111111111111111111101011111111111100111111111111110 +0111001111110100111111111100111111111011101111111111111110011101111111111111 +01011111111111111111111111111111111111111111111111111111111111111111011111111111 +11111111111111111111111111110111111111111111111111011111111101111001011111111111 +0001001111111001111111110100111111111011111111111111111110011101111111111110 +11111100111111111110111111111111111111111111111111111111111111111110111111111111 +11111111111111111111111111111111111111111111111111111111111101111111011111111111 +1111001111111111111111110100111111111101010111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111110111111111111111010011111111111 +1110001111111111011111111100111111111111111111111111111111101011111111111111 +10111111111111111111111111111111111111111111111111111111111111111101011111111111 +11111111111111111111111111111111111111111111111111101111111101001101111110111011 +0011110111110101101111110100111110111011111001111111111011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +11111111111111111111111111111111111111111111111111111111111110010011111111111111 +0110111111011101110111111000111000011111111100111111111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111110110110111111111111 +11111111111111111111111111111111111111111111111111111111111111001111011111010100 +1111111111011111111111111100011111110111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111110111111110001111111111110111 +1111100110011011111111111100111101111101111111111111111111011111111111111111 +01111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111110111111111111111111111011111111110001011111001001111 +1110101101111110111111111000110011111011111111111111111110011111111111111111 +01011111111111111111111111111111111111111111111111111111111111100111111111111111 +11111111111111111111111111111111111111111111111110011111111110001011011100010111 +1110100011111111111111111000001101111111111111111111111110011111111111111110 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111111111111111111001101011110111111 +1111101111001101111111111100111101111011111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111011111111111111101010011011111111 +1110001111111110111111111100111111111011011111111111111111111111111111111111 +10111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111111111111111111111111111001111101001111011 +1111101111101000111111111101111111111110001101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111111111111111111001111000101111111 +1111100011011100111111111101101001111111010100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111101001110111101111101 +0101000111010001010111110101010111111111111001111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111101111111011111111 +1011001100011101111111111101111101111110111110111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111010111111111111111111111001111111111010111111100111111 +0011001001101111010111111100111111111011011111111111111011111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110111111111111111111111110111111101001011111101011111 +0101001011000111110111110110111111111101011111111111111101111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111111101101111111001111011010110111 +1111111110011101111111111100111111111010011111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111110011001001111111110 +1111111011011111101111111000111111111011111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111011111111111001110110101110011 +1111001111101101111111011100111110111111111110111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110001001011001011111 +0111001111111101111111011000111111111111111101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110111111111111001111111110111111 +1110011111101001111010111100111111110111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111001111111110111101 +0111011111100111111111111100111111010111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111110101111011 +1111010111111111111011001000111111111111101101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111110110011011001111011 +0011011011011111111111011000000111111111110100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111100011111111111 +0111001100011111111110011110111101111111101101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110101111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111101 +1111011011011111111001111010111111111111111011111111111111111111111111111111 +11111001111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111110011111111111111111111111001111111111111111111111011 +1111111011101101111011111100111111111001111111111111111111111111111111111111 +11110011111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111101111111111111111111111111101111111111011111111111111 +0111111001110111111111101100111001111101011100111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111101011111111111111111111011111101111101111110110001 +0101001111011100110111010110111111111011001101111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111011111111111111111111111111111101111111111111011 +1111011111111001111101111110111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111110101101111111 +1111011110101001111111111110111111110111111111111111111110011111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111101110011011101111111 +1101001111011101111111110111101111110111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111111111111111101111111111111111 +11111111111111111111111111111111111111111111111111111111111111011001011111111111 +1111100111111111111111110111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111111111111 +11111111111111111111111111111111111111111111111111111111111110011111000011111111 +1111111111010011111111111110110110101111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011111111111111 +1111010111111111111111110110111010111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111110111001111111111111 +1111001111011111111111111111111100011111101011111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111011111111111 +1110001111011111111111111111111111110111110111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111011011111111111 +1111011110111111111111111110111111111111101111111111111111111111111111111111 +11111111111111111111111111111111111111111101111111111111111110110111111111111111 +11111111111111111111111111111111111111111111111111111111111110111010111001010111 +1111001011101111100111111000111111110111110111111111111010011111111111111111 +11111111111111111111111111111111111111111101111111111111111111010111111111111111 +11111111111111111111111111111111111111111111111111111111111110011111011101110111 +0011001001111101110011111100111111101111100111111111111010011111111111111111 +11111111111111111111111111111111111111111111111111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111011111011111111110 +0111000111011111101101111100111111111111111101111111111101011111111111111111 +11111111111111111111111111111111111111101011111111111111111110100111111111111111 +11111111111111111111111111111111111111111111111111111111111110111111111011101111 +1111001111000111111111111100101101111111111111111111111111111111111111111111 +11111111111111111111011111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111101011111111111111110111111111011 +0111111111111111110111111100111111111111111100111111111111111111111111111111 +11111111111111111111011111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111110011111111111111011011111111001 +0111001111111111111111111100111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111101111011111111111111 +0101001111111110100111110100111111111111111111111111111111111111111111111111 +11111111111111111010111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111101011111111100 +1111111111111111111111111110111111111111111111111111111111111111111111111111 +01111111111111111111111111111111001111111111000011111111111111111111101111111111 +11111111111111111111011111111111111011111101111010011101111111010110111101001001 +0011111111111111111111111100111111110110101111111011111011111011110011111011 +01011111111111111111111111111101001111111110110101100111111111111111111111111111 +11111111111111110111111101111111111101111110010011011111111101001001011110110111 +0101111111111111111111110100011111110111011111011111111101111001110111111011 +11111111111111111111111111111111101111111110111111011111111111111111111101111111 +11111111111111111111101001111111111101111101110100001111111111001111011110111111 +0111111111111111111111111100111100110111111111010011111111111111101111111111 +11111111111111111111111111111110101111111110110111111011111111111111100111111111 +11111111111111111011111101111111111101111111100111101101111110010111011011110100 +1110111011011111111111111000111110101111110111110111111111101111111111111111 +10111111111111111111111111111111001111111111011111001111011111111110011101111111 +11101001111111111111100111111111001111111111111011000110101111001011111101101111 +0111111010100111100011111110011011110111111111011011111111111011110111111101 +11111111111111111111111111111110001111111111110110011111101101111111011001111111 +11111101111111111111101100111111011111111111111100110111111110001011111101110111 +0110011011011101100101001110100100101111011110111111111111111101110111111111 +11111111111111111111111111111111101111111111110111111110110101111111001111111111 +11100001111111111110101101110111111101111111111011011101110111001101011111110011 +1111011011000101110011011110101101110111111101110011111111111100111111111101 +11111111111111111111111111111110101111111111111111111011011001111111011111111111 +11111111111111111011111001111111000111111111111111111111011111001111101011111110 +1110111101011111110111111110111101111111011111110111111111111111101111111101 +11111111111111111111111111111110011111111111110111111000110111111110111111111111 +11111111111111111000011011111110111111111111111111111111111110101111111111110111 +0110001011111111111010011011111111111111101011100011001011111101111111111111 +11011111111111111111111111111110011111111111111111111100001111111111111111111111 +11111111111111111100111101111111111111111110111111111111111110000011111111111111 +0010001001011111111011011101111111111111110111110010110111111111111011111110 +11111111111111111111111111111111001111111111111111111100111101111111111111111111 +11111111111111111111011101111111111111111111111111111111110111001111011111111010 +0111000111011111111110011101111111111111111101111010111101011111110111111111 +11111111111111111111111111111111001111111111111111111011101101111111111111111111 +11111111111111111011111101111111111111111111011111111100111110101101111111110111 +1110001110011111111101111111111111111111111111111011110111011111111111111111 +11110011111111111111111111111111011111111101111011011111111111111111011111111111 +11111111111111111110111111111111001101111111110011111110111111101111101001111111 +1111001101111101110001001110101110111111111111110011111011111100111111111111 +11111111111111111111111111111111011111011111111111001111111111111111111110111111 +11111101111111111110111111111111011101111111111111111101110011001001010001110111 +1011000011001101110101011100101101111111011111110001110011111111010011111111 +11111111111111111111111111111101001111111111111101010100111111111111011101111111 +11111111111111110110111111111111000001111111110001011101110101000111111111110111 +0101111111011101110111010100100001010111111111011010110101011100110111111111 +11111111111111111111111111111111001110111011111110011111111111111111111111111111 +11101111111111111110111111111110101111111101110111111011010111101110011111011111 +1111111110101011101110111110111101110110111111111011100111111111111111111111 +01111111111111111111111111111111111111111111110111101100111111111101011111111111 +11111111110111111111111111111111101100110011111111111111110111111111101110110001 +0111010111101111111111001111111110111111111101110010111110011111111111111011 +01011111111111111111111111111101101111111111101111010100011001111111011111111111 +11111111100111111111001111111111110001011111111111111111110001111011001111001010 +0101011001111111111111010110111001111111111100010110111110011111111111111011 +11111111111111111111111111111111101111111111111111110100111101111111111111111111 +11111111111111111111111100110111111101110011111111011111101111110111111100110111 +0101001111010101111110111111111111110111111011100011010111111111111111111111 +11111111111111111111111111111110111111111111111111111100111111111110111111111111 +11111110111111111111110111111111111101100011111111011111111110001100010111111111 +1001111111111101111111111111101101010111111111010011111111111111111111111111 +10111111111111111111111111111111010111111111111111110100111110111111101111111111 +11111111111111111111111110010111111111110011111011011111111111111011111110111011 +1101001101111001101111001100111110110111011111010011111111101111111111111101 +11111111111111111111111111111110001011011111111111111000111101011111111111111111 +11111111111111111111111111010111111111100000111100111111111110111001101111111101 +1110001011111101110111011100101111000111111111100111110111111111111111111111 +11111111111111111111111111111111000101011111111111111100111111110111111101111111 +11111111111111111111111111101111111111110011110011011111111111101111011101011111 +0011001011111111111111111011111111111110111111110010111111111111111111111101 +11111111111111111111111111111111011110011111111111111100011001110111110101111111 +11111111111111111111111111111111111111100011011111111111111111001011011111111111 +1111111111011011111110111111110110111111111111110011100111110111111111111101 +01111111111111111111111111111110001111111111111110011000111111111111111111111111 +11111111111111111111111011111111011101101110111111111110110110111010101111111011 +1110001110111111110110011101111111110111111111100011111111011111111111111111 +01011111111111111111111111111110001111111111111111001000111111111111111111111111 +11111111111111111111111101111111011011101110111111111110110110111011010111100111 +1110101111011111110111001101101001101111111100100111111110111111111111111110 +11111111111111111111111111111111101111111111111111111100111111111111111111111111 +11111111111111111111011111111110111111110111010111111111000111111011011110111101 +0111001111111111101111011101101111111111111111110011111111111111111111111111 +11111111111111111111111111111110101111111111111111111100111111111111111111111111 +11111111111111111111111101111011111111101111111111111110111110111101011110100111 +0111001111111110111111011100110101111111111111110011111111111111111111111111 +10111111111111111111111111111111011111111001110111111101111111110110011111111111 +11111111111111111111101111111101001111111111111111011110000111111111101111110011 +1111001011101111110011001101111111110111111111110011111111111001111111111111 +11111111111111111111111111111111011111111001110111111100101001100111011111111111 +11111111111111111111111001111111011111111110110010111111110011011010010111110111 +1111001011110111110111011101111111110111111111110110111111111101111111111111 +11111111111111111111111111111101111111111111111111110100100111111111111111111111 +11111111111111111111111101111111111101010101011111011111110101111001111101101101 +0001001101001101111101010101111111111111111111011110011111111111111111111111 +11111111111111111111111111111111111111111110101111111101111100111110111111111111 +11111111111111111111111111111110110101111111100111111111111011111111011100111111 +1111001011011110101110011100111110101111111111110011110111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111110111111111111111011111111010111111111101111111000111111111111111 +1111101111101111110111111111011110111001011111110111111111111111110111111011 +11011101111111111111111111111111111011111111111111110110111101111111111111111111 +11111111111111110111111111111110011101010010110111111111111101001111011101111111 +1101001011111111111111111111111111111111011111010010111111111110100111111011 +11111111111111111111111111111111111111111111111111110110111011111111111111111111 +11111111111111111111111111111111111111010010000111111111111111011011001101111111 +1110001101110101111111111111111101110111111111010010111111111111111111111111 +11111101111111111111111111111111111101111111111111111111101101111111111111111111 +11111111111111111011111111111011111101111111110111111011111110001110001111111111 +1101001011011101101111111111101101010100111111010111010111111111111111111111 +11111111111111111111111111111111111011111111111111110101011110111111111111111111 +11111001111111111111010010111110111111011011111011010101111111001111101111111111 +0101000111101001111011011111111011101111111111010001111111011111110111111101 +11111111111111111111111111111111111000011111111111111100101111011111111111111111 +11111001111111111011101101011100011111111011111110101101111110000010011101111110 +0110001001111101111101001111011101110111111111100010110110011110100111111111 +11111111111111111111111111111111111011011111111111111110110101110111111111111111 +11111111111111111111101101111011111111111111111001001011111111001011011101111011 +1111001111011101111111011111111101110111111111110010000011011111111111111101 +11111111111111111111111111111111111111011111111111111111111111110111111111111111 +11111111111111111101111101111011111111101111111111101101111110001101000101111111 +1111001111110001111110011111101101110111111111111111110011111111111111111101 +01111111111111111111111111111111111111111111111111111000100111111111111111111111 +11111111111111111011110001111111101101100011111011111110101110111101111111111010 +1010010110111111111101001111111111111110011110101010001111111111111111111011 +01011111111111111111111111111111111111111111111111111000101101111111111110111111 +11111111111111111011101101111111101100100010110001111111111110001011111111111111 +0110011111011111111111011111111111111111011101100010110111111111111111111011 +11111111111111111111111111111111111111111111111111111100101001111111111101111111 +11111111111111111110101101111111111001110001111111011111110111111111111111111111 +0111111011011111111111011111111111111111111111110011110111111111111111111110 +11111111111111111111111111111111111111111111111111111100111101111111111111111111 +11111111111111111111111101111111110111110011000111111111011110111111111111111101 +1111111111011111111110111111111111111110111111111110110111111111111111111111 +10111101111111111111011111111111111111111111111111011100111110110111101111111111 +11111111111111111111110100110011101100110011111111011111111111111011101001111011 +1111001111101111011111011111101111110111100100111011111111111110110111111101 +11111000111111111111011111111111111111111111111011011100111111110111111111111111 +11111111111111111111101101011101111100111110010111011111111111001010011001111111 +1011001111011101110111011111101101101111111101111011111111111111110111111111 +11111111111111111111111111111111111111111111111110110100111110000111110101111111 +11111111111111110111111000110111110001010011101111111111111101111101011111111101 +0101000111111111111010111111101101111111111101011011111111111110010111111101 +11111111111111111010111111111111111111111111111111111101111110111111101111111111 +11111111111111111111111111101111111111110010110010111111111111111011010111111111 +1111001110000111111111111111110001111111110011111111111111111110101111111111 +11111111111111111111111111111111111111111111111111111111100111111111101011111111 +11111111111111111111110101111111111110011111111111111111111111110100110101111111 +1111001111111011111111111111111111111111111101111110111011111110111111111111 +11111111111111111111111111111111111111111111111111111111101101110111111101111111 +11111111111111110100101111111111111111011110010111111111111101111011011101111111 +1101001001111101111111110110111111111111111101111110011111111111111111111111 +11111011111111111111111111111111111111111111111111111111101001111111101111111111 +11111111111111111100101101111111101111111110101111111111111101101111011011111111 +1101001111111111111111110110111111110111101111111110110101011110111111111111 +11111101111111111111111111111111111111111111111111111111111100111111111111111111 +11111111111111111000111101111111111111101111110111111111111111111111111111111111 +1111001111111111111111111100111111110111111011111111110111011111111111111111 +11111111111111111111111111111111111111011001101111111111111010111111111111111111 +11101111111111111111111111110100011111111011101111111111111101110111111100011111 +1101001001101110111111110111111110111111011111111101011011111111111110111111 +11111111111111111111111111111111111011011101110111111111111101111010011101111111 +11111111111111111000111110111011011111101111110011111111111110111001011110011111 +1110001011011111111111111010101101111111011111111110111101111111111101111111 +11111111111111111111111111111111111111011111111111111111111111110110101011111111 +11110101111111111100111111110111111111111110111111011110111111111110001100111111 +1111001010011110111111111110011110110110111111111111110111011111111110011111 +11111111111111111111111111111111110100011011111111111111111111010001111101111111 +11111101111111111100111111101011111111111111110111111111110110111011011010111111 +1111001111010110110111111100110001011011111111111110110111011111111111111111 +11111111111111111111111111111111111111111111110111011111111111111111011111111111 +11111111111111111011111011111111011111101101111011111111111110000111111111110111 +1110111110111011100101111000111011111011111111111111111111111001011111111111 +11111111111111111111111111111111111111111111111111011111111111111111110111111111 +11111111111111111011111101111110111111101111100111111111111110001110011111111111 +1110011111011101110001111000111101111111111111111111111111111100011111111111 +11111111111111111111111111111111111111111111111011111111111111111111111101111111 +11111111111111111101111111111111111111111111110101011111111111001111011111101111 +0111111111111111111111011110011111111001011111111111111111111111110111111111 +11111111111111111111111111111111111111111111101110111111111111111110111111111111 +11111111111111111001111111111111111111101110110111011111111111001111111111111011 +1111110111011111101111111110111101111111111111111111111111111011111111111111 +11111111111111111111111111111111111111011101111111111111111101111111111001111111 +11101101111111111111010111100111111111110011111011001111111111001111111101111110 +0111111110111000111111111110111111111111111111111110111111111100110111111111 +11111111111111111111011111111111111011011011111111111111101101111111111101111111 +11111101111111111111101101100011101111111111111111011111111111011111111111111101 +0111111111011000111011111110111111111111111110111110011111111111110111111111 +11111111111111111111111111111111111111011111111111111111011101111111111111111111 +11101001111111110101011101111111011101011111111011011111111101001111111111111111 +0101111111111111010111010110111111111111011101111111110011011011111111111111 +11111111111111111011111111111111110100011111111111111111110001111111111101111111 +11100111111111111111111001111111100111111111111000110111111111001111111011111111 +0111111111111111111001111110111111111111011111111110110111111111101111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111101111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111101111111111111101111111111111111110111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111101111111 +1111110111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111101111111111111111111111111111111111 +11111111111111111111111111111111111111010111111111111111111111111111110101111111 +1111111111111111111111111111111111010111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111101011111111111111111111111111111 +1111110111110111111111111111111111010111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111101111111111111111011111111111111011111111 +1111111111110011111111111111111111101111111111111111111111111111111111111111 +11111111111111111111111111111110111111111111111111111111111111001111111111111111 +11111111111111111111111111111111111111111111111110111111101111111111110011111111 +1111111111111011111111111111111111101111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111011111111111111111111111111111110111111101 +1111111111110111111101111111111111011111111111111111111111111111111111111111 +11111111111111111111111111111101011111111111111111111111111111011111111111111111 +11111111111111111111111111010111111111111111111101110011111111111111110111001111 +1111111111110101101111111111111111011100101111111111111111111011111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111110111111111111111111111111111111101101 +1111111111111111101101111111111111111110111111111111111111111010111111111111 +11111111111111111111111111111111111111111111111111111111111111011111111111111111 +11111111111111111111111111111111111111111111111111110110111111111111111111010111 +1111111111111111100011111111111111111101011111111111111111111001111111111111 +11111111111110011111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111110001111111111111111111111111111110111 +1111111111111111100011111111111111111111111111111111111111111101111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111101011 +1111111111111111111111111111111111111110111111111111111111111111111111111111 +11111111111011111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111101011 +1111111111111111111111111111111111111111100111111111111111111011111111111111 +11111111110111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111111111111111111111111110111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +11111111111111111111111111111111111111111111111111111111111111111111111111111111 +1111111111111111111111111111111111111111110111111111111111111111111111111111 +11111111111111111111111110111100111111111101011110111111111111111111101111111111 +11111111111011111111111111111111101111111111111111111110111111111111111111111011 +1111111111111111111011111111111111111111101111111111111111111110111111111111 +11111111111111111111111110111100111111111101001111110011111111110101111011111111 +11111111111011110011111111110101111011001111111111010110011100111111111101011010 +1100111111111101011010110011111111110101100111001111111111010111011111111111 +11111111001111111111010111011100111111111101001111111111111111111111101111111111 +11111111111011111111111111111111101111001111111111010110011111111111111111111011 +1111111111111111111011111111111111111111101111111111111111111110111111111111 +11111111001111111111011110111100111111111101111011111111111111111111101111111111 +11111111111011111111111111111111101111111111111111111110111100111111111101011010 +1100111111111101011010110011111111110101100111001111111111010111011111111111 +* +C2594* +N User Electronic Signature Data* +U00000000000000000000000000000000* +451D diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log new file mode 100644 index 0000000..d0353b8 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.log @@ -0,0 +1,4 @@ +---- MParTrce Tool Log File ---- + +==== Par Standard Out ==== +==== End of Par Standard Out ==== diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf new file mode 100644 index 0000000..2743d95 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf @@ -0,0 +1,4 @@ +#BLOCK ASYNCPATHS; +#BLOCK RESETPATHS; + +#FREQUENCY 200.000000 MHz; diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lsedata b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lsedata new file mode 100644 index 0000000..0f0f220 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lsedata @@ -0,0 +1,6331 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp new file mode 100644 index 0000000..e44642b --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mrp @@ -0,0 +1,336 @@ + + Lattice Mapping Report File for Design Module 'RAM2GS' + + +Design Information +------------------ + +Command line: map -a MachXO -p LCMXO640C -t TQFP100 -s 3 -oc Commercial + RAM2GS_LCMXO640C_impl1.ngd -o RAM2GS_LCMXO640C_impl1_map.ncd -pr + RAM2GS_LCMXO640C_impl1.prf -mp RAM2GS_LCMXO640C_impl1.mrp -lpf D:/OneDrive/ + Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf + -lpf + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf -c + 0 -gui -msgset + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml +Target Vendor: LATTICE +Target Device: LCMXO640CTQFP100 +Target Performance: 3 +Mapper: mj5g00, version: Diamond (64-bit) 3.12.1.454 +Mapped on: 08/15/23 05:03:22 + +Design Summary +-------------- + + Number of PFU registers: 102 out of 640 (16%) + Number of SLICEs: 71 out of 320 (22%) + SLICEs as Logic/ROM: 71 out of 320 (22%) + SLICEs as RAM: 0 out of 192 (0%) + SLICEs as Carry: 9 out of 320 (3%) + Number of LUT4s: 142 out of 640 (22%) + Number used as logic LUTs: 124 + Number used as distributed RAM: 0 + Number used as ripple logic: 18 + Number used as shift registers: 0 + Number of external PIOs: 67 out of 74 (91%) + Number of GSRs: 0 out of 1 (0%) + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + Number of TSALL: 0 out of 1 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of + distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and + ripple logic. + Number of clocks: 4 + Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Number of Clock Enables: 13 + Net PHI2_N_120_enable_4: 1 loads, 1 LSLICEs + Net RCLK_c_enable_4: 3 loads, 3 LSLICEs + Net RCLK_c_enable_23: 8 loads, 8 LSLICEs + Net RCLK_c_enable_12: 1 loads, 1 LSLICEs + Net RCLK_c_enable_3: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_5: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_6: 2 loads, 2 LSLICEs + Net RCLK_c_enable_24: 2 loads, 2 LSLICEs + Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs + Net Ready_N_292: 1 loads, 1 LSLICEs + + Page 1 + + + + +Design: RAM2GS Date: 08/15/23 05:03:22 + +Design Summary (cont) +--------------------- + Net RCLK_c_enable_11: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_25: 1 loads, 1 LSLICEs + Number of LSRs: 9 + Net RASr2: 1 loads, 1 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net C1Submitted_N_237: 2 loads, 2 LSLICEs + Net n2469: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net n1846: 2 loads, 2 LSLICEs + Net LEDEN_N_82: 1 loads, 1 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Net nRWE_N_177: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 23 loads + Net InitReady: 17 loads + Net RASr2: 14 loads + Net nRowColSel: 13 loads + Net MAin_c_0: 12 loads + Net nRowColSel_N_35: 12 loads + Net Din_c_3: 11 loads + Net Din_c_6: 11 loads + Net MAin_c_1: 11 loads + Net Din_c_4: 10 loads + + + + + Number of warnings: 0 + Number of errors: 0 + + +Design Errors/Warnings +---------------------- + + No errors or warnings present. + +IO (PIO) Attributes +------------------- + ++---------------------+-----------+-----------+------------+------------+ +| IO Name | Direction | Levelmode | IO | FIXEDDELAY | +| | | IO_TYPE | Register | | ++---------------------+-----------+-----------+------------+------------+ +| RD[7] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[6] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[5] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[4] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[3] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[2] | BIDIR | LVCMOS33 | | | + + Page 2 + + + + +Design: RAM2GS Date: 08/15/23 05:03:22 + +IO (PIO) Attributes (cont) +-------------------------- ++---------------------+-----------+-----------+------------+------------+ +| RD[1] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RD[0] | BIDIR | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[7] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[6] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[5] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[4] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[3] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[2] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[1] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Dout[0] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| LED | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RBA[1] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RBA[0] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[11] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[10] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[9] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[8] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[7] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[6] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[5] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[4] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[3] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[2] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[1] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RA[0] | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRCS | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RCKE | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRWE | OUTPUT | LVCMOS33 | | | + + Page 3 + + + + +Design: RAM2GS Date: 08/15/23 05:03:22 + +IO (PIO) Attributes (cont) +-------------------------- ++---------------------+-----------+-----------+------------+------------+ +| nRRAS | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nRCAS | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RDQMH | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RDQML | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nUFMCS | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMCLK | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMSDI | OUTPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| PHI2 | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[9] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[8] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[7] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[6] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[5] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[4] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[3] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[2] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[1] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| MAin[0] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| CROW[1] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| CROW[0] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[7] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[6] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[5] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[4] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[3] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[2] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[1] | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| Din[0] | INPUT | LVCMOS33 | | | + + Page 4 + + + + +Design: RAM2GS Date: 08/15/23 05:03:22 + +IO (PIO) Attributes (cont) +-------------------------- ++---------------------+-----------+-----------+------------+------------+ +| nCCAS | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nCRAS | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| nFWE | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| RCLK | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ +| UFMSDO | INPUT | LVCMOS33 | | | ++---------------------+-----------+-----------+------------+------------+ + +Removed logic +------------- + +Block i2 undriven or does not drive anything - clipped. +Block GSR_INST undriven or does not drive anything - clipped. +Signal nCRAS_N_9 was merged into signal nCRAS_c +Signal nCCAS_N_3 was merged into signal nCCAS_c +Signal PHI2_N_120 was merged into signal PHI2_c +Signal RASr2_N_63 was merged into signal RASr2 +Signal n1426 was merged into signal nRowColSel_N_35 +Signal nRWE_N_176 was merged into signal nRWE_N_177 +Signal n1425 was merged into signal nRowColSel_N_34 +Signal nFWE_N_5 was merged into signal nFWE_c +Signal n2477 was merged into signal Ready +Signal GND_net undriven or does not drive anything - clipped. +Signal VCC_net undriven or does not drive anything - clipped. +Signal FS_610_add_4_18/CO1 undriven or does not drive anything - clipped. +Signal FS_610_add_4_18/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_10/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_4/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_12/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_2/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_14/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_6/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_16/CO0 undriven or does not drive anything - clipped. +Signal FS_610_add_4_8/CO0 undriven or does not drive anything - clipped. +Block i2135 was optimized away. +Block i2134 was optimized away. +Block i2136 was optimized away. +Block RASr2_I_0_1_lut was optimized away. +Block i1137_1_lut was optimized away. +Block nRWE_I_50_1_lut was optimized away. +Block i1136_1_lut was optimized away. +Block i1_1_lut was optimized away. +Block i637_1_lut_rep_34 was optimized away. +Block i1 was optimized away. + +Run Time and Memory Usage +------------------------- + + Total CPU Time: 0 secs + Total REAL Time: 0 secs + Peak Memory Usage: 30 MB + + + Page 5 + + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. + Copyright (c) 1995 AT&T Corp. All rights reserved. + Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. + Copyright (c) 2001 Agere Systems All rights reserved. + Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights + reserved. diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt new file mode 100644 index 0000000..2d70ad1 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.mt @@ -0,0 +1,9 @@ +-v +1 + + +-gt + + +-mapchkpnt 0 +-sethld diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e new file mode 100644 index 0000000..737af10 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.n2e @@ -0,0 +1,596 @@ + +comp 0: SLICE_0 (FSLICE) + +comp 1: SLICE_1 (FSLICE) + +comp 2: SLICE_2 (FSLICE) + +comp 3: SLICE_3 (FSLICE) + +comp 4: SLICE_4 (FSLICE) + +comp 5: SLICE_5 (FSLICE) + +comp 6: SLICE_6 (FSLICE) + +comp 7: SLICE_7 (FSLICE) + +comp 8: SLICE_8 (FSLICE) + +comp 9: SLICE_9 (FSLICE) +n1413 = (~n2263*(~ADSubmitted*n2242+ADSubmitted*(~n2459+n2242))+n2263*(ADSubmitted*~n2459)) +ADSubmitted.D = n1413 +ADSubmitted.CLK = ~PHI2_c +ADSubmitted.SP = VCC +ADSubmitted.LSR = C1Submitted_N_237 +n2263 = (~MAin_c_1+(~MAin_c_0+n1326)) + +comp 10: SLICE_14 (FSLICE) +n6_adj_3 = (~MAin_c_1*C1Submitted+MAin_c_1*(C1Submitted*(nFWE_c+n1326))) +C1Submitted.D = n6_adj_3 +C1Submitted.CLK = ~PHI2_c +C1Submitted.SP = VCC +C1Submitted.LSR = C1Submitted_N_237 +n2284 = (C1Submitted+Din_c_6) + +comp 11: SLICE_18 (FSLICE) +CmdEnable_N_248 = (n15*(~n1326*(n2463*MAin_c_1))) +CmdEnable.D = CmdEnable_N_248 +CmdEnable.CLK = ~PHI2_c +CmdEnable.SP = PHI2_N_120_enable_7 +CmdEnable.LSR = GND +n1326 = (~MAin_c_5+(~n2316+(~MAin_c_2+n26))) + +comp 12: SLICE_19 (FSLICE) +n2568\001/BUF1 = VCC +CmdSubmitted.D = n2568\001/BUF1 +CmdSubmitted.CLK = ~PHI2_c +CmdSubmitted.SP = PHI2_N_120_enable_5 +CmdSubmitted.LSR = GND +n2472 = (~PHI2r2*(CmdSubmitted*PHI2r3)) + +comp 13: SLICE_23 (FSLICE) +Cmdn8MEGEN_N_264 = (~n1314*(~Din_c_4*n8MEGEN+Din_c_4*~Din_c_0)+n1314*n8MEGEN) +Cmdn8MEGEN.D = Cmdn8MEGEN_N_264 +Cmdn8MEGEN.CLK = ~PHI2_c +Cmdn8MEGEN.SP = PHI2_N_120_enable_4 +Cmdn8MEGEN.LSR = GND +n1314 = ((Din_c_6+Din_c_7)+Din_c_5) + +comp 14: SLICE_25 (FSLICE) +n2568\000/BUF1 = VCC +InitReady.D = n2568\000/BUF1 +InitReady.CLK = RCLK_c +InitReady.SP = RCLK_c_enable_25 +InitReady.LSR = GND +RCLK_c_enable_23 = (nRowColSel_N_35*(RASr2*(InitReady*~Ready))) + +comp 15: SLICE_26 (FSLICE) +n2568 = VCC +LEDEN.D = n2568 +LEDEN.CLK = RCLK_c +LEDEN.SP = RCLK_c_enable_12 +LEDEN.LSR = GND +LED_N_84 = ((~LEDEN+CBR)+nCRAS_c) + +comp 16: SLICE_31 (FSLICE) +n2209 = ((n2208+Ready)+nRCAS_N_165) +RA_0.D = n2209 +RA_0.CLK = RCLK_c +RA_0.SP = VCC +RA_0.LSR = ~nRWE_N_177 +n56 = (~Ready+nRowColSel_N_34) + +comp 17: SLICE_32 (FSLICE) +RA11_N_184 = (~n8MEGEN*(XOR8MEG@Din_c_6)+n8MEGEN*XOR8MEG) +RA_c.D = RA11_N_184 +RA_c.CLK = PHI2_c +RA_c.SP = VCC +RA_c.LSR = ~Ready +n2478 = (Din_c_6+Din_c_7) + +comp 18: SLICE_34 (FSLICE) +RCKEEN_N_121 = (~Ready*InitReady+Ready*RCKEEN_N_122) +RCKEEN.D = RCKEEN_N_121 +RCKEEN.CLK = RCLK_c +RCKEEN.SP = RCLK_c_enable_4 +RCKEEN.LSR = GND +n2467 = ((InitReady*RASr2)+Ready) + +comp 19: SLICE_35 (FSLICE) +RCKE_N_132 = (~RASr3*(~RASr2*(RCKEEN*RASr)+RASr2*RCKEEN)+RASr3*(~RASr2+RCKEEN)) +RCKE_c.D = RCKE_N_132 +RCKE_c.CLK = RCLK_c +RCKE_c.SP = VCC +RCKE_c.LSR = GND +nRWE_N_182 = (~RCKE_c+RASr2) +CASr2.D = CASr +CASr2.CLK = RCLK_c +CASr2.SP = VCC +CASr2.LSR = GND + +comp 20: SLICE_36 (FSLICE) +n2568\002/BUF1 = VCC +Ready.D = n2568\002/BUF1 +Ready.CLK = RCLK_c +Ready.SP = Ready_N_292 +Ready.LSR = GND +n2469 = (~Ready+nRowColSel_N_35) + +comp 21: SLICE_43 (FSLICE) +UFMCLK_N_224 = (~InitReady*n1160+InitReady*CmdUFMCLK) +UFMCLK_c.D = UFMCLK_N_224 +UFMCLK_c.CLK = RCLK_c +UFMCLK_c.SP = RCLK_c_enable_24 +UFMCLK_c.LSR = n1846 +n1160 = (~FS_1*(~n2462*FS_4)+FS_1*(~n2462*FS_4+n2462*~n62)) + +comp 22: SLICE_44 (FSLICE) +UFMSDI_N_231 = (~CmdUFMSDI*(~InitReady*(~n2462*n2461))+CmdUFMSDI*((~n2462*n2461)+InitReady)) +UFMSDI_c.D = UFMSDI_N_231 +UFMSDI_c.CLK = RCLK_c +UFMSDI_c.SP = RCLK_c_enable_24 +UFMSDI_c.LSR = n1846 +n2462 = (~FS_11+((n2471+n2272)+n2470)) + +comp 23: SLICE_49 (FSLICE) +XOR8MEG_N_110 = (~n2324*(Din_c_2*(~Din_c_3*Din_c_0))) +XOR8MEG.D = XOR8MEG_N_110 +XOR8MEG.CLK = ~PHI2_c +XOR8MEG.SP = PHI2_N_120_enable_1 +XOR8MEG.LSR = GND +n2324 = (~Din_c_1*(Din_c_4+n1314)+Din_c_1*((Din_c_4+LEDEN)+n1314)) + +comp 24: SLICE_56 (FSLICE) +n8MEGEN_N_91 = (~n1325*(~InitReady*~UFMSDO_c+InitReady*Cmdn8MEGEN)+n1325*Cmdn8MEGEN) +n8MEGEN.D = n8MEGEN_N_91 +n8MEGEN.CLK = RCLK_c +n8MEGEN.SP = RCLK_c_enable_11 +n8MEGEN.LSR = GND +n1325 = (~FS_10+(~FS_11+n2464)) + +comp 25: SLICE_58 (FSLICE) +nRCAS_N_161 = (((~CBR*Ready)+(n2427*~Ready)+(n2427*~CBR)+~RASr2)*nRowColSel_N_35)+((nRowColSel_N_34+~n15_adj_1+~Ready)*~nRowColSel_N_35) +nRCAS_c.D = nRCAS_N_161 +nRCAS_c.CLK = RCLK_c +nRCAS_c.SP = RCLK_c_enable_4 +nRCAS_c.LSR = GND + +comp 26: SLICE_60 (FSLICE) +nRCS_N_136 = (~nRowColSel_N_35*(~n2467+n2481)+nRowColSel_N_35*(~n13+n2481)) +nRCS_c.D = nRCS_N_136 +nRCS_c.CLK = RCLK_c +nRCS_c.SP = RCLK_c_enable_4 +nRCS_c.LSR = GND +n13 = (~Ready*(InitReady*RASr2)+Ready*(RASr2+RCKE_c)) + +comp 27: SLICE_61 (FSLICE) +n2138 = (((nRCS_N_139*~Ready)+~n13)*nRowColSel_N_35)+((n56+nRRAS_c+n6+nRowColSel_N_32)*~nRowColSel_N_35) +nRRAS_c.D = n2138 +nRRAS_c.CLK = RCLK_c +nRRAS_c.SP = VCC +nRRAS_c.LSR = GND + +comp 28: SLICE_63 (FSLICE) +nRWE_N_171 = (~n2208*(~Ready*~n33+Ready*nRWE_N_178)+n2208*(~Ready+nRWE_N_178)) +nRWE_c.D = nRWE_N_171 +nRWE_c.CLK = RCLK_c +nRWE_c.SP = RCLK_c_enable_3 +nRWE_c.LSR = GND +n2208 = ((~InitReady+(~RASr2+~nRowColSel_N_35))+nRCS_N_139) + +comp 29: SLICE_64 (FSLICE) +n1410 = (~nRowColSel_N_32*(nRowColSel+n1502)+nRowColSel_N_32*(~nRowColSel_N_28+n1502)) +nRowColSel.D = n1410 +nRowColSel.CLK = RCLK_c +nRowColSel.SP = VCC +nRowColSel.LSR = n2469 +RA_1_9 = (~nRowColSel*RowA_9+nRowColSel*MAin_c_9) + +comp 30: SLICE_65 (FSLICE) +n1503 = (nRowColSel_N_32+nRowColSel_N_33) +nRowColSel_N_32.D = n1503 +nRowColSel_N_32.CLK = RCLK_c +nRowColSel_N_32.SP = VCC +nRowColSel_N_32.LSR = ~RASr2 +n2414 = (InitReady*(Ready_N_296*(~RASr2*nRowColSel_N_32))) + +comp 31: SLICE_66 (FSLICE) +n1093 = (RASr2*~nRowColSel_N_32) +nRowColSel_N_33.D = n1093 +nRowColSel_N_33.CLK = RCLK_c +nRowColSel_N_33.SP = VCC +nRowColSel_N_33.LSR = ~nRowColSel_N_34 +RCLK_c_enable_4 = (((nRowColSel_N_32+n2469)+nRowColSel_N_34)+nRowColSel_N_33) + +comp 32: SLICE_67 (FSLICE) +n11 = (~CASr2+nRowColSel_N_33) +nRowColSel_N_34.D = n1093 +nRowColSel_N_34.CLK = RCLK_c +nRowColSel_N_34.SP = VCC +nRowColSel_N_34.LSR = ~nRowColSel_N_35 +n1417 = (~n2472*nUFMCS_c+n2472*~CmdUFMCS) + +comp 33: SLICE_68 (FSLICE) +n2322 = (((FS_0+FS_1)+FS_6)+FS_3) +nRowColSel_N_35.D = ~RASr2 +nRowColSel_N_35.CLK = RCLK_c +nRowColSel_N_35.SP = VCC +nRowColSel_N_35.LSR = GND +n2471 = (FS_17+FS_12) +CASr3.D = CASr2 +CASr3.CLK = RCLK_c +CASr3.SP = VCC +CASr3.LSR = GND + +comp 34: SLICE_69 (FSLICE) +n2164 = (~InitReady*n62+InitReady*n1417) +nUFMCS_c.D = n2164 +nUFMCS_c.CLK = RCLK_c +nUFMCS_c.SP = VCC +nUFMCS_c.LSR = LEDEN_N_82 +n62 = (FS_14*(FS_12*(n12*FS_17))) + +comp 35: RCKEEN_I_0_445/SLICE_70 (FSLICE) +RCKEEN_N_122 = (((~FWEr*~CBR)+~RASr2)*nRowColSel_N_35)+(((FWEr*n11*~CBR)+(nRowColSel_N_34*~CBR))*~nRowColSel_N_35) + +comp 36: i26/SLICE_71 (FSLICE) +n13_adj_2 = ((~n2284*n2476*MAin_c_1*MAin_c_0)*Din_c_2)+((~ADSubmitted*~MAin_c_0*n2475*~Din_c_5)*~Din_c_2) + +comp 37: i2099/SLICE_72 (FSLICE) +n2481 = (((nRowColSel_N_35*~Ready*nRCS_N_139)+(nRowColSel_N_34*~Ready*nRCS_N_139)+(~nRowColSel_N_35*~Ready)+(nRowColSel_N_34*~nRowColSel_N_35))*n15_adj_1)+(((~Ready*nRCS_N_139)+~nRowColSel_N_35)*~n15_adj_1) + +comp 38: i26_adj_28/SLICE_73 (FSLICE) +n15 = ((MAin_c_0*Din_c_2*Din_c_3*~Din_c_6)*Din_c_5)+((~MAin_c_0*~Din_c_2*~Din_c_3*Din_c_6)*~Din_c_5) + +comp 39: SLICE_74 (FSLICE) +n1 = (~CASr3*(CASr2*(FWEr*~CBR))) +RASr2.D = RASr +RASr2.CLK = RCLK_c +RASr2.SP = VCC +RASr2.LSR = GND +n15_adj_1 = (~n1*(nRowColSel_N_33*(~CBR*~FWEr))+n1*(~nRowColSel_N_33+(~CBR*~FWEr))) +RASr3.D = RASr2 +RASr3.CLK = RCLK_c +RASr3.SP = VCC +RASr3.LSR = GND + +comp 40: SLICE_75 (FSLICE) +n2214 = (FS_11*(~n2272*(~n2328*FS_10))) +RCLK_c_enable_12 = (~InitReady*(FS_11*n2214)) + +comp 41: SLICE_76 (FSLICE) +PHI2_N_120_enable_4 = (n2458*(~Din_c_4*~Din_c_5+Din_c_4*(~Din_c_5+Din_c_3))) +n732.D = n733 +n732.CLK = RCLK_c +n732.SP = RCLK_c_enable_23 +n732.LSR = GND +n2458 = (MAin_c_0*(n10*(~n1326*~nFWE_c))) +nRWE_N_177.D = n732 +nRWE_N_177.CLK = RCLK_c +nRWE_N_177.SP = RCLK_c_enable_23 +nRWE_N_177.LSR = GND + +comp 42: SLICE_77 (FSLICE) +n2290 = ((FS_2+FS_5)+FS_9) +n728.D = n729 +n728.CLK = RCLK_c +n728.SP = RCLK_c_enable_23 +n728.LSR = GND +n8 = (~FS_7*(~n2322*(FS_4*~n2290))) +n727.D = n728 +n727.CLK = RCLK_c +n727.SP = RCLK_c_enable_23 +n727.LSR = GND + +comp 43: SLICE_78 (FSLICE) +n1846 = (~InitReady*(~n2464*~FS_11)) +RowA_6.D = MAin_c_6 +RowA_6.CLK = ~nCRAS_c +RowA_6.SP = VCC +RowA_6.LSR = ~Ready +n2464 = (((FS_16+FS_14)+n2272)+n2471) +RowA_7.D = MAin_c_7 +RowA_7.CLK = ~nCRAS_c +RowA_7.SP = VCC +RowA_7.LSR = ~Ready + +comp 44: SLICE_79 (FSLICE) +C1Submitted_N_237 = (n2468*(~n1280*(n2463*~Din_c_2))) +CASr.D = ~nCCAS_c +CASr.CLK = RCLK_c +CASr.SP = VCC +CASr.LSR = GND +n2468 = (~Din_c_5*(~Din_c_3*Din_c_6)) +PHI2r2.D = PHI2r +PHI2r2.CLK = RCLK_c +PHI2r2.SP = VCC +PHI2r2.LSR = GND + +comp 45: SLICE_80 (FSLICE) +RCLK_c_enable_3 = (((~Ready+nRowColSel_N_32)+n1502)+nRowColSel_N_35) +n726.D = n727 +n726.CLK = RCLK_c +n726.SP = RCLK_c_enable_23 +n726.LSR = GND +n1502 = (nRowColSel_N_34+nRowColSel_N_33) +Ready_N_296.D = n726 +Ready_N_296.CLK = RCLK_c +Ready_N_296.SP = RCLK_c_enable_23 +Ready_N_296.LSR = GND + +comp 46: SLICE_81 (FSLICE) +n26 = (~Bank_5+(~n2278+(~n2314+Bank_2))) +CmdUFMCLK.D = Din_c_1 +CmdUFMCLK.CLK = ~PHI2_c +CmdUFMCLK.SP = PHI2_N_120_enable_6 +CmdUFMCLK.LSR = GND +n2278 = (Bank_3*Bank_6) +CmdUFMCS.D = Din_c_2 +CmdUFMCS.CLK = ~PHI2_c +CmdUFMCS.SP = PHI2_N_120_enable_6 +CmdUFMCS.LSR = GND + +comp 47: SLICE_82 (FSLICE) +n2460 = (nFWE_c+n1326) +n730.D = nRWE_N_177 +n730.CLK = RCLK_c +n730.SP = RCLK_c_enable_23 +n730.LSR = GND +PHI2_N_120_enable_7 = (~MAin_c_1*(~n14*(~n2460*MAin_c_0))+MAin_c_1*(~n14*~n2460)) +n729.D = n730 +n729.CLK = RCLK_c +n729.SP = RCLK_c_enable_23 +n729.LSR = GND + +comp 48: SLICE_83 (FSLICE) +n10 = (~MAin_c_1*(CmdEnable*(~n2478*Din_c_4))) +RASr.D = ~nCRAS_c +RASr.CLK = RCLK_c +RASr.SP = VCC +RASr.LSR = GND +PHI2_N_120_enable_6 = (n2476*(~n2460*(n10*MAin_c_0))) + +comp 49: SLICE_84 (FSLICE) +n2262 = ((~MAin_c_0+n1326)+MAin_c_1) +n738.D = nRCAS_N_165 +n738.CLK = RCLK_c +n738.SP = RCLK_c_enable_23 +n738.LSR = GND +PHI2_N_120_enable_1 = (~n1314*(~n2262*(CmdEnable*~n2473))) +n737.D = n738 +n737.CLK = RCLK_c +n737.SP = RCLK_c_enable_23 +n737.LSR = GND + +comp 50: SLICE_85 (FSLICE) +n2473 = (Din_c_4+nFWE_c) +RBA_c_0.D = CROW_c_0 +RBA_c_0.CLK = ~nCRAS_c +RBA_c_0.SP = VCC +RBA_c_0.LSR = ~Ready +n2242 = (n2474*(Din_c_5*(n2253*~n2473))) +RBA_c_1.D = CROW_c_1 +RBA_c_1.CLK = ~nCRAS_c +RBA_c_1.SP = VCC +RBA_c_1.LSR = ~Ready + +comp 51: SLICE_86 (FSLICE) +n2463 = (n2253*(~nFWE_c*~Din_c_4)) +n734.D = n735 +n734.CLK = RCLK_c +n734.SP = RCLK_c_enable_23 +n734.LSR = GND +n2253 = (~Din_c_1*(Din_c_0*Din_c_7)) +n733.D = n734 +n733.CLK = RCLK_c +n733.SP = RCLK_c_enable_23 +n733.LSR = GND + +comp 52: SLICE_87 (FSLICE) +RCLK_c_enable_11 = (~n8*(InitReady*n2472)+n8*(~InitReady*n7+InitReady*n2472)) +nRCS_N_139.D = Ready_N_296 +nRCS_N_139.CLK = RCLK_c +nRCS_N_139.SP = RCLK_c_enable_23 +nRCS_N_139.LSR = GND +n7 = (n2214*~FS_8) +nRCAS_N_165.D = nRCS_N_139 +nRCAS_N_165.CLK = RCLK_c +nRCAS_N_165.SP = RCLK_c_enable_23 +nRCAS_N_165.LSR = GND + +comp 53: SLICE_88 (FSLICE) +n2451 = (~FS_8*(~FS_5*(~FS_9*FS_7)+FS_5*(FS_9@FS_7))) +Bank_0.D = Din_c_0 +Bank_0.CLK = PHI2_c +Bank_0.SP = VCC +Bank_0.LSR = GND +n2461 = (~FS_10*(FS_6*n2451)) +Bank_1.D = Din_c_1 +Bank_1.CLK = PHI2_c +Bank_1.SP = VCC +Bank_1.LSR = GND + +comp 54: SLICE_89 (FSLICE) +n1280 = ((~MAin_c_1+n1326)+MAin_c_0) +WRD_0.D = Din_c_0 +WRD_0.CLK = ~nCCAS_c +WRD_0.SP = VCC +WRD_0.LSR = GND +n2459 = (MAin_c_1*(~n1326*~nFWE_c)) +WRD_1.D = Din_c_1 +WRD_1.CLK = ~nCCAS_c +WRD_1.SP = VCC +WRD_1.LSR = GND + +comp 55: SLICE_90 (FSLICE) +n2470 = (FS_16+FS_14) +RowA_8.D = MAin_c_8 +RowA_8.CLK = ~nCRAS_c +RowA_8.SP = VCC +RowA_8.LSR = ~Ready +n2328 = (((FS_17+FS_12)+FS_14)+FS_16) +RowA_9.D = MAin_c_9 +RowA_9.CLK = ~nCRAS_c +RowA_9.SP = VCC +RowA_9.LSR = ~Ready + +comp 56: SLICE_91 (FSLICE) +PHI2_N_120_enable_5 = (n2458*(~Din_c_5*Din_c_4+Din_c_5*(Din_c_4*Din_c_3))) +PHI2r3.D = PHI2r2 +PHI2r3.CLK = RCLK_c +PHI2r3.SP = VCC +PHI2r3.LSR = GND +n2476 = (Din_c_5*Din_c_3) +PHI2r.D = PHI2_c +PHI2r.CLK = RCLK_c +PHI2r.SP = VCC +PHI2r.LSR = GND + +comp 57: SLICE_92 (FSLICE) +n2474 = (Din_c_3*(Din_c_2*~Din_c_6)) +WRD_6.D = Din_c_6 +WRD_6.CLK = ~nCCAS_c +WRD_6.SP = VCC +WRD_6.LSR = GND +n2475 = (~Din_c_3*Din_c_6) +WRD_7.D = Din_c_7 +WRD_7.CLK = ~nCCAS_c +WRD_7.SP = VCC +WRD_7.LSR = GND + +comp 58: SLICE_93 (FSLICE) +RDQMH_c = (~nRowColSel+MAin_c_9) +CmdUFMSDI.D = Din_c_0 +CmdUFMSDI.CLK = ~PHI2_c +CmdUFMSDI.SP = PHI2_N_120_enable_6 +CmdUFMSDI.LSR = GND +RDQML_c = (~nRowColSel+~MAin_c_9) + +comp 59: SLICE_94 (FSLICE) +n12 = (FS_11*(FS_16*(FS_13*FS_15))) +n2272 = (FS_13+FS_15) + +comp 60: SLICE_95 (FSLICE) +LEDEN_N_82 = (~InitReady*(~FS_10*(~n2464*~FS_11))) +RowA_4.D = MAin_c_4 +RowA_4.CLK = ~nCRAS_c +RowA_4.SP = VCC +RowA_4.LSR = ~Ready +RCLK_c_enable_25 = (FS_10*n62) +RowA_5.D = MAin_c_5 +RowA_5.CLK = ~nCRAS_c +RowA_5.SP = VCC +RowA_5.LSR = ~Ready + +comp 61: SLICE_96 (FSLICE) +n2316 = (Bank_1*(Bank_4*(MAin_c_3*MAin_c_7))) +RowA_2.D = MAin_c_2 +RowA_2.CLK = ~nCRAS_c +RowA_2.SP = VCC +RowA_2.LSR = ~Ready +RA_1_3 = (~nRowColSel*RowA_3+nRowColSel*MAin_c_3) +RowA_3.D = MAin_c_3 +RowA_3.CLK = ~nCRAS_c +RowA_3.SP = VCC +RowA_3.LSR = ~Ready + +comp 62: SLICE_97 (FSLICE) +n2314 = (Bank_0*(Bank_7*(MAin_c_4*MAin_c_6))) +RowA_0.D = MAin_c_0 +RowA_0.CLK = ~nCRAS_c +RowA_0.SP = VCC +RowA_0.LSR = ~Ready +RA_1_4 = (~nRowColSel*RowA_4+nRowColSel*MAin_c_4) +RowA_1.D = MAin_c_1 +RowA_1.CLK = ~nCRAS_c +RowA_1.SP = VCC +RowA_1.LSR = ~Ready + +comp 63: SLICE_98 (FSLICE) +RA_1_8 = (~nRowColSel*RowA_8+nRowColSel*MAin_c_8) +CBR.D = ~nCCAS_c +CBR.CLK = ~nCRAS_c +CBR.SP = VCC +CBR.LSR = GND +RA_1_0 = (~nRowColSel*RowA_0+nRowColSel*MAin_c_0) +FWEr.D = ~nFWE_c +FWEr.CLK = ~nCRAS_c +FWEr.SP = VCC +FWEr.LSR = GND + +comp 64: SLICE_99 (FSLICE) +RA_1_7 = (~nRowColSel*RowA_7+nRowColSel*MAin_c_7) +Bank_6.D = Din_c_6 +Bank_6.CLK = PHI2_c +Bank_6.SP = VCC +Bank_6.LSR = GND +RA_1_1 = (~nRowColSel*RowA_1+nRowColSel*MAin_c_1) +Bank_7.D = Din_c_7 +Bank_7.CLK = PHI2_c +Bank_7.SP = VCC +Bank_7.LSR = GND + +comp 65: SLICE_100 (FSLICE) +RCLK_c_enable_24 = (~InitReady+(~PHI2r2*(CmdSubmitted*PHI2r3))) +n736.D = n737 +n736.CLK = RCLK_c +n736.SP = RCLK_c_enable_23 +n736.LSR = GND +n6 = (~Ready*((~InitReady+~RASr2)+nRowColSel_N_33)+Ready*nRowColSel_N_33) +n735.D = n736 +n735.CLK = RCLK_c +n735.SP = RCLK_c_enable_23 +n735.LSR = GND + +comp 66: SLICE_101 (FSLICE) +RA_1_6 = (~nRowColSel*RowA_6+nRowColSel*MAin_c_6) +Bank_4.D = Din_c_4 +Bank_4.CLK = PHI2_c +Bank_4.SP = VCC +Bank_4.LSR = GND +RA_1_2 = (~nRowColSel*RowA_2+nRowColSel*MAin_c_2) +Bank_5.D = Din_c_5 +Bank_5.CLK = PHI2_c +Bank_5.SP = VCC +Bank_5.LSR = GND + +comp 67: SLICE_102 (FSLICE) +n2427 = ((~InitReady+nRCS_N_139)+nRCAS_N_165) +Bank_2.D = Din_c_2 +Bank_2.CLK = PHI2_c +Bank_2.SP = VCC +Bank_2.LSR = GND +n33 = (nRCAS_N_165+nRWE_N_177) +Bank_3.D = Din_c_3 +Bank_3.CLK = PHI2_c +Bank_3.SP = VCC +Bank_3.LSR = GND + +comp 68: SLICE_103 (FSLICE) +nRowColSel_N_28 = ((~FWEr+CASr3)+CBR) +WRD_2.D = Din_c_2 +WRD_2.CLK = ~nCCAS_c +WRD_2.SP = VCC +WRD_2.LSR = GND +RA_1_5 = (~nRowColSel*RowA_5+nRowColSel*MAin_c_5) +WRD_3.D = Din_c_3 +WRD_3.CLK = ~nCCAS_c +WRD_3.SP = VCC +WRD_3.LSR = GND + +comp 69: SLICE_104 (FSLICE) +nRWE_N_178 = (~nRowColSel_N_35*(~n1+n1502)+nRowColSel_N_35*nRWE_N_182) +Ready_N_292 = (n2414+Ready) + +comp 70: SLICE_105 (FSLICE) +n14 = (n13_adj_2*(~Din_c_4*n2253)) +WRD_4.D = Din_c_4 +WRD_4.CLK = ~nCCAS_c +WRD_4.SP = VCC +WRD_4.LSR = GND +n984 = (nCCAS_c+nFWE_c) +WRD_5.D = Din_c_5 +WRD_5.CLK = ~nCCAS_c +WRD_5.SP = VCC +WRD_5.LSR = GND diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd new file mode 100644 index 0000000..405a3aa Binary files /dev/null and b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ncd differ diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ngd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ngd new file mode 100644 index 0000000..0546189 Binary files /dev/null and b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.ngd differ diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p2t b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p2t new file mode 100644 index 0000000..16daf53 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p2t @@ -0,0 +1,9 @@ +-w +-l 5 +-i 6 +-n 1 +-t 1 +-s 1 +-c 0 +-e 0 +-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p3t b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p3t new file mode 100644 index 0000000..221332e --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.p3t @@ -0,0 +1,5 @@ +-rem +-distrce +-log "RAM2GS_LCMXO640C_impl1.log" +-o "RAM2GS_LCMXO640C_impl1.csv" +-pr "RAM2GS_LCMXO640C_impl1.prf" diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad new file mode 100644 index 0000000..124dd5c --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pad @@ -0,0 +1,353 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO640C +Performance Grade: 3 +PACKAGE: TQFP100 +Package Status: Final Version 1.17 + +Tue Aug 15 05:03:28 2023 + +Pinout by Port Name: ++-----------+----------+---------------+-------+------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | Properties | ++-----------+----------+---------------+-------+------------------------------+ +| CROW[0] | 32/2 | LVCMOS33_IN | PB4C | SLEW:FAST PULL:UP | +| CROW[1] | 34/2 | LVCMOS33_IN | PB4E | SLEW:FAST PULL:UP | +| Din[0] | 21/3 | LVCMOS33_IN | PL10C | SLEW:FAST PULL:UP | +| Din[1] | 15/3 | LVCMOS33_IN | PL7B | SLEW:FAST PULL:UP | +| Din[2] | 14/3 | LVCMOS33_IN | PL5B | SLEW:FAST PULL:UP | +| Din[3] | 16/3 | LVCMOS33_IN | PL8C | SLEW:FAST PULL:UP | +| Din[4] | 18/3 | LVCMOS33_IN | PL9A | SLEW:FAST PULL:UP | +| Din[5] | 17/3 | LVCMOS33_IN | PL8D | SLEW:FAST PULL:UP | +| Din[6] | 20/3 | LVCMOS33_IN | PL10A | SLEW:FAST PULL:UP | +| Din[7] | 19/3 | LVCMOS33_IN | PL9C | SLEW:FAST PULL:UP | +| Dout[0] | 1/3 | LVCMOS33_OUT | PL2A | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[1] | 7/3 | LVCMOS33_OUT | PL3C | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[2] | 8/3 | LVCMOS33_OUT | PL3D | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[3] | 6/3 | LVCMOS33_OUT | PL3B | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[4] | 4/3 | LVCMOS33_OUT | PL2D | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[5] | 5/3 | LVCMOS33_OUT | PL3A | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[6] | 2/3 | LVCMOS33_OUT | PL2C | DRIVE:8mA SLEW:FAST PULL:UP | +| Dout[7] | 3/3 | LVCMOS33_OUT | PL2B | DRIVE:8mA SLEW:FAST PULL:UP | +| LED | 57/1 | LVCMOS33_OUT | PR10B | DRIVE:8mA SLEW:FAST PULL:UP | +| MAin[0] | 23/3 | LVCMOS33_IN | PL11C | SLEW:FAST PULL:UP | +| MAin[1] | 38/2 | LVCMOS33_IN | PB6B | SLEW:FAST PULL:UP | +| MAin[2] | 37/2 | LVCMOS33_IN | PB5D | SLEW:FAST PULL:UP | +| MAin[3] | 47/2 | LVCMOS33_IN | PB9C | SLEW:FAST PULL:UP | +| MAin[4] | 46/2 | LVCMOS33_IN | PB9A | SLEW:FAST PULL:UP | +| MAin[5] | 45/2 | LVCMOS33_IN | PB8D | SLEW:FAST PULL:UP | +| MAin[6] | 49/2 | LVCMOS33_IN | PB9D | SLEW:FAST PULL:UP | +| MAin[7] | 44/2 | LVCMOS33_IN | PB8C | SLEW:FAST PULL:UP | +| MAin[8] | 50/2 | LVCMOS33_IN | PB9F | SLEW:FAST PULL:UP | +| MAin[9] | 51/1 | LVCMOS33_IN | PR11D | SLEW:FAST PULL:UP | +| PHI2 | 39/2 | LVCMOS33_IN | PB6C | SLEW:FAST PULL:UP | +| RA[0] | 98/0 | LVCMOS33_OUT | PT2B | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[10] | 87/0 | LVCMOS33_OUT | PT5A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[11] | 79/0 | LVCMOS33_OUT | PT9A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[1] | 89/0 | LVCMOS33_OUT | PT4F | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[2] | 94/0 | LVCMOS33_OUT | PT3B | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[3] | 97/0 | LVCMOS33_OUT | PT2E | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[4] | 99/0 | LVCMOS33_OUT | PT2C | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[5] | 95/0 | LVCMOS33_OUT | PT3A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[6] | 91/0 | LVCMOS33_OUT | PT3F | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[7] | 100/0 | LVCMOS33_OUT | PT2A | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[8] | 96/0 | LVCMOS33_OUT | PT2F | DRIVE:8mA SLEW:FAST PULL:UP | +| RA[9] | 85/0 | LVCMOS33_OUT | PT6B | DRIVE:8mA SLEW:FAST PULL:UP | +| RBA[0] | 63/1 | LVCMOS33_OUT | PR7B | DRIVE:8mA SLEW:FAST PULL:UP | +| RBA[1] | 83/0 | LVCMOS33_OUT | PT7A | DRIVE:8mA SLEW:FAST PULL:UP | +| RCKE | 82/0 | LVCMOS33_OUT | PT7E | DRIVE:8mA SLEW:FAST PULL:UP | +| RCLK | 86/0 | LVCMOS33_IN | PT5B | SLEW:FAST PULL:UP | +| RDQMH | 76/0 | LVCMOS33_OUT | PT9F | DRIVE:8mA SLEW:FAST PULL:UP | +| RDQML | 61/1 | LVCMOS33_OUT | PR9B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[0] | 64/1 | LVCMOS33_BIDI | PR6C | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[1] | 65/1 | LVCMOS33_BIDI | PR6B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[2] | 66/1 | LVCMOS33_BIDI | PR5D | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[3] | 67/1 | LVCMOS33_BIDI | PR5B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[4] | 68/1 | LVCMOS33_BIDI | PR4D | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[5] | 69/1 | LVCMOS33_BIDI | PR4B | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[6] | 70/1 | LVCMOS33_BIDI | PR3D | DRIVE:8mA SLEW:FAST PULL:UP | +| RD[7] | 71/1 | LVCMOS33_BIDI | PR3B | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMCLK | 58/1 | LVCMOS33_OUT | PR10A | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMSDI | 56/1 | LVCMOS33_OUT | PR10C | DRIVE:8mA SLEW:FAST PULL:UP | +| UFMSDO | 55/1 | LVCMOS33_IN | PR10D | SLEW:FAST PULL:UP | +| nCCAS | 27/2 | LVCMOS33_IN | PB2C | SLEW:FAST PULL:UP | +| nCRAS | 43/2 | LVCMOS33_IN | PB8B | SLEW:FAST PULL:UP | +| nFWE | 22/3 | LVCMOS33_IN | PL11A | SLEW:FAST PULL:UP | +| nRCAS | 78/0 | LVCMOS33_OUT | PT9C | DRIVE:8mA SLEW:FAST PULL:UP | +| nRCS | 77/0 | LVCMOS33_OUT | PT9E | DRIVE:8mA SLEW:FAST PULL:UP | +| nRRAS | 73/1 | LVCMOS33_OUT | PR2B | DRIVE:8mA SLEW:FAST PULL:UP | +| nRWE | 72/1 | LVCMOS33_OUT | PR2D | DRIVE:8mA SLEW:FAST PULL:UP | +| nUFMCS | 53/1 | LVCMOS33_OUT | PR11C | DRIVE:8mA SLEW:FAST PULL:UP | ++-----------+----------+---------------+-------+------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 3.3V | +| 1 | 3.3V | +| 2 | | +| 3 | 3.3V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+---------------------+------------+---------------+-------+---------------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | ++----------+---------------------+------------+---------------+-------+---------------+ +| 1/3 | Dout[0] | LOCATED | LVCMOS33_OUT | PL2A | | +| 2/3 | Dout[6] | LOCATED | LVCMOS33_OUT | PL2C | | +| 3/3 | Dout[7] | LOCATED | LVCMOS33_OUT | PL2B | | +| 4/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL2D | | +| 5/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL3A | | +| 6/3 | Dout[3] | LOCATED | LVCMOS33_OUT | PL3B | | +| 7/3 | Dout[1] | LOCATED | LVCMOS33_OUT | PL3C | | +| 8/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL3D | | +| 9/3 | unused, PULL:UP | | | PL4A | | +| 11/3 | unused, PULL:UP | | | PL4C | | +| 13/3 | unused, PULL:UP | | | PL4D | | +| 14/3 | Din[2] | LOCATED | LVCMOS33_IN | PL5B | GSR_PADN | +| 15/3 | Din[1] | LOCATED | LVCMOS33_IN | PL7B | | +| 16/3 | Din[3] | LOCATED | LVCMOS33_IN | PL8C | TSALLPAD | +| 17/3 | Din[5] | LOCATED | LVCMOS33_IN | PL8D | | +| 18/3 | Din[4] | LOCATED | LVCMOS33_IN | PL9A | | +| 19/3 | Din[7] | LOCATED | LVCMOS33_IN | PL9C | | +| 20/3 | Din[6] | LOCATED | LVCMOS33_IN | PL10A | | +| 21/3 | Din[0] | LOCATED | LVCMOS33_IN | PL10C | | +| 22/3 | nFWE | LOCATED | LVCMOS33_IN | PL11A | | +| 23/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL11C | | +| 27/2 | nCCAS | LOCATED | LVCMOS33_IN | PB2C | | +| 32/2 | CROW[0] | LOCATED | LVCMOS33_IN | PB4C | | +| 34/2 | CROW[1] | LOCATED | LVCMOS33_IN | PB4E | | +| 36/2 | unused, PULL:UP | | | PB5B | PCLKT2_1 | +| 37/2 | MAin[2] | LOCATED | LVCMOS33_IN | PB5D | | +| 38/2 | MAin[1] | LOCATED | LVCMOS33_IN | PB6B | PCLKT2_0 | +| 39/2 | PHI2 | LOCATED | LVCMOS33_IN | PB6C | | +| 43/2 | nCRAS | LOCATED | LVCMOS33_IN | PB8B | | +| 44/2 | MAin[7] | LOCATED | LVCMOS33_IN | PB8C | | +| 45/2 | MAin[5] | LOCATED | LVCMOS33_IN | PB8D | | +| 46/2 | MAin[4] | LOCATED | LVCMOS33_IN | PB9A | | +| 47/2 | MAin[3] | LOCATED | LVCMOS33_IN | PB9C | | +| 49/2 | MAin[6] | LOCATED | LVCMOS33_IN | PB9D | | +| 50/2 | MAin[8] | LOCATED | LVCMOS33_IN | PB9F | | +| 51/1 | MAin[9] | LOCATED | LVCMOS33_IN | PR11D | | +| 52/1 | unused, PULL:UP | | | PR11B | | +| 53/1 | nUFMCS | LOCATED | LVCMOS33_OUT | PR11C | | +| 54/1 | unused, PULL:UP | | | PR11A | | +| 55/1 | UFMSDO | LOCATED | LVCMOS33_IN | PR10D | | +| 56/1 | UFMSDI | LOCATED | LVCMOS33_OUT | PR10C | | +| 57/1 | LED | LOCATED | LVCMOS33_OUT | PR10B | | +| 58/1 | UFMCLK | LOCATED | LVCMOS33_OUT | PR10A | | +| 59/1 | unused, PULL:UP | | | PR9D | | +| 61/1 | RDQML | LOCATED | LVCMOS33_OUT | PR9B | | +| 63/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR7B | | +| 64/1 | RD[0] | LOCATED | LVCMOS33_BIDI | PR6C | | +| 65/1 | RD[1] | LOCATED | LVCMOS33_BIDI | PR6B | | +| 66/1 | RD[2] | LOCATED | LVCMOS33_BIDI | PR5D | | +| 67/1 | RD[3] | LOCATED | LVCMOS33_BIDI | PR5B | | +| 68/1 | RD[4] | LOCATED | LVCMOS33_BIDI | PR4D | | +| 69/1 | RD[5] | LOCATED | LVCMOS33_BIDI | PR4B | | +| 70/1 | RD[6] | LOCATED | LVCMOS33_BIDI | PR3D | | +| 71/1 | RD[7] | LOCATED | LVCMOS33_BIDI | PR3B | | +| 72/1 | nRWE | LOCATED | LVCMOS33_OUT | PR2D | | +| 73/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR2B | | +| 76/0 | RDQMH | LOCATED | LVCMOS33_OUT | PT9F | | +| 77/0 | nRCS | LOCATED | LVCMOS33_OUT | PT9E | | +| 78/0 | nRCAS | LOCATED | LVCMOS33_OUT | PT9C | | +| 79/0 | RA[11] | LOCATED | LVCMOS33_OUT | PT9A | | +| 82/0 | RCKE | LOCATED | LVCMOS33_OUT | PT7E | D7 | +| 83/0 | RBA[1] | LOCATED | LVCMOS33_OUT | PT7A | D6 | +| 85/0 | RA[9] | LOCATED | LVCMOS33_OUT | PT6B | PCLKT0_1 | +| 86/0 | RCLK | LOCATED | LVCMOS33_IN | PT5B | PCLKT0_0 | +| 87/0 | RA[10] | LOCATED | LVCMOS33_OUT | PT5A | | +| 89/0 | RA[1] | LOCATED | LVCMOS33_OUT | PT4F | | +| 91/0 | RA[6] | LOCATED | LVCMOS33_OUT | PT3F | D3 | +| 94/0 | RA[2] | LOCATED | LVCMOS33_OUT | PT3B | | +| 95/0 | RA[5] | LOCATED | LVCMOS33_OUT | PT3A | | +| 96/0 | RA[8] | LOCATED | LVCMOS33_OUT | PT2F | D2 | +| 97/0 | RA[3] | LOCATED | LVCMOS33_OUT | PT2E | | +| 98/0 | RA[0] | LOCATED | LVCMOS33_OUT | PT2B | D1 | +| 99/0 | RA[4] | LOCATED | LVCMOS33_OUT | PT2C | | +| 100/0 | RA[7] | LOCATED | LVCMOS33_OUT | PT2A | | +| PB2A/2 | unused, PULL:UP | | | PB2A | | +| PB2B/2 | unused, PULL:UP | | | PB2B | | +| PB2D/2 | unused, PULL:UP | | | PB2D | | +| PB3A/2 | unused, PULL:UP | | | PB3A | | +| PB3B/2 | unused, PULL:UP | | | PB3B | | +| PB3C/2 | unused, PULL:UP | | | PB3C | | +| PB3D/2 | unused, PULL:UP | | | PB3D | | +| PB4A/2 | unused, PULL:UP | | | PB4A | | +| PB4B/2 | unused, PULL:UP | | | PB4B | | +| PB4D/2 | unused, PULL:UP | | | PB4D | | +| PB4F/2 | unused, PULL:UP | | | PB4F | | +| PB5A/2 | unused, PULL:UP | | | PB5A | | +| PB5C/2 | unused, PULL:UP | | | PB5C | | +| PB6A/2 | unused, PULL:UP | | | PB6A | | +| PB6D/2 | unused, PULL:UP | | | PB6D | | +| PB7A/2 | unused, PULL:UP | | | PB7A | | +| PB7B/2 | unused, PULL:UP | | | PB7B | | +| PB7C/2 | unused, PULL:UP | | | PB7C | | +| PB7D/2 | unused, PULL:UP | | | PB7D | | +| PB7E/2 | unused, PULL:UP | | | PB7E | | +| PB7F/2 | unused, PULL:UP | | | PB7F | | +| PB8A/2 | unused, PULL:UP | | | PB8A | | +| PB9B/2 | unused, PULL:UP | | | PB9B | | +| PB9E/0 | unused, PULL:UP | | | PB9E | | +| PL4B/3 | unused, PULL:UP | | | PL4B | | +| PL5A/3 | unused, PULL:UP | | | PL5A | | +| PL5C/3 | unused, PULL:UP | | | PL5C | | +| PL5D/3 | unused, PULL:UP | | | PL5D | | +| PL6A/3 | unused, PULL:UP | | | PL6A | | +| PL6B/3 | unused, PULL:UP | | | PL6B | | +| PL6C/3 | unused, PULL:UP | | | PL6C | | +| PL6D/3 | unused, PULL:UP | | | PL6D | | +| PL7A/3 | unused, PULL:UP | | | PL7A | | +| PL7C/3 | unused, PULL:UP | | | PL7C | | +| PL7D/3 | unused, PULL:UP | | | PL7D | | +| PL8A/3 | unused, PULL:UP | | | PL8A | | +| PL8B/3 | unused, PULL:UP | | | PL8B | | +| PL9B/3 | unused, PULL:UP | | | PL9B | | +| PL9D/3 | unused, PULL:UP | | | PL9D | | +| PL10B/3 | unused, PULL:UP | | | PL10B | | +| PL10D/3 | unused, PULL:UP | | | PL10D | | +| PL11B/3 | unused, PULL:UP | | | PL11B | | +| PL11D/3 | unused, PULL:UP | | | PL11D | | +| PR2A/1 | unused, PULL:UP | | | PR2A | | +| PR2C/1 | unused, PULL:UP | | | PR2C | | +| PR3A/1 | unused, PULL:UP | | | PR3A | | +| PR3C/1 | unused, PULL:UP | | | PR3C | | +| PR4A/1 | unused, PULL:UP | | | PR4A | | +| PR4C/1 | unused, PULL:UP | | | PR4C | | +| PR5A/1 | unused, PULL:UP | | | PR5A | | +| PR5C/1 | unused, PULL:UP | | | PR5C | | +| PR6A/1 | unused, PULL:UP | | | PR6A | | +| PR6D/1 | unused, PULL:UP | | | PR6D | | +| PR7A/1 | unused, PULL:UP | | | PR7A | | +| PR7C/1 | unused, PULL:UP | | | PR7C | | +| PR7D/1 | unused, PULL:UP | | | PR7D | | +| PR8A/1 | unused, PULL:UP | | | PR8A | | +| PR8B/1 | unused, PULL:UP | | | PR8B | | +| PR8C/1 | unused, PULL:UP | | | PR8C | | +| PR8D/1 | unused, PULL:UP | | | PR8D | | +| PR9A/1 | unused, PULL:UP | | | PR9A | | +| PR9C/1 | unused, PULL:UP | | | PR9C | | +| PT2D/0 | unused, PULL:UP | | | PT2D | | +| PT3C/0 | unused, PULL:UP | | | PT3C | | +| PT3D/0 | unused, PULL:UP | | | PT3D | | +| PT3E/0 | unused, PULL:UP | | | PT3E | | +| PT4A/0 | unused, PULL:UP | | | PT4A | | +| PT4B/0 | unused, PULL:UP | | | PT4B | | +| PT4C/0 | unused, PULL:UP | | | PT4C | | +| PT4D/0 | unused, PULL:UP | | | PT4D | | +| PT4E/0 | unused, PULL:UP | | | PT4E | | +| PT5C/0 | unused, PULL:UP | | | PT5C | | +| PT5D/0 | unused, PULL:UP | | | PT5D | | +| PT6A/0 | unused, PULL:UP | | | PT6A | | +| PT6C/0 | unused, PULL:UP | | | PT6C | | +| PT6D/0 | unused, PULL:UP | | | PT6D | | +| PT7B/0 | unused, PULL:UP | | | PT7B | | +| PT7C/0 | unused, PULL:UP | | | PT7C | | +| PT7D/0 | unused, PULL:UP | | | PT7D | | +| PT7F/0 | unused, PULL:UP | | | PT7F | | +| PT8A/0 | unused, PULL:UP | | | PT8A | | +| PT8B/0 | unused, PULL:UP | | | PT8B | | +| PT8C/0 | unused, PULL:UP | | | PT8C | | +| PT8D/0 | unused, PULL:UP | | | PT8D | | +| PT9B/0 | unused, PULL:UP | | | PT9B | | +| PT9D/0 | unused, PULL:UP | | | PT9D | | +| TCK/2 | | | | TCK | TCK | +| TDI/2 | | | | TDI | TDID0 | +| TDO/2 | | | | TDO | TDO | +| TMS/2 | | | | TMS | TMS | ++----------+---------------------+------------+---------------+-------+---------------+ + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "CROW[0]" SITE "32"; +LOCATE COMP "CROW[1]" SITE "34"; +LOCATE COMP "Din[0]" SITE "21"; +LOCATE COMP "Din[1]" SITE "15"; +LOCATE COMP "Din[2]" SITE "14"; +LOCATE COMP "Din[3]" SITE "16"; +LOCATE COMP "Din[4]" SITE "18"; +LOCATE COMP "Din[5]" SITE "17"; +LOCATE COMP "Din[6]" SITE "20"; +LOCATE COMP "Din[7]" SITE "19"; +LOCATE COMP "Dout[0]" SITE "1"; +LOCATE COMP "Dout[1]" SITE "7"; +LOCATE COMP "Dout[2]" SITE "8"; +LOCATE COMP "Dout[3]" SITE "6"; +LOCATE COMP "Dout[4]" SITE "4"; +LOCATE COMP "Dout[5]" SITE "5"; +LOCATE COMP "Dout[6]" SITE "2"; +LOCATE COMP "Dout[7]" SITE "3"; +LOCATE COMP "LED" SITE "57"; +LOCATE COMP "MAin[0]" SITE "23"; +LOCATE COMP "MAin[1]" SITE "38"; +LOCATE COMP "MAin[2]" SITE "37"; +LOCATE COMP "MAin[3]" SITE "47"; +LOCATE COMP "MAin[4]" SITE "46"; +LOCATE COMP "MAin[5]" SITE "45"; +LOCATE COMP "MAin[6]" SITE "49"; +LOCATE COMP "MAin[7]" SITE "44"; +LOCATE COMP "MAin[8]" SITE "50"; +LOCATE COMP "MAin[9]" SITE "51"; +LOCATE COMP "PHI2" SITE "39"; +LOCATE COMP "RA[0]" SITE "98"; +LOCATE COMP "RA[10]" SITE "87"; +LOCATE COMP "RA[11]" SITE "79"; +LOCATE COMP "RA[1]" SITE "89"; +LOCATE COMP "RA[2]" SITE "94"; +LOCATE COMP "RA[3]" SITE "97"; +LOCATE COMP "RA[4]" SITE "99"; +LOCATE COMP "RA[5]" SITE "95"; +LOCATE COMP "RA[6]" SITE "91"; +LOCATE COMP "RA[7]" SITE "100"; +LOCATE COMP "RA[8]" SITE "96"; +LOCATE COMP "RA[9]" SITE "85"; +LOCATE COMP "RBA[0]" SITE "63"; +LOCATE COMP "RBA[1]" SITE "83"; +LOCATE COMP "RCKE" SITE "82"; +LOCATE COMP "RCLK" SITE "86"; +LOCATE COMP "RDQMH" SITE "76"; +LOCATE COMP "RDQML" SITE "61"; +LOCATE COMP "RD[0]" SITE "64"; +LOCATE COMP "RD[1]" SITE "65"; +LOCATE COMP "RD[2]" SITE "66"; +LOCATE COMP "RD[3]" SITE "67"; +LOCATE COMP "RD[4]" SITE "68"; +LOCATE COMP "RD[5]" SITE "69"; +LOCATE COMP "RD[6]" SITE "70"; +LOCATE COMP "RD[7]" SITE "71"; +LOCATE COMP "UFMCLK" SITE "58"; +LOCATE COMP "UFMSDI" SITE "56"; +LOCATE COMP "UFMSDO" SITE "55"; +LOCATE COMP "nCCAS" SITE "27"; +LOCATE COMP "nCRAS" SITE "43"; +LOCATE COMP "nFWE" SITE "22"; +LOCATE COMP "nRCAS" SITE "78"; +LOCATE COMP "nRCS" SITE "77"; +LOCATE COMP "nRRAS" SITE "73"; +LOCATE COMP "nRWE" SITE "72"; +LOCATE COMP "nUFMCS" SITE "53"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:28 2023 + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par new file mode 100644 index 0000000..ca08894 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.par @@ -0,0 +1,253 @@ +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:25 2023 + +C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t +RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir +RAM2GS_LCMXO640C_impl1.prf -gui -msgset +D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml + + +Preference file: RAM2GS_LCMXO640C_impl1.prf. + +Level/ Number Worst Timing Worst Timing Run NCD +Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status +---------- -------- ----- ------ ----------- ----------- ---- ------ +5_1 * 0 -9.822 909228 0.273 0 04 Completed + +* : Design saved. + +Total (real) run time for 1-seed: 4 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd" +Tue Aug 15 05:03:25 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf +Preference file: RAM2GS_LCMXO640C_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67/159 42% used + 67/74 90% bonded + SLICE 71/320 22% used + + + +Number of Signals: 262 +Number of Connections: 662 + +Pin Constraint Summary: + 67 out of 67 pins locked (100% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +......... +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +......... +Placer score = 1223575. +Finished Placer Phase 1. REAL time: 3 secs + +Starting Placer Phase 2. +. +Placer score = 1220793 +Finished Placer Phase 2. REAL time: 3 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 1 out of 4 (25%) + General PIO: 1 out of 160 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 4 (50%) + SECONDARY: 1 out of 4 (25%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 out of 159 (42.1%) PIO sites used. + 67 out of 74 (90.5%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+------------+------------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | ++----------+----------------+------------+------------+------------+ +| 0 | 18 / 18 (100%) | 3.3V | - | - | +| 1 | 18 / 21 ( 85%) | 3.3V | - | - | +| 2 | 13 / 14 ( 92%) | - | - | - | +| 3 | 18 / 21 ( 85%) | 3.3V | - | - | ++----------+----------------+------------+------------+------------+ + +Total placer CPU time: 3 secs + +Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd. + +0 connections routed; 662 unrouted. +Starting router resource preassignment +WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew. +WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks. This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew. + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=7 clock_loads=4 + +Completed router resource preassignment. Real time: 3 secs + +Start NBR router at 05:03:28 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:28 08/15/23 + +Start NBR section for initial routing at 05:03:28 08/15/23 +Level 1, iteration 1 +0(0.00%) conflict; 559(84.44%) untouched conns; 717961 (nbr) score; +Estimated worst slack/total negative slack: -9.776ns/-717.961ns; real time: 3 secs +Level 2, iteration 1 +7(0.03%) conflicts; 496(74.92%) untouched conns; 699022 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-699.022ns; real time: 3 secs +Level 3, iteration 1 +9(0.03%) conflicts; 252(38.07%) untouched conns; 765745 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-765.746ns; real time: 3 secs +Level 4, iteration 1 +9(0.03%) conflicts; 0(0.00%) untouched conn; 781820 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-781.821ns; real time: 4 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:29 08/15/23 +Level 4, iteration 1 +5(0.02%) conflicts; 0(0.00%) untouched conn; 781048 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-781.049ns; real time: 4 secs +Level 4, iteration 2 +4(0.01%) conflicts; 0(0.00%) untouched conn; 780690 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.691ns; real time: 4 secs +Level 4, iteration 3 +4(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs +Level 4, iteration 4 +2(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs +Level 4, iteration 5 +2(0.01%) conflicts; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs +Level 4, iteration 6 +0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs + +Start NBR section for re-routing at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 776978 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-776.979ns; real time: 4 secs + +Start NBR section for post-routing at 05:03:29 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 260 (39.27%) + Estimated worst slack : -9.822ns + Timing score : 909228 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + +WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew. + Signal=nCCAS_c loads=7 clock_loads=4 + +Total CPU time 4 secs +Total REAL time: 4 secs +Completely routed. +End of route. 662 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 909228 + +Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd. + + +All signals are completely routed. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -9.822 +PAR_SUMMARY::Timing score> = 909.228 +PAR_SUMMARY::Worst slack> = 0.273 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 4 secs +Total REAL time to completion: 4 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf new file mode 100644 index 0000000..5fdb83b --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.prf @@ -0,0 +1,81 @@ +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:22 2023 + +SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ; +LOCATE COMP "RD[7]" SITE "71" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "MAin[9]" SITE "51" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "UFMSDO" SITE "55" ; +SCHEMATIC END ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +COMMERCIAL ; + +// No timing preferences found. TRCE invokes auto-generation of timing preferences +// Section Autogen +FREQUENCY NET "RCLK_c" 283.768 MHz ; +FREQUENCY NET "PHI2_c" 120.077 MHz ; +// End Section Autogen diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt new file mode 100644 index 0000000..916dbc3 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.pt @@ -0,0 +1,10 @@ +-v +10 + + + + +-gt +-sethld +-sp 3 +-sphld m diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.t2b b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.t2b new file mode 100644 index 0000000..aa05f83 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.t2b @@ -0,0 +1,2 @@ + +-g ES:No diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1 b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1 new file mode 100644 index 0000000..f6f527e --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.tw1 @@ -0,0 +1,353 @@ + +Loading design for application trce from file ram2gs_lcmxo640c_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:23 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf +Design file: ram2gs_lcmxo640c_impl1_map.ncd +Preference file: ram2gs_lcmxo640c_impl1.prf +Device,speed: LCMXO640C,3 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + 383 items scored, 213 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 5.089ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i14 (from RCLK_c +) + Destination: FF Data in n8MEGEN_418 (to RCLK_c +) + + Delay: 8.369ns (24.4% logic, 75.6% route), 5 logic levels. + + Constraint Details: + + 8.369ns physical path delay SLICE_1 to SLICE_56 exceeds + 3.524ns delay constraint less + 0.244ns CE_SET requirement (totaling 3.280ns) by 5.089ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_56: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_1.CLK to SLICE_1.Q0 SLICE_1 (from RCLK_c) +ROUTE 5 e 1.441 SLICE_1.Q0 to SLICE_90.C1 FS_14 +CTOF_DEL --- 0.371 SLICE_90.C1 to SLICE_90.F1 SLICE_90 +ROUTE 1 e 1.441 SLICE_90.F1 to SLICE_75.B0 n2328 +CTOF_DEL --- 0.371 SLICE_75.B0 to SLICE_75.F0 SLICE_75 +ROUTE 2 e 1.441 SLICE_75.F0 to SLICE_87.B1 n2214 +CTOF_DEL --- 0.371 SLICE_87.B1 to SLICE_87.F1 SLICE_87 +ROUTE 1 e 0.561 SLICE_87.F1 to SLICE_87.A0 n7 +CTOF_DEL --- 0.371 SLICE_87.A0 to SLICE_87.F0 SLICE_87 +ROUTE 1 e 1.441 SLICE_87.F0 to SLICE_56.CE RCLK_c_enable_11 (to RCLK_c) + -------- + 8.369 (24.4% logic, 75.6% route), 5 logic levels. + +Warning: 116.104MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + 106 items scored, 97 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 7.535ns (weighted slack = -15.070ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 11.061ns (21.8% logic, 78.2% route), 6 logic levels. + + Constraint Details: + + 11.061ns physical path delay SLICE_88 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.638ns LSR_SET requirement (totaling 3.526ns) by 7.535ns + + Physical Path Details: + + Data path SLICE_88 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 SLICE_88.CLK to SLICE_88.Q0 SLICE_88 (from PHI2_c) +ROUTE 1 e 1.441 SLICE_88.Q0 to SLICE_97.D0 Bank_0 +CTOF_DEL --- 0.371 SLICE_97.D0 to SLICE_97.F0 SLICE_97 +ROUTE 1 e 1.441 SLICE_97.F0 to SLICE_81.B0 n2314 +CTOF_DEL --- 0.371 SLICE_81.B0 to SLICE_81.F0 SLICE_81 +ROUTE 1 e 1.441 SLICE_81.F0 to SLICE_18.B1 n26 +CTOF_DEL --- 0.371 SLICE_18.B1 to SLICE_18.F1 SLICE_18 +ROUTE 8 e 1.441 SLICE_18.F1 to SLICE_89.B0 n1326 +CTOF_DEL --- 0.371 SLICE_89.B0 to SLICE_89.F0 SLICE_89 +ROUTE 1 e 1.441 SLICE_89.F0 to SLICE_79.C0 n1280 +CTOF_DEL --- 0.371 SLICE_79.C0 to SLICE_79.F0 SLICE_79 +ROUTE 2 e 1.441 SLICE_79.F0 to SLICE_14.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 11.061 (21.8% logic, 78.2% route), 6 logic levels. + +Warning: 42.739MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 283.768 MHz| 116.104 MHz| 5 * + | | | +FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 120.077 MHz| 42.739 MHz| 6 * + | | | +---------------------------------------------------------------------------- + + +2 preferences(marked by "*" above) not met. + +---------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +---------------------------------------------------------------------------- +n1326 | 8| 96| 30.97% + | | | +n26 | 1| 72| 23.23% + | | | +---------------------------------------------------------------------------- + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 310 Score: 1346529 +Cumulative negative slack: 874289 + +Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:23 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf +Design file: ram2gs_lcmxo640c_impl1_map.ncd +Preference file: ram2gs_lcmxo640c_impl1.prf +Device,speed: LCMXO640C,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + 383 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.342ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i4 (from RCLK_c +) + Destination: FF Data in IS_FSM__i5 (to RCLK_c +) + + Delay: 0.325ns (38.8% logic, 61.2% route), 1 logic levels. + + Constraint Details: + + 0.325ns physical path delay SLICE_100 to SLICE_100 meets + -0.017ns M_HLD and + 0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns + + Physical Path Details: + + Data path SLICE_100 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 SLICE_100.CLK to SLICE_100.Q0 SLICE_100 (from RCLK_c) +ROUTE 1 e 0.199 SLICE_100.Q0 to SLICE_100.M1 n736 (to RCLK_c) + -------- + 0.325 (38.8% logic, 61.2% route), 1 logic levels. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + 106 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.430ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.411ns (51.3% logic, 48.7% route), 2 logic levels. + + Constraint Details: + + 0.411ns physical path delay SLICE_14 to SLICE_14 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint requirement (totaling -0.019ns) by 0.430ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 SLICE_14.CLK to SLICE_14.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 e 0.199 SLICE_14.Q0 to SLICE_14.C0 C1Submitted +CTOF_DEL --- 0.074 SLICE_14.C0 to SLICE_14.F0 SLICE_14 +ROUTE 1 e 0.001 SLICE_14.F0 to SLICE_14.DI0 n6_adj_3 (to PHI2_c) + -------- + 0.411 (51.3% logic, 48.7% route), 2 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 0.000 ns| 0.342 ns| 1 + | | | +FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 0.000 ns| 0.430 ns| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 310 (setup), 0 (hold) +Score: 1346529 (setup), 0 (hold) +Cumulative negative slack: 874289 (874289+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr new file mode 100644 index 0000000..5ebed7c --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.twr @@ -0,0 +1,2161 @@ + +Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:29 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf +Design file: ram2gs_lcmxo640c_impl1.ncd +Preference file: ram2gs_lcmxo640c_impl1.prf +Device,speed: LCMXO640C,3 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + 383 items scored, 233 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 5.082ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i13 (from RCLK_c +) + Destination: FF Data in UFMSDI_417 (to RCLK_c +) + + Delay: 7.980ns (21.0% logic, 79.0% route), 4 logic levels. + + Constraint Details: + + 7.980ns physical path delay SLICE_3 to SLICE_44 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.626ns LSR_SET requirement (totaling 2.898ns) by 5.082ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5C.CLK to R3C5C.Q1 SLICE_3 (from RCLK_c) +ROUTE 3 1.372 R3C5C.Q1 to R3C2D.C1 FS_13 +CTOF_DEL --- 0.371 R3C2D.C1 to R3C2D.F1 SLICE_94 +ROUTE 3 1.278 R3C2D.F1 to R4C5B.D1 n2272 +CTOF_DEL --- 0.371 R4C5B.D1 to R4C5B.F1 SLICE_78 +ROUTE 3 0.528 R4C5B.F1 to R4C5B.C0 n2464 +CTOF_DEL --- 0.371 R4C5B.C0 to R4C5B.F0 SLICE_78 +ROUTE 2 3.129 R4C5B.F0 to R9C9C.LSR n1846 (to RCLK_c) + -------- + 7.980 (21.0% logic, 79.0% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C5C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R9C9C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.998ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in UFMSDI_417 (to RCLK_c +) + + Delay: 7.896ns (21.2% logic, 78.8% route), 4 logic levels. + + Constraint Details: + + 7.896ns physical path delay SLICE_3 to SLICE_44 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.626ns LSR_SET requirement (totaling 2.898ns) by 4.998ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5C.CLK to R3C5C.Q0 SLICE_3 (from RCLK_c) +ROUTE 4 1.063 R3C5C.Q0 to R3C6C.A1 FS_12 +CTOF_DEL --- 0.371 R3C6C.A1 to R3C6C.F1 SLICE_68 +ROUTE 2 1.503 R3C6C.F1 to R4C5B.A1 n2471 +CTOF_DEL --- 0.371 R4C5B.A1 to R4C5B.F1 SLICE_78 +ROUTE 3 0.528 R4C5B.F1 to R4C5B.C0 n2464 +CTOF_DEL --- 0.371 R4C5B.C0 to R4C5B.F0 SLICE_78 +ROUTE 2 3.129 R4C5B.F0 to R9C9C.LSR n1846 (to RCLK_c) + -------- + 7.896 (21.2% logic, 78.8% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C5C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R9C9C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.889ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in UFMSDI_417 (to RCLK_c +) + + Delay: 7.787ns (21.5% logic, 78.5% route), 4 logic levels. + + Constraint Details: + + 7.787ns physical path delay SLICE_1 to SLICE_44 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.626ns LSR_SET requirement (totaling 2.898ns) by 4.889ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5D.CLK to R3C5D.Q1 SLICE_1 (from RCLK_c) +ROUTE 3 1.179 R3C5D.Q1 to R3C2D.D1 FS_15 +CTOF_DEL --- 0.371 R3C2D.D1 to R3C2D.F1 SLICE_94 +ROUTE 3 1.278 R3C2D.F1 to R4C5B.D1 n2272 +CTOF_DEL --- 0.371 R4C5B.D1 to R4C5B.F1 SLICE_78 +ROUTE 3 0.528 R4C5B.F1 to R4C5B.C0 n2464 +CTOF_DEL --- 0.371 R4C5B.C0 to R4C5B.F0 SLICE_78 +ROUTE 2 3.129 R4C5B.F0 to R9C9C.LSR n1846 (to RCLK_c) + -------- + 7.787 (21.5% logic, 78.5% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C5D.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R9C9C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.800ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i17 (from RCLK_c +) + Destination: FF Data in UFMSDI_417 (to RCLK_c +) + + Delay: 7.698ns (21.7% logic, 78.3% route), 4 logic levels. + + Constraint Details: + + 7.698ns physical path delay SLICE_8 to SLICE_44 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.626ns LSR_SET requirement (totaling 2.898ns) by 4.800ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_44: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C6A.CLK to R3C6A.Q1 SLICE_8 (from RCLK_c) +ROUTE 4 0.865 R3C6A.Q1 to R3C6C.C1 FS_17 +CTOF_DEL --- 0.371 R3C6C.C1 to R3C6C.F1 SLICE_68 +ROUTE 2 1.503 R3C6C.F1 to R4C5B.A1 n2471 +CTOF_DEL --- 0.371 R4C5B.A1 to R4C5B.F1 SLICE_78 +ROUTE 3 0.528 R4C5B.F1 to R4C5B.C0 n2464 +CTOF_DEL --- 0.371 R4C5B.C0 to R4C5B.F0 SLICE_78 +ROUTE 2 3.129 R4C5B.F0 to R9C9C.LSR n1846 (to RCLK_c) + -------- + 7.698 (21.7% logic, 78.3% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C6A.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_44: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R9C9C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.458ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i13 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 7.801ns (26.2% logic, 73.8% route), 5 logic levels. + + Constraint Details: + + 7.801ns physical path delay SLICE_3 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 4.458ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5C.CLK to R3C5C.Q1 SLICE_3 (from RCLK_c) +ROUTE 3 1.372 R3C5C.Q1 to R3C2D.C1 FS_13 +CTOF_DEL --- 0.371 R3C2D.C1 to R3C2D.F1 SLICE_94 +ROUTE 3 1.777 R3C2D.F1 to R9C9C.D1 n2272 +CTOF_DEL --- 0.371 R9C9C.D1 to R9C9C.F1 SLICE_44 +ROUTE 2 2.111 R9C9C.F1 to R3C2B.A1 n2462 +CTOF_DEL --- 0.371 R3C2B.A1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 7.801 (26.2% logic, 73.8% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C5C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.352ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i13 (from RCLK_c +) + Destination: FF Data in LEDEN_419 (to RCLK_c +) + + Delay: 7.632ns (21.9% logic, 78.1% route), 4 logic levels. + + Constraint Details: + + 7.632ns physical path delay SLICE_3 to SLICE_26 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 3.280ns) by 4.352ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_26: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5C.CLK to R3C5C.Q1 SLICE_3 (from RCLK_c) +ROUTE 3 1.372 R3C5C.Q1 to R3C2D.C1 FS_13 +CTOF_DEL --- 0.371 R3C2D.C1 to R3C2D.F1 SLICE_94 +ROUTE 3 1.471 R3C2D.F1 to R4C5C.C0 n2272 +CTOF_DEL --- 0.371 R4C5C.C0 to R4C5C.F0 SLICE_75 +ROUTE 2 0.513 R4C5C.F0 to R4C5C.C1 n2214 +CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 SLICE_75 +ROUTE 1 2.603 R4C5C.F1 to R9C9B.CE RCLK_c_enable_12 (to RCLK_c) + -------- + 7.632 (21.9% logic, 78.1% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C5C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_26: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R9C9B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.293ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i12 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 7.636ns (26.8% logic, 73.2% route), 5 logic levels. + + Constraint Details: + + 7.636ns physical path delay SLICE_3 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 4.293ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5C.CLK to R3C5C.Q0 SLICE_3 (from RCLK_c) +ROUTE 4 1.063 R3C5C.Q0 to R3C6C.A1 FS_12 +CTOF_DEL --- 0.371 R3C6C.A1 to R3C6C.F1 SLICE_68 +ROUTE 2 1.921 R3C6C.F1 to R9C9C.C1 n2471 +CTOF_DEL --- 0.371 R9C9C.C1 to R9C9C.F1 SLICE_44 +ROUTE 2 2.111 R9C9C.F1 to R3C2B.A1 n2462 +CTOF_DEL --- 0.371 R3C2B.A1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 7.636 (26.8% logic, 73.2% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C5C.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.265ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 7.608ns (26.9% logic, 73.1% route), 5 logic levels. + + Constraint Details: + + 7.608ns physical path delay SLICE_1 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 4.265ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5D.CLK to R3C5D.Q1 SLICE_1 (from RCLK_c) +ROUTE 3 1.179 R3C5D.Q1 to R3C2D.D1 FS_15 +CTOF_DEL --- 0.371 R3C2D.D1 to R3C2D.F1 SLICE_94 +ROUTE 3 1.777 R3C2D.F1 to R9C9C.D1 n2272 +CTOF_DEL --- 0.371 R9C9C.D1 to R9C9C.F1 SLICE_44 +ROUTE 2 2.111 R9C9C.F1 to R3C2B.A1 n2462 +CTOF_DEL --- 0.371 R3C2B.A1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 7.608 (26.9% logic, 73.1% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C5D.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.226ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i16 (from RCLK_c +) + Destination: FF Data in UFMCLK_416 (to RCLK_c +) + + Delay: 7.569ns (27.0% logic, 73.0% route), 5 logic levels. + + Constraint Details: + + 7.569ns physical path delay SLICE_8 to SLICE_43 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.181ns DIN_SET requirement (totaling 3.343ns) by 4.226ns + + Physical Path Details: + + Data path SLICE_8 to SLICE_43: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C6A.CLK to R3C6A.Q0 SLICE_8 (from RCLK_c) +ROUTE 5 0.873 R3C6A.Q0 to R3C6B.C0 FS_16 +CTOF_DEL --- 0.371 R3C6B.C0 to R3C6B.F0 SLICE_90 +ROUTE 1 2.044 R3C6B.F0 to R9C9C.A1 n2470 +CTOF_DEL --- 0.371 R9C9C.A1 to R9C9C.F1 SLICE_44 +ROUTE 2 2.111 R9C9C.F1 to R3C2B.A1 n2462 +CTOF_DEL --- 0.371 R3C2B.A1 to R3C2B.F1 SLICE_43 +ROUTE 1 0.497 R3C2B.F1 to R3C2B.C0 n1160 +CTOF_DEL --- 0.371 R3C2B.C0 to R3C2B.F0 SLICE_43 +ROUTE 1 0.000 R3C2B.F0 to R3C2B.DI0 UFMCLK_N_224 (to RCLK_c) + -------- + 7.569 (27.0% logic, 73.0% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_8: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C6A.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_43: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C2B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.159ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in LEDEN_419 (to RCLK_c +) + + Delay: 7.439ns (22.5% logic, 77.5% route), 4 logic levels. + + Constraint Details: + + 7.439ns physical path delay SLICE_1 to SLICE_26 exceeds + 3.524ns delay constraint less + 0.000ns skew and + 0.244ns CE_SET requirement (totaling 3.280ns) by 4.159ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_26: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R3C5D.CLK to R3C5D.Q1 SLICE_1 (from RCLK_c) +ROUTE 3 1.179 R3C5D.Q1 to R3C2D.D1 FS_15 +CTOF_DEL --- 0.371 R3C2D.D1 to R3C2D.F1 SLICE_94 +ROUTE 3 1.471 R3C2D.F1 to R4C5C.C0 n2272 +CTOF_DEL --- 0.371 R4C5C.C0 to R4C5C.F0 SLICE_75 +ROUTE 2 0.513 R4C5C.F0 to R4C5C.C1 n2214 +CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 SLICE_75 +ROUTE 1 2.603 R4C5C.F1 to R9C9B.CE RCLK_c_enable_12 (to RCLK_c) + -------- + 7.439 (22.5% logic, 77.5% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R3C5D.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_26: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 1.425 86.PADDI to R9C9B.CLK RCLK_c + -------- + 1.425 (0.0% logic, 100.0% route), 0 logic levels. + +Warning: 116.198MHz is the maximum frequency for this preference. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + 106 items scored, 95 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path exceeds requirements by 4.911ns (weighted slack = -9.822ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 8.437ns (28.6% logic, 71.4% route), 6 logic levels. + + Constraint Details: + + 8.437ns physical path delay SLICE_99 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.911ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 2.159 R2C2A.Q1 to R7C9A.D0 Bank_7 +CTOF_DEL --- 0.371 R7C9A.D0 to R7C9A.F0 SLICE_97 +ROUTE 1 1.026 R7C9A.F0 to R5C9C.A0 n2314 +CTOF_DEL --- 0.371 R5C9C.A0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.947 R5C9D.F1 to R6C9B.C0 n1326 +CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 SLICE_89 +ROUTE 1 0.497 R6C9B.F0 to R6C9D.C0 n1280 +CTOF_DEL --- 0.371 R6C9D.C0 to R6C9D.F0 SLICE_79 +ROUTE 2 1.089 R6C9D.F0 to R6C7A.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 8.437 (28.6% logic, 71.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R2C2A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R6C7A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.644ns (weighted slack = -9.288ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) + FF CmdUFMCLK_413 + + Delay: 8.543ns (28.3% logic, 71.7% route), 6 logic levels. + + Constraint Details: + + 8.543ns physical path delay SLICE_99 to SLICE_81 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.644ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 2.159 R2C2A.Q1 to R7C9A.D0 Bank_7 +CTOF_DEL --- 0.371 R7C9A.D0 to R7C9A.F0 SLICE_97 +ROUTE 1 1.026 R7C9A.F0 to R5C9C.A0 n2314 +CTOF_DEL --- 0.371 R5C9C.A0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.945 R5C9D.F1 to R7C9D.C0 n1326 +CTOF_DEL --- 0.371 R7C9D.C0 to R7C9D.F0 SLICE_82 +ROUTE 2 0.513 R7C9D.F0 to R7C9C.C1 n2460 +CTOF_DEL --- 0.371 R7C9C.C1 to R7C9C.F1 SLICE_83 +ROUTE 2 1.181 R7C9C.F1 to R5C9C.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 8.543 (28.3% logic, 71.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R2C2A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R5C9C.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.644ns (weighted slack = -9.288ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) + + Delay: 8.543ns (28.3% logic, 71.7% route), 6 logic levels. + + Constraint Details: + + 8.543ns physical path delay SLICE_99 to SLICE_93 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.644ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 2.159 R2C2A.Q1 to R7C9A.D0 Bank_7 +CTOF_DEL --- 0.371 R7C9A.D0 to R7C9A.F0 SLICE_97 +ROUTE 1 1.026 R7C9A.F0 to R5C9C.A0 n2314 +CTOF_DEL --- 0.371 R5C9C.A0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.945 R5C9D.F1 to R7C9D.C0 n1326 +CTOF_DEL --- 0.371 R7C9D.C0 to R7C9D.F0 SLICE_82 +ROUTE 2 0.513 R7C9D.F0 to R7C9C.C1 n2460 +CTOF_DEL --- 0.371 R7C9C.C1 to R7C9C.F1 SLICE_83 +ROUTE 2 1.181 R7C9C.F1 to R10C9A.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 8.543 (28.3% logic, 71.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R2C2A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R10C9A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.536ns (weighted slack = -9.072ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 8.435ns (28.6% logic, 71.4% route), 6 logic levels. + + Constraint Details: + + 8.435ns physical path delay SLICE_99 to SLICE_18 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.536ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 2.159 R2C2A.Q1 to R7C9A.D0 Bank_7 +CTOF_DEL --- 0.371 R7C9A.D0 to R7C9A.F0 SLICE_97 +ROUTE 1 1.026 R7C9A.F0 to R5C9C.A0 n2314 +CTOF_DEL --- 0.371 R5C9C.A0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.945 R5C9D.F1 to R7C9D.C0 n1326 +CTOF_DEL --- 0.371 R7C9D.C0 to R7C9D.F0 SLICE_82 +ROUTE 2 0.513 R7C9D.F0 to R7C9D.C1 n2460 +CTOF_DEL --- 0.371 R7C9D.C1 to R7C9D.F1 SLICE_82 +ROUTE 1 1.073 R7C9D.F1 to R5C9D.CE PHI2_N_120_enable_7 (to PHI2_c) + -------- + 8.435 (28.6% logic, 71.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R2C2A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R5C9D.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.485ns (weighted slack = -8.970ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 8.011ns (30.1% logic, 69.9% route), 6 logic levels. + + Constraint Details: + + 8.011ns physical path delay SLICE_99 to SLICE_9 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.485ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 2.159 R2C2A.Q1 to R7C9A.D0 Bank_7 +CTOF_DEL --- 0.371 R7C9A.D0 to R7C9A.F0 SLICE_97 +ROUTE 1 1.026 R7C9A.F0 to R5C9C.A0 n2314 +CTOF_DEL --- 0.371 R5C9C.A0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.947 R5C9D.F1 to R6C9B.C0 n1326 +CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 SLICE_89 +ROUTE 1 0.497 R6C9B.F0 to R6C9D.C0 n1280 +CTOF_DEL --- 0.371 R6C9D.C0 to R6C9D.F0 SLICE_79 +ROUTE 2 0.663 R6C9D.F0 to R6C9C.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 8.011 (30.1% logic, 69.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R2C2A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R6C9C.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.400ns (weighted slack = -8.800ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in CmdSubmitted_411 (to PHI2_c -) + + Delay: 8.299ns (29.1% logic, 70.9% route), 6 logic levels. + + Constraint Details: + + 8.299ns physical path delay SLICE_99 to SLICE_19 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.400ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 2.159 R2C2A.Q1 to R7C9A.D0 Bank_7 +CTOF_DEL --- 0.371 R7C9A.D0 to R7C9A.F0 SLICE_97 +ROUTE 1 1.026 R7C9A.F0 to R5C9C.A0 n2314 +CTOF_DEL --- 0.371 R5C9C.A0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.680 R5C9D.F1 to R5C9B.D1 n1326 +CTOF_DEL --- 0.371 R5C9B.D1 to R5C9B.F1 SLICE_76 +ROUTE 2 1.068 R5C9B.F1 to R5C7C.D0 n2458 +CTOF_DEL --- 0.371 R5C7C.D0 to R5C7C.F0 SLICE_91 +ROUTE 1 0.647 R5C7C.F0 to R5C7D.CE PHI2_N_120_enable_5 (to PHI2_c) + -------- + 8.299 (29.1% logic, 70.9% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R2C2A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R5C7D.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.271ns (weighted slack = -8.542ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i7 (from PHI2_c +) + Destination: FF Data in Cmdn8MEGEN_410 (to PHI2_c -) + + Delay: 8.170ns (29.6% logic, 70.4% route), 6 logic levels. + + Constraint Details: + + 8.170ns physical path delay SLICE_99 to SLICE_23 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.265ns CE_SET requirement (totaling 3.899ns) by 4.271ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 SLICE_99 (from PHI2_c) +ROUTE 1 2.159 R2C2A.Q1 to R7C9A.D0 Bank_7 +CTOF_DEL --- 0.371 R7C9A.D0 to R7C9A.F0 SLICE_97 +ROUTE 1 1.026 R7C9A.F0 to R5C9C.A0 n2314 +CTOF_DEL --- 0.371 R5C9C.A0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.680 R5C9D.F1 to R5C9B.D1 n1326 +CTOF_DEL --- 0.371 R5C9B.D1 to R5C9B.F1 SLICE_76 +ROUTE 2 0.513 R5C9B.F1 to R5C9B.C0 n2458 +CTOF_DEL --- 0.371 R5C9B.C0 to R5C9B.F0 SLICE_76 +ROUTE 1 1.073 R5C9B.F0 to R5C8B.CE PHI2_N_120_enable_4 (to PHI2_c) + -------- + 8.170 (29.6% logic, 70.4% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R2C2A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R5C8B.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.250ns (weighted slack = -8.500ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i1 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 7.776ns (26.3% logic, 73.7% route), 5 logic levels. + + Constraint Details: + + 7.776ns physical path delay SLICE_88 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.250ns + + Physical Path Details: + + Data path SLICE_88 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R9C3B.CLK to R9C3B.Q1 SLICE_88 (from PHI2_c) +ROUTE 1 1.616 R9C3B.Q1 to R9C9A.D0 Bank_1 +CTOF_DEL --- 0.371 R9C9A.D0 to R9C9A.F0 SLICE_96 +ROUTE 1 1.583 R9C9A.F0 to R5C9D.A1 n2316 +CTOF_DEL --- 0.371 R5C9D.A1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.947 R5C9D.F1 to R6C9B.C0 n1326 +CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 SLICE_89 +ROUTE 1 0.497 R6C9B.F0 to R6C9D.C0 n1280 +CTOF_DEL --- 0.371 R6C9D.C0 to R6C9D.F0 SLICE_79 +ROUTE 2 1.089 R6C9D.F0 to R6C7A.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 7.776 (26.3% logic, 73.7% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R9C3B.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R6C7A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.196ns (weighted slack = -8.392ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i0 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 7.722ns (31.3% logic, 68.7% route), 6 logic levels. + + Constraint Details: + + 7.722ns physical path delay SLICE_88 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.196ns + + Physical Path Details: + + Data path SLICE_88 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R9C3B.CLK to R9C3B.Q0 SLICE_88 (from PHI2_c) +ROUTE 1 1.444 R9C3B.Q0 to R7C9A.C0 Bank_0 +CTOF_DEL --- 0.371 R7C9A.C0 to R7C9A.F0 SLICE_97 +ROUTE 1 1.026 R7C9A.F0 to R5C9C.A0 n2314 +CTOF_DEL --- 0.371 R5C9C.A0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.947 R5C9D.F1 to R6C9B.C0 n1326 +CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 SLICE_89 +ROUTE 1 0.497 R6C9B.F0 to R6C9D.C0 n1280 +CTOF_DEL --- 0.371 R6C9D.C0 to R6C9D.F0 SLICE_79 +ROUTE 2 1.089 R6C9D.F0 to R6C7A.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 7.722 (31.3% logic, 68.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_88: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R9C3B.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R6C7A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + +Error: The following path exceeds requirements by 4.179ns (weighted slack = -8.358ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Bank_i6 (from PHI2_c +) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 7.705ns (31.3% logic, 68.7% route), 6 logic levels. + + Constraint Details: + + 7.705ns physical path delay SLICE_99 to SLICE_14 exceeds + 4.164ns delay constraint less + 0.000ns skew and + 0.638ns LSR_SET requirement (totaling 3.526ns) by 4.179ns + + Physical Path Details: + + Data path SLICE_99 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 SLICE_99 (from PHI2_c) +ROUTE 1 1.956 R2C2A.Q0 to R5C9C.C1 Bank_6 +CTOF_DEL --- 0.371 R5C9C.C1 to R5C9C.F1 SLICE_81 +ROUTE 1 0.497 R5C9C.F1 to R5C9C.C0 n2278 +CTOF_DEL --- 0.371 R5C9C.C0 to R5C9C.F0 SLICE_81 +ROUTE 1 0.304 R5C9C.F0 to R5C9D.D1 n26 +CTOF_DEL --- 0.371 R5C9D.D1 to R5C9D.F1 SLICE_18 +ROUTE 8 0.947 R5C9D.F1 to R6C9B.C0 n1326 +CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 SLICE_89 +ROUTE 1 0.497 R6C9B.F0 to R6C9D.C0 n1280 +CTOF_DEL --- 0.371 R6C9D.C0 to R6C9D.F0 SLICE_79 +ROUTE 2 1.089 R6C9D.F0 to R6C7A.LSR C1Submitted_N_237 (to PHI2_c) + -------- + 7.705 (31.3% logic, 68.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_99: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R2C2A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 3.668 39.PADDI to R6C7A.CLK PHI2_c + -------- + 3.668 (0.0% logic, 100.0% route), 0 logic levels. + +Warning: 55.096MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 283.768 MHz| 116.198 MHz| 4 * + | | | +FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 120.077 MHz| 55.096 MHz| 6 * + | | | +---------------------------------------------------------------------------- + + +2 preferences(marked by "*" above) not met. + +---------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +---------------------------------------------------------------------------- +n1326 | 8| 94| 28.66% + | | | +n26 | 1| 70| 21.34% + | | | +---------------------------------------------------------------------------- + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Setup): +--------------- + +Timing errors: 328 Score: 909228 +Cumulative negative slack: 648187 + +Constraints cover 489 paths, 2 nets, and 415 connections (62.69% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:30 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf +Design file: ram2gs_lcmxo640c_impl1.ncd +Preference file: ram2gs_lcmxo640c_impl1.prf +Device,speed: LCMXO640C,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + 383 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i4 (from RCLK_c +) + Destination: FF Data in IS_FSM__i5 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_100 to SLICE_100 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_100 to SLICE_100: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R4C8B.CLK to R4C8B.Q0 SLICE_100 (from RCLK_c) +ROUTE 1 0.130 R4C8B.Q0 to R4C8B.M1 n736 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_100: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R4C8B.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_100: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R4C8B.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i8 (from RCLK_c +) + Destination: FF Data in IS_FSM__i9 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_76 to SLICE_76 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_76 to SLICE_76: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R5C9B.CLK to R5C9B.Q0 SLICE_76 (from RCLK_c) +ROUTE 1 0.130 R5C9B.Q0 to R5C9B.M1 n732 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_76: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R5C9B.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_76: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R5C9B.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i12 (from RCLK_c +) + Destination: FF Data in IS_FSM__i13 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_77 to SLICE_77 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_77 to SLICE_77: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R3C6D.CLK to R3C6D.Q0 SLICE_77 (from RCLK_c) +ROUTE 1 0.130 R3C6D.Q0 to R3C6D.M1 n728 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_77: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R3C6D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_77: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R3C6D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i14 (from RCLK_c +) + Destination: FF Data in IS_FSM__i15 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_80 to SLICE_80 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_80 to SLICE_80: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R3C8C.CLK to R3C8C.Q0 SLICE_80 (from RCLK_c) +ROUTE 1 0.130 R3C8C.Q0 to R3C8C.M1 n726 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_80: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R3C8C.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_80: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R3C8C.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i10 (from RCLK_c +) + Destination: FF Data in IS_FSM__i11 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_82 to SLICE_82 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_82 to SLICE_82: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R7C9D.CLK to R7C9D.Q0 SLICE_82 (from RCLK_c) +ROUTE 1 0.130 R7C9D.Q0 to R7C9D.M1 n730 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_82: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R7C9D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_82: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R7C9D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i2 (from RCLK_c +) + Destination: FF Data in IS_FSM__i3 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_84 to SLICE_84 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_84 to SLICE_84: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R5C8C.CLK to R5C8C.Q0 SLICE_84 (from RCLK_c) +ROUTE 1 0.130 R5C8C.Q0 to R5C8C.M1 n738 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_84: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R5C8C.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_84: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R5C8C.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.273ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i6 (from RCLK_c +) + Destination: FF Data in IS_FSM__i7 (to RCLK_c +) + + Delay: 0.256ns (49.2% logic, 50.8% route), 1 logic levels. + + Constraint Details: + + 0.256ns physical path delay SLICE_86 to SLICE_86 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.273ns + + Physical Path Details: + + Data path SLICE_86 to SLICE_86: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R5C8D.CLK to R5C8D.Q0 SLICE_86 (from RCLK_c) +ROUTE 1 0.130 R5C8D.Q0 to R5C8D.M1 n734 (to RCLK_c) + -------- + 0.256 (49.2% logic, 50.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_86: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R5C8D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_86: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R5C8D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.277ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q IS_FSM__i0 (from RCLK_c +) + Destination: FF Data in IS_FSM__i1 (to RCLK_c +) + + Delay: 0.260ns (48.5% logic, 51.5% route), 1 logic levels. + + Constraint Details: + + 0.260ns physical path delay SLICE_87 to SLICE_87 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.277ns + + Physical Path Details: + + Data path SLICE_87 to SLICE_87: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R4C5A.CLK to R4C5A.Q0 SLICE_87 (from RCLK_c) +ROUTE 6 0.134 R4C5A.Q0 to R4C5A.M1 nRCS_N_139 (to RCLK_c) + -------- + 0.260 (48.5% logic, 51.5% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_87: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R4C5A.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_87: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R4C5A.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.290ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q RASr2_380 (from RCLK_c +) + Destination: FF Data in RASr3_381 (to RCLK_c +) + + Delay: 0.273ns (46.2% logic, 53.8% route), 1 logic levels. + + Constraint Details: + + 0.273ns physical path delay SLICE_74 to SLICE_74 meets + -0.017ns M_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.017ns) by 0.290ns + + Physical Path Details: + + Data path SLICE_74 to SLICE_74: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R4C7A.CLK to R4C7A.Q0 SLICE_74 (from RCLK_c) +ROUTE 14 0.147 R4C7A.Q0 to R4C7A.M1 RASr2 (to RCLK_c) + -------- + 0.273 (46.2% logic, 53.8% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_74: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R4C7A.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_74: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R4C7A.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.301ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS_610__i15 (from RCLK_c +) + Destination: FF Data in FS_610_add_4_16 (to RCLK_c +) + FF FS_610__i15 + FF FS_610__i14 + + Delay: 0.257ns (49.0% logic, 51.0% route), 1 logic levels. + + Constraint Details: + + 0.257ns physical path delay SLICE_1 to SLICE_1 meets + -0.044ns LUT_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.044ns) by 0.301ns + + Physical Path Details: + + Data path SLICE_1 to SLICE_1: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.126 R3C5D.CLK to R3C5D.Q1 SLICE_1 (from RCLK_c) +ROUTE 3 0.131 R3C5D.Q1 to R3C5D.A1 FS_15 (to RCLK_c) + -------- + 0.257 (49.0% logic, 51.0% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R3C5D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path RCLK to SLICE_1: + + Name Fanout Delay (ns) Site Resource +ROUTE 40 0.351 86.PADDI to R3C5D.CLK RCLK_c + -------- + 0.351 (0.0% logic, 100.0% route), 0 logic levels. + + +================================================================================ +Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + 106 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.361ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in C1Submitted_406 (to PHI2_c -) + + Delay: 0.342ns (61.7% logic, 38.3% route), 2 logic levels. + + Constraint Details: + + 0.342ns physical path delay SLICE_14 to SLICE_14 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.361ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R6C7A.CLK to R6C7A.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 0.131 R6C7A.Q0 to R6C7A.A0 C1Submitted +CTOF_DEL --- 0.074 R6C7A.A0 to R6C7A.F0 SLICE_14 +ROUTE 1 0.000 R6C7A.F0 to R6C7A.DI0 n6_adj_3 (to PHI2_c) + -------- + 0.342 (61.7% logic, 38.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R6C7A.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R6C7A.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.361ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_407 (from PHI2_c -) + Destination: FF Data in ADSubmitted_407 (to PHI2_c -) + + Delay: 0.342ns (61.7% logic, 38.3% route), 2 logic levels. + + Constraint Details: + + 0.342ns physical path delay SLICE_9 to SLICE_9 meets + -0.019ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.019ns) by 0.361ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R6C9C.CLK to R6C9C.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.131 R6C9C.Q0 to R6C9C.A0 ADSubmitted +CTOF_DEL --- 0.074 R6C9C.A0 to R6C9C.F0 SLICE_9 +ROUTE 1 0.000 R6C9C.F0 to R6C9C.DI0 n1413 (to PHI2_c) + -------- + 0.342 (61.7% logic, 38.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R6C9C.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R6C9C.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.585ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in XOR8MEG_408 (to PHI2_c -) + + Delay: 0.562ns (37.5% logic, 62.5% route), 2 logic levels. + + Constraint Details: + + 0.562ns physical path delay SLICE_18 to SLICE_49 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 0.585ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_49: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C9D.CLK to R5C9D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.221 R5C9D.Q0 to R5C8C.B1 CmdEnable +CTOF_DEL --- 0.074 R5C8C.B1 to R5C8C.F1 SLICE_84 +ROUTE 1 0.130 R5C8C.F1 to R5C8A.CE PHI2_N_120_enable_1 (to PHI2_c) + -------- + 0.562 (37.5% logic, 62.5% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C9D.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_49: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C8A.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.885ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdUFMCS_412 (to PHI2_c -) + FF CmdUFMCLK_413 + + Delay: 0.862ns (33.1% logic, 66.9% route), 3 logic levels. + + Constraint Details: + + 0.862ns physical path delay SLICE_18 to SLICE_81 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 0.885ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C9D.CLK to R5C9D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.145 R5C9D.Q0 to R7C9C.D0 CmdEnable +CTOF_DEL --- 0.074 R7C9C.D0 to R7C9C.F0 SLICE_83 +ROUTE 2 0.196 R7C9C.F0 to R7C9C.A1 n10 +CTOF_DEL --- 0.074 R7C9C.A1 to R7C9C.F1 SLICE_83 +ROUTE 2 0.236 R7C9C.F1 to R5C9C.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 0.862 (33.1% logic, 66.9% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C9D.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_81: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C9C.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.885ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdUFMSDI_414 (to PHI2_c -) + + Delay: 0.862ns (33.1% logic, 66.9% route), 3 logic levels. + + Constraint Details: + + 0.862ns physical path delay SLICE_18 to SLICE_93 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 0.885ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C9D.CLK to R5C9D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.145 R5C9D.Q0 to R7C9C.D0 CmdEnable +CTOF_DEL --- 0.074 R7C9C.D0 to R7C9C.F0 SLICE_83 +ROUTE 2 0.196 R7C9C.F0 to R7C9C.A1 n10 +CTOF_DEL --- 0.074 R7C9C.A1 to R7C9C.F1 SLICE_83 +ROUTE 2 0.236 R7C9C.F1 to R10C9A.CE PHI2_N_120_enable_6 (to PHI2_c) + -------- + 0.862 (33.1% logic, 66.9% route), 3 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C9D.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_93: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R10C9A.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.146ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in Cmdn8MEGEN_410 (to PHI2_c -) + + Delay: 1.123ns (32.0% logic, 68.0% route), 4 logic levels. + + Constraint Details: + + 1.123ns physical path delay SLICE_18 to SLICE_23 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 1.146ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C9D.CLK to R5C9D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.145 R5C9D.Q0 to R7C9C.D0 CmdEnable +CTOF_DEL --- 0.074 R7C9C.D0 to R7C9C.F0 SLICE_83 +ROUTE 2 0.300 R7C9C.F0 to R5C9B.A1 n10 +CTOF_DEL --- 0.074 R5C9B.A1 to R5C9B.F1 SLICE_76 +ROUTE 2 0.103 R5C9B.F1 to R5C9B.C0 n2458 +CTOF_DEL --- 0.074 R5C9B.C0 to R5C9B.F0 SLICE_76 +ROUTE 1 0.216 R5C9B.F0 to R5C8B.CE PHI2_N_120_enable_4 (to PHI2_c) + -------- + 1.123 (32.0% logic, 68.0% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C9D.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_23: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C8B.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.173ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdEnable_405 (from PHI2_c -) + Destination: FF Data in CmdSubmitted_411 (to PHI2_c -) + + Delay: 1.150ns (31.2% logic, 68.8% route), 4 logic levels. + + Constraint Details: + + 1.150ns physical path delay SLICE_18 to SLICE_19 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 1.173ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C9D.CLK to R5C9D.Q0 SLICE_18 (from PHI2_c) +ROUTE 2 0.145 R5C9D.Q0 to R7C9C.D0 CmdEnable +CTOF_DEL --- 0.074 R7C9C.D0 to R7C9C.F0 SLICE_83 +ROUTE 2 0.300 R7C9C.F0 to R5C9B.A1 n10 +CTOF_DEL --- 0.074 R5C9B.A1 to R5C9B.F1 SLICE_76 +ROUTE 2 0.216 R5C9B.F1 to R5C7C.D0 n2458 +CTOF_DEL --- 0.074 R5C7C.D0 to R5C7C.F0 SLICE_91 +ROUTE 1 0.130 R5C7C.F0 to R5C7D.CE PHI2_N_120_enable_5 (to PHI2_c) + -------- + 1.150 (31.2% logic, 68.8% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C9D.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_19: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C7D.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.573ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q ADSubmitted_407 (from PHI2_c -) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 1.550ns (26.5% logic, 73.5% route), 4 logic levels. + + Constraint Details: + + 1.550ns physical path delay SLICE_9 to SLICE_18 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 1.573ns + + Physical Path Details: + + Data path SLICE_9 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R6C9C.CLK to R6C9C.Q0 SLICE_9 (from PHI2_c) +ROUTE 2 0.310 R6C9C.Q0 to R5C7A.A0 ADSubmitted +CTOOFX_DEL --- 0.125 R5C7A.A0 to R5C7A.OFX0 i26/SLICE_71 +ROUTE 1 0.296 R5C7A.OFX0 to R4C9A.A0 n13_adj_2 +CTOF_DEL --- 0.074 R4C9A.A0 to R4C9A.F0 SLICE_105 +ROUTE 1 0.318 R4C9A.F0 to R7C9D.B1 n14 +CTOF_DEL --- 0.074 R7C9D.B1 to R7C9D.F1 SLICE_82 +ROUTE 1 0.216 R7C9D.F1 to R5C9D.CE PHI2_N_120_enable_7 (to PHI2_c) + -------- + 1.550 (26.5% logic, 73.5% route), 4 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_9: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R6C9C.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C9D.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 1.708ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q C1Submitted_406 (from PHI2_c -) + Destination: FF Data in CmdEnable_405 (to PHI2_c -) + + Delay: 1.685ns (28.5% logic, 71.5% route), 5 logic levels. + + Constraint Details: + + 1.685ns physical path delay SLICE_14 to SLICE_18 meets + -0.023ns CE_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.023ns) by 1.708ns + + Physical Path Details: + + Data path SLICE_14 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R6C7A.CLK to R6C7A.Q0 SLICE_14 (from PHI2_c) +ROUTE 2 0.196 R6C7A.Q0 to R6C7A.A1 C1Submitted +CTOF_DEL --- 0.074 R6C7A.A1 to R6C7A.F1 SLICE_14 +ROUTE 1 0.179 R6C7A.F1 to R5C7A.C1 n2284 +CTOOFX_DEL --- 0.121 R5C7A.C1 to R5C7A.OFX0 i26/SLICE_71 +ROUTE 1 0.296 R5C7A.OFX0 to R4C9A.A0 n13_adj_2 +CTOF_DEL --- 0.074 R4C9A.A0 to R4C9A.F0 SLICE_105 +ROUTE 1 0.318 R4C9A.F0 to R7C9D.B1 n14 +CTOF_DEL --- 0.074 R7C9D.B1 to R7C9D.F1 SLICE_82 +ROUTE 1 0.216 R7C9D.F1 to R5C9D.CE PHI2_N_120_enable_7 (to PHI2_c) + -------- + 1.685 (28.5% logic, 71.5% route), 5 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_14: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R6C7A.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C9D.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 4.684ns (weighted slack = 9.368ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q XOR8MEG_408 (from PHI2_c -) + Destination: FF Data in RA11_385 (to PHI2_c +) + + Delay: 0.512ns (41.2% logic, 58.8% route), 2 logic levels. + + Constraint Details: + + 0.512ns physical path delay SLICE_49 to SLICE_32 meets + -0.008ns DIN_HLD and + -4.164ns delay constraint less + 0.000ns skew requirement (totaling -4.172ns) by 4.684ns + + Physical Path Details: + + Data path SLICE_49 to SLICE_32: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.137 R5C8A.CLK to R5C8A.Q0 SLICE_49 (from PHI2_c) +ROUTE 1 0.301 R5C8A.Q0 to R2C9A.C0 XOR8MEG +CTOF_DEL --- 0.074 R2C9A.C0 to R2C9A.F0 SLICE_32 +ROUTE 1 0.000 R2C9A.F0 to R2C9A.DI0 RA11_N_184 (to PHI2_c) + -------- + 0.512 (41.2% logic, 58.8% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path PHI2 to SLICE_49: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R5C8A.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path PHI2 to SLICE_32: + + Name Fanout Delay (ns) Site Resource +ROUTE 14 0.903 39.PADDI to R2C9A.CLK PHI2_c + -------- + 0.903 (0.0% logic, 100.0% route), 0 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY NET "RCLK_c" 283.768000 MHz ; | 0.000 ns| 0.273 ns| 1 + | | | +FREQUENCY NET "PHI2_c" 120.077000 MHz ; | 0.000 ns| 0.361 ns| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 4 clocks: + +Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9 + No transfer within this clock domain is found + +Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7 + No transfer within this clock domain is found + +Clock Domain: RCLK_c Source: RCLK.PAD Loads: 40 + Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ; + + Data transfers from: + Clock Domain: nCRAS_c Source: nCRAS.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + Clock Domain: PHI2_c Source: PHI2.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + +Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14 + Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ; + + Data transfers from: + Clock Domain: RCLK_c Source: RCLK.PAD + Not reported because source and destination domains are unrelated. + To report these transfers please refer to preference CLKSKEWDIFF to define + external clock skew between clock ports. + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 489 paths, 2 nets, and 415 connections (62.69% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 328 (setup), 0 (hold) +Score: 909228 (setup), 0 (hold) +Cumulative negative slack: 648187 (648187+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html new file mode 100644 index 0000000..c5459ef --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_bgn.html @@ -0,0 +1,111 @@ + +Bitgen Report + + +
    BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:32 2023
+
+
+Command: bitgen -w -g ES:No -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+
+Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application Bitgen from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2GS_LCMXO640C_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                             ES  |                           No**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit".
+Total CPU Time: 0 secs 
+Total REAL Time: 0 secs 
+Peak Memory Usage: 46 MB
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html new file mode 100644 index 0000000..3bd2593 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_iotiming.html @@ -0,0 +1,203 @@ + +I/O Timing Report + + +
    I/O Timing Report
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 4
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+// Design: RAM2GS
+// Package: TQFP100
+// ncd File: ram2gs_lcmxo640c_impl1.ncd
+// Version: Diamond (64-bit) 3.12.1.454
+// Written on Tue Aug 15 05:03:31 2023
+// M: Minimum Performance Grade
+// iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 5, 4, 3):
+
+// Input Setup and Hold Times
+
+Port    Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+CROW[0] nCRAS F    -0.236      M       3.076     3
+CROW[1] nCRAS F    -0.216      M       2.985     3
+Din[0]  PHI2  F     6.373      3       2.684     3
+Din[0]  nCCAS F     1.094      3       0.245     3
+Din[1]  PHI2  F     5.890      3       2.684     3
+Din[1]  nCCAS F     1.106      3       0.247     3
+Din[2]  PHI2  F     4.774      3       2.292     3
+Din[2]  nCCAS F     1.207      3       0.231     3
+Din[3]  PHI2  F     8.665      3       1.537     3
+Din[3]  nCCAS F     0.786      3       0.612     3
+Din[4]  PHI2  F     5.483      3       1.881     3
+Din[4]  nCCAS F     1.180      3       0.282     3
+Din[5]  PHI2  F     7.162      3       1.124     3
+Din[5]  nCCAS F     0.802      3       0.635     3
+Din[6]  PHI2  F     8.125      3       1.435     3
+Din[6]  nCCAS F     1.142      3       0.086     3
+Din[7]  PHI2  F     8.015      3       1.300     3
+Din[7]  nCCAS F     1.259      3      -0.010     M
+MAin[0] PHI2  F     6.577      3       0.639     3
+MAin[0] nCRAS F    -0.004      M       2.291     3
+MAin[1] PHI2  F     6.880      3       1.958     3
+MAin[1] nCRAS F     1.424      3       1.006     3
+MAin[2] PHI2  F     4.559      3       0.456     3
+MAin[2] nCRAS F    -0.209      M       2.966     3
+MAin[3] PHI2  F     5.604      3      -0.096     M
+MAin[3] nCRAS F    -0.323      M       3.369     3
+MAin[4] PHI2  F     6.263      3      -0.211     M
+MAin[4] nCRAS F    -0.086      M       2.536     3
+MAin[5] PHI2  F     4.291      3       0.703     3
+MAin[5] nCRAS F     1.052      3       1.326     3
+MAin[6] PHI2  F     5.837      3      -0.133     M
+MAin[6] nCRAS F    -0.017      M       2.334     3
+MAin[7] PHI2  F     6.302      3      -0.241     M
+MAin[7] nCRAS F    -0.106      M       2.631     3
+MAin[8] nCRAS F    -0.086      M       2.542     3
+MAin[9] nCRAS F     0.549      3       1.796     3
+PHI2    RCLK  R     4.937      3      -0.562     M
+UFMSDO  RCLK  R     2.296      3      -0.152     M
+nCCAS   RCLK  R     1.639      3      -0.029     M
+nCCAS   nCRAS F    -0.229      M       3.059     3
+nCRAS   RCLK  R     1.104      3       0.341     3
+nFWE    PHI2  F     5.086      3       1.672     3
+nFWE    nCRAS F     0.037      3       2.231     3
+
+
+// Clock to Output Delay
+
+Port   Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+LED    RCLK  R     7.152         3        1.423          M
+LED    nCRAS F    12.128         3        2.429          M
+RA[0]  RCLK  R     9.839         3        1.974          M
+RA[0]  nCRAS F    12.557         3        2.494          M
+RA[10] RCLK  R     5.747         3        1.141          M
+RA[11] PHI2  R     7.990         3        1.574          M
+RA[1]  RCLK  R    10.012         3        2.010          M
+RA[1]  nCRAS F    12.750         3        2.545          M
+RA[2]  RCLK  R    10.522         3        2.116          M
+RA[2]  nCRAS F    12.564         3        2.494          M
+RA[3]  RCLK  R    10.341         3        2.077          M
+RA[3]  nCRAS F    11.973         3        2.372          M
+RA[4]  RCLK  R     9.672         3        1.940          M
+RA[4]  nCRAS F    13.443         3        2.679          M
+RA[5]  RCLK  R     9.440         3        1.890          M
+RA[5]  nCRAS F    10.958         3        2.155          M
+RA[6]  RCLK  R    10.605         3        2.138          M
+RA[6]  nCRAS F    13.114         3        2.628          M
+RA[7]  RCLK  R     8.842         3        1.782          M
+RA[7]  nCRAS F    10.779         3        2.148          M
+RA[8]  RCLK  R    10.258         3        2.067          M
+RA[8]  nCRAS F    12.925         3        2.579          M
+RA[9]  RCLK  R     7.160         3        1.425          M
+RA[9]  nCRAS F     9.857         3        1.950          M
+RBA[0] nCRAS F    10.935         3        2.169          M
+RBA[1] nCRAS F    10.976         3        2.184          M
+RCKE   RCLK  R     5.747         3        1.141          M
+RDQMH  RCLK  R     9.890         3        1.991          M
+RDQML  RCLK  R     9.338         3        1.859          M
+RD[0]  nCCAS F     7.488         3        1.591          M
+RD[1]  nCCAS F     8.012         3        1.701          M
+RD[2]  nCCAS F     8.965         3        1.912          M
+RD[3]  nCCAS F     8.965         3        1.912          M
+RD[4]  nCCAS F     7.951         3        1.691          M
+RD[5]  nCCAS F     7.951         3        1.691          M
+RD[6]  nCCAS F     8.012         3        1.701          M
+RD[7]  nCCAS F     8.384         3        1.785          M
+UFMCLK RCLK  R     7.986         3        1.598          M
+UFMSDI RCLK  R     5.747         3        1.141          M
+nRCAS  RCLK  R     5.747         3        1.141          M
+nRCS   RCLK  R     5.747         3        1.141          M
+nRRAS  RCLK  R     6.929         3        1.373          M
+nRWE   RCLK  R     7.375         3        1.459          M
+nUFMCS RCLK  R     7.996         3        1.601          M
+WARNING: you must also run trce with hold speed: 3
+WARNING: you must also run trce with setup speed: M
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_lattice.synproj b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_lattice.synproj new file mode 100644 index 0000000..b97508a --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_lattice.synproj @@ -0,0 +1,41 @@ +-a "MachXO" +-d LCMXO640C +-t TQFP100 +-s 3 +-frequency 200 +-optimization_goal Balanced +-bram_utilization 100 +-ramstyle Auto +-romstyle auto +-dsp_utilization 100 +-use_dsp 1 +-use_carry_chain 1 +-carry_chain_length 0 +-force_gsr Auto +-resource_sharing 1 +-propagate_constants 1 +-remove_duplicate_regs 1 +-mux_style Auto +-max_fanout 1000 +-fsm_encoding_style Auto +-twr_paths 3 +-fix_gated_clocks 1 +-loop_limit 1950 + + + +-use_io_insertion 1 +-resolve_mixed_drivers 0 +-use_io_reg auto + + +-lpf 1 +-p "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C" +-ver "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v" +-top RAM2GS + + +-p "C:/lscc/diamond/3.12/ispfpga/mj5g00/data" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C" + +-ngd "RAM2GS_LCMXO640C_impl1.ngd" + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.asd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.asd new file mode 100644 index 0000000..a2decba --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.asd @@ -0,0 +1,13 @@ +[ActiveSupport MAP] +Device = LCMXO640C; +Package = TQFP100; +Performance = 3; +LUTS_avail = 640; +LUTS_used = 142; +FF_avail = 640; +FF_used = 102; +INPUT_LVCMOS33 = 26; +OUTPUT_LVCMOS33 = 33; +BIDI_LVCMOS33 = 8; +IO_avail = 74; +IO_used = 67; diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam new file mode 100644 index 0000000..99dec6c --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.cam @@ -0,0 +1,99 @@ +[ START MERGED ] +nCRAS_N_9 nCRAS_c +nCCAS_N_3 nCCAS_c +n2477 Ready +nFWE_N_5 nFWE_c +PHI2_N_120 PHI2_c +n1425 nRowColSel_N_34 +nRWE_N_176 nRWE_N_177 +RASr2_N_63 RASr2 +n1426 nRowColSel_N_35 +[ END MERGED ] +[ START CLIPPED ] +GND_net +VCC_net +FS_610_add_4_18/CO1 +FS_610_add_4_18/CO0 +FS_610_add_4_10/CO0 +FS_610_add_4_4/CO0 +FS_610_add_4_12/CO0 +FS_610_add_4_2/CO0 +FS_610_add_4_14/CO0 +FS_610_add_4_6/CO0 +FS_610_add_4_16/CO0 +FS_610_add_4_8/CO0 +[ END CLIPPED ] +[ START DESIGN PREFS ] +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Tue Aug 15 05:03:22 2023 + +SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ; +LOCATE COMP "RD[7]" SITE "71" ; +LOCATE COMP "RD[6]" SITE "70" ; +LOCATE COMP "RD[5]" SITE "69" ; +LOCATE COMP "RD[4]" SITE "68" ; +LOCATE COMP "RD[3]" SITE "67" ; +LOCATE COMP "RD[2]" SITE "66" ; +LOCATE COMP "RD[1]" SITE "65" ; +LOCATE COMP "RD[0]" SITE "64" ; +LOCATE COMP "Dout[7]" SITE "3" ; +LOCATE COMP "Dout[6]" SITE "2" ; +LOCATE COMP "Dout[5]" SITE "5" ; +LOCATE COMP "Dout[4]" SITE "4" ; +LOCATE COMP "Dout[3]" SITE "6" ; +LOCATE COMP "Dout[2]" SITE "8" ; +LOCATE COMP "Dout[1]" SITE "7" ; +LOCATE COMP "Dout[0]" SITE "1" ; +LOCATE COMP "LED" SITE "57" ; +LOCATE COMP "RBA[1]" SITE "83" ; +LOCATE COMP "RBA[0]" SITE "63" ; +LOCATE COMP "RA[11]" SITE "79" ; +LOCATE COMP "RA[10]" SITE "87" ; +LOCATE COMP "RA[9]" SITE "85" ; +LOCATE COMP "RA[8]" SITE "96" ; +LOCATE COMP "RA[7]" SITE "100" ; +LOCATE COMP "RA[6]" SITE "91" ; +LOCATE COMP "RA[5]" SITE "95" ; +LOCATE COMP "RA[4]" SITE "99" ; +LOCATE COMP "RA[3]" SITE "97" ; +LOCATE COMP "RA[2]" SITE "94" ; +LOCATE COMP "RA[1]" SITE "89" ; +LOCATE COMP "RA[0]" SITE "98" ; +LOCATE COMP "nRCS" SITE "77" ; +LOCATE COMP "RCKE" SITE "82" ; +LOCATE COMP "nRWE" SITE "72" ; +LOCATE COMP "nRRAS" SITE "73" ; +LOCATE COMP "nRCAS" SITE "78" ; +LOCATE COMP "RDQMH" SITE "76" ; +LOCATE COMP "RDQML" SITE "61" ; +LOCATE COMP "nUFMCS" SITE "53" ; +LOCATE COMP "UFMCLK" SITE "58" ; +LOCATE COMP "UFMSDI" SITE "56" ; +LOCATE COMP "PHI2" SITE "39" ; +LOCATE COMP "MAin[9]" SITE "51" ; +LOCATE COMP "MAin[8]" SITE "50" ; +LOCATE COMP "MAin[7]" SITE "44" ; +LOCATE COMP "MAin[6]" SITE "49" ; +LOCATE COMP "MAin[5]" SITE "45" ; +LOCATE COMP "MAin[4]" SITE "46" ; +LOCATE COMP "MAin[3]" SITE "47" ; +LOCATE COMP "MAin[2]" SITE "37" ; +LOCATE COMP "MAin[1]" SITE "38" ; +LOCATE COMP "MAin[0]" SITE "23" ; +LOCATE COMP "CROW[1]" SITE "34" ; +LOCATE COMP "CROW[0]" SITE "32" ; +LOCATE COMP "Din[7]" SITE "19" ; +LOCATE COMP "Din[6]" SITE "20" ; +LOCATE COMP "Din[5]" SITE "17" ; +LOCATE COMP "Din[4]" SITE "18" ; +LOCATE COMP "Din[3]" SITE "16" ; +LOCATE COMP "Din[2]" SITE "14" ; +LOCATE COMP "Din[1]" SITE "15" ; +LOCATE COMP "Din[0]" SITE "21" ; +LOCATE COMP "nCCAS" SITE "27" ; +LOCATE COMP "nCRAS" SITE "43" ; +LOCATE COMP "nFWE" SITE "22" ; +LOCATE COMP "RCLK" SITE "86" ; +LOCATE COMP "UFMSDO" SITE "55" ; +SCHEMATIC END ; +[ END DESIGN PREFS ] diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.hrr b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.hrr new file mode 100644 index 0000000..c405991 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.hrr @@ -0,0 +1,10 @@ +--------------------------------------------------- +Report for cell RAM2GS + Instance path: RAM2GS + Cell usage: + cell count Res Usage(%) + SLIC 71.00 100.0 + LUT4 124.00 100.0 + IOBUF 67 100.0 + PFUREG 102 100.0 + RIPPLE 9 100.0 diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.ncd b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.ncd new file mode 100644 index 0000000..43f5ab2 Binary files /dev/null and b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_map.ncd differ diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.sdf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.sdf new file mode 100644 index 0000000..1cdd848 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.sdf @@ -0,0 +1,3036 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Tue Aug 15 05:03:24 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7I) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8I) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_14") + (INSTANCE SLICE_14I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_18") + (INSTANCE SLICE_18I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_23") + (INSTANCE SLICE_23I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_25") + (INSTANCE SLICE_25I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_26") + (INSTANCE SLICE_26I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_31") + (INSTANCE SLICE_31I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_34") + (INSTANCE SLICE_34I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_35") + (INSTANCE SLICE_35I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_36") + (INSTANCE SLICE_36I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_43") + (INSTANCE SLICE_43I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_49") + (INSTANCE SLICE_49I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_56") + (INSTANCE SLICE_56I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_58") + (INSTANCE SLICE_58I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_60") + (INSTANCE SLICE_60I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_61") + (INSTANCE SLICE_61I) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_63") + (INSTANCE SLICE_63I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_64") + (INSTANCE SLICE_64I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_65") + (INSTANCE SLICE_65I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_66") + (INSTANCE SLICE_66I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_67") + (INSTANCE SLICE_67I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_68") + (INSTANCE SLICE_68I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_69") + (INSTANCE SLICE_69I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "RCKEEN_I_0_445_SLICE_70") + (INSTANCE RCKEEN_I_0_445_SLICE_70I) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i26_SLICE_71") + (INSTANCE i26_SLICE_71I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i2099_SLICE_72") + (INSTANCE i2099_SLICE_72I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i26_adj_28_SLICE_73") + (INSTANCE i26_adj_28_SLICE_73I) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_74") + (INSTANCE SLICE_74I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_75") + (INSTANCE SLICE_75I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_76") + (INSTANCE SLICE_76I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_80") + (INSTANCE SLICE_80I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_81") + (INSTANCE SLICE_81I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_84") + (INSTANCE SLICE_84I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_85") + (INSTANCE SLICE_85I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100I) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_102") + (INSTANCE SLICE_102I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_103") + (INSTANCE SLICE_103I) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_104") + (INSTANCE SLICE_104I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_105") + (INSTANCE SLICE_105I) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "RD_7_B") + (INSTANCE RD_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD7 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD7 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD7) (1250:1250:1250)) + (WIDTH (negedge RD7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_6_B") + (INSTANCE RD_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD6 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD6 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD6) (1250:1250:1250)) + (WIDTH (negedge RD6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_5_B") + (INSTANCE RD_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD5 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD5 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD5) (1250:1250:1250)) + (WIDTH (negedge RD5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_4_B") + (INSTANCE RD_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD4 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD4 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD4) (1250:1250:1250)) + (WIDTH (negedge RD4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_3_B") + (INSTANCE RD_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD3 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD3 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD3) (1250:1250:1250)) + (WIDTH (negedge RD3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_2_B") + (INSTANCE RD_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD2 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD2 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD2) (1250:1250:1250)) + (WIDTH (negedge RD2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_1_B") + (INSTANCE RD_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD1 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD1 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD1) (1250:1250:1250)) + (WIDTH (negedge RD1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_0_B") + (INSTANCE RD_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD0 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD0 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD0) (1250:1250:1250)) + (WIDTH (negedge RD0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Dout_7_B") + (INSTANCE Dout_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout7 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_6_B") + (INSTANCE Dout_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout6 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_5_B") + (INSTANCE Dout_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout5 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_4_B") + (INSTANCE Dout_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout4 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_3_B") + (INSTANCE Dout_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout3 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_2_B") + (INSTANCE Dout_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout2 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1_B") + (INSTANCE Dout_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0_B") + (INSTANCE Dout_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "LEDB") + (INSTANCE LEDI) + (DELAY + (ABSOLUTE + (IOPATH PADDO LEDS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_B") + (INSTANCE RBA_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_0_B") + (INSTANCE RBA_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_11_B") + (INSTANCE RA_11_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA11 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_10_B") + (INSTANCE RA_10_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA10 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_9_B") + (INSTANCE RA_9_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA9 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_8_B") + (INSTANCE RA_8_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA8 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_7_B") + (INSTANCE RA_7_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA7 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_6_B") + (INSTANCE RA_6_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA6 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_5_B") + (INSTANCE RA_5_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA5 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_4_B") + (INSTANCE RA_4_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA4 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_3_B") + (INSTANCE RA_3_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA3 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_2_B") + (INSTANCE RA_2_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA2 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_1_B") + (INSTANCE RA_1_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_0_B") + (INSTANCE RA_0_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRCSB") + (INSTANCE nRCSI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCSS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RCKEB") + (INSTANCE RCKEI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RCKES (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRWEB") + (INSTANCE nRWEI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRWES (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRRASB") + (INSTANCE nRRASI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRRASS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRCASB") + (INSTANCE nRCASI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCASS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMHB") + (INSTANCE RDQMHI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMHS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMLB") + (INSTANCE RDQMLI) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMLS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nUFMCSB") + (INSTANCE nUFMCSI) + (DELAY + (ABSOLUTE + (IOPATH PADDO nUFMCSS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "UFMCLKB") + (INSTANCE UFMCLKI) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMCLKS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "UFMSDIB") + (INSTANCE UFMSDII) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMSDIS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "PHI2B") + (INSTANCE PHI2I) + (DELAY + (ABSOLUTE + (IOPATH PHI2S PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI2S) (1250:1250:1250)) + (WIDTH (negedge PHI2S) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_9_B") + (INSTANCE MAin_9_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (1250:1250:1250)) + (WIDTH (negedge MAin9) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_8_B") + (INSTANCE MAin_8_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (1250:1250:1250)) + (WIDTH (negedge MAin8) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_7_B") + (INSTANCE MAin_7_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (1250:1250:1250)) + (WIDTH (negedge MAin7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_6_B") + (INSTANCE MAin_6_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (1250:1250:1250)) + (WIDTH (negedge MAin6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_5_B") + (INSTANCE MAin_5_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (1250:1250:1250)) + (WIDTH (negedge MAin5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_4_B") + (INSTANCE MAin_4_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (1250:1250:1250)) + (WIDTH (negedge MAin4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_3_B") + (INSTANCE MAin_3_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (1250:1250:1250)) + (WIDTH (negedge MAin3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_2_B") + (INSTANCE MAin_2_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (1250:1250:1250)) + (WIDTH (negedge MAin2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_1_B") + (INSTANCE MAin_1_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (1250:1250:1250)) + (WIDTH (negedge MAin1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_0_B") + (INSTANCE MAin_0_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (1250:1250:1250)) + (WIDTH (negedge MAin0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "CROW_1_B") + (INSTANCE CROW_1_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (1250:1250:1250)) + (WIDTH (negedge CROW1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "CROW_0_B") + (INSTANCE CROW_0_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (1250:1250:1250)) + (WIDTH (negedge CROW0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_7_B") + (INSTANCE Din_7_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (1250:1250:1250)) + (WIDTH (negedge Din7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_6_B") + (INSTANCE Din_6_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (1250:1250:1250)) + (WIDTH (negedge Din6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_5_B") + (INSTANCE Din_5_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (1250:1250:1250)) + (WIDTH (negedge Din5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_4_B") + (INSTANCE Din_4_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (1250:1250:1250)) + (WIDTH (negedge Din4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_3_B") + (INSTANCE Din_3_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (1250:1250:1250)) + (WIDTH (negedge Din3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_2_B") + (INSTANCE Din_2_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (1250:1250:1250)) + (WIDTH (negedge Din2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_1_B") + (INSTANCE Din_1_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (1250:1250:1250)) + (WIDTH (negedge Din1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_0_B") + (INSTANCE Din_0_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (1250:1250:1250)) + (WIDTH (negedge Din0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nCCASB") + (INSTANCE nCCASI) + (DELAY + (ABSOLUTE + (IOPATH nCCASS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCCASS) (1250:1250:1250)) + (WIDTH (negedge nCCASS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nCRASB") + (INSTANCE nCRASI) + (DELAY + (ABSOLUTE + (IOPATH nCRASS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCRASS) (1250:1250:1250)) + (WIDTH (negedge nCRASS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nFWEB") + (INSTANCE nFWEI) + (DELAY + (ABSOLUTE + (IOPATH nFWES PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nFWES) (1250:1250:1250)) + (WIDTH (negedge nFWES) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RCLKB") + (INSTANCE RCLKI) + (DELAY + (ABSOLUTE + (IOPATH RCLKS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RCLKS) (1250:1250:1250)) + (WIDTH (negedge RCLKS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "UFMSDOB") + (INSTANCE UFMSDOI) + (DELAY + (ABSOLUTE + (IOPATH UFMSDOS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge UFMSDOS) (1250:1250:1250)) + (WIDTH (negedge UFMSDOS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0I/Q1 SLICE_0I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_77I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q1 SLICE_88I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_0I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_68I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/Q0 SLICE_88I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_0I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_1I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_2I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_3I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_4I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_5I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_6I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_7I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_8I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_25I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_26I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_31I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_34I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_35I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_36I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_43I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_44I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_56I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_58I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_60I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_61I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_63I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_64I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_65I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_66I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_67I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_68I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_69I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_74I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_76I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_77I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_79I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_80I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_82I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_83I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_84I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_86I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_87I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_91I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLKI/PADDI SLICE_100I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/FCO SLICE_0I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0I/FCO SLICE_7I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_1I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_94I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q1 SLICE_94I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_1I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_69I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_78I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_90I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/Q0 SLICE_90I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/FCO SLICE_1I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1I/FCO SLICE_8I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_2I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_77I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q1 SLICE_88I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_2I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_43I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2I/Q0 SLICE_77I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/FCO SLICE_2I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_3I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_94I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q1 SLICE_94I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_3I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_68I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_69I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3I/Q0 SLICE_90I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/FCO SLICE_3I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_4I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_43I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q1 SLICE_68I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_4I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/Q0 SLICE_68I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4I/FCO SLICE_6I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_5I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_44I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_56I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_75I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_75I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_78I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_94I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q1 SLICE_95I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_5I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_56I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_75I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_88I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_95I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5I/Q0 SLICE_95I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/FCO SLICE_5I/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_6I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q1 SLICE_68I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_6I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6I/Q0 SLICE_77I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q1 SLICE_7I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q1 SLICE_77I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q1 SLICE_88I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_7I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_87I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7I/Q0 SLICE_88I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_8I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_68I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_69I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q1 SLICE_90I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_8I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_78I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_90I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_90I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8I/Q0 SLICE_94I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_9I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_14I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_18I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI i26_SLICE_71I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_82I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_83I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_84I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_89I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_89I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_97I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_1_I/PADDI SLICE_99I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_9I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_14I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_18I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_76I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_82I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_84I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_89I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F1 SLICE_89I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_9I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI i26_SLICE_71I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI i26_SLICE_71I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI i26_adj_28_SLICE_73I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI i26_adj_28_SLICE_73I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_76I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_82I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_83I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_84I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_89I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_97I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_0_I/PADDI SLICE_98I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/F1 SLICE_9I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 SLICE_9I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/Q0 i26_SLICE_71I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F1 SLICE_9I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/F1 SLICE_9I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9I/F0 SLICE_9I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F0 SLICE_9I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F0 SLICE_14I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_9I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_14I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_18I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_19I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_23I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_32I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_49I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_81I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_88I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_91I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_93I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_99I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_101I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2I/PADDI SLICE_102I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_14I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_23I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_32I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_32I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI i26_adj_28_SLICE_73I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI i26_adj_28_SLICE_73I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_79I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_92I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_92I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_92I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_6_I/PADDI SLICE_99I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14I/Q0 SLICE_14I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14I/Q0 SLICE_14I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_14I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_76I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_82I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_85I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_86I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_89I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_98I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWEI/PADDI SLICE_105I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14I/F0 SLICE_14I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14I/F1 i26_SLICE_71I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_18I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_95I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_5_I/PADDI SLICE_103I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F0 SLICE_18I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F0 SLICE_18I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_18I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_96I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_2_I/PADDI SLICE_101I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT i26_adj_28_SLICE_73I/OFX0 SLICE_18I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F0 SLICE_18I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F0 SLICE_79I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/F0 SLICE_18I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F1 SLICE_18I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/Q0 SLICE_83I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18I/Q0 SLICE_84I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q1 SLICE_19I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q1 SLICE_91I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q1 SLICE_100I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/Q0 SLICE_19I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/Q0 SLICE_100I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q0 SLICE_19I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q0 SLICE_100I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F0 SLICE_19I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F0 SLICE_19I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F1 SLICE_67I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19I/F1 SLICE_87I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_23I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI i26_SLICE_71I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI i26_adj_28_SLICE_73I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_76I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_79I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_85I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_91I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_91I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_101I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_5_I/PADDI SLICE_105I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_23I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_32I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_86I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_92I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_7_I/PADDI SLICE_99I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F1 SLICE_23I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F1 SLICE_49I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F1 SLICE_84I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_23I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_49I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_76I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_83I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_85I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_86I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_91I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_101I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_105I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_4_I/PADDI SLICE_105I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/Q0 SLICE_23I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/Q0 SLICE_32I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_23I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_49I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_86I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_88I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_89I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_0_I/PADDI SLICE_93I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/F0 SLICE_23I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F0 SLICE_23I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23I/Q0 SLICE_56I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_25I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_36I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_58I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_60I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_61I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_63I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_67I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 RCKEEN_I_0_445_SLICE_70I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 i2099_SLICE_72I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 i2099_SLICE_72I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_80I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q0 SLICE_104I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_25I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_34I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_35I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_35I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_58I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_60I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_63I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_65I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_65I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_66I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_68I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 RCKEEN_I_0_445_SLICE_70I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_74I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q0 SLICE_100I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_25I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_34I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_34I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_43I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_44I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_56I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_60I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_63I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_65I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_69I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_75I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_78I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_87I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_95I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_100I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_100I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/Q0 SLICE_102I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_25I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_31I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_31I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_32I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_34I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_34I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_36I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_58I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_58I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_60I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_61I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_63I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 i2099_SLICE_72I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 i2099_SLICE_72I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_78I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_80I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_85I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_90I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_95I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_96I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_97I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_100I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/Q0 SLICE_104I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F0 SLICE_25I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/F1 SLICE_25I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_76I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_77I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_80I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_82I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_84I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_86I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_87I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25I/F1 SLICE_100I/CE (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_26I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_78I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_83I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_85I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_90I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_95I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_96I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_97I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRASI/PADDI SLICE_98I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_26I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_58I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 RCKEEN_I_0_445_SLICE_70I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 RCKEEN_I_0_445_SLICE_70I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_74I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_74I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q0 SLICE_103I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_26I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/Q0 SLICE_49I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/F0 SLICE_26I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F1 SLICE_26I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26I/F1 LEDI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_31I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_58I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_66I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_66I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 RCKEEN_I_0_445_SLICE_70I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 i2099_SLICE_72I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/Q0 SLICE_80I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 SLICE_31I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 SLICE_84I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 SLICE_102I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q1 SLICE_102I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63I/F1 SLICE_31I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63I/F1 SLICE_63I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31I/F0 SLICE_31I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q1 SLICE_31I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q1 SLICE_82I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q1 SLICE_102I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31I/Q0 RA_10_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31I/F1 SLICE_61I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49I/Q0 SLICE_32I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/F0 SLICE_32I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/Q0 RA_11_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32I/F1 SLICE_83I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT RCKEEN_I_0_445_SLICE_70I/OFX0 SLICE_34I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34I/F0 SLICE_34I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F1 SLICE_34I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F1 SLICE_58I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F1 SLICE_60I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34I/Q0 SLICE_35I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34I/F1 SLICE_60I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q0 SLICE_35I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q0 SLICE_60I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q0 RCKEI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/Q1 SLICE_35I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/Q0 SLICE_35I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/Q0 SLICE_74I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F0 SLICE_35I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/Q0 SLICE_35I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/F1 SLICE_104I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q1 SLICE_67I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q1 SLICE_68I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35I/Q1 SLICE_74I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/F0 SLICE_36I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F1 SLICE_36I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/F1 SLICE_64I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36I/F1 SLICE_66I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F1 SLICE_43I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F1 SLICE_44I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F1 SLICE_43I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F1 SLICE_69I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F1 SLICE_95I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43I/F1 SLICE_43I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q0 SLICE_43I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43I/F0 SLICE_43I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F0 SLICE_43I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F0 SLICE_44I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F0 SLICE_43I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F0 SLICE_44I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43I/Q0 UFMCLKI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F0 SLICE_44I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F1 SLICE_44I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F1 SLICE_75I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F1 SLICE_78I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F1 SLICE_44I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F1 SLICE_78I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/Q0 SLICE_44I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F1 SLICE_44I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/F0 SLICE_44I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44I/Q0 UFMSDII/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_49I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_81I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_86I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_88I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_1_I/PADDI SLICE_89I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49I/F1 SLICE_49I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_49I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI i26_SLICE_71I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI i26_adj_28_SLICE_73I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI i26_adj_28_SLICE_73I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_79I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_81I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_92I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_102I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_2_I/PADDI SLICE_103I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_49I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI i26_adj_28_SLICE_73I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI i26_adj_28_SLICE_73I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_76I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_79I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_91I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_91I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_92I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_92I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_102I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din_3_I/PADDI SLICE_103I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49I/F0 SLICE_49I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/F1 SLICE_49I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F1 SLICE_56I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F1 SLICE_78I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/F1 SLICE_95I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/F1 SLICE_56I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDOI/PADDI SLICE_56I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56I/F0 SLICE_56I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F0 SLICE_56I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/F0 SLICE_58I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 SLICE_58I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F1 i2099_SLICE_72I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58I/OFX0 SLICE_58I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58I/Q0 nRCASI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60I/F1 SLICE_60I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60I/F1 SLICE_61I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT i2099_SLICE_72I/OFX0 SLICE_60I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60I/F0 SLICE_60I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60I/Q0 nRCSI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 SLICE_61I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 SLICE_63I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 i2099_SLICE_72I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 i2099_SLICE_72I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 SLICE_87I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/Q0 SLICE_102I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_61I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_64I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_65I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_65I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_66I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_66I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/Q0 SLICE_80I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/F1 SLICE_61I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/Q0 SLICE_61I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/Q0 nRRASI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61I/OFX0 SLICE_61I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104I/F0 SLICE_63I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/F1 SLICE_63I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63I/F0 SLICE_63I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F0 SLICE_63I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63I/Q0 nRWEI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_64I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_64I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_93I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_93I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_96I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_97I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_98I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_98I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_99I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_99I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_101I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_101I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/Q0 SLICE_103I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_64I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_90I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_93I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_9_I/PADDI SLICE_93I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/Q1 SLICE_64I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/F0 SLICE_64I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_64I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_80I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/F1 SLICE_104I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/F0 SLICE_64I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64I/F1 RA_9_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/Q1 SLICE_65I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/Q1 SLICE_87I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_65I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_66I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_67I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_74I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_80I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/Q0 SLICE_100I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F0 SLICE_65I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65I/F1 SLICE_104I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F0 SLICE_66I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66I/F0 SLICE_67I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/Q1 SLICE_67I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 SLICE_67I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/Q0 nUFMCSI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/F0 RCKEEN_I_0_445_SLICE_70I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67I/F1 SLICE_69I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/F0 SLICE_77I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q1 SLICE_74I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68I/Q1 SLICE_103I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94I/F0 SLICE_69I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69I/F0 SLICE_69I/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/F0 SLICE_69I/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 RCKEEN_I_0_445_SLICE_70I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 RCKEEN_I_0_445_SLICE_70I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_74I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_74I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/Q1 SLICE_103I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F1 i26_SLICE_71I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/F1 SLICE_83I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F1 i26_SLICE_71I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT i26_SLICE_71I/OFX0 SLICE_105I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F0 SLICE_74I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74I/F0 SLICE_104I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F0 SLICE_75I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75I/F0 SLICE_87I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/F1 SLICE_75I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F0 SLICE_76I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F0 SLICE_83I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F1 SLICE_76I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/F1 SLICE_91I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76I/Q0 SLICE_76I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/Q1 SLICE_76I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F0 SLICE_77I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/Q0 SLICE_77I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/Q1 SLICE_77I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/F1 SLICE_87I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77I/Q1 SLICE_80I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_78I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_96I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_7_I/PADDI SLICE_99I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_78I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_97I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_6_I/PADDI SLICE_101I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/Q0 SLICE_101I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78I/Q1 SLICE_99I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79I/F1 SLICE_79I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/F0 SLICE_79I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91I/Q1 SLICE_79I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_79I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_89I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_92I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_98I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_103I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_105I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nCCASI/PADDI SLICE_105I/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80I/Q0 SLICE_80I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/Q1 SLICE_81I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/Q0 SLICE_81I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/Q1 SLICE_81I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81I/F1 SLICE_81I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/F0 SLICE_81I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102I/Q0 SLICE_81I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F1 SLICE_81I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83I/F1 SLICE_93I/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F0 SLICE_82I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F0 SLICE_82I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/F0 SLICE_83I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82I/Q0 SLICE_82I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/F0 SLICE_84I/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_84I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/F0 SLICE_85I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/Q0 SLICE_84I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84I/Q1 SLICE_100I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/F0 SLICE_85I/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F1 SLICE_85I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F1 SLICE_86I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/F1 SLICE_105I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT CROW_1_I/PADDI SLICE_85I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW_0_I/PADDI SLICE_85I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/Q0 RBA_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85I/Q1 RBA_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86I/Q0 SLICE_86I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/Q1 SLICE_86I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87I/F1 SLICE_87I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/F0 SLICE_88I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/Q0 SLICE_97I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88I/Q1 SLICE_96I/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/Q0 RD_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89I/Q1 RD_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin_8_I/PADDI SLICE_90I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_8_I/PADDI SLICE_98I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90I/Q0 SLICE_98I/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/Q0 RD_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92I/Q1 RD_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/F0 RDQMHI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93I/F1 RDQMLI/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_95I/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_97I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_4_I/PADDI SLICE_97I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/Q0 SLICE_97I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95I/Q1 SLICE_103I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_96I/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_96I/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin_3_I/PADDI SLICE_96I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/Q1 SLICE_96I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/Q0 SLICE_96I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/Q0 SLICE_101I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96I/F1 RA_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/Q1 SLICE_97I/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/Q0 SLICE_98I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/F1 RA_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97I/Q1 SLICE_99I/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/F0 RA_8_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98I/F1 RA_0_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F0 RA_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99I/F1 RA_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100I/Q0 SLICE_100I/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/F0 RA_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101I/F1 RA_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/Q0 RD_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/F1 RA_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103I/Q1 RD_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/Q0 RD_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_7_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_6_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_5_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_4_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_3_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_2_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_1_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/F1 RD_0_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105I/Q1 RD_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_7_I/PADDI Dout_7_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_6_I/PADDI Dout_6_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_5_I/PADDI Dout_5_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_4_I/PADDI Dout_4_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_3_I/PADDI Dout_3_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_2_I/PADDI Dout_2_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_1_I/PADDI Dout_1_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD_0_I/PADDI Dout_0_I/PADDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.vho b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.vho new file mode 100644 index 0000000..3bd68d2 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvho.vho @@ -0,0 +1,26269 @@ + +-- VHDL netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +-- ldbanno -n VHDL -o RAM2GS_LCMXO640C_impl1_mapvho.vho -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd +-- Netlist created on Tue Aug 15 05:03:22 2023 +-- Netlist written on Tue Aug 15 05:03:24 2023 +-- Design is for device LCMXO640C +-- Design is for package TQFP100 +-- Design is for performance grade 3 + +-- entity vmuxregsre + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vmuxregsre is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre : ENTITY IS TRUE; + + end vmuxregsre; + + architecture Structure of vmuxregsre is + component FL1P3DX + generic (GSR: String); + port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; + CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; + Q: out Std_logic); + end component; + begin + INST01: FL1P3DX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity vcc + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vcc is + port (PWR1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vcc : ENTITY IS TRUE; + + end vcc; + + architecture Structure of vcc is + component VHI + port (Z: out Std_logic); + end component; + begin + INST1: VHI + port map (Z=>PWR1); + end Structure; + +-- entity gnd + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity gnd is + port (PWR0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF gnd : ENTITY IS TRUE; + + end gnd; + + architecture Structure of gnd is + component VLO + port (Z: out Std_logic); + end component; + begin + INST1: VLO + port map (Z=>PWR0); + end Structure; + +-- entity ccu2B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity ccu2B is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu2B : ENTITY IS TRUE; + + end ccu2B; + + architecture Structure of ccu2B is + component CCU2 + generic (INIT0: String; INIT1: String; INJECT1_0: String; + INJECT1_1: String); + port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; + C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; + B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; + S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; + COUT1: out Std_logic); + end component; + begin + inst1: CCU2 + generic map (INIT0 => "0xfaaa", INIT1 => "0xfaaa", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1); + end Structure; + +-- entity SLICE_0 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_0 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_0"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_0 : ENTITY IS TRUE; + + end SLICE_0; + + architecture Structure of SLICE_0 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_0_FS_610_add_4_8_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_0_FS_610_add_4_8_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i7: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_0_FS_610_add_4_8_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i6: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_0_FS_610_add_4_8_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_8: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_0_FS_610_add_4_8_S0, + S1=>SLICE_0_FS_610_add_4_8_S1, CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_1 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_1 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_1"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_1 : ENTITY IS TRUE; + + end SLICE_1; + + architecture Structure of SLICE_1 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_1_FS_610_add_4_16_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_1_FS_610_add_4_16_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i15: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_1_FS_610_add_4_16_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i14: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_1_FS_610_add_4_16_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_16: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_1_FS_610_add_4_16_S0, S1=>SLICE_1_FS_610_add_4_16_S1, + CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_2 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_2 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_2"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_2 : ENTITY IS TRUE; + + end SLICE_2; + + architecture Structure of SLICE_2 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_2_FS_610_add_4_6_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_2_FS_610_add_4_6_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i5: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_2_FS_610_add_4_6_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i4: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_2_FS_610_add_4_6_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_6: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_2_FS_610_add_4_6_S0, + S1=>SLICE_2_FS_610_add_4_6_S1, CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_3 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_3 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_3"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_3 : ENTITY IS TRUE; + + end SLICE_3; + + architecture Structure of SLICE_3 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_3_FS_610_add_4_14_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_3_FS_610_add_4_14_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i13: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_3_FS_610_add_4_14_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i12: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_3_FS_610_add_4_14_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_14: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_3_FS_610_add_4_14_S0, S1=>SLICE_3_FS_610_add_4_14_S1, + CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity ccu20001 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity ccu20001 is + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF ccu20001 : ENTITY IS TRUE; + + end ccu20001; + + architecture Structure of ccu20001 is + component CCU2 + generic (INIT0: String; INIT1: String; INJECT1_0: String; + INJECT1_1: String); + port (CIN: in Std_logic; A0: in Std_logic; B0: in Std_logic; + C0: in Std_logic; D0: in Std_logic; A1: in Std_logic; + B1: in Std_logic; C1: in Std_logic; D1: in Std_logic; + S0: out Std_logic; S1: out Std_logic; COUT0: out Std_logic; + COUT1: out Std_logic); + end component; + begin + inst1: CCU2 + generic map (INIT0 => "0x0555", INIT1 => "0xfaaa", INJECT1_0 => "NO", + INJECT1_1 => "NO") + port map (CIN=>CI, A0=>A0, B0=>B0, C0=>C0, D0=>D0, A1=>A1, B1=>B1, + C1=>C1, D1=>D1, S0=>S0, S1=>S1, COUT0=>CO0, COUT1=>CO1); + end Structure; + +-- entity SLICE_4 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_4 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_4"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_4 : ENTITY IS TRUE; + + end SLICE_4; + + architecture Structure of SLICE_4 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_4_FS_610_add_4_2_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_4_FS_610_add_4_2_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu20001 + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i1: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_4_FS_610_add_4_2_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i0: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_4_FS_610_add_4_2_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_2: ccu20001 + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>GNDI, S0=>SLICE_4_FS_610_add_4_2_S0, + S1=>SLICE_4_FS_610_add_4_2_S1, CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, Q0_out, Q1_out, FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_5 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_5 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_5"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_5 : ENTITY IS TRUE; + + end SLICE_5; + + architecture Structure of SLICE_5 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_5_FS_610_add_4_12_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_5_FS_610_add_4_12_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i11: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_5_FS_610_add_4_12_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i10: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_5_FS_610_add_4_12_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_12: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_5_FS_610_add_4_12_S0, S1=>SLICE_5_FS_610_add_4_12_S1, + CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_6 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_6 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_6"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_6 : ENTITY IS TRUE; + + end SLICE_6; + + architecture Structure of SLICE_6 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_6_FS_610_add_4_4_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_6_FS_610_add_4_4_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i3: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_6_FS_610_add_4_4_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i2: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_6_FS_610_add_4_4_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_4: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, S0=>SLICE_6_FS_610_add_4_4_S0, + S1=>SLICE_6_FS_610_add_4_4_S1, CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_7 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_7 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_7"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_FCO : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_FCI_FCO : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_7 : ENTITY IS TRUE; + + end SLICE_7; + + architecture Structure of SLICE_7 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + signal FCO_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_7_FS_610_add_4_10_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_7_FS_610_add_4_10_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i9: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_7_FS_610_add_4_10_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i8: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_7_FS_610_add_4_10_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_10: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_7_FS_610_add_4_10_S0, S1=>SLICE_7_FS_610_add_4_10_S1, + CO0=>open, CO1=>FCO_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out, + FCO_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + VARIABLE FCO_zd : std_logic := 'X'; + VARIABLE FCO_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + FCO_zd := FCO_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => FCO, OutSignalName => "FCO", OutTemp => FCO_zd, + Paths => (0 => (InputChangeTime => A1_dly'last_event, + PathDelay => tpd_A1_FCO, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_dly'last_event, + PathDelay => tpd_A0_FCO, + PathCondition => TRUE), + 2 => (InputChangeTime => FCI_dly'last_event, + PathDelay => tpd_FCI_FCO, + PathCondition => TRUE)), + GlitchData => FCO_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_8 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_8 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_8"; + + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tipd_FCI : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_A1_CLK : VitalDelayType := 0 ns; + tsetup_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_A0_CLK : VitalDelayType := 0 ns; + tsetup_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_A0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_FCI_CLK : VitalDelayType := 0 ns; + tsetup_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_FCI_CLK_noedge_posedge : VitalDelayType := 0 ns); + + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_8 : ENTITY IS TRUE; + + end SLICE_8; + + architecture Structure of SLICE_8 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal A1_ipd : std_logic := 'X'; + signal A1_dly : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal A0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal FCI_ipd : std_logic := 'X'; + signal FCI_dly : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal SLICE_8_FS_610_add_4_18_S1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_8_FS_610_add_4_18_S0: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component ccu2B + port (A0: in Std_logic; B0: in Std_logic; C0: in Std_logic; + D0: in Std_logic; A1: in Std_logic; B1: in Std_logic; + C1: in Std_logic; D1: in Std_logic; CI: in Std_logic; + S0: out Std_logic; S1: out Std_logic; CO0: out Std_logic; + CO1: out Std_logic); + end component; + begin + FS_610_i17: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_8_FS_610_add_4_18_S1, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_610_i16: vmuxregsre + port map (D0=>VCCI, D1=>SLICE_8_FS_610_add_4_18_S0, SD=>VCCI, SP=>VCCI, + CK=>CLK_dly, LSR=>GNDI, Q=>Q0_out); + FS_610_add_4_18: ccu2B + port map (A0=>A0_dly, B0=>GNDI, C0=>GNDI, D0=>GNDI, A1=>A1_dly, B1=>GNDI, + C1=>GNDI, D1=>GNDI, CI=>FCI_dly, + S0=>SLICE_8_FS_610_add_4_18_S0, S1=>SLICE_8_FS_610_add_4_18_S1, + CO0=>open, CO1=>open); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + VitalWireDelay(FCI_ipd, FCI, tipd_FCI); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(A1_dly, A1_ipd, tisd_A1_CLK); + VitalSignalDelay(A0_dly, A0_ipd, tisd_A0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + VitalSignalDelay(FCI_dly, FCI_ipd, tisd_FCI_CLK); + END BLOCK; + + VitalBehavior : PROCESS (A1_dly, A0_dly, CLK_dly, FCI_dly, Q0_out, Q1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_A1_CLK : x01 := '0'; + VARIABLE A1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_A0_CLK : x01 := '0'; + VARIABLE A0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_FCI_CLK : x01 := '0'; + VARIABLE FCI_CLK_TimingDatash : VitalTimingDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => A1_dly, + TestSignalName => "A1", + TestDelay => tisd_A1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A1_CLK_noedge_posedge, + SetupLow => tsetup_A1_CLK_noedge_posedge, + HoldHigh => thold_A1_CLK_noedge_posedge, + HoldLow => thold_A1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A1_CLK_TimingDatash, + Violation => tviol_A1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => A0_dly, + TestSignalName => "A0", + TestDelay => tisd_A0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_A0_CLK_noedge_posedge, + SetupLow => tsetup_A0_CLK_noedge_posedge, + HoldHigh => thold_A0_CLK_noedge_posedge, + HoldLow => thold_A0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => A0_CLK_TimingDatash, + Violation => tviol_A0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => FCI_dly, + TestSignalName => "FCI", + TestDelay => tisd_FCI_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_FCI_CLK_noedge_posedge, + SetupLow => tsetup_FCI_CLK_noedge_posedge, + HoldHigh => thold_FCI_CLK_noedge_posedge, + HoldLow => thold_FCI_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => FCI_CLK_TimingDatash, + Violation => tviol_FCI_CLK, + MsgSeverity => warning); + + END IF; + + Q0_zd := Q0_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut4 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut4 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut4 : ENTITY IS TRUE; + + end lut4; + + architecture Structure of lut4 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xDFDF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40002 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40002 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40002 : ENTITY IS TRUE; + + end lut40002; + + architecture Structure of lut40002 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x50DC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0003 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vmuxregsre0003 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0003 : ENTITY IS TRUE; + + end vmuxregsre0003; + + architecture Structure of vmuxregsre0003 is + component FL1P3IY + generic (GSR: String); + port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; + CK: in Std_logic; SD: in Std_logic; CD: in Std_logic; + Q: out Std_logic); + end component; + begin + INST01: FL1P3IY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, CD=>LSR, Q=>Q); + end Structure; + +-- entity inverter + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity inverter is + port (I: in Std_logic; Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF inverter : ENTITY IS TRUE; + + end inverter; + + architecture Structure of inverter is + component INV + port (A: in Std_logic; Z: out Std_logic); + end component; + begin + INST1: INV + port map (A=>I, Z=>Z); + end Structure; + +-- entity SLICE_9 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_9 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_9"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_9 : ENTITY IS TRUE; + + end SLICE_9; + + architecture Structure of SLICE_9 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40002 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1125_4_lut: lut40002 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + ADSubmitted_407: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40004 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40004 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40004 : ENTITY IS TRUE; + + end lut40004; + + architecture Structure of lut40004 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xEEEE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40005 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40005 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40005 : ENTITY IS TRUE; + + end lut40005; + + architecture Structure of lut40005 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xE0F0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0006 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vmuxregsre0006 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0006 : ENTITY IS TRUE; + + end vmuxregsre0006; + + architecture Structure of vmuxregsre0006 is + component FL1P3JY + generic (GSR: String); + port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; + CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; + Q: out Std_logic); + end component; + begin + INST01: FL1P3JY + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); + end Structure; + +-- entity SLICE_14 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_14 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_14"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_14 : ENTITY IS TRUE; + + end SLICE_14; + + architecture Structure of SLICE_14 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40005 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + begin + i1988_2_lut: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2062_2_lut_3_lut_4_lut: lut40005 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + C1Submitted_406: vmuxregsre0006 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40007 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40007 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40007 : ENTITY IS TRUE; + + end lut40007; + + architecture Structure of lut40007 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xDFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40008 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40008 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40008 : ENTITY IS TRUE; + + end lut40008; + + architecture Structure of lut40008 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0800") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_18 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_18 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_18"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_18 : ENTITY IS TRUE; + + end SLICE_18; + + architecture Structure of SLICE_18 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40007 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i13_4_lut: lut40007 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut_adj_21: lut40008 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdEnable_405: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40009 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40009 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40009 : ENTITY IS TRUE; + + end lut40009; + + architecture Structure of lut40009 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0808") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40010 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40010 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40010 : ENTITY IS TRUE; + + end lut40010; + + architecture Structure of lut40010 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_19 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_19 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_19"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_19 : ENTITY IS TRUE; + + end SLICE_19; + + architecture Structure of SLICE_19 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_rep_29: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n2568_001_BUF1_BUF1: lut40010 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + CmdSubmitted_411: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, DI0_dly, CE_dly, CLK_dly, + F0_out, Q0_out, F1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40011 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40011 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40011 : ENTITY IS TRUE; + + end lut40011; + + architecture Structure of lut40011 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFEFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40012 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40012 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40012 : ENTITY IS TRUE; + + end lut40012; + + architecture Structure of lut40012 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCC5C") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_23 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_23 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_23"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_23 : ENTITY IS TRUE; + + end SLICE_23; + + architecture Structure of SLICE_23 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40012 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut_adj_2: lut40011 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + Cmdn8MEGEN_I_93_4_lut: lut40012 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Cmdn8MEGEN_410: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40013 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40013 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40013 : ENTITY IS TRUE; + + end lut40013; + + architecture Structure of lut40013 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x4000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_25 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_25 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_25"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_25 : ENTITY IS TRUE; + + end SLICE_25; + + architecture Structure of SLICE_25 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_3_lut_4_lut_4_lut: lut40013 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + n2568_000_BUF1_BUF1: lut40010 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + InitReady_394: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, DI0_dly, CE_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40014 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40014 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40014 : ENTITY IS TRUE; + + end lut40014; + + architecture Structure of lut40014 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFDFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_26 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_26 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_26"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_26 : ENTITY IS TRUE; + + end SLICE_26; + + architecture Structure of SLICE_26 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2049_3_lut: lut40014 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + m1_lut: lut40010 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + LEDEN_419: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, DI0_dly, CE_dly, CLK_dly, + F0_out, Q0_out, F1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40015 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40015 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40015 : ENTITY IS TRUE; + + end lut40015; + + architecture Structure of lut40015 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xDDDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_31 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_31 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_31"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_31 : ENTITY IS TRUE; + + end SLICE_31; + + architecture Structure of SLICE_31 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_2_lut: lut40015 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_adj_27: lut40011 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RA10_400: vmuxregsre0006 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, + LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40016 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40016 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40016 : ENTITY IS TRUE; + + end lut40016; + + architecture Structure of lut40016 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xC6C6") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_32 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_32 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_32"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_32 : ENTITY IS TRUE; + + end SLICE_32; + + architecture Structure of SLICE_32 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40016 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Din_7_I_0_462_i6_2_lut_rep_35: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RA11_I_54_3_lut: lut40016 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RA11_385: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, DI0_dly, + LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40017 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40017 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40017 : ENTITY IS TRUE; + + end lut40017; + + architecture Structure of lut40017 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xF8F8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40018 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40018 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40018 : ENTITY IS TRUE; + + end lut40018; + + architecture Structure of lut40018 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCACA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_34 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_34 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_34"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_34 : ENTITY IS TRUE; + + end SLICE_34; + + architecture Structure of SLICE_34 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40017 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i78_2_lut_rep_24_3_lut: lut40017 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1259_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + RCKEEN_401: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40019 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40019 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40019 : ENTITY IS TRUE; + + end lut40019; + + architecture Structure of lut40019 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xBBBB") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40020 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40020 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40020 : ENTITY IS TRUE; + + end lut40020; + + architecture Structure of lut40020 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCFC8") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_35 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_35 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_35"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_35 : ENTITY IS TRUE; + + end SLICE_35; + + architecture Structure of SLICE_35 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40020 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut: lut40019 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKE_I_0_449_4_lut: lut40020 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CASr2_383: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + RCKE_395: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + DI0_dly, M1_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_36 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_36 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_36"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_36 : ENTITY IS TRUE; + + end SLICE_36; + + architecture Structure of SLICE_36 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40010 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40015 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i771_2_lut_rep_26_2_lut: lut40015 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n2568_002_BUF1_BUF1: lut40010 + port map (A=>GNDI, B=>GNDI, C=>GNDI, D=>GNDI, Z=>F0_out); + Ready_404: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, + Q0_out, F1_out) + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0 <= F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40021 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40021 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40021 : ENTITY IS TRUE; + + end lut40021; + + architecture Structure of lut40021 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x3A0A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40022 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40022 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40022 : ENTITY IS TRUE; + + end lut40022; + + architecture Structure of lut40022 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xACAC") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_43 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_43 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_43"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_43 : ENTITY IS TRUE; + + end SLICE_43; + + architecture Structure of SLICE_43 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40021 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40022 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i919_4_lut: lut40021 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i886_3_lut: lut40022 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + UFMCLK_416: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40023 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40023 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40023 : ENTITY IS TRUE; + + end lut40023; + + architecture Structure of lut40023 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFEFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40024 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40024 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40024 : ENTITY IS TRUE; + + end lut40024; + + architecture Structure of lut40024 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xF202") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_44 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_44 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_44"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_44 : ENTITY IS TRUE; + + end SLICE_44; + + architecture Structure of SLICE_44 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40023 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40024 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_19_4_lut: lut40023 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + n2454_bdd_3_lut_4_lut: lut40024 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + UFMSDI_417: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, LSR_dly, CLK_dly, F0_out, Q0_out, + F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40025 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40025 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40025 : ENTITY IS TRUE; + + end lut40025; + + architecture Structure of lut40025 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFEFA") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40026 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40026 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40026 : ENTITY IS TRUE; + + end lut40026; + + architecture Structure of lut40026 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_49 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_49 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_49"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_49 : ENTITY IS TRUE; + + end SLICE_49; + + architecture Structure of SLICE_49 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40025 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2028_4_lut: lut40025 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut_adj_12: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + XOR8MEG_408: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_negedge, + SetupLow => tsetup_DI0_CLK_noedge_negedge, + HoldHigh => thold_DI0_CLK_noedge_negedge, + HoldLow => thold_DI0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40027 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40027 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40027 : ENTITY IS TRUE; + + end lut40027; + + architecture Structure of lut40027 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCCC5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_56 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_56 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_56"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_56 : ENTITY IS TRUE; + + end SLICE_56; + + architecture Structure of SLICE_56 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut4 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40027 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_3_lut_adj_4: lut4 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n8MEGEN_I_14_4_lut: lut40027 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + n8MEGEN_418: vmuxregsre + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40028 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40028 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40028 : ENTITY IS TRUE; + + end lut40028; + + architecture Structure of lut40028 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x7F2F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40029 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40029 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40029 : ENTITY IS TRUE; + + end lut40029; + + architecture Structure of lut40029 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xBFBF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity vmuxregsre0030 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity vmuxregsre0030 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + + ATTRIBUTE Vital_Level0 OF vmuxregsre0030 : ENTITY IS TRUE; + + end vmuxregsre0030; + + architecture Structure of vmuxregsre0030 is + component FL1P3BX + generic (GSR: String); + port (D0: in Std_logic; D1: in Std_logic; SP: in Std_logic; + CK: in Std_logic; SD: in Std_logic; PD: in Std_logic; + Q: out Std_logic); + end component; + begin + INST01: FL1P3BX + generic map (GSR => "DISABLED") + port map (D0=>D0, D1=>D1, SP=>SP, CK=>CK, SD=>SD, PD=>LSR, Q=>Q); + end Structure; + +-- entity selmux2 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity selmux2 is + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF selmux2 : ENTITY IS TRUE; + + end selmux2; + + architecture Structure of selmux2 is + component MUX21 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + begin + INST1: MUX21 + port map (D0=>D0, D1=>D1, SD=>SD, Z=>Z); + end Structure; + +-- entity SLICE_58 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_58 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_58"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; + Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_58 : ENTITY IS TRUE; + + end SLICE_58; + + architecture Structure of SLICE_58 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal SLICE_58_SLICE_58_K1_H1: Std_logic; + signal GNDI: Std_logic; + signal SLICE_58_i2095_GATE_H0: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40028 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40029 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0030 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + begin + SLICE_58_K1: lut40028 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>SLICE_58_SLICE_58_K1_H1); + i2095_GATE: lut40029 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, + Z=>SLICE_58_i2095_GATE_H0); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nRCAS_398: vmuxregsre0030 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + SLICE_58_K0K1MUX: selmux2 + port map (D0=>SLICE_58_i2095_GATE_H0, D1=>SLICE_58_SLICE_58_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, M0_ipd, CE_dly, CLK_dly, OFX0_out, Q0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + OFX0_zd := OFX0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40031 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40031 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40031 : ENTITY IS TRUE; + + end lut40031; + + architecture Structure of lut40031 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFA88") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40032 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40032 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40032 : ENTITY IS TRUE; + + end lut40032; + + architecture Structure of lut40032 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCFDD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_60 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_60 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_60"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_60 : ENTITY IS TRUE; + + end SLICE_60; + + architecture Structure of SLICE_60 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0030 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40031 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40032 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1234_4_lut_4_lut: lut40031 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut_adj_17: lut40032 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRCS_396: vmuxregsre0030 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40033 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40033 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40033 : ENTITY IS TRUE; + + end lut40033; + + architecture Structure of lut40033 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x7373") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40034 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40034 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40034 : ENTITY IS TRUE; + + end lut40034; + + architecture Structure of lut40034 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFFFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_61 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_61 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_61"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_61 : ENTITY IS TRUE; + + end SLICE_61; + + architecture Structure of SLICE_61 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal SLICE_61_SLICE_61_K1_H1: Std_logic; + signal SLICE_61_i16_GATE_H0: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0030 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40033 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40034 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + SLICE_61_K1: lut40033 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, + Z=>SLICE_61_SLICE_61_K1_H1); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i16_GATE: lut40034 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>SLICE_61_i16_GATE_H0); + nRRAS_397: vmuxregsre0030 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + SLICE_61_K0K1MUX: selmux2 + port map (D0=>SLICE_61_i16_GATE_H0, D1=>SLICE_61_SLICE_61_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, M0_ipd, CLK_dly, OFX0_out, Q0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + OFX0_zd := OFX0_out; + Q0_zd := Q0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40035 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40035 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40035 : ENTITY IS TRUE; + + end lut40035; + + architecture Structure of lut40035 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFF7F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40036 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40036 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40036 : ENTITY IS TRUE; + + end lut40036; + + architecture Structure of lut40036 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCFC5") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_63 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_63 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_63"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_63 : ENTITY IS TRUE; + + end SLICE_63; + + architecture Structure of SLICE_63 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0030 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40035 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40036 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_4_lut_adj_8: lut40035 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + nRWE_I_0_455_4_lut: lut40036 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRWE_399: vmuxregsre0030 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, DI0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40037 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40037 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40037 : ENTITY IS TRUE; + + end lut40037; + + architecture Structure of lut40037 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCFEE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_64 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_64 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_64"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_64 : ENTITY IS TRUE; + + end SLICE_64; + + architecture Structure of SLICE_64 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40037 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i10_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_4_lut: lut40037 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + nRowColSel_402: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40038 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40038 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40038 : ENTITY IS TRUE; + + end lut40038; + + architecture Structure of lut40038 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_65 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_65 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_65"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_65 : ENTITY IS TRUE; + + end SLICE_65; + + architecture Structure of SLICE_65 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40038 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + Ready_bdd_4_lut: lut40038 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_adj_25: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_FSM_i4: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40039 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40039 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40039 : ENTITY IS TRUE; + + end lut40039; + + architecture Structure of lut40039 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFFFE") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40040 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40040 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40040 : ENTITY IS TRUE; + + end lut40040; + + architecture Structure of lut40040 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x4444") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_66 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_66 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_66"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_66 : ENTITY IS TRUE; + + end SLICE_66; + + architecture Structure of SLICE_66 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_4_lut: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2057_2_lut: lut40040 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + S_FSM_i3: vmuxregsre0003 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40041 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40041 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40041 : ENTITY IS TRUE; + + end lut40041; + + architecture Structure of lut40041 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x3A3A") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_67 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_67 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_67"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_67 : ENTITY IS TRUE; + + end SLICE_67; + + architecture Structure of SLICE_67 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40041 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1129_3_lut: lut40041 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_adj_23: lut40019 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + S_FSM_i2: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_NOTIN, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, + LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_68 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_68 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_68"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_68 : ENTITY IS TRUE; + + end SLICE_68; + + architecture Structure of SLICE_68 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal M0_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2024_2_lut_rep_28: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2026_4_lut: lut40039 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CASr3_384: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + S_FSM_i1: vmuxregsre + port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + M0_INVERTERIN: inverter + port map (I=>M0_dly, Z=>M0_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40042 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40042 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40042 : ENTITY IS TRUE; + + end lut40042; + + architecture Structure of lut40042 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x8000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_69 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_69 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_69"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_DI0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_DI0_CLK : VitalDelayType := 0 ns; + tsetup_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_DI0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_69 : ENTITY IS TRUE; + + end SLICE_69; + + architecture Structure of SLICE_69 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal DI0_ipd : std_logic := 'X'; + signal DI0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i6_4_lut: lut40042 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i11_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + nUFMCS_415: vmuxregsre0006 + port map (D0=>VCCI, D1=>DI0_dly, SD=>VCCI, SP=>VCCI, CK=>CLK_dly, + LSR=>LSR_dly, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(DI0_ipd, DI0, tipd_DI0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(DI0_dly, DI0_ipd, tisd_DI0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, DI0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_DI0_CLK : x01 := '0'; + VARIABLE DI0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => DI0_dly, + TestSignalName => "DI0", + TestDelay => tisd_DI0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_DI0_CLK_noedge_posedge, + SetupLow => tsetup_DI0_CLK_noedge_posedge, + HoldHigh => thold_DI0_CLK_noedge_posedge, + HoldLow => thold_DI0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => DI0_CLK_TimingDatash, + Violation => tviol_DI0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_posedge, + SetupLow => tsetup_LSR_CLK_noedge_posedge, + HoldHigh => thold_LSR_CLK_noedge_posedge, + HoldLow => thold_LSR_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40043 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40043 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40043 : ENTITY IS TRUE; + + end lut40043; + + architecture Structure of lut40043 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x1F1F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40044 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40044 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40044 : ENTITY IS TRUE; + + end lut40044; + + architecture Structure of lut40044 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x5540") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity RCKEEN_I_0_445_SLICE_70 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RCKEEN_I_0_445_SLICE_70 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCKEEN_I_0_445_SLICE_70"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RCKEEN_I_0_445_SLICE_70 : ENTITY IS TRUE; + + end RCKEEN_I_0_445_SLICE_70; + + architecture Structure of RCKEEN_I_0_445_SLICE_70 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_SLICE_70_K1_H1: Std_logic; + signal RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_GATE_H0: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40043 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40044 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + RCKEEN_I_0_445_SLICE_70_K1: lut40043 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, + Z=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_SLICE_70_K1_H1); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RCKEEN_I_0_445_GATE: lut40044 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_GATE_H0); + RCKEEN_I_0_445_SLICE_70_K0K1MUX: selmux2 + port map (D0=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_GATE_H0, + D1=>RCKEEN_I_0_445_SLICE_70_RCKEEN_I_0_445_SLICE_70_K1_H1, + SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40045 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40045 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40045 : ENTITY IS TRUE; + + end lut40045; + + architecture Structure of lut40045 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0080") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40046 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40046 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40046 : ENTITY IS TRUE; + + end lut40046; + + architecture Structure of lut40046 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity i26_SLICE_71 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity i26_SLICE_71 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "i26_SLICE_71"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF i26_SLICE_71 : ENTITY IS TRUE; + + end i26_SLICE_71; + + architecture Structure of i26_SLICE_71 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal i26_SLICE_71_i26_SLICE_71_K1_H1: Std_logic; + signal i26_SLICE_71_i26_GATE_H0: Std_logic; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40045 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40046 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i26_SLICE_71_K1: lut40045 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>i26_SLICE_71_i26_SLICE_71_K1_H1); + i26_GATE: lut40046 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>i26_SLICE_71_i26_GATE_H0); + i26_SLICE_71_K0K1MUX: selmux2 + port map (D0=>i26_SLICE_71_i26_GATE_H0, + D1=>i26_SLICE_71_i26_SLICE_71_K1_H1, SD=>M0_ipd, Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 8 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40047 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40047 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40047 : ENTITY IS TRUE; + + end lut40047; + + architecture Structure of lut40047 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2F23") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40048 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40048 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40048 : ENTITY IS TRUE; + + end lut40048; + + architecture Structure of lut40048 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2F2F") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity i2099_SLICE_72 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity i2099_SLICE_72 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "i2099_SLICE_72"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF i2099_SLICE_72 : ENTITY IS TRUE; + + end i2099_SLICE_72; + + architecture Structure of i2099_SLICE_72 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal i2099_SLICE_72_i2099_SLICE_72_K1_H1: Std_logic; + signal GNDI: Std_logic; + signal i2099_SLICE_72_i2099_GATE_H0: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40047 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40048 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2099_SLICE_72_K1: lut40047 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>i2099_SLICE_72_i2099_SLICE_72_K1_H1); + i2099_GATE: lut40048 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, + Z=>i2099_SLICE_72_i2099_GATE_H0); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2099_SLICE_72_K0K1MUX: selmux2 + port map (D0=>i2099_SLICE_72_i2099_GATE_H0, + D1=>i2099_SLICE_72_i2099_SLICE_72_K1_H1, SD=>M0_ipd, + Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40049 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40049 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40049 : ENTITY IS TRUE; + + end lut40049; + + architecture Structure of lut40049 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x4000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40050 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40050 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40050 : ENTITY IS TRUE; + + end lut40050; + + architecture Structure of lut40050 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0002") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity i26_adj_28_SLICE_73 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity i26_adj_28_SLICE_73 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "i26_adj_28_SLICE_73"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_OFX0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_M0_OFX0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + OFX0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF i26_adj_28_SLICE_73 : ENTITY IS TRUE; + + end i26_adj_28_SLICE_73; + + architecture Structure of i26_adj_28_SLICE_73 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal OFX0_out : std_logic := 'X'; + + signal i26_adj_28_SLICE_73_i26_adj_28_SLICE_73_K1_H1: Std_logic; + signal i26_adj_28_SLICE_73_i26_adj_28_GATE_H0: Std_logic; + component selmux2 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + Z: out Std_logic); + end component; + component lut40049 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40050 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i26_adj_28_SLICE_73_K1: lut40049 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, + Z=>i26_adj_28_SLICE_73_i26_adj_28_SLICE_73_K1_H1); + i26_adj_28_GATE: lut40050 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, + Z=>i26_adj_28_SLICE_73_i26_adj_28_GATE_H0); + i26_adj_28_SLICE_73_K0K1MUX: selmux2 + port map (D0=>i26_adj_28_SLICE_73_i26_adj_28_GATE_H0, + D1=>i26_adj_28_SLICE_73_i26_adj_28_SLICE_73_K1_H1, SD=>M0_ipd, + Z=>OFX0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M0_ipd, OFX0_out) + VARIABLE OFX0_zd : std_logic := 'X'; + VARIABLE OFX0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + OFX0_zd := OFX0_out; + + VitalPathDelay01 ( + OutSignal => OFX0, OutSignalName => "OFX0", OutTemp => OFX0_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_OFX0, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_OFX0, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_OFX0, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_OFX0, + PathCondition => TRUE), + 4 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_OFX0, + PathCondition => TRUE), + 5 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_OFX0, + PathCondition => TRUE), + 6 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_OFX0, + PathCondition => TRUE), + 7 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_OFX0, + PathCondition => TRUE), + 8 => (InputChangeTime => M0_ipd'last_event, + PathDelay => tpd_M0_OFX0, + PathCondition => TRUE)), + GlitchData => OFX0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40051 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40051 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40051 : ENTITY IS TRUE; + + end lut40051; + + architecture Structure of lut40051 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x1F10") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40052 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40052 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40052 : ENTITY IS TRUE; + + end lut40052; + + architecture Structure of lut40052 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0040") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_74 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_74 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_74"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_74 : ENTITY IS TRUE; + + end SLICE_74; + + architecture Structure of SLICE_74 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40051 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40052 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i35_3_lut_4_lut: lut40051 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i3_4_lut: lut40052 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RASr3_381: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RASr2_380: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40053 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40053 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40053 : ENTITY IS TRUE; + + end lut40053; + + architecture Structure of lut40053 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0200") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_75 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_75 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_75"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_75 : ENTITY IS TRUE; + + end SLICE_75; + + architecture Structure of SLICE_75 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40053 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i7_4_lut: lut40053 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40054 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40054 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40054 : ENTITY IS TRUE; + + end lut40054; + + architecture Structure of lut40054 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x1000") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40055 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40055 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40055 : ENTITY IS TRUE; + + end lut40055; + + architecture Structure of lut40055 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xB300") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_76 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_76 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_76"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_76 : ENTITY IS TRUE; + + end SLICE_76; + + architecture Structure of SLICE_76 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40054 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40055 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i5_3_lut_rep_15_4_lut: lut40054 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_4_lut_4_lut: lut40055 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i9: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i8: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40056 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40056 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40056 : ENTITY IS TRUE; + + end lut40056; + + architecture Structure of lut40056 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0004") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_77 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_77 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_77"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_77 : ENTITY IS TRUE; + + end SLICE_77; + + architecture Structure of SLICE_77 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40011 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40056 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i3_4_lut_adj_18: lut40056 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1994_3_lut: lut40011 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i13: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i12: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40057 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40057 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40057 : ENTITY IS TRUE; + + end lut40057; + + architecture Structure of lut40057 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0101") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_78 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_78 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_78"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_78 : ENTITY IS TRUE; + + end SLICE_78; + + architecture Structure of SLICE_78 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40057 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i5_3_lut_rep_21_4_lut: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2065_2_lut_3_lut: lut40057 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowA_i7: vmuxregsre0003 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i6: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40058 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40058 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40058 : ENTITY IS TRUE; + + end lut40058; + + architecture Structure of lut40058 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0202") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40059 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40059 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40059 : ENTITY IS TRUE; + + end lut40059; + + architecture Structure of lut40059 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0400") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_79 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_79 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_79"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_79 : ENTITY IS TRUE; + + end SLICE_79; + + architecture Structure of SLICE_79 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal M0_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40058 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40059 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_25_3_lut: lut40058 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_4_lut: lut40059 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + PHI2r2_377: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CASr_382: vmuxregsre + port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + M0_INVERTERIN: inverter + port map (I=>M0_dly, Z=>M0_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40060 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40060 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40060 : ENTITY IS TRUE; + + end lut40060; + + architecture Structure of lut40060 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xFFFD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_80 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_80 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_80"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_80 : ENTITY IS TRUE; + + end SLICE_80; + + architecture Structure of SLICE_80 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40060 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_16: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_3_lut_4_lut_4_lut: lut40060 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i15: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i14: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40061 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40061 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40061 : ENTITY IS TRUE; + + end lut40061; + + architecture Structure of lut40061 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x8888") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40062 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40062 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40062 : ENTITY IS TRUE; + + end lut40062; + + architecture Structure of lut40062 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xBFFF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_81 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_81 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_81"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_81 : ENTITY IS TRUE; + + end SLICE_81; + + architecture Structure of SLICE_81 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40062 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1982_2_lut: lut40061 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i12_4_lut: lut40062 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + CmdUFMCS_412: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + CmdUFMCLK_413: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40063 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40063 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40063 : ENTITY IS TRUE; + + end lut40063; + + architecture Structure of lut40063 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0302") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_82 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_82 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_82"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_82 : ENTITY IS TRUE; + + end SLICE_82; + + architecture Structure of SLICE_82 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40063 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2052_4_lut: lut40063 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1990_2_lut_rep_17: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i11: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i10: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_83 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_83 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_83"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_83 : ENTITY IS TRUE; + + end SLICE_83; + + architecture Structure of SLICE_83 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal M0_NOTIN: Std_logic; + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40008 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40026 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_4_lut: lut40008 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i4_4_lut: lut40026 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RASr_379: vmuxregsre + port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + M0_INVERTERIN: inverter + port map (I=>M0_dly, Z=>M0_NOTIN); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M0_dly, CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_84 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_84 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_84"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_84 : ENTITY IS TRUE; + + end SLICE_84; + + architecture Structure of SLICE_84 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40056 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_4_lut_adj_11: lut40056 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_3_lut_adj_5: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_85 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_85 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_85"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_85 : ENTITY IS TRUE; + + end SLICE_85; + + architecture Structure of SLICE_85 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40013 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_4_lut_adj_15: lut40013 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2004_2_lut_rep_30: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RBA_i2: vmuxregsre0003 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RBA_i1: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40064 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40064 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40064 : ENTITY IS TRUE; + + end lut40064; + + architecture Structure of lut40064 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x1010") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_86 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_86 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_86"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_86 : ENTITY IS TRUE; + + end SLICE_86; + + architecture Structure of SLICE_86 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40064 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_3_lut_adj_10: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1_2_lut_rep_20_3_lut: lut40064 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + IS_FSM_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40065 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40065 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40065 : ENTITY IS TRUE; + + end lut40065; + + architecture Structure of lut40065 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xCAC0") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_87 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_87 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_87"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_87 : ENTITY IS TRUE; + + end SLICE_87; + + architecture Structure of SLICE_87 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40040 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40065 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_2_lut: lut40040 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i17_4_lut: lut40065 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + IS_FSM_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40066 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40066 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40066 : ENTITY IS TRUE; + + end lut40066; + + architecture Structure of lut40066 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0062") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_88 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_88 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_88"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_88 : ENTITY IS TRUE; + + end SLICE_88; + + architecture Structure of SLICE_88 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40009 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40066 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2452_bdd_2_lut_rep_18_3_lut: lut40009 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + FS_6_bdd_4_lut: lut40066 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + Bank_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_89 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_89 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_89"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_89 : ENTITY IS TRUE; + + end SLICE_89; + + architecture Structure of SLICE_89 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40064 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_16_3_lut: lut40064 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_adj_1: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + WRD_i1: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i0: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_90 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_90 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_90"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_90 : ENTITY IS TRUE; + + end SLICE_90; + + architecture Structure of SLICE_90 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40039 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2032_2_lut_3_lut_4_lut: lut40039 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i2_2_lut_rep_27: lut40004 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + RowA_i9: vmuxregsre0006 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i8: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40067 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40067 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40067 : ENTITY IS TRUE; + + end lut40067; + + architecture Structure of lut40067 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x8C00") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_91 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_91 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_91"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_91 : ENTITY IS TRUE; + + end SLICE_91; + + architecture Structure of SLICE_91 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40067 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_33: lut40061 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_4_lut_adj_3: lut40067 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + PHI2r_376: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + PHI2r3_378: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40068 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40068 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40068 : ENTITY IS TRUE; + + end lut40068; + + architecture Structure of lut40068 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2222") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40069 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40069 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40069 : ENTITY IS TRUE; + + end lut40069; + + architecture Structure of lut40069 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x4040") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_92 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_92 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_92"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_92 : ENTITY IS TRUE; + + end SLICE_92; + + architecture Structure of SLICE_92 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40068 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40069 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_rep_32: lut40068 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_rep_31: lut40069 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + WRD_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40070 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40070 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40070 : ENTITY IS TRUE; + + end lut40070; + + architecture Structure of lut40070 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x7777") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_93 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_93 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_93"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_93 : ENTITY IS TRUE; + + end SLICE_93; + + architecture Structure of SLICE_93 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40019 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40070 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2060_2_lut: lut40070 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i1512_2_lut: lut40019 + port map (A=>A0_ipd, B=>B0_ipd, C=>GNDI, D=>GNDI, Z=>F0_out); + CmdUFMSDI_414: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, B0_ipd, A0_ipd, M0_dly, CE_dly, + CLK_dly, F0_out, Q0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_negedge, + SetupLow => tsetup_CE_CLK_noedge_negedge, + HoldHigh => thold_CE_CLK_noedge_negedge, + HoldLow => thold_CE_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_94 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_94 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_94"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_94 : ENTITY IS TRUE; + + end SLICE_94; + + architecture Structure of SLICE_94 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1976_2_lut: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i5_4_lut: lut40042 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40071 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40071 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40071 : ENTITY IS TRUE; + + end lut40071; + + architecture Structure of lut40071 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x0001") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_95 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_95 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_95"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_95 : ENTITY IS TRUE; + + end SLICE_95; + + architecture Structure of SLICE_95 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component vmuxregsre0006 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component lut40061 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40071 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_22: lut40061 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2055_3_lut_4_lut: lut40071 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i5: vmuxregsre0006 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i4: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_96 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_96 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_96"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_96 : ENTITY IS TRUE; + + end SLICE_96; + + architecture Structure of SLICE_96 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i4_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2020_4_lut: lut40042 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i3: vmuxregsre0003 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i2: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_97 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_97 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_97"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_LSR : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_LSR_CLK : VitalDelayType := 0 ns; + tsetup_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_LSR_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_97 : ENTITY IS TRUE; + + end SLICE_97; + + architecture Structure of SLICE_97 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal LSR_ipd : std_logic := 'X'; + signal LSR_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal LSR_NOTIN: Std_logic; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component vmuxregsre0003 + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40042 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i5_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2018_4_lut: lut40042 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + RowA_i1: vmuxregsre0003 + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + LSR_INVERTERIN: inverter + port map (I=>LSR_dly, Z=>LSR_NOTIN); + RowA_i0: vmuxregsre0003 + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>LSR_NOTIN, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(LSR_ipd, LSR, tipd_LSR); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(LSR_dly, LSR_ipd, tisd_LSR_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, + A0_ipd, M1_dly, M0_dly, LSR_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_LSR_CLK : x01 := '0'; + VARIABLE LSR_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => LSR_dly, + TestSignalName => "LSR", + TestDelay => tisd_LSR_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_LSR_CLK_noedge_negedge, + SetupLow => tsetup_LSR_CLK_noedge_negedge, + HoldHigh => thold_LSR_CLK_noedge_negedge, + HoldLow => thold_LSR_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => LSR_CLK_TimingDatash, + Violation => tviol_LSR_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_98 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_98 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_98"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_98 : ENTITY IS TRUE; + + end SLICE_98; + + architecture Structure of SLICE_98 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal M1_NOTIN: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + signal M0_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i1_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i9_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + FWEr_389: vmuxregsre + port map (D0=>M1_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + M1_INVERTERIN: inverter + port map (I=>M1_dly, Z=>M1_NOTIN); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + CBR_390: vmuxregsre + port map (D0=>M0_NOTIN, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + M0_INVERTERIN: inverter + port map (I=>M0_dly, Z=>M0_NOTIN); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_99 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_99 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_99"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_99 : ENTITY IS TRUE; + + end SLICE_99; + + architecture Structure of SLICE_99 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i2_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i8_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i7: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i6: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40072 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40072 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40072 : ENTITY IS TRUE; + + end lut40072; + + architecture Structure of lut40072 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xF0F7") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity lut40073 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40073 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40073 : ENTITY IS TRUE; + + end lut40073; + + architecture Structure of lut40073 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x08FF") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_100 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_100 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_100"; + + tipd_D1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CE : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_D1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_CE_CLK : VitalDelayType := 0 ns; + tsetup_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_CE_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_100 : ENTITY IS TRUE; + + end SLICE_100; + + architecture Structure of SLICE_100 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal D1_ipd : std_logic := 'X'; + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CE_ipd : std_logic := 'X'; + signal CE_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal VCCI: Std_logic; + signal GNDI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40072 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40073 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i2_2_lut_3_lut_4_lut: lut40072 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>D1_ipd, Z=>F1_out); + i1_2_lut_4_lut_adj_7: lut40073 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + IS_FSM_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + DRIVEGND: gnd + port map (PWR0=>GNDI); + IS_FSM_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>CE_dly, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(D1_ipd, D1, tipd_D1); + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CE_ipd, CE, tipd_CE); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CE_dly, CE_ipd, tisd_CE_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (D1_ipd, C1_ipd, B1_ipd, A1_ipd, D0_ipd, C0_ipd, + B0_ipd, A0_ipd, M1_dly, M0_dly, CE_dly, CLK_dly, F0_out, Q0_out, F1_out, + Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CE_CLK : x01 := '0'; + VARIABLE CE_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => CE_dly, + TestSignalName => "CE", + TestDelay => tisd_CE_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_CE_CLK_noedge_posedge, + SetupLow => tsetup_CE_CLK_noedge_posedge, + HoldHigh => thold_CE_CLK_noedge_posedge, + HoldLow => thold_CE_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => CE_CLK_TimingDatash, + Violation => tviol_CE_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => D1_ipd'last_event, + PathDelay => tpd_D1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 3 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_101 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_101 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_101"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_101 : ENTITY IS TRUE; + + end SLICE_101; + + architecture Structure of SLICE_101 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i3_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + MAin_9_I_0_427_i7_3_lut: lut40018 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_102 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_102 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_102"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_posedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_posedge : VitalDelayType := 0 ns; + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_102 : ENTITY IS TRUE; + + end SLICE_102; + + architecture Structure of SLICE_102 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1_2_lut_adj_26: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + InitReady_bdd_3_lut: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + Bank_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + Bank_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_dly, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_posedge, + SetupLow => tsetup_M1_CLK_noedge_posedge, + HoldHigh => thold_M1_CLK_noedge_posedge, + HoldLow => thold_M1_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_posedge, + SetupLow => tsetup_M0_CLK_noedge_posedge, + HoldHigh => thold_M0_CLK_noedge_posedge, + HoldLow => thold_M0_CLK_noedge_posedge, + CheckEnabled => TRUE, + RefTransition => '/', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity SLICE_103 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_103 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_103"; + + tipd_C1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_C1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_103 : ENTITY IS TRUE; + + end SLICE_103; + + architecture Structure of SLICE_103 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal C1_ipd : std_logic := 'X'; + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40014 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40018 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + MAin_9_I_0_427_i6_3_lut: lut40018 + port map (A=>A1_ipd, B=>B1_ipd, C=>C1_ipd, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_adj_14: lut40014 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + WRD_i3: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i2: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(C1_ipd, C1, tipd_C1); + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (C1_ipd, B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, + M1_dly, M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => C1_ipd'last_event, + PathDelay => tpd_C1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 2 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40074 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40074 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40074 : ENTITY IS TRUE; + + end lut40074; + + architecture Structure of lut40074 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0xF0DD") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_104 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_104 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_104"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_D0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_D0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns)); + + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_104 : ENTITY IS TRUE; + + end SLICE_104; + + architecture Structure of SLICE_104 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal D0_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40074 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + n2414_bdd_2_lut: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + n1_bdd_4_lut: lut40074 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>D0_ipd, Z=>F0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(D0_ipd, D0, tipd_D0); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, D0_ipd, C0_ipd, B0_ipd, A0_ipd, + F0_out, F1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + F0_zd := F0_out; + F1_zd := F1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => D0_ipd'last_event, + PathDelay => tpd_D0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 3 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity lut40075 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity lut40075 is + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + + ATTRIBUTE Vital_Level0 OF lut40075 : ENTITY IS TRUE; + + end lut40075; + + architecture Structure of lut40075 is + component ROM16X1 + generic (initval: String); + port (AD0: in Std_logic; AD1: in Std_logic; AD2: in Std_logic; + AD3: in Std_logic; DO0: out Std_logic); + end component; + begin + INST10: ROM16X1 + generic map (initval => "0x2020") + port map (AD0=>A, AD1=>B, AD2=>C, AD3=>D, DO0=>Z); + end Structure; + +-- entity SLICE_105 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity SLICE_105 is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "SLICE_105"; + + tipd_B1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_C0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_B0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_A0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M1 : VitalDelayType01 := (0 ns, 0 ns); + tipd_M0 : VitalDelayType01 := (0 ns, 0 ns); + tipd_CLK : VitalDelayType01 := (0 ns, 0 ns); + tpd_B1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A1_F1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_C0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_B0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_A0_F0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CLK_Q1 : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CLK : VitalDelayType := 0 ns; + tpw_CLK_posedge : VitalDelayType := 0 ns; + tpw_CLK_negedge : VitalDelayType := 0 ns; + ticd_CLK : VitalDelayType := 0 ns; + tisd_M1_CLK : VitalDelayType := 0 ns; + tsetup_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M1_CLK_noedge_negedge : VitalDelayType := 0 ns; + tisd_M0_CLK : VitalDelayType := 0 ns; + tsetup_M0_CLK_noedge_negedge : VitalDelayType := 0 ns; + thold_M0_CLK_noedge_negedge : VitalDelayType := 0 ns); + + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF SLICE_105 : ENTITY IS TRUE; + + end SLICE_105; + + architecture Structure of SLICE_105 is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal B1_ipd : std_logic := 'X'; + signal A1_ipd : std_logic := 'X'; + signal C0_ipd : std_logic := 'X'; + signal B0_ipd : std_logic := 'X'; + signal A0_ipd : std_logic := 'X'; + signal M1_ipd : std_logic := 'X'; + signal M1_dly : std_logic := 'X'; + signal M0_ipd : std_logic := 'X'; + signal M0_dly : std_logic := 'X'; + signal CLK_ipd : std_logic := 'X'; + signal CLK_dly : std_logic := 'X'; + signal F0_out : std_logic := 'X'; + signal Q0_out : std_logic := 'X'; + signal F1_out : std_logic := 'X'; + signal Q1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + signal VCCI: Std_logic; + signal CLK_NOTIN: Std_logic; + component vmuxregsre + port (D0: in Std_logic; D1: in Std_logic; SD: in Std_logic; + SP: in Std_logic; CK: in Std_logic; LSR: in Std_logic; + Q: out Std_logic); + end component; + component vcc + port (PWR1: out Std_logic); + end component; + component gnd + port (PWR0: out Std_logic); + end component; + component inverter + port (I: in Std_logic; Z: out Std_logic); + end component; + component lut40004 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + component lut40075 + port (A: in Std_logic; B: in Std_logic; C: in Std_logic; D: in Std_logic; + Z: out Std_logic); + end component; + begin + i1513_2_lut: lut40004 + port map (A=>A1_ipd, B=>B1_ipd, C=>GNDI, D=>GNDI, Z=>F1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + i2_3_lut_adj_20: lut40075 + port map (A=>A0_ipd, B=>B0_ipd, C=>C0_ipd, D=>GNDI, Z=>F0_out); + WRD_i5: vmuxregsre + port map (D0=>M1_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q1_out); + DRIVEVCC: vcc + port map (PWR1=>VCCI); + CLK_INVERTERIN: inverter + port map (I=>CLK_dly, Z=>CLK_NOTIN); + WRD_i4: vmuxregsre + port map (D0=>M0_dly, D1=>VCCI, SD=>GNDI, SP=>VCCI, CK=>CLK_NOTIN, + LSR=>GNDI, Q=>Q0_out); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(B1_ipd, B1, tipd_B1); + VitalWireDelay(A1_ipd, A1, tipd_A1); + VitalWireDelay(C0_ipd, C0, tipd_C0); + VitalWireDelay(B0_ipd, B0, tipd_B0); + VitalWireDelay(A0_ipd, A0, tipd_A0); + VitalWireDelay(M1_ipd, M1, tipd_M1); + VitalWireDelay(M0_ipd, M0, tipd_M0); + VitalWireDelay(CLK_ipd, CLK, tipd_CLK); + END BLOCK; + + -- Setup and Hold DELAYs + SignalDelay : BLOCK + BEGIN + VitalSignalDelay(M1_dly, M1_ipd, tisd_M1_CLK); + VitalSignalDelay(M0_dly, M0_ipd, tisd_M0_CLK); + VitalSignalDelay(CLK_dly, CLK_ipd, ticd_CLK); + END BLOCK; + + VitalBehavior : PROCESS (B1_ipd, A1_ipd, C0_ipd, B0_ipd, A0_ipd, M1_dly, + M0_dly, CLK_dly, F0_out, Q0_out, F1_out, Q1_out) + VARIABLE F0_zd : std_logic := 'X'; + VARIABLE F0_GlitchData : VitalGlitchDataType; + VARIABLE Q0_zd : std_logic := 'X'; + VARIABLE Q0_GlitchData : VitalGlitchDataType; + VARIABLE F1_zd : std_logic := 'X'; + VARIABLE F1_GlitchData : VitalGlitchDataType; + VARIABLE Q1_zd : std_logic := 'X'; + VARIABLE Q1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_M1_CLK : x01 := '0'; + VARIABLE M1_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_M0_CLK : x01 := '0'; + VARIABLE M0_CLK_TimingDatash : VitalTimingDataType; + VARIABLE tviol_CLK_CLK : x01 := '0'; + VARIABLE periodcheckinfo_CLK : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalSetupHoldCheck ( + TestSignal => M1_dly, + TestSignalName => "M1", + TestDelay => tisd_M1_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M1_CLK_noedge_negedge, + SetupLow => tsetup_M1_CLK_noedge_negedge, + HoldHigh => thold_M1_CLK_noedge_negedge, + HoldLow => thold_M1_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M1_CLK_TimingDatash, + Violation => tviol_M1_CLK, + MsgSeverity => warning); + VitalSetupHoldCheck ( + TestSignal => M0_dly, + TestSignalName => "M0", + TestDelay => tisd_M0_CLK, + RefSignal => CLK_dly, + RefSignalName => "CLK", + RefDelay => ticd_CLK, + SetupHigh => tsetup_M0_CLK_noedge_negedge, + SetupLow => tsetup_M0_CLK_noedge_negedge, + HoldHigh => thold_M0_CLK_noedge_negedge, + HoldLow => thold_M0_CLK_noedge_negedge, + CheckEnabled => TRUE, + RefTransition => '\', + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + TimingData => M0_CLK_TimingDatash, + Violation => tviol_M0_CLK, + MsgSeverity => warning); + VitalPeriodPulseCheck ( + TestSignal => CLK_ipd, + TestSignalName => "CLK", + Period => tperiod_CLK, + PulseWidthHigh => tpw_CLK_posedge, + PulseWidthLow => tpw_CLK_negedge, + PeriodData => periodcheckinfo_CLK, + Violation => tviol_CLK_CLK, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + F0_zd := F0_out; + Q0_zd := Q0_out; + F1_zd := F1_out; + Q1_zd := Q1_out; + + VitalPathDelay01 ( + OutSignal => F0, OutSignalName => "F0", OutTemp => F0_zd, + Paths => (0 => (InputChangeTime => C0_ipd'last_event, + PathDelay => tpd_C0_F0, + PathCondition => TRUE), + 1 => (InputChangeTime => B0_ipd'last_event, + PathDelay => tpd_B0_F0, + PathCondition => TRUE), + 2 => (InputChangeTime => A0_ipd'last_event, + PathDelay => tpd_A0_F0, + PathCondition => TRUE)), + GlitchData => F0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q0, OutSignalName => "Q0", OutTemp => Q0_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q0, + PathCondition => TRUE)), + GlitchData => Q0_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => F1, OutSignalName => "F1", OutTemp => F1_zd, + Paths => (0 => (InputChangeTime => B1_ipd'last_event, + PathDelay => tpd_B1_F1, + PathCondition => TRUE), + 1 => (InputChangeTime => A1_ipd'last_event, + PathDelay => tpd_A1_F1, + PathCondition => TRUE)), + GlitchData => F1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01 ( + OutSignal => Q1, OutSignalName => "Q1", OutTemp => Q1_zd, + Paths => (0 => (InputChangeTime => CLK_dly'last_event, + PathDelay => tpd_CLK_Q1, + PathCondition => TRUE)), + GlitchData => Q1_GlitchData, + Mode => ondetect, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mjiobuf + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity mjiobuf is + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + + ATTRIBUTE Vital_Level0 OF mjiobuf : ENTITY IS TRUE; + + end mjiobuf; + + architecture Structure of mjiobuf is + component IBPU + port (I: in Std_logic; O: out Std_logic); + end component; + component OBZPU + port (I: in Std_logic; T: in Std_logic; O: out Std_logic); + end component; + begin + INST1: IBPU + port map (I=>PADI, O=>Z); + INST2: OBZPU + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity RD_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_7_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD7 : VitalDelayType := 0 ns; + tpw_RD7_posedge : VitalDelayType := 0 ns; + tpw_RD7_negedge : VitalDelayType := 0 ns; + tpd_RD7_RD7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD7: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_7_B : ENTITY IS TRUE; + + end RD_7_B; + + architecture Structure of RD_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD7_ipd : std_logic := 'X'; + signal RD7_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_7_713: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD7_out, + PADI=>RD7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD7_ipd, RD7, tipd_RD7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD7_ipd, RD7_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD7_zd : std_logic := 'X'; + VARIABLE RD7_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD7_RD7 : x01 := '0'; + VARIABLE periodcheckinfo_RD7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD7_ipd, + TestSignalName => "RD7", + Period => tperiod_RD7, + PulseWidthHigh => tpw_RD7_posedge, + PulseWidthLow => tpw_RD7_negedge, + PeriodData => periodcheckinfo_RD7, + Violation => tviol_RD7_RD7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD7_zd := RD7_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD7_ipd'last_event, + PathDelay => tpd_RD7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD7, OutSignalName => "RD7", OutTemp => RD7_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD7, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD7, + PathCondition => TRUE)), + GlitchData => RD7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_6_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD6 : VitalDelayType := 0 ns; + tpw_RD6_posedge : VitalDelayType := 0 ns; + tpw_RD6_negedge : VitalDelayType := 0 ns; + tpd_RD6_RD6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD6: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_6_B : ENTITY IS TRUE; + + end RD_6_B; + + architecture Structure of RD_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD6_ipd : std_logic := 'X'; + signal RD6_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_6_714: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD6_out, + PADI=>RD6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD6_ipd, RD6, tipd_RD6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD6_ipd, RD6_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD6_zd : std_logic := 'X'; + VARIABLE RD6_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD6_RD6 : x01 := '0'; + VARIABLE periodcheckinfo_RD6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD6_ipd, + TestSignalName => "RD6", + Period => tperiod_RD6, + PulseWidthHigh => tpw_RD6_posedge, + PulseWidthLow => tpw_RD6_negedge, + PeriodData => periodcheckinfo_RD6, + Violation => tviol_RD6_RD6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD6_zd := RD6_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD6_ipd'last_event, + PathDelay => tpd_RD6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD6, OutSignalName => "RD6", OutTemp => RD6_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD6, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD6, + PathCondition => TRUE)), + GlitchData => RD6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_5_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD5 : VitalDelayType := 0 ns; + tpw_RD5_posedge : VitalDelayType := 0 ns; + tpw_RD5_negedge : VitalDelayType := 0 ns; + tpd_RD5_RD5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD5: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_5_B : ENTITY IS TRUE; + + end RD_5_B; + + architecture Structure of RD_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD5_ipd : std_logic := 'X'; + signal RD5_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_5_715: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD5_out, + PADI=>RD5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD5_ipd, RD5, tipd_RD5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD5_ipd, RD5_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD5_zd : std_logic := 'X'; + VARIABLE RD5_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD5_RD5 : x01 := '0'; + VARIABLE periodcheckinfo_RD5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD5_ipd, + TestSignalName => "RD5", + Period => tperiod_RD5, + PulseWidthHigh => tpw_RD5_posedge, + PulseWidthLow => tpw_RD5_negedge, + PeriodData => periodcheckinfo_RD5, + Violation => tviol_RD5_RD5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD5_zd := RD5_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD5_ipd'last_event, + PathDelay => tpd_RD5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD5, OutSignalName => "RD5", OutTemp => RD5_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD5, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD5, + PathCondition => TRUE)), + GlitchData => RD5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_4_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD4 : VitalDelayType := 0 ns; + tpw_RD4_posedge : VitalDelayType := 0 ns; + tpw_RD4_negedge : VitalDelayType := 0 ns; + tpd_RD4_RD4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD4: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_4_B : ENTITY IS TRUE; + + end RD_4_B; + + architecture Structure of RD_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD4_ipd : std_logic := 'X'; + signal RD4_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_4_716: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD4_out, + PADI=>RD4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD4_ipd, RD4, tipd_RD4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD4_ipd, RD4_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD4_zd : std_logic := 'X'; + VARIABLE RD4_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD4_RD4 : x01 := '0'; + VARIABLE periodcheckinfo_RD4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD4_ipd, + TestSignalName => "RD4", + Period => tperiod_RD4, + PulseWidthHigh => tpw_RD4_posedge, + PulseWidthLow => tpw_RD4_negedge, + PeriodData => periodcheckinfo_RD4, + Violation => tviol_RD4_RD4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD4_zd := RD4_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD4_ipd'last_event, + PathDelay => tpd_RD4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD4, OutSignalName => "RD4", OutTemp => RD4_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD4, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD4, + PathCondition => TRUE)), + GlitchData => RD4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_3_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD3 : VitalDelayType := 0 ns; + tpw_RD3_posedge : VitalDelayType := 0 ns; + tpw_RD3_negedge : VitalDelayType := 0 ns; + tpd_RD3_RD3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD3: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_3_B : ENTITY IS TRUE; + + end RD_3_B; + + architecture Structure of RD_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD3_ipd : std_logic := 'X'; + signal RD3_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_3_717: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD3_out, + PADI=>RD3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD3_ipd, RD3, tipd_RD3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD3_ipd, RD3_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD3_zd : std_logic := 'X'; + VARIABLE RD3_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD3_RD3 : x01 := '0'; + VARIABLE periodcheckinfo_RD3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD3_ipd, + TestSignalName => "RD3", + Period => tperiod_RD3, + PulseWidthHigh => tpw_RD3_posedge, + PulseWidthLow => tpw_RD3_negedge, + PeriodData => periodcheckinfo_RD3, + Violation => tviol_RD3_RD3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD3_zd := RD3_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD3_ipd'last_event, + PathDelay => tpd_RD3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD3, OutSignalName => "RD3", OutTemp => RD3_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD3, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD3, + PathCondition => TRUE)), + GlitchData => RD3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_2_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD2 : VitalDelayType := 0 ns; + tpw_RD2_posedge : VitalDelayType := 0 ns; + tpw_RD2_negedge : VitalDelayType := 0 ns; + tpd_RD2_RD2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD2: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_2_B : ENTITY IS TRUE; + + end RD_2_B; + + architecture Structure of RD_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD2_ipd : std_logic := 'X'; + signal RD2_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_2_718: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD2_out, + PADI=>RD2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD2_ipd, RD2, tipd_RD2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD2_ipd, RD2_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD2_zd : std_logic := 'X'; + VARIABLE RD2_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD2_RD2 : x01 := '0'; + VARIABLE periodcheckinfo_RD2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD2_ipd, + TestSignalName => "RD2", + Period => tperiod_RD2, + PulseWidthHigh => tpw_RD2_posedge, + PulseWidthLow => tpw_RD2_negedge, + PeriodData => periodcheckinfo_RD2, + Violation => tviol_RD2_RD2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD2_zd := RD2_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD2_ipd'last_event, + PathDelay => tpd_RD2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD2, OutSignalName => "RD2", OutTemp => RD2_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD2, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD2, + PathCondition => TRUE)), + GlitchData => RD2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_1_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD1 : VitalDelayType := 0 ns; + tpw_RD1_posedge : VitalDelayType := 0 ns; + tpw_RD1_negedge : VitalDelayType := 0 ns; + tpd_RD1_RD1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD1: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_1_B : ENTITY IS TRUE; + + end RD_1_B; + + architecture Structure of RD_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD1_ipd : std_logic := 'X'; + signal RD1_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_1_719: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD1_out, + PADI=>RD1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD1_ipd, RD1, tipd_RD1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD1_ipd, RD1_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD1_zd : std_logic := 'X'; + VARIABLE RD1_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD1_RD1 : x01 := '0'; + VARIABLE periodcheckinfo_RD1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD1_ipd, + TestSignalName => "RD1", + Period => tperiod_RD1, + PulseWidthHigh => tpw_RD1_posedge, + PulseWidthLow => tpw_RD1_negedge, + PeriodData => periodcheckinfo_RD1, + Violation => tviol_RD1_RD1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD1_zd := RD1_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD1_ipd'last_event, + PathDelay => tpd_RD1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD1, OutSignalName => "RD1", OutTemp => RD1_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD1, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD1, + PathCondition => TRUE)), + GlitchData => RD1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RD_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RD_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RD_0_B"; + + tipd_PADDT : VitalDelayType01 := (0 ns, 0 ns); + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tipd_RD0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDT_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_PADDO_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns); + tpd_RD0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RD0 : VitalDelayType := 0 ns; + tpw_RD0_posedge : VitalDelayType := 0 ns; + tpw_RD0_negedge : VitalDelayType := 0 ns; + tpd_RD0_RD0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD0: inout Std_logic); + + ATTRIBUTE Vital_Level0 OF RD_0_B : ENTITY IS TRUE; + + end RD_0_B; + + architecture Structure of RD_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PADDT_ipd : std_logic := 'X'; + signal PADDO_ipd : std_logic := 'X'; + signal RD0_ipd : std_logic := 'X'; + signal RD0_out : std_logic := 'Z'; + + component mjiobuf + port (I: in Std_logic; T: in Std_logic; Z: out Std_logic; + PAD: out Std_logic; PADI: in Std_logic); + end component; + begin + Dout_pad_0_720: mjiobuf + port map (I=>PADDO_ipd, T=>PADDT_ipd, Z=>PADDI_out, PAD=>RD0_out, + PADI=>RD0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDT_ipd, PADDT, tipd_PADDT); + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + VitalWireDelay(RD0_ipd, RD0, tipd_RD0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PADDT_ipd, PADDO_ipd, RD0_ipd, RD0_out) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + VARIABLE RD0_zd : std_logic := 'X'; + VARIABLE RD0_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RD0_RD0 : x01 := '0'; + VARIABLE periodcheckinfo_RD0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RD0_ipd, + TestSignalName => "RD0", + Period => tperiod_RD0, + PulseWidthHigh => tpw_RD0_posedge, + PulseWidthLow => tpw_RD0_negedge, + PeriodData => periodcheckinfo_RD0, + Violation => tviol_RD0_RD0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + RD0_zd := RD0_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RD0_ipd'last_event, + PathDelay => tpd_RD0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + VitalPathDelay01Z ( + OutSignal => RD0, OutSignalName => "RD0", OutTemp => RD0_zd, + Paths => (0 => (InputChangeTime => PADDT_ipd'last_event, + PathDelay => tpd_PADDT_RD0, + PathCondition => TRUE), + 1 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RD0, + PathCondition => TRUE)), + GlitchData => RD0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mjiobuf0076 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity mjiobuf0076 is + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + + ATTRIBUTE Vital_Level0 OF mjiobuf0076 : ENTITY IS TRUE; + + end mjiobuf0076; + + architecture Structure of mjiobuf0076 is + component OBZPU + port (I: in Std_logic; T: in Std_logic; O: out Std_logic); + end component; + begin + INST5: OBZPU + port map (I=>I, T=>T, O=>PAD); + end Structure; + +-- entity Dout_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_7_B : ENTITY IS TRUE; + + end Dout_7_B; + + architecture Structure of Dout_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout7_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_7: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout7_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout7_out) + VARIABLE Dout7_zd : std_logic := 'X'; + VARIABLE Dout7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout7_zd := Dout7_out; + + VitalPathDelay01Z ( + OutSignal => Dout7, OutSignalName => "Dout7", OutTemp => Dout7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout7, + PathCondition => TRUE)), + GlitchData => Dout7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_6_B : ENTITY IS TRUE; + + end Dout_6_B; + + architecture Structure of Dout_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout6_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_6: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout6_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout6_out) + VARIABLE Dout6_zd : std_logic := 'X'; + VARIABLE Dout6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout6_zd := Dout6_out; + + VitalPathDelay01Z ( + OutSignal => Dout6, OutSignalName => "Dout6", OutTemp => Dout6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout6, + PathCondition => TRUE)), + GlitchData => Dout6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_5_B : ENTITY IS TRUE; + + end Dout_5_B; + + architecture Structure of Dout_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout5_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_5: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout5_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout5_out) + VARIABLE Dout5_zd : std_logic := 'X'; + VARIABLE Dout5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout5_zd := Dout5_out; + + VitalPathDelay01Z ( + OutSignal => Dout5, OutSignalName => "Dout5", OutTemp => Dout5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout5, + PathCondition => TRUE)), + GlitchData => Dout5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_4_B : ENTITY IS TRUE; + + end Dout_4_B; + + architecture Structure of Dout_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout4_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_4: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout4_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout4_out) + VARIABLE Dout4_zd : std_logic := 'X'; + VARIABLE Dout4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout4_zd := Dout4_out; + + VitalPathDelay01Z ( + OutSignal => Dout4, OutSignalName => "Dout4", OutTemp => Dout4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout4, + PathCondition => TRUE)), + GlitchData => Dout4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_3_B : ENTITY IS TRUE; + + end Dout_3_B; + + architecture Structure of Dout_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout3_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_3: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout3_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout3_out) + VARIABLE Dout3_zd : std_logic := 'X'; + VARIABLE Dout3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout3_zd := Dout3_out; + + VitalPathDelay01Z ( + OutSignal => Dout3, OutSignalName => "Dout3", OutTemp => Dout3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout3, + PathCondition => TRUE)), + GlitchData => Dout3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_2_B : ENTITY IS TRUE; + + end Dout_2_B; + + architecture Structure of Dout_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout2_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_2: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout2_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout2_out) + VARIABLE Dout2_zd : std_logic := 'X'; + VARIABLE Dout2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout2_zd := Dout2_out; + + VitalPathDelay01Z ( + OutSignal => Dout2, OutSignalName => "Dout2", OutTemp => Dout2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout2, + PathCondition => TRUE)), + GlitchData => Dout2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_1_B : ENTITY IS TRUE; + + end Dout_1_B; + + architecture Structure of Dout_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_1: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout1_out) + VARIABLE Dout1_zd : std_logic := 'X'; + VARIABLE Dout1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout1_zd := Dout1_out; + + VitalPathDelay01Z ( + OutSignal => Dout1, OutSignalName => "Dout1", OutTemp => Dout1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout1, + PathCondition => TRUE)), + GlitchData => Dout1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Dout_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Dout_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Dout_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_Dout0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; Dout0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF Dout_0_B : ENTITY IS TRUE; + + end Dout_0_B; + + architecture Structure of Dout_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal Dout0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + Dout_pad_0: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>Dout0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, Dout0_out) + VARIABLE Dout0_zd : std_logic := 'X'; + VARIABLE Dout0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + Dout0_zd := Dout0_out; + + VitalPathDelay01Z ( + OutSignal => Dout0, OutSignalName => "Dout0", OutTemp => Dout0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_Dout0, + PathCondition => TRUE)), + GlitchData => Dout0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity LEDB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity LEDB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "LEDB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_LEDS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; LEDS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF LEDB : ENTITY IS TRUE; + + end LEDB; + + architecture Structure of LEDB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal LEDS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + LED_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>LEDS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, LEDS_out) + VARIABLE LEDS_zd : std_logic := 'X'; + VARIABLE LEDS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + LEDS_zd := LEDS_out; + + VitalPathDelay01Z ( + OutSignal => LEDS, OutSignalName => "LEDS", OutTemp => LEDS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_LEDS, + PathCondition => TRUE)), + GlitchData => LEDS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RBA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RBA1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RBA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_1_B : ENTITY IS TRUE; + + end RBA_1_B; + + architecture Structure of RBA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RBA1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_1: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RBA1_out) + VARIABLE RBA1_zd : std_logic := 'X'; + VARIABLE RBA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA1_zd := RBA1_out; + + VitalPathDelay01Z ( + OutSignal => RBA1, OutSignalName => "RBA1", OutTemp => RBA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RBA1, + PathCondition => TRUE)), + GlitchData => RBA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RBA_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RBA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RBA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RBA0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RBA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RBA_0_B : ENTITY IS TRUE; + + end RBA_0_B; + + architecture Structure of RBA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RBA0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RBA_pad_0: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RBA0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RBA0_out) + VARIABLE RBA0_zd : std_logic := 'X'; + VARIABLE RBA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RBA0_zd := RBA0_out; + + VitalPathDelay01Z ( + OutSignal => RBA0, OutSignalName => "RBA0", OutTemp => RBA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RBA0, + PathCondition => TRUE)), + GlitchData => RBA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_11_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_11_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_11_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA11 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RA11: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_11_B : ENTITY IS TRUE; + + end RA_11_B; + + architecture Structure of RA_11_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA11_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_11: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA11_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA11_out) + VARIABLE RA11_zd : std_logic := 'X'; + VARIABLE RA11_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA11_zd := RA11_out; + + VitalPathDelay01Z ( + OutSignal => RA11, OutSignalName => "RA11", OutTemp => RA11_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA11, + PathCondition => TRUE)), + GlitchData => RA11_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_10_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_10_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_10_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA10 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RA10: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_10_B : ENTITY IS TRUE; + + end RA_10_B; + + architecture Structure of RA_10_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA10_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_10: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA10_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA10_out) + VARIABLE RA10_zd : std_logic := 'X'; + VARIABLE RA10_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA10_zd := RA10_out; + + VitalPathDelay01Z ( + OutSignal => RA10, OutSignalName => "RA10", OutTemp => RA10_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA10, + PathCondition => TRUE)), + GlitchData => RA10_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_9_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_9_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA9 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA9: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_9_B : ENTITY IS TRUE; + + end RA_9_B; + + architecture Structure of RA_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA9_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_9: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA9_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA9_out) + VARIABLE RA9_zd : std_logic := 'X'; + VARIABLE RA9_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA9_zd := RA9_out; + + VitalPathDelay01Z ( + OutSignal => RA9, OutSignalName => "RA9", OutTemp => RA9_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA9, + PathCondition => TRUE)), + GlitchData => RA9_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_8_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_8_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA8 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA8: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_8_B : ENTITY IS TRUE; + + end RA_8_B; + + architecture Structure of RA_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA8_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_8: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA8_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA8_out) + VARIABLE RA8_zd : std_logic := 'X'; + VARIABLE RA8_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA8_zd := RA8_out; + + VitalPathDelay01Z ( + OutSignal => RA8, OutSignalName => "RA8", OutTemp => RA8_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA8, + PathCondition => TRUE)), + GlitchData => RA8_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_7_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA7 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA7: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_7_B : ENTITY IS TRUE; + + end RA_7_B; + + architecture Structure of RA_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA7_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_7: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA7_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA7_out) + VARIABLE RA7_zd : std_logic := 'X'; + VARIABLE RA7_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA7_zd := RA7_out; + + VitalPathDelay01Z ( + OutSignal => RA7, OutSignalName => "RA7", OutTemp => RA7_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA7, + PathCondition => TRUE)), + GlitchData => RA7_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_6_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA6 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA6: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_6_B : ENTITY IS TRUE; + + end RA_6_B; + + architecture Structure of RA_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA6_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_6: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA6_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA6_out) + VARIABLE RA6_zd : std_logic := 'X'; + VARIABLE RA6_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA6_zd := RA6_out; + + VitalPathDelay01Z ( + OutSignal => RA6, OutSignalName => "RA6", OutTemp => RA6_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA6, + PathCondition => TRUE)), + GlitchData => RA6_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_5_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA5 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA5: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_5_B : ENTITY IS TRUE; + + end RA_5_B; + + architecture Structure of RA_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA5_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_5: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA5_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA5_out) + VARIABLE RA5_zd : std_logic := 'X'; + VARIABLE RA5_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA5_zd := RA5_out; + + VitalPathDelay01Z ( + OutSignal => RA5, OutSignalName => "RA5", OutTemp => RA5_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA5, + PathCondition => TRUE)), + GlitchData => RA5_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_4_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA4 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA4: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_4_B : ENTITY IS TRUE; + + end RA_4_B; + + architecture Structure of RA_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA4_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_4: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA4_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA4_out) + VARIABLE RA4_zd : std_logic := 'X'; + VARIABLE RA4_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA4_zd := RA4_out; + + VitalPathDelay01Z ( + OutSignal => RA4, OutSignalName => "RA4", OutTemp => RA4_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA4, + PathCondition => TRUE)), + GlitchData => RA4_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_3_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA3 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA3: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_3_B : ENTITY IS TRUE; + + end RA_3_B; + + architecture Structure of RA_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA3_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_3: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA3_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA3_out) + VARIABLE RA3_zd : std_logic := 'X'; + VARIABLE RA3_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA3_zd := RA3_out; + + VitalPathDelay01Z ( + OutSignal => RA3, OutSignalName => "RA3", OutTemp => RA3_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA3, + PathCondition => TRUE)), + GlitchData => RA3_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_2_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA2 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA2: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_2_B : ENTITY IS TRUE; + + end RA_2_B; + + architecture Structure of RA_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA2_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_2: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA2_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA2_out) + VARIABLE RA2_zd : std_logic := 'X'; + VARIABLE RA2_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA2_zd := RA2_out; + + VitalPathDelay01Z ( + OutSignal => RA2, OutSignalName => "RA2", OutTemp => RA2_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA2, + PathCondition => TRUE)), + GlitchData => RA2_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_1_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA1 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA1: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_1_B : ENTITY IS TRUE; + + end RA_1_B; + + architecture Structure of RA_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA1_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_1: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA1_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA1_out) + VARIABLE RA1_zd : std_logic := 'X'; + VARIABLE RA1_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA1_zd := RA1_out; + + VitalPathDelay01Z ( + OutSignal => RA1, OutSignalName => "RA1", OutTemp => RA1_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA1, + PathCondition => TRUE)), + GlitchData => RA1_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RA_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RA_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RA_0_B"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RA0 : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns)); + + port (PADDO: in Std_logic; RA0: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RA_0_B : ENTITY IS TRUE; + + end RA_0_B; + + architecture Structure of RA_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RA0_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RA_pad_0: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RA0_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RA0_out) + VARIABLE RA0_zd : std_logic := 'X'; + VARIABLE RA0_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RA0_zd := RA0_out; + + VitalPathDelay01Z ( + OutSignal => RA0, OutSignalName => "RA0", OutTemp => RA0_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RA0, + PathCondition => TRUE)), + GlitchData => RA0_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCSB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nRCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCSB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRCSS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nRCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCSB : ENTITY IS TRUE; + + end nRCSB; + + architecture Structure of nRCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRCSS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCS_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCSS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRCSS_out) + VARIABLE nRCSS_zd : std_logic := 'X'; + VARIABLE nRCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCSS_zd := nRCSS_out; + + VitalPathDelay01Z ( + OutSignal => nRCSS, OutSignalName => "nRCSS", OutTemp => nRCSS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRCSS, + PathCondition => TRUE)), + GlitchData => nRCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCKEB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RCKEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCKEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RCKES : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RCKES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RCKEB : ENTITY IS TRUE; + + end RCKEB; + + architecture Structure of RCKEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RCKES_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RCKE_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RCKES_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RCKES_out) + VARIABLE RCKES_zd : std_logic := 'X'; + VARIABLE RCKES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RCKES_zd := RCKES_out; + + VitalPathDelay01Z ( + OutSignal => RCKES, OutSignalName => "RCKES", OutTemp => RCKES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RCKES, + PathCondition => TRUE)), + GlitchData => RCKES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRWEB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nRWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRWEB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRWES : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nRWES: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRWEB : ENTITY IS TRUE; + + end nRWEB; + + architecture Structure of nRWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRWES_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRWE_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRWES_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRWES_out) + VARIABLE nRWES_zd : std_logic := 'X'; + VARIABLE nRWES_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRWES_zd := nRWES_out; + + VitalPathDelay01Z ( + OutSignal => nRWES, OutSignalName => "nRWES", OutTemp => nRWES_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRWES, + PathCondition => TRUE)), + GlitchData => nRWES_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRRASB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nRRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRRASB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRRASS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nRRASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRRASB : ENTITY IS TRUE; + + end nRRASB; + + architecture Structure of nRRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRRASS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRRAS_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRRASS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRRASS_out) + VARIABLE nRRASS_zd : std_logic := 'X'; + VARIABLE nRRASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRRASS_zd := nRRASS_out; + + VitalPathDelay01Z ( + OutSignal => nRRASS, OutSignalName => "nRRASS", OutTemp => nRRASS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRRASS, + PathCondition => TRUE)), + GlitchData => nRRASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nRCASB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nRCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nRCASB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_nRCASS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nRCASS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nRCASB : ENTITY IS TRUE; + + end nRCASB; + + architecture Structure of nRCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nRCASS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nRCAS_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nRCASS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nRCASS_out) + VARIABLE nRCASS_zd : std_logic := 'X'; + VARIABLE nRCASS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nRCASS_zd := nRCASS_out; + + VitalPathDelay01Z ( + OutSignal => nRCASS, OutSignalName => "nRCASS", OutTemp => nRCASS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nRCASS, + PathCondition => TRUE)), + GlitchData => nRCASS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMHB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RDQMHB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMHB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMHS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMHB : ENTITY IS TRUE; + + end RDQMHB; + + architecture Structure of RDQMHB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMHS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQMH_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMHS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMHS_out) + VARIABLE RDQMHS_zd : std_logic := 'X'; + VARIABLE RDQMHS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMHS_zd := RDQMHS_out; + + VitalPathDelay01Z ( + OutSignal => RDQMHS, OutSignalName => "RDQMHS", OutTemp => RDQMHS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMHS, + PathCondition => TRUE)), + GlitchData => RDQMHS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RDQMLB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RDQMLB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RDQMLB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + tpd_PADDO_RDQMLS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF RDQMLB : ENTITY IS TRUE; + + end RDQMLB; + + architecture Structure of RDQMLB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal RDQMLS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + RDQML_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>RDQMLS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, RDQMLS_out) + VARIABLE RDQMLS_zd : std_logic := 'X'; + VARIABLE RDQMLS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + RDQMLS_zd := RDQMLS_out; + + VitalPathDelay01Z ( + OutSignal => RDQMLS, OutSignalName => "RDQMLS", OutTemp => RDQMLS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_RDQMLS, + PathCondition => TRUE)), + GlitchData => RDQMLS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nUFMCSB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nUFMCSB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nUFMCSB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + + tpd_PADDO_nUFMCSS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF nUFMCSB : ENTITY IS TRUE; + + end nUFMCSB; + + architecture Structure of nUFMCSB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal nUFMCSS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + nUFMCS_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>nUFMCSS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, nUFMCSS_out) + VARIABLE nUFMCSS_zd : std_logic := 'X'; + VARIABLE nUFMCSS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + nUFMCSS_zd := nUFMCSS_out; + + VitalPathDelay01Z ( + OutSignal => nUFMCSS, OutSignalName => "nUFMCSS", OutTemp => nUFMCSS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_nUFMCSS, + PathCondition => TRUE)), + GlitchData => nUFMCSS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMCLKB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity UFMCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMCLKB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + + tpd_PADDO_UFMCLKS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMCLKB : ENTITY IS TRUE; + + end UFMCLKB; + + architecture Structure of UFMCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal UFMCLKS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMCLK_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMCLKS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, UFMCLKS_out) + VARIABLE UFMCLKS_zd : std_logic := 'X'; + VARIABLE UFMCLKS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMCLKS_zd := UFMCLKS_out; + + VitalPathDelay01Z ( + OutSignal => UFMCLKS, OutSignalName => "UFMCLKS", OutTemp => UFMCLKS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_UFMCLKS, + PathCondition => TRUE)), + GlitchData => UFMCLKS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDIB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity UFMSDIB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDIB"; + + tipd_PADDO : VitalDelayType01 := (0 ns, 0 ns); + + tpd_PADDO_UFMSDIS : VitalDelayType01Z := (0 ns, 0 ns, 0 ns , 0 ns, 0 ns, 0 ns) + ); + + port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDIB : ENTITY IS TRUE; + + end UFMSDIB; + + architecture Structure of UFMSDIB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDO_ipd : std_logic := 'X'; + signal UFMSDIS_out : std_logic := 'X'; + + signal GNDI: Std_logic; + component gnd + port (PWR0: out Std_logic); + end component; + component mjiobuf0076 + port (I: in Std_logic; T: in Std_logic; PAD: out Std_logic); + end component; + begin + UFMSDI_pad: mjiobuf0076 + port map (I=>PADDO_ipd, T=>GNDI, PAD=>UFMSDIS_out); + DRIVEGND: gnd + port map (PWR0=>GNDI); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PADDO_ipd, PADDO, tipd_PADDO); + END BLOCK; + + VitalBehavior : PROCESS (PADDO_ipd, UFMSDIS_out) + VARIABLE UFMSDIS_zd : std_logic := 'X'; + VARIABLE UFMSDIS_GlitchData : VitalGlitchDataType; + + + BEGIN + + IF (TimingChecksOn) THEN + + END IF; + + UFMSDIS_zd := UFMSDIS_out; + + VitalPathDelay01Z ( + OutSignal => UFMSDIS, OutSignalName => "UFMSDIS", OutTemp => UFMSDIS_zd, + Paths => (0 => (InputChangeTime => PADDO_ipd'last_event, + PathDelay => tpd_PADDO_UFMSDIS, + PathCondition => TRUE)), + GlitchData => UFMSDIS_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity mjiobuf0077 + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity mjiobuf0077 is + port (Z: out Std_logic; PAD: in Std_logic); + + ATTRIBUTE Vital_Level0 OF mjiobuf0077 : ENTITY IS TRUE; + + end mjiobuf0077; + + architecture Structure of mjiobuf0077 is + component IBPU + port (I: in Std_logic; O: out Std_logic); + end component; + begin + INST1: IBPU + port map (I=>PAD, O=>Z); + end Structure; + +-- entity PHI2B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity PHI2B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "PHI2B"; + + tipd_PHI2S : VitalDelayType01 := (0 ns, 0 ns); + tpd_PHI2S_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_PHI2S : VitalDelayType := 0 ns; + tpw_PHI2S_posedge : VitalDelayType := 0 ns; + tpw_PHI2S_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; PHI2S: in Std_logic); + + ATTRIBUTE Vital_Level0 OF PHI2B : ENTITY IS TRUE; + + end PHI2B; + + architecture Structure of PHI2B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal PHI2S_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + PHI2_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>PHI2S_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(PHI2S_ipd, PHI2S, tipd_PHI2S); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, PHI2S_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_PHI2S_PHI2S : x01 := '0'; + VARIABLE periodcheckinfo_PHI2S : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => PHI2S_ipd, + TestSignalName => "PHI2S", + Period => tperiod_PHI2S, + PulseWidthHigh => tpw_PHI2S_posedge, + PulseWidthLow => tpw_PHI2S_negedge, + PeriodData => periodcheckinfo_PHI2S, + Violation => tviol_PHI2S_PHI2S, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => PHI2S_ipd'last_event, + PathDelay => tpd_PHI2S_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_9_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_9_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_9_B"; + + tipd_MAin9 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin9_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin9 : VitalDelayType := 0 ns; + tpw_MAin9_posedge : VitalDelayType := 0 ns; + tpw_MAin9_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin9: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_9_B : ENTITY IS TRUE; + + end MAin_9_B; + + architecture Structure of MAin_9_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin9_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_9: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin9_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin9_ipd, MAin9, tipd_MAin9); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin9_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin9_MAin9 : x01 := '0'; + VARIABLE periodcheckinfo_MAin9 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin9_ipd, + TestSignalName => "MAin9", + Period => tperiod_MAin9, + PulseWidthHigh => tpw_MAin9_posedge, + PulseWidthLow => tpw_MAin9_negedge, + PeriodData => periodcheckinfo_MAin9, + Violation => tviol_MAin9_MAin9, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin9_ipd'last_event, + PathDelay => tpd_MAin9_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_8_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_8_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_8_B"; + + tipd_MAin8 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin8_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin8 : VitalDelayType := 0 ns; + tpw_MAin8_posedge : VitalDelayType := 0 ns; + tpw_MAin8_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin8: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_8_B : ENTITY IS TRUE; + + end MAin_8_B; + + architecture Structure of MAin_8_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin8_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_8: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin8_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin8_ipd, MAin8, tipd_MAin8); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin8_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin8_MAin8 : x01 := '0'; + VARIABLE periodcheckinfo_MAin8 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin8_ipd, + TestSignalName => "MAin8", + Period => tperiod_MAin8, + PulseWidthHigh => tpw_MAin8_posedge, + PulseWidthLow => tpw_MAin8_negedge, + PeriodData => periodcheckinfo_MAin8, + Violation => tviol_MAin8_MAin8, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin8_ipd'last_event, + PathDelay => tpd_MAin8_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_7_B"; + + tipd_MAin7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin7 : VitalDelayType := 0 ns; + tpw_MAin7_posedge : VitalDelayType := 0 ns; + tpw_MAin7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_7_B : ENTITY IS TRUE; + + end MAin_7_B; + + architecture Structure of MAin_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin7_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_7: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin7_ipd, MAin7, tipd_MAin7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin7_MAin7 : x01 := '0'; + VARIABLE periodcheckinfo_MAin7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin7_ipd, + TestSignalName => "MAin7", + Period => tperiod_MAin7, + PulseWidthHigh => tpw_MAin7_posedge, + PulseWidthLow => tpw_MAin7_negedge, + PeriodData => periodcheckinfo_MAin7, + Violation => tviol_MAin7_MAin7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin7_ipd'last_event, + PathDelay => tpd_MAin7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_6_B"; + + tipd_MAin6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin6 : VitalDelayType := 0 ns; + tpw_MAin6_posedge : VitalDelayType := 0 ns; + tpw_MAin6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_6_B : ENTITY IS TRUE; + + end MAin_6_B; + + architecture Structure of MAin_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin6_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_6: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin6_ipd, MAin6, tipd_MAin6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin6_MAin6 : x01 := '0'; + VARIABLE periodcheckinfo_MAin6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin6_ipd, + TestSignalName => "MAin6", + Period => tperiod_MAin6, + PulseWidthHigh => tpw_MAin6_posedge, + PulseWidthLow => tpw_MAin6_negedge, + PeriodData => periodcheckinfo_MAin6, + Violation => tviol_MAin6_MAin6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin6_ipd'last_event, + PathDelay => tpd_MAin6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_5_B"; + + tipd_MAin5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin5 : VitalDelayType := 0 ns; + tpw_MAin5_posedge : VitalDelayType := 0 ns; + tpw_MAin5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_5_B : ENTITY IS TRUE; + + end MAin_5_B; + + architecture Structure of MAin_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin5_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_5: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin5_ipd, MAin5, tipd_MAin5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin5_MAin5 : x01 := '0'; + VARIABLE periodcheckinfo_MAin5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin5_ipd, + TestSignalName => "MAin5", + Period => tperiod_MAin5, + PulseWidthHigh => tpw_MAin5_posedge, + PulseWidthLow => tpw_MAin5_negedge, + PeriodData => periodcheckinfo_MAin5, + Violation => tviol_MAin5_MAin5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin5_ipd'last_event, + PathDelay => tpd_MAin5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_4_B"; + + tipd_MAin4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin4 : VitalDelayType := 0 ns; + tpw_MAin4_posedge : VitalDelayType := 0 ns; + tpw_MAin4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_4_B : ENTITY IS TRUE; + + end MAin_4_B; + + architecture Structure of MAin_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin4_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_4: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin4_ipd, MAin4, tipd_MAin4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin4_MAin4 : x01 := '0'; + VARIABLE periodcheckinfo_MAin4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin4_ipd, + TestSignalName => "MAin4", + Period => tperiod_MAin4, + PulseWidthHigh => tpw_MAin4_posedge, + PulseWidthLow => tpw_MAin4_negedge, + PeriodData => periodcheckinfo_MAin4, + Violation => tviol_MAin4_MAin4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin4_ipd'last_event, + PathDelay => tpd_MAin4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_3_B"; + + tipd_MAin3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin3 : VitalDelayType := 0 ns; + tpw_MAin3_posedge : VitalDelayType := 0 ns; + tpw_MAin3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_3_B : ENTITY IS TRUE; + + end MAin_3_B; + + architecture Structure of MAin_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin3_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_3: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin3_ipd, MAin3, tipd_MAin3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin3_MAin3 : x01 := '0'; + VARIABLE periodcheckinfo_MAin3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin3_ipd, + TestSignalName => "MAin3", + Period => tperiod_MAin3, + PulseWidthHigh => tpw_MAin3_posedge, + PulseWidthLow => tpw_MAin3_negedge, + PeriodData => periodcheckinfo_MAin3, + Violation => tviol_MAin3_MAin3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin3_ipd'last_event, + PathDelay => tpd_MAin3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_2_B"; + + tipd_MAin2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin2 : VitalDelayType := 0 ns; + tpw_MAin2_posedge : VitalDelayType := 0 ns; + tpw_MAin2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_2_B : ENTITY IS TRUE; + + end MAin_2_B; + + architecture Structure of MAin_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin2_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_2: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin2_ipd, MAin2, tipd_MAin2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin2_MAin2 : x01 := '0'; + VARIABLE periodcheckinfo_MAin2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin2_ipd, + TestSignalName => "MAin2", + Period => tperiod_MAin2, + PulseWidthHigh => tpw_MAin2_posedge, + PulseWidthLow => tpw_MAin2_negedge, + PeriodData => periodcheckinfo_MAin2, + Violation => tviol_MAin2_MAin2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin2_ipd'last_event, + PathDelay => tpd_MAin2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_1_B"; + + tipd_MAin1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin1 : VitalDelayType := 0 ns; + tpw_MAin1_posedge : VitalDelayType := 0 ns; + tpw_MAin1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_1_B : ENTITY IS TRUE; + + end MAin_1_B; + + architecture Structure of MAin_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin1_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_1: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin1_ipd, MAin1, tipd_MAin1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin1_MAin1 : x01 := '0'; + VARIABLE periodcheckinfo_MAin1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin1_ipd, + TestSignalName => "MAin1", + Period => tperiod_MAin1, + PulseWidthHigh => tpw_MAin1_posedge, + PulseWidthLow => tpw_MAin1_negedge, + PeriodData => periodcheckinfo_MAin1, + Violation => tviol_MAin1_MAin1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin1_ipd'last_event, + PathDelay => tpd_MAin1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity MAin_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity MAin_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "MAin_0_B"; + + tipd_MAin0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_MAin0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_MAin0 : VitalDelayType := 0 ns; + tpw_MAin0_posedge : VitalDelayType := 0 ns; + tpw_MAin0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; MAin0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF MAin_0_B : ENTITY IS TRUE; + + end MAin_0_B; + + architecture Structure of MAin_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal MAin0_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + MAin_pad_0: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>MAin0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(MAin0_ipd, MAin0, tipd_MAin0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, MAin0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_MAin0_MAin0 : x01 := '0'; + VARIABLE periodcheckinfo_MAin0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => MAin0_ipd, + TestSignalName => "MAin0", + Period => tperiod_MAin0, + PulseWidthHigh => tpw_MAin0_posedge, + PulseWidthLow => tpw_MAin0_negedge, + PeriodData => periodcheckinfo_MAin0, + Violation => tviol_MAin0_MAin0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => MAin0_ipd'last_event, + PathDelay => tpd_MAin0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity CROW_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_1_B"; + + tipd_CROW1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW1 : VitalDelayType := 0 ns; + tpw_CROW1_posedge : VitalDelayType := 0 ns; + tpw_CROW1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_1_B : ENTITY IS TRUE; + + end CROW_1_B; + + architecture Structure of CROW_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW1_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_1: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>CROW1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW1_ipd, CROW1, tipd_CROW1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW1_CROW1 : x01 := '0'; + VARIABLE periodcheckinfo_CROW1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW1_ipd, + TestSignalName => "CROW1", + Period => tperiod_CROW1, + PulseWidthHigh => tpw_CROW1_posedge, + PulseWidthLow => tpw_CROW1_negedge, + PeriodData => periodcheckinfo_CROW1, + Violation => tviol_CROW1_CROW1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW1_ipd'last_event, + PathDelay => tpd_CROW1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity CROW_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity CROW_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "CROW_0_B"; + + tipd_CROW0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_CROW0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_CROW0 : VitalDelayType := 0 ns; + tpw_CROW0_posedge : VitalDelayType := 0 ns; + tpw_CROW0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; CROW0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF CROW_0_B : ENTITY IS TRUE; + + end CROW_0_B; + + architecture Structure of CROW_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal CROW0_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + CROW_pad_0: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>CROW0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(CROW0_ipd, CROW0, tipd_CROW0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, CROW0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_CROW0_CROW0 : x01 := '0'; + VARIABLE periodcheckinfo_CROW0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => CROW0_ipd, + TestSignalName => "CROW0", + Period => tperiod_CROW0, + PulseWidthHigh => tpw_CROW0_posedge, + PulseWidthLow => tpw_CROW0_negedge, + PeriodData => periodcheckinfo_CROW0, + Violation => tviol_CROW0_CROW0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => CROW0_ipd'last_event, + PathDelay => tpd_CROW0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_7_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_7_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_7_B"; + + tipd_Din7 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din7_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din7 : VitalDelayType := 0 ns; + tpw_Din7_posedge : VitalDelayType := 0 ns; + tpw_Din7_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din7: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_7_B : ENTITY IS TRUE; + + end Din_7_B; + + architecture Structure of Din_7_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din7_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_7: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din7_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din7_ipd, Din7, tipd_Din7); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din7_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din7_Din7 : x01 := '0'; + VARIABLE periodcheckinfo_Din7 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din7_ipd, + TestSignalName => "Din7", + Period => tperiod_Din7, + PulseWidthHigh => tpw_Din7_posedge, + PulseWidthLow => tpw_Din7_negedge, + PeriodData => periodcheckinfo_Din7, + Violation => tviol_Din7_Din7, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din7_ipd'last_event, + PathDelay => tpd_Din7_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_6_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_6_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_6_B"; + + tipd_Din6 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din6_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din6 : VitalDelayType := 0 ns; + tpw_Din6_posedge : VitalDelayType := 0 ns; + tpw_Din6_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din6: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_6_B : ENTITY IS TRUE; + + end Din_6_B; + + architecture Structure of Din_6_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din6_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_6: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din6_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din6_ipd, Din6, tipd_Din6); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din6_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din6_Din6 : x01 := '0'; + VARIABLE periodcheckinfo_Din6 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din6_ipd, + TestSignalName => "Din6", + Period => tperiod_Din6, + PulseWidthHigh => tpw_Din6_posedge, + PulseWidthLow => tpw_Din6_negedge, + PeriodData => periodcheckinfo_Din6, + Violation => tviol_Din6_Din6, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din6_ipd'last_event, + PathDelay => tpd_Din6_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_5_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_5_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_5_B"; + + tipd_Din5 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din5_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din5 : VitalDelayType := 0 ns; + tpw_Din5_posedge : VitalDelayType := 0 ns; + tpw_Din5_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din5: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_5_B : ENTITY IS TRUE; + + end Din_5_B; + + architecture Structure of Din_5_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din5_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_5: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din5_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din5_ipd, Din5, tipd_Din5); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din5_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din5_Din5 : x01 := '0'; + VARIABLE periodcheckinfo_Din5 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din5_ipd, + TestSignalName => "Din5", + Period => tperiod_Din5, + PulseWidthHigh => tpw_Din5_posedge, + PulseWidthLow => tpw_Din5_negedge, + PeriodData => periodcheckinfo_Din5, + Violation => tviol_Din5_Din5, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din5_ipd'last_event, + PathDelay => tpd_Din5_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_4_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_4_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_4_B"; + + tipd_Din4 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din4_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din4 : VitalDelayType := 0 ns; + tpw_Din4_posedge : VitalDelayType := 0 ns; + tpw_Din4_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din4: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_4_B : ENTITY IS TRUE; + + end Din_4_B; + + architecture Structure of Din_4_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din4_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_4: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din4_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din4_ipd, Din4, tipd_Din4); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din4_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din4_Din4 : x01 := '0'; + VARIABLE periodcheckinfo_Din4 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din4_ipd, + TestSignalName => "Din4", + Period => tperiod_Din4, + PulseWidthHigh => tpw_Din4_posedge, + PulseWidthLow => tpw_Din4_negedge, + PeriodData => periodcheckinfo_Din4, + Violation => tviol_Din4_Din4, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din4_ipd'last_event, + PathDelay => tpd_Din4_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_3_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_3_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_3_B"; + + tipd_Din3 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din3_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din3 : VitalDelayType := 0 ns; + tpw_Din3_posedge : VitalDelayType := 0 ns; + tpw_Din3_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din3: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_3_B : ENTITY IS TRUE; + + end Din_3_B; + + architecture Structure of Din_3_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din3_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_3: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din3_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din3_ipd, Din3, tipd_Din3); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din3_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din3_Din3 : x01 := '0'; + VARIABLE periodcheckinfo_Din3 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din3_ipd, + TestSignalName => "Din3", + Period => tperiod_Din3, + PulseWidthHigh => tpw_Din3_posedge, + PulseWidthLow => tpw_Din3_negedge, + PeriodData => periodcheckinfo_Din3, + Violation => tviol_Din3_Din3, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din3_ipd'last_event, + PathDelay => tpd_Din3_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_2_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_2_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_2_B"; + + tipd_Din2 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din2_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din2 : VitalDelayType := 0 ns; + tpw_Din2_posedge : VitalDelayType := 0 ns; + tpw_Din2_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din2: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_2_B : ENTITY IS TRUE; + + end Din_2_B; + + architecture Structure of Din_2_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din2_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_2: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din2_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din2_ipd, Din2, tipd_Din2); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din2_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din2_Din2 : x01 := '0'; + VARIABLE periodcheckinfo_Din2 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din2_ipd, + TestSignalName => "Din2", + Period => tperiod_Din2, + PulseWidthHigh => tpw_Din2_posedge, + PulseWidthLow => tpw_Din2_negedge, + PeriodData => periodcheckinfo_Din2, + Violation => tviol_Din2_Din2, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din2_ipd'last_event, + PathDelay => tpd_Din2_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_1_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_1_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_1_B"; + + tipd_Din1 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din1_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din1 : VitalDelayType := 0 ns; + tpw_Din1_posedge : VitalDelayType := 0 ns; + tpw_Din1_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din1: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_1_B : ENTITY IS TRUE; + + end Din_1_B; + + architecture Structure of Din_1_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din1_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_1: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din1_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din1_ipd, Din1, tipd_Din1); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din1_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din1_Din1 : x01 := '0'; + VARIABLE periodcheckinfo_Din1 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din1_ipd, + TestSignalName => "Din1", + Period => tperiod_Din1, + PulseWidthHigh => tpw_Din1_posedge, + PulseWidthLow => tpw_Din1_negedge, + PeriodData => periodcheckinfo_Din1, + Violation => tviol_Din1_Din1, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din1_ipd'last_event, + PathDelay => tpd_Din1_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity Din_0_B + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity Din_0_B is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "Din_0_B"; + + tipd_Din0 : VitalDelayType01 := (0 ns, 0 ns); + tpd_Din0_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_Din0 : VitalDelayType := 0 ns; + tpw_Din0_posedge : VitalDelayType := 0 ns; + tpw_Din0_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; Din0: in Std_logic); + + ATTRIBUTE Vital_Level0 OF Din_0_B : ENTITY IS TRUE; + + end Din_0_B; + + architecture Structure of Din_0_B is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal Din0_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + Din_pad_0: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>Din0_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(Din0_ipd, Din0, tipd_Din0); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, Din0_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_Din0_Din0 : x01 := '0'; + VARIABLE periodcheckinfo_Din0 : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => Din0_ipd, + TestSignalName => "Din0", + Period => tperiod_Din0, + PulseWidthHigh => tpw_Din0_posedge, + PulseWidthLow => tpw_Din0_negedge, + PeriodData => periodcheckinfo_Din0, + Violation => tviol_Din0_Din0, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => Din0_ipd'last_event, + PathDelay => tpd_Din0_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCCASB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nCCASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCCASB"; + + tipd_nCCASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCCASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCCASS : VitalDelayType := 0 ns; + tpw_nCCASS_posedge : VitalDelayType := 0 ns; + tpw_nCCASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCCASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCCASB : ENTITY IS TRUE; + + end nCCASB; + + architecture Structure of nCCASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCCASS_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCCAS_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>nCCASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCCASS_ipd, nCCASS, tipd_nCCASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCCASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCCASS_nCCASS : x01 := '0'; + VARIABLE periodcheckinfo_nCCASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCCASS_ipd, + TestSignalName => "nCCASS", + Period => tperiod_nCCASS, + PulseWidthHigh => tpw_nCCASS_posedge, + PulseWidthLow => tpw_nCCASS_negedge, + PeriodData => periodcheckinfo_nCCASS, + Violation => tviol_nCCASS_nCCASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCCASS_ipd'last_event, + PathDelay => tpd_nCCASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nCRASB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nCRASB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nCRASB"; + + tipd_nCRASS : VitalDelayType01 := (0 ns, 0 ns); + tpd_nCRASS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nCRASS : VitalDelayType := 0 ns; + tpw_nCRASS_posedge : VitalDelayType := 0 ns; + tpw_nCRASS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nCRASS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nCRASB : ENTITY IS TRUE; + + end nCRASB; + + architecture Structure of nCRASB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nCRASS_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nCRAS_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>nCRASS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nCRASS_ipd, nCRASS, tipd_nCRASS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nCRASS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nCRASS_nCRASS : x01 := '0'; + VARIABLE periodcheckinfo_nCRASS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nCRASS_ipd, + TestSignalName => "nCRASS", + Period => tperiod_nCRASS, + PulseWidthHigh => tpw_nCRASS_posedge, + PulseWidthLow => tpw_nCRASS_negedge, + PeriodData => periodcheckinfo_nCRASS, + Violation => tviol_nCRASS_nCRASS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nCRASS_ipd'last_event, + PathDelay => tpd_nCRASS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity nFWEB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity nFWEB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "nFWEB"; + + tipd_nFWES : VitalDelayType01 := (0 ns, 0 ns); + tpd_nFWES_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_nFWES : VitalDelayType := 0 ns; + tpw_nFWES_posedge : VitalDelayType := 0 ns; + tpw_nFWES_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; nFWES: in Std_logic); + + ATTRIBUTE Vital_Level0 OF nFWEB : ENTITY IS TRUE; + + end nFWEB; + + architecture Structure of nFWEB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal nFWES_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + nFWE_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>nFWES_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(nFWES_ipd, nFWES, tipd_nFWES); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, nFWES_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_nFWES_nFWES : x01 := '0'; + VARIABLE periodcheckinfo_nFWES : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => nFWES_ipd, + TestSignalName => "nFWES", + Period => tperiod_nFWES, + PulseWidthHigh => tpw_nFWES_posedge, + PulseWidthLow => tpw_nFWES_negedge, + PeriodData => periodcheckinfo_nFWES, + Violation => tviol_nFWES_nFWES, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => nFWES_ipd'last_event, + PathDelay => tpd_nFWES_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RCLKB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RCLKB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "RCLKB"; + + tipd_RCLKS : VitalDelayType01 := (0 ns, 0 ns); + tpd_RCLKS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_RCLKS : VitalDelayType := 0 ns; + tpw_RCLKS_posedge : VitalDelayType := 0 ns; + tpw_RCLKS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; RCLKS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF RCLKB : ENTITY IS TRUE; + + end RCLKB; + + architecture Structure of RCLKB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal RCLKS_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + RCLK_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>RCLKS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(RCLKS_ipd, RCLKS, tipd_RCLKS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, RCLKS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_RCLKS_RCLKS : x01 := '0'; + VARIABLE periodcheckinfo_RCLKS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => RCLKS_ipd, + TestSignalName => "RCLKS", + Period => tperiod_RCLKS, + PulseWidthHigh => tpw_RCLKS_posedge, + PulseWidthLow => tpw_RCLKS_negedge, + PeriodData => periodcheckinfo_RCLKS, + Violation => tviol_RCLKS_RCLKS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => RCLKS_ipd'last_event, + PathDelay => tpd_RCLKS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity UFMSDOB + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity UFMSDOB is + -- miscellaneous vital GENERICs + GENERIC ( + TimingChecksOn : boolean := TRUE; + XOn : boolean := FALSE; + MsgOn : boolean := TRUE; + InstancePath : string := "UFMSDOB"; + + tipd_UFMSDOS : VitalDelayType01 := (0 ns, 0 ns); + tpd_UFMSDOS_PADDI : VitalDelayType01 := (0 ns, 0 ns); + tperiod_UFMSDOS : VitalDelayType := 0 ns; + tpw_UFMSDOS_posedge : VitalDelayType := 0 ns; + tpw_UFMSDOS_negedge : VitalDelayType := 0 ns); + + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + + ATTRIBUTE Vital_Level0 OF UFMSDOB : ENTITY IS TRUE; + + end UFMSDOB; + + architecture Structure of UFMSDOB is + ATTRIBUTE Vital_Level0 OF Structure : ARCHITECTURE IS TRUE; + + signal PADDI_out : std_logic := 'X'; + signal UFMSDOS_ipd : std_logic := 'X'; + + component mjiobuf0077 + port (Z: out Std_logic; PAD: in Std_logic); + end component; + begin + UFMSDO_pad: mjiobuf0077 + port map (Z=>PADDI_out, PAD=>UFMSDOS_ipd); + + -- INPUT PATH DELAYs + WireDelay : BLOCK + BEGIN + VitalWireDelay(UFMSDOS_ipd, UFMSDOS, tipd_UFMSDOS); + END BLOCK; + + VitalBehavior : PROCESS (PADDI_out, UFMSDOS_ipd) + VARIABLE PADDI_zd : std_logic := 'X'; + VARIABLE PADDI_GlitchData : VitalGlitchDataType; + + VARIABLE tviol_UFMSDOS_UFMSDOS : x01 := '0'; + VARIABLE periodcheckinfo_UFMSDOS : VitalPeriodDataType; + + BEGIN + + IF (TimingChecksOn) THEN + VitalPeriodPulseCheck ( + TestSignal => UFMSDOS_ipd, + TestSignalName => "UFMSDOS", + Period => tperiod_UFMSDOS, + PulseWidthHigh => tpw_UFMSDOS_posedge, + PulseWidthLow => tpw_UFMSDOS_negedge, + PeriodData => periodcheckinfo_UFMSDOS, + Violation => tviol_UFMSDOS_UFMSDOS, + MsgOn => MsgOn, XOn => XOn, + HeaderMsg => InstancePath, + CheckEnabled => TRUE, + MsgSeverity => warning); + + END IF; + + PADDI_zd := PADDI_out; + + VitalPathDelay01 ( + OutSignal => PADDI, OutSignalName => "PADDI", OutTemp => PADDI_zd, + Paths => (0 => (InputChangeTime => UFMSDOS_ipd'last_event, + PathDelay => tpd_UFMSDOS_PADDI, + PathCondition => TRUE)), + GlitchData => PADDI_GlitchData, + Mode => vitaltransport, XOn => XOn, MsgOn => MsgOn); + + END PROCESS; + + end Structure; + +-- entity RAM2GS + library IEEE, vital2000, MACHXO; + use IEEE.STD_LOGIC_1164.all; + use vital2000.vital_timing.all; + use MACHXO.COMPONENTS.ALL; + + entity RAM2GS is + port (PHI2: in Std_logic; MAin: in Std_logic_vector (9 downto 0); + CROW: in Std_logic_vector (1 downto 0); + Din: in Std_logic_vector (7 downto 0); + Dout: out Std_logic_vector (7 downto 0); nCCAS: in Std_logic; + nCRAS: in Std_logic; nFWE: in Std_logic; LED: out Std_logic; + RBA: out Std_logic_vector (1 downto 0); + RA: out Std_logic_vector (11 downto 0); + RD: inout Std_logic_vector (7 downto 0); nRCS: out Std_logic; + RCLK: in Std_logic; RCKE: out Std_logic; nRWE: out Std_logic; + nRRAS: out Std_logic; nRCAS: out Std_logic; RDQMH: out Std_logic; + RDQML: out Std_logic; nUFMCS: out Std_logic; UFMCLK: out Std_logic; + UFMSDI: out Std_logic; UFMSDO: in Std_logic); + + + + end RAM2GS; + + architecture Structure of RAM2GS is + signal FS_7: Std_logic; + signal FS_6: Std_logic; + signal RCLK_c: Std_logic; + signal n2010: Std_logic; + signal n2011: Std_logic; + signal FS_15: Std_logic; + signal FS_14: Std_logic; + signal n2014: Std_logic; + signal n2015: Std_logic; + signal FS_5: Std_logic; + signal FS_4: Std_logic; + signal n2009: Std_logic; + signal FS_13: Std_logic; + signal FS_12: Std_logic; + signal n2013: Std_logic; + signal FS_1: Std_logic; + signal FS_0: Std_logic; + signal n2008: Std_logic; + signal FS_11: Std_logic; + signal FS_10: Std_logic; + signal n2012: Std_logic; + signal FS_3: Std_logic; + signal FS_2: Std_logic; + signal FS_9: Std_logic; + signal FS_8: Std_logic; + signal FS_17: Std_logic; + signal FS_16: Std_logic; + signal MAin_c_1: Std_logic; + signal n1326: Std_logic; + signal MAin_c_0: Std_logic; + signal n2263: Std_logic; + signal ADSubmitted: Std_logic; + signal n2242: Std_logic; + signal n2459: Std_logic; + signal n1413: Std_logic; + signal C1Submitted_N_237: Std_logic; + signal PHI2_c: Std_logic; + signal Din_c_6: Std_logic; + signal C1Submitted: Std_logic; + signal nFWE_c: Std_logic; + signal n6_adj_3: Std_logic; + signal n2284: Std_logic; + signal MAin_c_5: Std_logic; + signal n2316: Std_logic; + signal n26: Std_logic; + signal MAin_c_2: Std_logic; + signal n15: Std_logic; + signal n2463: Std_logic; + signal CmdEnable_N_248: Std_logic; + signal PHI2_N_120_enable_7: Std_logic; + signal CmdEnable: Std_logic; + signal PHI2r2: Std_logic; + signal CmdSubmitted: Std_logic; + signal PHI2r3: Std_logic; + signal n2568_001_BUF1: Std_logic; + signal PHI2_N_120_enable_5: Std_logic; + signal n2472: Std_logic; + signal Din_c_5: Std_logic; + signal Din_c_7: Std_logic; + signal n1314: Std_logic; + signal Din_c_4: Std_logic; + signal n8MEGEN: Std_logic; + signal Din_c_0: Std_logic; + signal Cmdn8MEGEN_N_264: Std_logic; + signal PHI2_N_120_enable_4: Std_logic; + signal Cmdn8MEGEN: Std_logic; + signal nRowColSel_N_35: Std_logic; + signal RASr2: Std_logic; + signal InitReady: Std_logic; + signal Ready: Std_logic; + signal n2568_000_BUF1: Std_logic; + signal RCLK_c_enable_25: Std_logic; + signal RCLK_c_enable_23: Std_logic; + signal nCRAS_c: Std_logic; + signal CBR: Std_logic; + signal LEDEN: Std_logic; + signal n2568: Std_logic; + signal RCLK_c_enable_12: Std_logic; + signal LED_N_84: Std_logic; + signal nRowColSel_N_34: Std_logic; + signal nRCAS_N_165: Std_logic; + signal n2208: Std_logic; + signal n2209: Std_logic; + signal nRWE_N_177: Std_logic; + signal RA_0S: Std_logic; + signal n56: Std_logic; + signal XOR8MEG: Std_logic; + signal RA11_N_184: Std_logic; + signal RA_c: Std_logic; + signal n2478: Std_logic; + signal RCKEEN_N_122: Std_logic; + signal RCKEEN_N_121: Std_logic; + signal RCLK_c_enable_4: Std_logic; + signal RCKEEN: Std_logic; + signal n2467: Std_logic; + signal RCKE_c: Std_logic; + signal RASr3: Std_logic; + signal RASr: Std_logic; + signal RCKE_N_132: Std_logic; + signal CASr: Std_logic; + signal nRWE_N_182: Std_logic; + signal CASr2: Std_logic; + signal n2568_002_BUF1: Std_logic; + signal Ready_N_292: Std_logic; + signal n2469: Std_logic; + signal n2462: Std_logic; + signal n62: Std_logic; + signal n1160: Std_logic; + signal CmdUFMCLK: Std_logic; + signal UFMCLK_N_224: Std_logic; + signal RCLK_c_enable_24: Std_logic; + signal n1846: Std_logic; + signal UFMCLK_c: Std_logic; + signal n2470: Std_logic; + signal n2272: Std_logic; + signal n2471: Std_logic; + signal CmdUFMSDI: Std_logic; + signal n2461: Std_logic; + signal UFMSDI_N_231: Std_logic; + signal UFMSDI_c: Std_logic; + signal Din_c_1: Std_logic; + signal n2324: Std_logic; + signal Din_c_2: Std_logic; + signal Din_c_3: Std_logic; + signal XOR8MEG_N_110: Std_logic; + signal PHI2_N_120_enable_1: Std_logic; + signal n2464: Std_logic; + signal n1325: Std_logic; + signal UFMSDO_c: Std_logic; + signal n8MEGEN_N_91: Std_logic; + signal RCLK_c_enable_11: Std_logic; + signal n2427: Std_logic; + signal n15_adj_1: Std_logic; + signal nRCAS_N_161: Std_logic; + signal nRCAS_c: Std_logic; + signal n13: Std_logic; + signal n2481: Std_logic; + signal nRCS_N_136: Std_logic; + signal nRCS_c: Std_logic; + signal nRCS_N_139: Std_logic; + signal nRowColSel_N_32: Std_logic; + signal n6: Std_logic; + signal nRRAS_c: Std_logic; + signal n2138: Std_logic; + signal nRWE_N_178: Std_logic; + signal n33: Std_logic; + signal nRWE_N_171: Std_logic; + signal RCLK_c_enable_3: Std_logic; + signal nRWE_c: Std_logic; + signal nRowColSel: Std_logic; + signal MAin_c_9: Std_logic; + signal RowA_9: Std_logic; + signal nRowColSel_N_28: Std_logic; + signal n1502: Std_logic; + signal n1410: Std_logic; + signal RA_1_9: Std_logic; + signal Ready_N_296: Std_logic; + signal nRowColSel_N_33: Std_logic; + signal n1503: Std_logic; + signal n2414: Std_logic; + signal n1093: Std_logic; + signal CmdUFMCS: Std_logic; + signal nUFMCS_c: Std_logic; + signal n11: Std_logic; + signal n1417: Std_logic; + signal n2322: Std_logic; + signal CASr3: Std_logic; + signal n12: Std_logic; + signal n2164: Std_logic; + signal LEDEN_N_82: Std_logic; + signal FWEr: Std_logic; + signal n2476: Std_logic; + signal n2475: Std_logic; + signal n13_adj_2: Std_logic; + signal n1: Std_logic; + signal n2214: Std_logic; + signal n2328: Std_logic; + signal n10: Std_logic; + signal n2458: Std_logic; + signal n732: Std_logic; + signal n733: Std_logic; + signal n2290: Std_logic; + signal n728: Std_logic; + signal n729: Std_logic; + signal n8: Std_logic; + signal n727: Std_logic; + signal MAin_c_7: Std_logic; + signal MAin_c_6: Std_logic; + signal RowA_6: Std_logic; + signal RowA_7: Std_logic; + signal n2468: Std_logic; + signal n1280: Std_logic; + signal PHI2r: Std_logic; + signal nCCAS_c: Std_logic; + signal n726: Std_logic; + signal Bank_3: Std_logic; + signal Bank_6: Std_logic; + signal Bank_5: Std_logic; + signal n2278: Std_logic; + signal n2314: Std_logic; + signal Bank_2: Std_logic; + signal PHI2_N_120_enable_6: Std_logic; + signal n14: Std_logic; + signal n2460: Std_logic; + signal n730: Std_logic; + signal n2262: Std_logic; + signal n2473: Std_logic; + signal n738: Std_logic; + signal n737: Std_logic; + signal n2474: Std_logic; + signal n2253: Std_logic; + signal CROW_c_1: Std_logic; + signal CROW_c_0: Std_logic; + signal RBA_c_0: Std_logic; + signal RBA_c_1: Std_logic; + signal n734: Std_logic; + signal n735: Std_logic; + signal n7: Std_logic; + signal n2451: Std_logic; + signal Bank_0: Std_logic; + signal Bank_1: Std_logic; + signal WRD_0: Std_logic; + signal WRD_1: Std_logic; + signal MAin_c_8: Std_logic; + signal RowA_8: Std_logic; + signal WRD_6: Std_logic; + signal WRD_7: Std_logic; + signal RDQMH_c: Std_logic; + signal RDQML_c: Std_logic; + signal MAin_c_4: Std_logic; + signal RowA_4: Std_logic; + signal RowA_5: Std_logic; + signal MAin_c_3: Std_logic; + signal RowA_3: Std_logic; + signal Bank_4: Std_logic; + signal RowA_2: Std_logic; + signal RA_1_3: Std_logic; + signal Bank_7: Std_logic; + signal RowA_0: Std_logic; + signal RA_1_4: Std_logic; + signal RowA_1: Std_logic; + signal RA_1_8: Std_logic; + signal RA_1_0: Std_logic; + signal RA_1_7: Std_logic; + signal RA_1_1: Std_logic; + signal n736: Std_logic; + signal RA_1_6: Std_logic; + signal RA_1_2: Std_logic; + signal WRD_2: Std_logic; + signal RA_1_5: Std_logic; + signal WRD_3: Std_logic; + signal WRD_4: Std_logic; + signal n984: Std_logic; + signal WRD_5: Std_logic; + signal Dout_c: Std_logic; + signal Dout_0S: Std_logic; + signal Dout_1S: Std_logic; + signal Dout_2S: Std_logic; + signal Dout_3S: Std_logic; + signal Dout_4S: Std_logic; + signal Dout_5S: Std_logic; + signal Dout_6S: Std_logic; + signal VCCI: Std_logic; + signal GNDI_TSALL: Std_logic; + component VHI + port (Z: out Std_logic); + end component; + component VLO + port (Z: out Std_logic); + end component; + component PUR + port (PUR: in Std_logic); + end component; + component GSR + port (GSR: in Std_logic); + end component; + component TSALL + port (TSALL: in Std_logic); + end component; + component SLICE_0 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_1 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_2 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_3 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_4 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + Q0: out Std_logic; Q1: out Std_logic; FCO: out Std_logic); + end component; + component SLICE_5 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_6 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_7 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic; + FCO: out Std_logic); + end component; + component SLICE_8 + port (A1: in Std_logic; A0: in Std_logic; CLK: in Std_logic; + FCI: in Std_logic; Q0: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_9 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_14 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_18 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_19 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_23 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_25 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_26 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_31 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_32 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_34 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_35 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; M1: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_36 + port (B1: in Std_logic; A1: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_43 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_44 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_49 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_56 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_58 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; OFX0: out Std_logic; + Q0: out Std_logic); + end component; + component SLICE_60 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_61 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; OFX0: out Std_logic; Q0: out Std_logic); + end component; + component SLICE_63 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; DI0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_64 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_65 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_66 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + DI0: in Std_logic; LSR: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_67 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_68 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_69 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; DI0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component RCKEEN_I_0_445_SLICE_70 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + end component; + component i26_SLICE_71 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + OFX0: out Std_logic); + end component; + component i2099_SLICE_72 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; OFX0: out Std_logic); + end component; + component i26_adj_28_SLICE_73 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + OFX0: out Std_logic); + end component; + component SLICE_74 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_75 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_76 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_77 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_78 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_79 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_80 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_81 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_82 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_83 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_84 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CE: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_85 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_86 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_87 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_88 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_89 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_90 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_91 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_92 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_93 + port (B1: in Std_logic; A1: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M0: in Std_logic; CE: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic); + end component; + component SLICE_94 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_95 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; LSR: in Std_logic; + CLK: in Std_logic; F0: out Std_logic; Q0: out Std_logic; + F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_96 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_97 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + D0: in Std_logic; C0: in Std_logic; B0: in Std_logic; + A0: in Std_logic; M1: in Std_logic; M0: in Std_logic; + LSR: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_98 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_99 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_100 + port (D1: in Std_logic; C1: in Std_logic; B1: in Std_logic; + A1: in Std_logic; D0: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CE: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_101 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_102 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component SLICE_103 + port (C1: in Std_logic; B1: in Std_logic; A1: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + M1: in Std_logic; M0: in Std_logic; CLK: in Std_logic; + F0: out Std_logic; Q0: out Std_logic; F1: out Std_logic; + Q1: out Std_logic); + end component; + component SLICE_104 + port (B1: in Std_logic; A1: in Std_logic; D0: in Std_logic; + C0: in Std_logic; B0: in Std_logic; A0: in Std_logic; + F0: out Std_logic; F1: out Std_logic); + end component; + component SLICE_105 + port (B1: in Std_logic; A1: in Std_logic; C0: in Std_logic; + B0: in Std_logic; A0: in Std_logic; M1: in Std_logic; + M0: in Std_logic; CLK: in Std_logic; F0: out Std_logic; + Q0: out Std_logic; F1: out Std_logic; Q1: out Std_logic); + end component; + component RD_7_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD7: inout Std_logic); + end component; + component RD_6_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD6: inout Std_logic); + end component; + component RD_5_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD5: inout Std_logic); + end component; + component RD_4_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD4: inout Std_logic); + end component; + component RD_3_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD3: inout Std_logic); + end component; + component RD_2_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD2: inout Std_logic); + end component; + component RD_1_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD1: inout Std_logic); + end component; + component RD_0_B + port (PADDI: out Std_logic; PADDT: in Std_logic; PADDO: in Std_logic; + RD0: inout Std_logic); + end component; + component Dout_7_B + port (PADDO: in Std_logic; Dout7: out Std_logic); + end component; + component Dout_6_B + port (PADDO: in Std_logic; Dout6: out Std_logic); + end component; + component Dout_5_B + port (PADDO: in Std_logic; Dout5: out Std_logic); + end component; + component Dout_4_B + port (PADDO: in Std_logic; Dout4: out Std_logic); + end component; + component Dout_3_B + port (PADDO: in Std_logic; Dout3: out Std_logic); + end component; + component Dout_2_B + port (PADDO: in Std_logic; Dout2: out Std_logic); + end component; + component Dout_1_B + port (PADDO: in Std_logic; Dout1: out Std_logic); + end component; + component Dout_0_B + port (PADDO: in Std_logic; Dout0: out Std_logic); + end component; + component LEDB + port (PADDO: in Std_logic; LEDS: out Std_logic); + end component; + component RBA_1_B + port (PADDO: in Std_logic; RBA1: out Std_logic); + end component; + component RBA_0_B + port (PADDO: in Std_logic; RBA0: out Std_logic); + end component; + component RA_11_B + port (PADDO: in Std_logic; RA11: out Std_logic); + end component; + component RA_10_B + port (PADDO: in Std_logic; RA10: out Std_logic); + end component; + component RA_9_B + port (PADDO: in Std_logic; RA9: out Std_logic); + end component; + component RA_8_B + port (PADDO: in Std_logic; RA8: out Std_logic); + end component; + component RA_7_B + port (PADDO: in Std_logic; RA7: out Std_logic); + end component; + component RA_6_B + port (PADDO: in Std_logic; RA6: out Std_logic); + end component; + component RA_5_B + port (PADDO: in Std_logic; RA5: out Std_logic); + end component; + component RA_4_B + port (PADDO: in Std_logic; RA4: out Std_logic); + end component; + component RA_3_B + port (PADDO: in Std_logic; RA3: out Std_logic); + end component; + component RA_2_B + port (PADDO: in Std_logic; RA2: out Std_logic); + end component; + component RA_1_B + port (PADDO: in Std_logic; RA1: out Std_logic); + end component; + component RA_0_B + port (PADDO: in Std_logic; RA0: out Std_logic); + end component; + component nRCSB + port (PADDO: in Std_logic; nRCSS: out Std_logic); + end component; + component RCKEB + port (PADDO: in Std_logic; RCKES: out Std_logic); + end component; + component nRWEB + port (PADDO: in Std_logic; nRWES: out Std_logic); + end component; + component nRRASB + port (PADDO: in Std_logic; nRRASS: out Std_logic); + end component; + component nRCASB + port (PADDO: in Std_logic; nRCASS: out Std_logic); + end component; + component RDQMHB + port (PADDO: in Std_logic; RDQMHS: out Std_logic); + end component; + component RDQMLB + port (PADDO: in Std_logic; RDQMLS: out Std_logic); + end component; + component nUFMCSB + port (PADDO: in Std_logic; nUFMCSS: out Std_logic); + end component; + component UFMCLKB + port (PADDO: in Std_logic; UFMCLKS: out Std_logic); + end component; + component UFMSDIB + port (PADDO: in Std_logic; UFMSDIS: out Std_logic); + end component; + component PHI2B + port (PADDI: out Std_logic; PHI2S: in Std_logic); + end component; + component MAin_9_B + port (PADDI: out Std_logic; MAin9: in Std_logic); + end component; + component MAin_8_B + port (PADDI: out Std_logic; MAin8: in Std_logic); + end component; + component MAin_7_B + port (PADDI: out Std_logic; MAin7: in Std_logic); + end component; + component MAin_6_B + port (PADDI: out Std_logic; MAin6: in Std_logic); + end component; + component MAin_5_B + port (PADDI: out Std_logic; MAin5: in Std_logic); + end component; + component MAin_4_B + port (PADDI: out Std_logic; MAin4: in Std_logic); + end component; + component MAin_3_B + port (PADDI: out Std_logic; MAin3: in Std_logic); + end component; + component MAin_2_B + port (PADDI: out Std_logic; MAin2: in Std_logic); + end component; + component MAin_1_B + port (PADDI: out Std_logic; MAin1: in Std_logic); + end component; + component MAin_0_B + port (PADDI: out Std_logic; MAin0: in Std_logic); + end component; + component CROW_1_B + port (PADDI: out Std_logic; CROW1: in Std_logic); + end component; + component CROW_0_B + port (PADDI: out Std_logic; CROW0: in Std_logic); + end component; + component Din_7_B + port (PADDI: out Std_logic; Din7: in Std_logic); + end component; + component Din_6_B + port (PADDI: out Std_logic; Din6: in Std_logic); + end component; + component Din_5_B + port (PADDI: out Std_logic; Din5: in Std_logic); + end component; + component Din_4_B + port (PADDI: out Std_logic; Din4: in Std_logic); + end component; + component Din_3_B + port (PADDI: out Std_logic; Din3: in Std_logic); + end component; + component Din_2_B + port (PADDI: out Std_logic; Din2: in Std_logic); + end component; + component Din_1_B + port (PADDI: out Std_logic; Din1: in Std_logic); + end component; + component Din_0_B + port (PADDI: out Std_logic; Din0: in Std_logic); + end component; + component nCCASB + port (PADDI: out Std_logic; nCCASS: in Std_logic); + end component; + component nCRASB + port (PADDI: out Std_logic; nCRASS: in Std_logic); + end component; + component nFWEB + port (PADDI: out Std_logic; nFWES: in Std_logic); + end component; + component RCLKB + port (PADDI: out Std_logic; RCLKS: in Std_logic); + end component; + component UFMSDOB + port (PADDI: out Std_logic; UFMSDOS: in Std_logic); + end component; + begin + SLICE_0I: SLICE_0 + port map (A1=>FS_7, A0=>FS_6, CLK=>RCLK_c, FCI=>n2010, Q0=>FS_6, + Q1=>FS_7, FCO=>n2011); + SLICE_1I: SLICE_1 + port map (A1=>FS_15, A0=>FS_14, CLK=>RCLK_c, FCI=>n2014, Q0=>FS_14, + Q1=>FS_15, FCO=>n2015); + SLICE_2I: SLICE_2 + port map (A1=>FS_5, A0=>FS_4, CLK=>RCLK_c, FCI=>n2009, Q0=>FS_4, + Q1=>FS_5, FCO=>n2010); + SLICE_3I: SLICE_3 + port map (A1=>FS_13, A0=>FS_12, CLK=>RCLK_c, FCI=>n2013, Q0=>FS_12, + Q1=>FS_13, FCO=>n2014); + SLICE_4I: SLICE_4 + port map (A1=>FS_1, A0=>FS_0, CLK=>RCLK_c, Q0=>FS_0, Q1=>FS_1, + FCO=>n2008); + SLICE_5I: SLICE_5 + port map (A1=>FS_11, A0=>FS_10, CLK=>RCLK_c, FCI=>n2012, Q0=>FS_10, + Q1=>FS_11, FCO=>n2013); + SLICE_6I: SLICE_6 + port map (A1=>FS_3, A0=>FS_2, CLK=>RCLK_c, FCI=>n2008, Q0=>FS_2, + Q1=>FS_3, FCO=>n2009); + SLICE_7I: SLICE_7 + port map (A1=>FS_9, A0=>FS_8, CLK=>RCLK_c, FCI=>n2011, Q0=>FS_8, + Q1=>FS_9, FCO=>n2012); + SLICE_8I: SLICE_8 + port map (A1=>FS_17, A0=>FS_16, CLK=>RCLK_c, FCI=>n2015, Q0=>FS_16, + Q1=>FS_17); + SLICE_9I: SLICE_9 + port map (C1=>MAin_c_1, B1=>n1326, A1=>MAin_c_0, D0=>n2263, + C0=>ADSubmitted, B0=>n2242, A0=>n2459, DI0=>n1413, + LSR=>C1Submitted_N_237, CLK=>PHI2_c, F0=>n1413, + Q0=>ADSubmitted, F1=>n2263); + SLICE_14I: SLICE_14 + port map (B1=>Din_c_6, A1=>C1Submitted, D0=>MAin_c_1, C0=>C1Submitted, + B0=>n1326, A0=>nFWE_c, DI0=>n6_adj_3, LSR=>C1Submitted_N_237, + CLK=>PHI2_c, F0=>n6_adj_3, Q0=>C1Submitted, F1=>n2284); + SLICE_18I: SLICE_18 + port map (D1=>MAin_c_5, C1=>n2316, B1=>n26, A1=>MAin_c_2, D0=>n15, + C0=>n1326, B0=>n2463, A0=>MAin_c_1, DI0=>CmdEnable_N_248, + CE=>PHI2_N_120_enable_7, CLK=>PHI2_c, F0=>CmdEnable_N_248, + Q0=>CmdEnable, F1=>n1326); + SLICE_19I: SLICE_19 + port map (C1=>PHI2r2, B1=>CmdSubmitted, A1=>PHI2r3, DI0=>n2568_001_BUF1, + CE=>PHI2_N_120_enable_5, CLK=>PHI2_c, F0=>n2568_001_BUF1, + Q0=>CmdSubmitted, F1=>n2472); + SLICE_23I: SLICE_23 + port map (C1=>Din_c_5, B1=>Din_c_7, A1=>Din_c_6, D0=>n1314, C0=>Din_c_4, + B0=>n8MEGEN, A0=>Din_c_0, DI0=>Cmdn8MEGEN_N_264, + CE=>PHI2_N_120_enable_4, CLK=>PHI2_c, F0=>Cmdn8MEGEN_N_264, + Q0=>Cmdn8MEGEN, F1=>n1314); + SLICE_25I: SLICE_25 + port map (D1=>nRowColSel_N_35, C1=>RASr2, B1=>InitReady, A1=>Ready, + DI0=>n2568_000_BUF1, CE=>RCLK_c_enable_25, CLK=>RCLK_c, + F0=>n2568_000_BUF1, Q0=>InitReady, F1=>RCLK_c_enable_23); + SLICE_26I: SLICE_26 + port map (C1=>nCRAS_c, B1=>CBR, A1=>LEDEN, DI0=>n2568, + CE=>RCLK_c_enable_12, CLK=>RCLK_c, F0=>n2568, Q0=>LEDEN, + F1=>LED_N_84); + SLICE_31I: SLICE_31 + port map (B1=>nRowColSel_N_34, A1=>Ready, C0=>nRCAS_N_165, B0=>Ready, + A0=>n2208, DI0=>n2209, LSR=>nRWE_N_177, CLK=>RCLK_c, F0=>n2209, + Q0=>RA_0S, F1=>n56); + SLICE_32I: SLICE_32 + port map (B1=>Din_c_7, A1=>Din_c_6, C0=>n8MEGEN, B0=>XOR8MEG, + A0=>Din_c_6, DI0=>RA11_N_184, LSR=>Ready, CLK=>PHI2_c, + F0=>RA11_N_184, Q0=>RA_c, F1=>n2478); + SLICE_34I: SLICE_34 + port map (C1=>Ready, B1=>InitReady, A1=>RASr2, C0=>Ready, + B0=>RCKEEN_N_122, A0=>InitReady, DI0=>RCKEEN_N_121, + CE=>RCLK_c_enable_4, CLK=>RCLK_c, F0=>RCKEEN_N_121, Q0=>RCKEEN, + F1=>n2467); + SLICE_35I: SLICE_35 + port map (B1=>RCKE_c, A1=>RASr2, D0=>RASr3, C0=>RASr2, B0=>RCKEEN, + A0=>RASr, DI0=>RCKE_N_132, M1=>CASr, CLK=>RCLK_c, + F0=>RCKE_N_132, Q0=>RCKE_c, F1=>nRWE_N_182, Q1=>CASr2); + SLICE_36I: SLICE_36 + port map (B1=>nRowColSel_N_35, A1=>Ready, DI0=>n2568_002_BUF1, + CE=>Ready_N_292, CLK=>RCLK_c, F0=>n2568_002_BUF1, Q0=>Ready, + F1=>n2469); + SLICE_43I: SLICE_43 + port map (D1=>FS_1, C1=>n2462, B1=>n62, A1=>FS_4, C0=>InitReady, + B0=>n1160, A0=>CmdUFMCLK, DI0=>UFMCLK_N_224, + CE=>RCLK_c_enable_24, LSR=>n1846, CLK=>RCLK_c, + F0=>UFMCLK_N_224, Q0=>UFMCLK_c, F1=>n1160); + SLICE_44I: SLICE_44 + port map (D1=>FS_11, C1=>n2470, B1=>n2272, A1=>n2471, D0=>CmdUFMSDI, + C0=>InitReady, B0=>n2462, A0=>n2461, DI0=>UFMSDI_N_231, + CE=>RCLK_c_enable_24, LSR=>n1846, CLK=>RCLK_c, + F0=>UFMSDI_N_231, Q0=>UFMSDI_c, F1=>n2462); + SLICE_49I: SLICE_49 + port map (D1=>Din_c_1, C1=>n1314, B1=>LEDEN, A1=>Din_c_4, D0=>n2324, + C0=>Din_c_2, B0=>Din_c_3, A0=>Din_c_0, DI0=>XOR8MEG_N_110, + CE=>PHI2_N_120_enable_1, CLK=>PHI2_c, F0=>XOR8MEG_N_110, + Q0=>XOR8MEG, F1=>n2324); + SLICE_56I: SLICE_56 + port map (C1=>FS_10, B1=>n2464, A1=>FS_11, D0=>n1325, C0=>InitReady, + B0=>Cmdn8MEGEN, A0=>UFMSDO_c, DI0=>n8MEGEN_N_91, + CE=>RCLK_c_enable_11, CLK=>RCLK_c, F0=>n8MEGEN_N_91, + Q0=>n8MEGEN, F1=>n1325); + SLICE_58I: SLICE_58 + port map (D1=>n2427, C1=>RASr2, B1=>CBR, A1=>Ready, C0=>Ready, + B0=>n15_adj_1, A0=>nRowColSel_N_34, DI0=>nRCAS_N_161, + M0=>nRowColSel_N_35, CE=>RCLK_c_enable_4, CLK=>RCLK_c, + OFX0=>nRCAS_N_161, Q0=>nRCAS_c); + SLICE_60I: SLICE_60 + port map (D1=>Ready, C1=>RCKE_c, B1=>InitReady, A1=>RASr2, + D0=>nRowColSel_N_35, C0=>n13, B0=>n2481, A0=>n2467, + DI0=>nRCS_N_136, CE=>RCLK_c_enable_4, CLK=>RCLK_c, + F0=>nRCS_N_136, Q0=>nRCS_c, F1=>n13); + SLICE_61I: SLICE_61 + port map (C1=>nRCS_N_139, B1=>n13, A1=>Ready, D0=>nRowColSel_N_32, + C0=>n6, B0=>nRRAS_c, A0=>n56, DI0=>n2138, M0=>nRowColSel_N_35, + CLK=>RCLK_c, OFX0=>n2138, Q0=>nRRAS_c); + SLICE_63I: SLICE_63 + port map (D1=>nRCS_N_139, C1=>InitReady, B1=>RASr2, A1=>nRowColSel_N_35, + D0=>n2208, C0=>Ready, B0=>nRWE_N_178, A0=>n33, DI0=>nRWE_N_171, + CE=>RCLK_c_enable_3, CLK=>RCLK_c, F0=>nRWE_N_171, Q0=>nRWE_c, + F1=>n2208); + SLICE_64I: SLICE_64 + port map (C1=>nRowColSel, B1=>MAin_c_9, A1=>RowA_9, D0=>nRowColSel_N_32, + C0=>nRowColSel_N_28, B0=>n1502, A0=>nRowColSel, DI0=>n1410, + LSR=>n2469, CLK=>RCLK_c, F0=>n1410, Q0=>nRowColSel, F1=>RA_1_9); + SLICE_65I: SLICE_65 + port map (D1=>InitReady, C1=>Ready_N_296, B1=>RASr2, A1=>nRowColSel_N_32, + B0=>nRowColSel_N_33, A0=>nRowColSel_N_32, DI0=>n1503, + LSR=>RASr2, CLK=>RCLK_c, F0=>n1503, Q0=>nRowColSel_N_32, + F1=>n2414); + SLICE_66I: SLICE_66 + port map (D1=>nRowColSel_N_33, C1=>nRowColSel_N_34, B1=>n2469, + A1=>nRowColSel_N_32, B0=>RASr2, A0=>nRowColSel_N_32, + DI0=>n1093, LSR=>nRowColSel_N_34, CLK=>RCLK_c, F0=>n1093, + Q0=>nRowColSel_N_33, F1=>RCLK_c_enable_4); + SLICE_67I: SLICE_67 + port map (C1=>n2472, B1=>CmdUFMCS, A1=>nUFMCS_c, B0=>CASr2, + A0=>nRowColSel_N_33, M0=>n1093, LSR=>nRowColSel_N_35, + CLK=>RCLK_c, F0=>n11, Q0=>nRowColSel_N_34, F1=>n1417); + SLICE_68I: SLICE_68 + port map (B1=>FS_12, A1=>FS_17, D0=>FS_3, C0=>FS_6, B0=>FS_1, A0=>FS_0, + M1=>CASr2, M0=>RASr2, CLK=>RCLK_c, F0=>n2322, + Q0=>nRowColSel_N_35, F1=>n2471, Q1=>CASr3); + SLICE_69I: SLICE_69 + port map (D1=>FS_14, C1=>FS_12, B1=>n12, A1=>FS_17, C0=>InitReady, + B0=>n1417, A0=>n62, DI0=>n2164, LSR=>LEDEN_N_82, CLK=>RCLK_c, + F0=>n2164, Q0=>nUFMCS_c, F1=>n62); + RCKEEN_I_0_445_SLICE_70I: RCKEEN_I_0_445_SLICE_70 + port map (C1=>RASr2, B1=>FWEr, A1=>CBR, D0=>nRowColSel_N_34, C0=>FWEr, + B0=>n11, A0=>CBR, M0=>nRowColSel_N_35, OFX0=>RCKEEN_N_122); + i26_SLICE_71I: i26_SLICE_71 + port map (D1=>n2284, C1=>n2476, B1=>MAin_c_1, A1=>MAin_c_0, + D0=>ADSubmitted, C0=>MAin_c_0, B0=>n2475, A0=>Din_c_5, + M0=>Din_c_2, OFX0=>n13_adj_2); + i2099_SLICE_72I: i2099_SLICE_72 + port map (D1=>nRowColSel_N_34, C1=>nRowColSel_N_35, B1=>Ready, + A1=>nRCS_N_139, C0=>nRowColSel_N_35, B0=>Ready, A0=>nRCS_N_139, + M0=>n15_adj_1, OFX0=>n2481); + i26_adj_28_SLICE_73I: i26_adj_28_SLICE_73 + port map (D1=>MAin_c_0, C1=>Din_c_2, B1=>Din_c_3, A1=>Din_c_6, + D0=>MAin_c_0, C0=>Din_c_2, B0=>Din_c_3, A0=>Din_c_6, + M0=>Din_c_5, OFX0=>n15); + SLICE_74I: SLICE_74 + port map (D1=>n1, C1=>nRowColSel_N_33, B1=>CBR, A1=>FWEr, D0=>CASr3, + C0=>CASr2, B0=>FWEr, A0=>CBR, M1=>RASr2, M0=>RASr, CLK=>RCLK_c, + F0=>n1, Q0=>RASr2, F1=>n15_adj_1, Q1=>RASr3); + SLICE_75I: SLICE_75 + port map (C1=>InitReady, B1=>FS_11, A1=>n2214, D0=>FS_11, C0=>n2272, + B0=>n2328, A0=>FS_10, F0=>n2214, F1=>RCLK_c_enable_12); + SLICE_76I: SLICE_76 + port map (D1=>MAin_c_0, C1=>n10, B1=>n1326, A1=>nFWE_c, D0=>n2458, + C0=>Din_c_4, B0=>Din_c_5, A0=>Din_c_3, M1=>n732, M0=>n733, + CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>PHI2_N_120_enable_4, + Q0=>n732, F1=>n2458, Q1=>nRWE_N_177); + SLICE_77I: SLICE_77 + port map (D1=>FS_7, C1=>n2322, B1=>FS_4, A1=>n2290, C0=>FS_9, B0=>FS_5, + A0=>FS_2, M1=>n728, M0=>n729, CE=>RCLK_c_enable_23, + CLK=>RCLK_c, F0=>n2290, Q0=>n728, F1=>n8, Q1=>n727); + SLICE_78I: SLICE_78 + port map (D1=>n2471, C1=>n2272, B1=>FS_14, A1=>FS_16, C0=>InitReady, + B0=>n2464, A0=>FS_11, M1=>MAin_c_7, M0=>MAin_c_6, LSR=>Ready, + CLK=>nCRAS_c, F0=>n1846, Q0=>RowA_6, F1=>n2464, Q1=>RowA_7); + SLICE_79I: SLICE_79 + port map (C1=>Din_c_5, B1=>Din_c_3, A1=>Din_c_6, D0=>n2468, C0=>n1280, + B0=>n2463, A0=>Din_c_2, M1=>PHI2r, M0=>nCCAS_c, CLK=>RCLK_c, + F0=>C1Submitted_N_237, Q0=>CASr, F1=>n2468, Q1=>PHI2r2); + SLICE_80I: SLICE_80 + port map (B1=>nRowColSel_N_33, A1=>nRowColSel_N_34, D0=>nRowColSel_N_35, + C0=>n1502, B0=>nRowColSel_N_32, A0=>Ready, M1=>n726, M0=>n727, + CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>RCLK_c_enable_3, + Q0=>n726, F1=>n1502, Q1=>Ready_N_296); + SLICE_81I: SLICE_81 + port map (B1=>Bank_3, A1=>Bank_6, D0=>Bank_5, C0=>n2278, B0=>n2314, + A0=>Bank_2, M1=>Din_c_2, M0=>Din_c_1, CE=>PHI2_N_120_enable_6, + CLK=>PHI2_c, F0=>n26, Q0=>CmdUFMCLK, F1=>n2278, Q1=>CmdUFMCS); + SLICE_82I: SLICE_82 + port map (D1=>MAin_c_1, C1=>n14, B1=>n2460, A1=>MAin_c_0, B0=>n1326, + A0=>nFWE_c, M1=>n730, M0=>nRWE_N_177, CE=>RCLK_c_enable_23, + CLK=>RCLK_c, F0=>n2460, Q0=>n730, F1=>PHI2_N_120_enable_7, + Q1=>n729); + SLICE_83I: SLICE_83 + port map (D1=>n2476, C1=>n2460, B1=>n10, A1=>MAin_c_0, D0=>MAin_c_1, + C0=>CmdEnable, B0=>n2478, A0=>Din_c_4, M0=>nCRAS_c, + CLK=>RCLK_c, F0=>n10, Q0=>RASr, F1=>PHI2_N_120_enable_6); + SLICE_84I: SLICE_84 + port map (D1=>n1314, C1=>n2262, B1=>CmdEnable, A1=>n2473, C0=>MAin_c_1, + B0=>n1326, A0=>MAin_c_0, M1=>n738, M0=>nRCAS_N_165, + CE=>RCLK_c_enable_23, CLK=>RCLK_c, F0=>n2262, Q0=>n738, + F1=>PHI2_N_120_enable_1, Q1=>n737); + SLICE_85I: SLICE_85 + port map (D1=>n2474, C1=>Din_c_5, B1=>n2253, A1=>n2473, B0=>nFWE_c, + A0=>Din_c_4, M1=>CROW_c_1, M0=>CROW_c_0, LSR=>Ready, + CLK=>nCRAS_c, F0=>n2473, Q0=>RBA_c_0, F1=>n2242, Q1=>RBA_c_1); + SLICE_86I: SLICE_86 + port map (C1=>Din_c_1, B1=>Din_c_0, A1=>Din_c_7, C0=>n2253, B0=>nFWE_c, + A0=>Din_c_4, M1=>n734, M0=>n735, CE=>RCLK_c_enable_23, + CLK=>RCLK_c, F0=>n2463, Q0=>n734, F1=>n2253, Q1=>n733); + SLICE_87I: SLICE_87 + port map (B1=>n2214, A1=>FS_8, D0=>n8, C0=>InitReady, B0=>n2472, A0=>n7, + M1=>nRCS_N_139, M0=>Ready_N_296, CE=>RCLK_c_enable_23, + CLK=>RCLK_c, F0=>RCLK_c_enable_11, Q0=>nRCS_N_139, F1=>n7, + Q1=>nRCAS_N_165); + SLICE_88I: SLICE_88 + port map (C1=>FS_10, B1=>FS_6, A1=>n2451, D0=>FS_8, C0=>FS_5, B0=>FS_9, + A0=>FS_7, M1=>Din_c_1, M0=>Din_c_0, CLK=>PHI2_c, F0=>n2451, + Q0=>Bank_0, F1=>n2461, Q1=>Bank_1); + SLICE_89I: SLICE_89 + port map (C1=>MAin_c_1, B1=>n1326, A1=>nFWE_c, C0=>MAin_c_0, B0=>n1326, + A0=>MAin_c_1, M1=>Din_c_1, M0=>Din_c_0, CLK=>nCCAS_c, + F0=>n1280, Q0=>WRD_0, F1=>n2459, Q1=>WRD_1); + SLICE_90I: SLICE_90 + port map (D1=>FS_16, C1=>FS_14, B1=>FS_12, A1=>FS_17, B0=>FS_14, + A0=>FS_16, M1=>MAin_c_9, M0=>MAin_c_8, LSR=>Ready, + CLK=>nCRAS_c, F0=>n2470, Q0=>RowA_8, F1=>n2328, Q1=>RowA_9); + SLICE_91I: SLICE_91 + port map (B1=>Din_c_5, A1=>Din_c_3, D0=>n2458, C0=>Din_c_5, B0=>Din_c_4, + A0=>Din_c_3, M1=>PHI2_c, M0=>PHI2r2, CLK=>RCLK_c, + F0=>PHI2_N_120_enable_5, Q0=>PHI2r3, F1=>n2476, Q1=>PHI2r); + SLICE_92I: SLICE_92 + port map (B1=>Din_c_3, A1=>Din_c_6, C0=>Din_c_3, B0=>Din_c_2, + A0=>Din_c_6, M1=>Din_c_7, M0=>Din_c_6, CLK=>nCCAS_c, F0=>n2474, + Q0=>WRD_6, F1=>n2475, Q1=>WRD_7); + SLICE_93I: SLICE_93 + port map (B1=>nRowColSel, A1=>MAin_c_9, B0=>nRowColSel, A0=>MAin_c_9, + M0=>Din_c_0, CE=>PHI2_N_120_enable_6, CLK=>PHI2_c, F0=>RDQMH_c, + Q0=>CmdUFMSDI, F1=>RDQML_c); + SLICE_94I: SLICE_94 + port map (B1=>FS_15, A1=>FS_13, D0=>FS_11, C0=>FS_16, B0=>FS_13, + A0=>FS_15, F0=>n12, F1=>n2272); + SLICE_95I: SLICE_95 + port map (B1=>FS_10, A1=>n62, D0=>InitReady, C0=>FS_10, B0=>n2464, + A0=>FS_11, M1=>MAin_c_5, M0=>MAin_c_4, LSR=>Ready, + CLK=>nCRAS_c, F0=>LEDEN_N_82, Q0=>RowA_4, F1=>RCLK_c_enable_25, + Q1=>RowA_5); + SLICE_96I: SLICE_96 + port map (C1=>nRowColSel, B1=>MAin_c_3, A1=>RowA_3, D0=>Bank_1, + C0=>Bank_4, B0=>MAin_c_3, A0=>MAin_c_7, M1=>MAin_c_3, + M0=>MAin_c_2, LSR=>Ready, CLK=>nCRAS_c, F0=>n2316, Q0=>RowA_2, + F1=>RA_1_3, Q1=>RowA_3); + SLICE_97I: SLICE_97 + port map (C1=>nRowColSel, B1=>MAin_c_4, A1=>RowA_4, D0=>Bank_0, + C0=>Bank_7, B0=>MAin_c_4, A0=>MAin_c_6, M1=>MAin_c_1, + M0=>MAin_c_0, LSR=>Ready, CLK=>nCRAS_c, F0=>n2314, Q0=>RowA_0, + F1=>RA_1_4, Q1=>RowA_1); + SLICE_98I: SLICE_98 + port map (C1=>nRowColSel, B1=>MAin_c_0, A1=>RowA_0, C0=>nRowColSel, + B0=>MAin_c_8, A0=>RowA_8, M1=>nFWE_c, M0=>nCCAS_c, + CLK=>nCRAS_c, F0=>RA_1_8, Q0=>CBR, F1=>RA_1_0, Q1=>FWEr); + SLICE_99I: SLICE_99 + port map (C1=>nRowColSel, B1=>MAin_c_1, A1=>RowA_1, C0=>nRowColSel, + B0=>MAin_c_7, A0=>RowA_7, M1=>Din_c_7, M0=>Din_c_6, + CLK=>PHI2_c, F0=>RA_1_7, Q0=>Bank_6, F1=>RA_1_1, Q1=>Bank_7); + SLICE_100I: SLICE_100 + port map (D1=>Ready, C1=>nRowColSel_N_33, B1=>InitReady, A1=>RASr2, + D0=>InitReady, C0=>PHI2r2, B0=>CmdSubmitted, A0=>PHI2r3, + M1=>n736, M0=>n737, CE=>RCLK_c_enable_23, CLK=>RCLK_c, + F0=>RCLK_c_enable_24, Q0=>n736, F1=>n6, Q1=>n735); + SLICE_101I: SLICE_101 + port map (C1=>nRowColSel, B1=>MAin_c_2, A1=>RowA_2, C0=>nRowColSel, + B0=>MAin_c_6, A0=>RowA_6, M1=>Din_c_5, M0=>Din_c_4, + CLK=>PHI2_c, F0=>RA_1_6, Q0=>Bank_4, F1=>RA_1_2, Q1=>Bank_5); + SLICE_102I: SLICE_102 + port map (B1=>nRWE_N_177, A1=>nRCAS_N_165, C0=>nRCAS_N_165, + B0=>nRCS_N_139, A0=>InitReady, M1=>Din_c_3, M0=>Din_c_2, + CLK=>PHI2_c, F0=>n2427, Q0=>Bank_2, F1=>n33, Q1=>Bank_3); + SLICE_103I: SLICE_103 + port map (C1=>nRowColSel, B1=>MAin_c_5, A1=>RowA_5, C0=>CBR, B0=>CASr3, + A0=>FWEr, M1=>Din_c_3, M0=>Din_c_2, CLK=>nCCAS_c, + F0=>nRowColSel_N_28, Q0=>WRD_2, F1=>RA_1_5, Q1=>WRD_3); + SLICE_104I: SLICE_104 + port map (B1=>Ready, A1=>n2414, D0=>nRowColSel_N_35, C0=>nRWE_N_182, + B0=>n1502, A0=>n1, F0=>nRWE_N_178, F1=>Ready_N_292); + SLICE_105I: SLICE_105 + port map (B1=>nFWE_c, A1=>nCCAS_c, C0=>n13_adj_2, B0=>Din_c_4, A0=>n2253, + M1=>Din_c_5, M0=>Din_c_4, CLK=>nCCAS_c, F0=>n14, Q0=>WRD_4, + F1=>n984, Q1=>WRD_5); + RD_7_I: RD_7_B + port map (PADDI=>Dout_c, PADDT=>n984, PADDO=>WRD_7, RD7=>RD(7)); + RD_6_I: RD_6_B + port map (PADDI=>Dout_0S, PADDT=>n984, PADDO=>WRD_6, RD6=>RD(6)); + RD_5_I: RD_5_B + port map (PADDI=>Dout_1S, PADDT=>n984, PADDO=>WRD_5, RD5=>RD(5)); + RD_4_I: RD_4_B + port map (PADDI=>Dout_2S, PADDT=>n984, PADDO=>WRD_4, RD4=>RD(4)); + RD_3_I: RD_3_B + port map (PADDI=>Dout_3S, PADDT=>n984, PADDO=>WRD_3, RD3=>RD(3)); + RD_2_I: RD_2_B + port map (PADDI=>Dout_4S, PADDT=>n984, PADDO=>WRD_2, RD2=>RD(2)); + RD_1_I: RD_1_B + port map (PADDI=>Dout_5S, PADDT=>n984, PADDO=>WRD_1, RD1=>RD(1)); + RD_0_I: RD_0_B + port map (PADDI=>Dout_6S, PADDT=>n984, PADDO=>WRD_0, RD0=>RD(0)); + Dout_7_I: Dout_7_B + port map (PADDO=>Dout_c, Dout7=>Dout(7)); + Dout_6_I: Dout_6_B + port map (PADDO=>Dout_0S, Dout6=>Dout(6)); + Dout_5_I: Dout_5_B + port map (PADDO=>Dout_1S, Dout5=>Dout(5)); + Dout_4_I: Dout_4_B + port map (PADDO=>Dout_2S, Dout4=>Dout(4)); + Dout_3_I: Dout_3_B + port map (PADDO=>Dout_3S, Dout3=>Dout(3)); + Dout_2_I: Dout_2_B + port map (PADDO=>Dout_4S, Dout2=>Dout(2)); + Dout_1_I: Dout_1_B + port map (PADDO=>Dout_5S, Dout1=>Dout(1)); + Dout_0_I: Dout_0_B + port map (PADDO=>Dout_6S, Dout0=>Dout(0)); + LEDI: LEDB + port map (PADDO=>LED_N_84, LEDS=>LED); + RBA_1_I: RBA_1_B + port map (PADDO=>RBA_c_1, RBA1=>RBA(1)); + RBA_0_I: RBA_0_B + port map (PADDO=>RBA_c_0, RBA0=>RBA(0)); + RA_11_I: RA_11_B + port map (PADDO=>RA_c, RA11=>RA(11)); + RA_10_I: RA_10_B + port map (PADDO=>RA_0S, RA10=>RA(10)); + RA_9_I: RA_9_B + port map (PADDO=>RA_1_9, RA9=>RA(9)); + RA_8_I: RA_8_B + port map (PADDO=>RA_1_8, RA8=>RA(8)); + RA_7_I: RA_7_B + port map (PADDO=>RA_1_7, RA7=>RA(7)); + RA_6_I: RA_6_B + port map (PADDO=>RA_1_6, RA6=>RA(6)); + RA_5_I: RA_5_B + port map (PADDO=>RA_1_5, RA5=>RA(5)); + RA_4_I: RA_4_B + port map (PADDO=>RA_1_4, RA4=>RA(4)); + RA_3_I: RA_3_B + port map (PADDO=>RA_1_3, RA3=>RA(3)); + RA_2_I: RA_2_B + port map (PADDO=>RA_1_2, RA2=>RA(2)); + RA_1_I: RA_1_B + port map (PADDO=>RA_1_1, RA1=>RA(1)); + RA_0_I: RA_0_B + port map (PADDO=>RA_1_0, RA0=>RA(0)); + nRCSI: nRCSB + port map (PADDO=>nRCS_c, nRCSS=>nRCS); + RCKEI: RCKEB + port map (PADDO=>RCKE_c, RCKES=>RCKE); + nRWEI: nRWEB + port map (PADDO=>nRWE_c, nRWES=>nRWE); + nRRASI: nRRASB + port map (PADDO=>nRRAS_c, nRRASS=>nRRAS); + nRCASI: nRCASB + port map (PADDO=>nRCAS_c, nRCASS=>nRCAS); + RDQMHI: RDQMHB + port map (PADDO=>RDQMH_c, RDQMHS=>RDQMH); + RDQMLI: RDQMLB + port map (PADDO=>RDQML_c, RDQMLS=>RDQML); + nUFMCSI: nUFMCSB + port map (PADDO=>nUFMCS_c, nUFMCSS=>nUFMCS); + UFMCLKI: UFMCLKB + port map (PADDO=>UFMCLK_c, UFMCLKS=>UFMCLK); + UFMSDII: UFMSDIB + port map (PADDO=>UFMSDI_c, UFMSDIS=>UFMSDI); + PHI2I: PHI2B + port map (PADDI=>PHI2_c, PHI2S=>PHI2); + MAin_9_I: MAin_9_B + port map (PADDI=>MAin_c_9, MAin9=>MAin(9)); + MAin_8_I: MAin_8_B + port map (PADDI=>MAin_c_8, MAin8=>MAin(8)); + MAin_7_I: MAin_7_B + port map (PADDI=>MAin_c_7, MAin7=>MAin(7)); + MAin_6_I: MAin_6_B + port map (PADDI=>MAin_c_6, MAin6=>MAin(6)); + MAin_5_I: MAin_5_B + port map (PADDI=>MAin_c_5, MAin5=>MAin(5)); + MAin_4_I: MAin_4_B + port map (PADDI=>MAin_c_4, MAin4=>MAin(4)); + MAin_3_I: MAin_3_B + port map (PADDI=>MAin_c_3, MAin3=>MAin(3)); + MAin_2_I: MAin_2_B + port map (PADDI=>MAin_c_2, MAin2=>MAin(2)); + MAin_1_I: MAin_1_B + port map (PADDI=>MAin_c_1, MAin1=>MAin(1)); + MAin_0_I: MAin_0_B + port map (PADDI=>MAin_c_0, MAin0=>MAin(0)); + CROW_1_I: CROW_1_B + port map (PADDI=>CROW_c_1, CROW1=>CROW(1)); + CROW_0_I: CROW_0_B + port map (PADDI=>CROW_c_0, CROW0=>CROW(0)); + Din_7_I: Din_7_B + port map (PADDI=>Din_c_7, Din7=>Din(7)); + Din_6_I: Din_6_B + port map (PADDI=>Din_c_6, Din6=>Din(6)); + Din_5_I: Din_5_B + port map (PADDI=>Din_c_5, Din5=>Din(5)); + Din_4_I: Din_4_B + port map (PADDI=>Din_c_4, Din4=>Din(4)); + Din_3_I: Din_3_B + port map (PADDI=>Din_c_3, Din3=>Din(3)); + Din_2_I: Din_2_B + port map (PADDI=>Din_c_2, Din2=>Din(2)); + Din_1_I: Din_1_B + port map (PADDI=>Din_c_1, Din1=>Din(1)); + Din_0_I: Din_0_B + port map (PADDI=>Din_c_0, Din0=>Din(0)); + nCCASI: nCCASB + port map (PADDI=>nCCAS_c, nCCASS=>nCCAS); + nCRASI: nCRASB + port map (PADDI=>nCRAS_c, nCRASS=>nCRAS); + nFWEI: nFWEB + port map (PADDI=>nFWE_c, nFWES=>nFWE); + RCLKI: RCLKB + port map (PADDI=>RCLK_c, RCLKS=>RCLK); + UFMSDOI: UFMSDOB + port map (PADDI=>UFMSDO_c, UFMSDOS=>UFMSDO); + VHI_INST: VHI + port map (Z=>VCCI); + PUR_INST: PUR + port map (PUR=>VCCI); + GSR_INST: GSR + port map (GSR=>VCCI); + VLO_INST: VLO + port map (Z=>GNDI_TSALL); + TSALL_INST: TSALL + port map (TSALL=>GNDI_TSALL); + end Structure; + + + + library IEEE, vital2000, MACHXO; + configuration Structure_CON of RAM2GS is + for Structure + end for; + end Structure_CON; + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.sdf b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.sdf new file mode 100644 index 0000000..bf5db84 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.sdf @@ -0,0 +1,3036 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2GS") + (DATE "Tue Aug 15 05:03:24 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7) + (DELAY + (ABSOLUTE + (IOPATH A1 FCO (619:692:766)(619:692:766)) + (IOPATH A0 FCO (713:797:882)(713:797:882)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + (IOPATH FCI FCO (115:128:141)(115:128:141)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8) + (DELAY + (ABSOLUTE + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD A1 (posedge CLK) (417:466:515)(-161:-170:-179)) + (SETUPHOLD A0 (posedge CLK) (693:775:857)(-167:-176:-185)) + (SETUPHOLD FCI (posedge CLK) (542:606:671)(-378:-400:-423)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_14") + (INSTANCE SLICE_14) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_18") + (INSTANCE SLICE_18) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_19") + (INSTANCE SLICE_19) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_23") + (INSTANCE SLICE_23) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_25") + (INSTANCE SLICE_25) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_26") + (INSTANCE SLICE_26) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_31") + (INSTANCE SLICE_31) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_32") + (INSTANCE SLICE_32) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_34") + (INSTANCE SLICE_34) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_35") + (INSTANCE SLICE_35) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_36") + (INSTANCE SLICE_36) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_43") + (INSTANCE SLICE_43) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_44") + (INSTANCE SLICE_44) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_49") + (INSTANCE SLICE_49) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (negedge CLK) (174:174:174)(-78:-78:-78)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_56") + (INSTANCE SLICE_56) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_58") + (INSTANCE SLICE_58) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_60") + (INSTANCE SLICE_60) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_61") + (INSTANCE SLICE_61) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_63") + (INSTANCE SLICE_63) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_64") + (INSTANCE SLICE_64) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_65") + (INSTANCE SLICE_65) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_66") + (INSTANCE SLICE_66) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_67") + (INSTANCE SLICE_67) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_68") + (INSTANCE SLICE_68) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_69") + (INSTANCE SLICE_69) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (181:181:181)(-35:-35:-35)) + (SETUPHOLD LSR (posedge CLK) (505:565:626)(-211:-223:-235)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "RCKEEN_I_0_445_SLICE_70") + (INSTANCE RCKEEN_I_0_445\/SLICE_70) + (DELAY + (ABSOLUTE + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i26_SLICE_71") + (INSTANCE i26\/SLICE_71) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i2099_SLICE_72") + (INSTANCE i2099\/SLICE_72) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "i26_adj_28_SLICE_73") + (INSTANCE i26_adj_28\/SLICE_73) + (DELAY + (ABSOLUTE + (IOPATH D1 OFX0 (496:555:615)(496:555:615)) + (IOPATH C1 OFX0 (496:555:615)(496:555:615)) + (IOPATH B1 OFX0 (496:555:615)(496:555:615)) + (IOPATH A1 OFX0 (496:555:615)(496:555:615)) + (IOPATH D0 OFX0 (508:569:631)(508:569:631)) + (IOPATH C0 OFX0 (508:569:631)(508:569:631)) + (IOPATH B0 OFX0 (508:569:631)(508:569:631)) + (IOPATH A0 OFX0 (508:569:631)(508:569:631)) + (IOPATH M0 OFX0 (405:453:501)(405:453:501)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_74") + (INSTANCE SLICE_74) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_75") + (INSTANCE SLICE_75) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_76") + (INSTANCE SLICE_76) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_77") + (INSTANCE SLICE_77) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_78") + (INSTANCE SLICE_78) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_79") + (INSTANCE SLICE_79) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_80") + (INSTANCE SLICE_80) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_81") + (INSTANCE SLICE_81) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_82") + (INSTANCE SLICE_82) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_83") + (INSTANCE SLICE_83) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_84") + (INSTANCE SLICE_84) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_85") + (INSTANCE SLICE_85) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_86") + (INSTANCE SLICE_86) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_87") + (INSTANCE SLICE_87) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_88") + (INSTANCE SLICE_88) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_89") + (INSTANCE SLICE_89) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_90") + (INSTANCE SLICE_90) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_91") + (INSTANCE SLICE_91) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_92") + (INSTANCE SLICE_92) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_93") + (INSTANCE SLICE_93) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD CE (negedge CLK) (213:239:265)(-85:-90:-95)) + ) + ) + (CELL + (CELLTYPE "SLICE_94") + (INSTANCE SLICE_94) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_95") + (INSTANCE SLICE_95) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_96") + (INSTANCE SLICE_96) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_97") + (INSTANCE SLICE_97) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD LSR (negedge CLK) (515:576:638)(-218:-231:-244)) + ) + ) + (CELL + (CELLTYPE "SLICE_98") + (INSTANCE SLICE_98) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_99") + (INSTANCE SLICE_99) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_100") + (INSTANCE SLICE_100) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (301:336:371)(301:336:371)) + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD CE (posedge CLK) (197:220:244)(-71:-76:-81)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_101") + (INSTANCE SLICE_101) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_102") + (INSTANCE SLICE_102) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (515:537:560)(515:537:560)) + (IOPATH CLK Q1 (515:537:560)(515:537:560)) + ) + ) + (TIMINGCHECK + (SETUPHOLD M1 (posedge CLK) (146:162:179)(-60:-64:-69)) + (SETUPHOLD M0 (posedge CLK) (146:162:179)(-60:-64:-69)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + ) + (CELL + (CELLTYPE "SLICE_103") + (INSTANCE SLICE_103) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (301:336:371)(301:336:371)) + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "SLICE_104") + (INSTANCE SLICE_104) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH D0 F0 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + ) + ) + ) + (CELL + (CELLTYPE "SLICE_105") + (INSTANCE SLICE_105) + (DELAY + (ABSOLUTE + (IOPATH B1 F1 (301:336:371)(301:336:371)) + (IOPATH A1 F1 (301:336:371)(301:336:371)) + (IOPATH C0 F0 (301:336:371)(301:336:371)) + (IOPATH B0 F0 (301:336:371)(301:336:371)) + (IOPATH A0 F0 (301:336:371)(301:336:371)) + (IOPATH CLK Q0 (560:586:613)(560:586:613)) + (IOPATH CLK Q1 (560:586:613)(560:586:613)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1000:1000:1000)) + (WIDTH (negedge CLK) (1000:1000:1000)) + ) + (TIMINGCHECK + (SETUPHOLD M1 (negedge CLK) (99:111:123)(-24:-24:-25)) + (SETUPHOLD M0 (negedge CLK) (99:111:123)(-24:-24:-25)) + ) + ) + (CELL + (CELLTYPE "RD_7_") + (INSTANCE RD\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD7 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD7 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD7) (1250:1250:1250)) + (WIDTH (negedge RD7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_6_") + (INSTANCE RD\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD6 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD6 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD6) (1250:1250:1250)) + (WIDTH (negedge RD6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_5_") + (INSTANCE RD\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD5 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD5 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD5) (1250:1250:1250)) + (WIDTH (negedge RD5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_4_") + (INSTANCE RD\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD4 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD4 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD4) (1250:1250:1250)) + (WIDTH (negedge RD4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_3_") + (INSTANCE RD\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD3 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD3 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD3) (1250:1250:1250)) + (WIDTH (negedge RD3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_2_") + (INSTANCE RD\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD2 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD2 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD2) (1250:1250:1250)) + (WIDTH (negedge RD2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_1_") + (INSTANCE RD\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD1 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD1 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD1) (1250:1250:1250)) + (WIDTH (negedge RD1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RD_0_") + (INSTANCE RD\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDT RD0 (2347:2347:2347)(2347:2347:2347)(2347:2347:2347)(2347:2347:2347) + (2347:2347:2347)(2347:2347:2347)) + (IOPATH PADDO RD0 (1882:1882:1882)(1882:1882:1882)) + (IOPATH RD0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RD0) (1250:1250:1250)) + (WIDTH (negedge RD0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Dout_7_") + (INSTANCE Dout\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout7 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_6_") + (INSTANCE Dout\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout6 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_5_") + (INSTANCE Dout\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout5 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_4_") + (INSTANCE Dout\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout4 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_3_") + (INSTANCE Dout\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout3 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_2_") + (INSTANCE Dout\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout2 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1_") + (INSTANCE Dout\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0_") + (INSTANCE Dout\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO Dout0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "LED") + (INSTANCE LED_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO LED (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_1_") + (INSTANCE RBA\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RBA_0_") + (INSTANCE RBA\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RBA0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_11_") + (INSTANCE RA\[11\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA11 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_10_") + (INSTANCE RA\[10\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA10 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_9_") + (INSTANCE RA\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA9 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_8_") + (INSTANCE RA\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA8 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_7_") + (INSTANCE RA\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA7 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_6_") + (INSTANCE RA\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA6 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_5_") + (INSTANCE RA\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA5 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_4_") + (INSTANCE RA\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA4 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_3_") + (INSTANCE RA\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA3 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_2_") + (INSTANCE RA\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA2 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_1_") + (INSTANCE RA\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA1 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RA_0_") + (INSTANCE RA\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RA0 (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRCS") + (INSTANCE nRCS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RCKE") + (INSTANCE RCKE_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RCKE (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRWE") + (INSTANCE nRWE_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRWE (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRRAS") + (INSTANCE nRRAS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRRAS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nRCAS") + (INSTANCE nRCAS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nRCAS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RDQMH") + (INSTANCE RDQMH_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQMH (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "RDQML") + (INSTANCE RDQML_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO RDQML (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "nUFMCS") + (INSTANCE nUFMCS_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO nUFMCS (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "UFMCLK") + (INSTANCE UFMCLK_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMCLK (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "UFMSDI") + (INSTANCE UFMSDI_I) + (DELAY + (ABSOLUTE + (IOPATH PADDO UFMSDI (1882:1882:1882)(1882:1882:1882)) + ) + ) + ) + (CELL + (CELLTYPE "PHI2") + (INSTANCE PHI2_I) + (DELAY + (ABSOLUTE + (IOPATH PHI2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI2) (1250:1250:1250)) + (WIDTH (negedge PHI2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_9_") + (INSTANCE MAin\[9\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin9 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin9) (1250:1250:1250)) + (WIDTH (negedge MAin9) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_8_") + (INSTANCE MAin\[8\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin8 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin8) (1250:1250:1250)) + (WIDTH (negedge MAin8) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_7_") + (INSTANCE MAin\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin7) (1250:1250:1250)) + (WIDTH (negedge MAin7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_6_") + (INSTANCE MAin\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin6) (1250:1250:1250)) + (WIDTH (negedge MAin6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_5_") + (INSTANCE MAin\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin5) (1250:1250:1250)) + (WIDTH (negedge MAin5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_4_") + (INSTANCE MAin\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin4) (1250:1250:1250)) + (WIDTH (negedge MAin4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_3_") + (INSTANCE MAin\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin3) (1250:1250:1250)) + (WIDTH (negedge MAin3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_2_") + (INSTANCE MAin\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin2) (1250:1250:1250)) + (WIDTH (negedge MAin2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_1_") + (INSTANCE MAin\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin1) (1250:1250:1250)) + (WIDTH (negedge MAin1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "MAin_0_") + (INSTANCE MAin\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH MAin0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge MAin0) (1250:1250:1250)) + (WIDTH (negedge MAin0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "CROW_1_") + (INSTANCE CROW\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW1) (1250:1250:1250)) + (WIDTH (negedge CROW1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "CROW_0_") + (INSTANCE CROW\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH CROW0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CROW0) (1250:1250:1250)) + (WIDTH (negedge CROW0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_7_") + (INSTANCE Din\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (1250:1250:1250)) + (WIDTH (negedge Din7) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_6_") + (INSTANCE Din\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (1250:1250:1250)) + (WIDTH (negedge Din6) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_5_") + (INSTANCE Din\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (1250:1250:1250)) + (WIDTH (negedge Din5) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_4_") + (INSTANCE Din\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (1250:1250:1250)) + (WIDTH (negedge Din4) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_3_") + (INSTANCE Din\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (1250:1250:1250)) + (WIDTH (negedge Din3) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_2_") + (INSTANCE Din\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (1250:1250:1250)) + (WIDTH (negedge Din2) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_1_") + (INSTANCE Din\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (1250:1250:1250)) + (WIDTH (negedge Din1) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "Din_0_") + (INSTANCE Din\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (1250:1250:1250)) + (WIDTH (negedge Din0) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nCCAS") + (INSTANCE nCCAS_I) + (DELAY + (ABSOLUTE + (IOPATH nCCAS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCCAS) (1250:1250:1250)) + (WIDTH (negedge nCCAS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nCRAS") + (INSTANCE nCRAS_I) + (DELAY + (ABSOLUTE + (IOPATH nCRAS PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nCRAS) (1250:1250:1250)) + (WIDTH (negedge nCRAS) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "nFWE") + (INSTANCE nFWE_I) + (DELAY + (ABSOLUTE + (IOPATH nFWE PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nFWE) (1250:1250:1250)) + (WIDTH (negedge nFWE) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RCLK") + (INSTANCE RCLK_I) + (DELAY + (ABSOLUTE + (IOPATH RCLK PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge RCLK) (1250:1250:1250)) + (WIDTH (negedge RCLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "UFMSDO") + (INSTANCE UFMSDO_I) + (DELAY + (ABSOLUTE + (IOPATH UFMSDO PADDI (867:965:1063)(867:965:1063)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge UFMSDO) (1250:1250:1250)) + (WIDTH (negedge UFMSDO) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "RAM2GS") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_77/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_88/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_0/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_68/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q0 SLICE_88/B1 (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_25/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_31/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_34/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_35/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_56/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_58/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_60/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_61/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_63/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_64/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_65/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_66/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_67/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_68/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_69/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_74/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_76/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_77/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_79/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_80/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_82/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_83/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_84/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_86/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_87/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_91/CLK (0:0:0)(0:0:0)) + (INTERCONNECT RCLK_I/PADDI SLICE_100/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/FCO SLICE_0/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/FCO SLICE_7/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_1/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_94/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q1 SLICE_94/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_69/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_78/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_90/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_90/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/FCO SLICE_1/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/FCO SLICE_8/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_77/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_88/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_43/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q0 SLICE_77/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/FCO SLICE_2/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_94/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_94/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_68/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_69/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q0 SLICE_90/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/FCO SLICE_3/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_43/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_68/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q0 SLICE_68/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/FCO SLICE_6/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_44/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_56/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_75/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_75/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_78/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_94/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_95/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_56/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_75/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_88/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_95/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q0 SLICE_95/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/FCO SLICE_5/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_68/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q0 SLICE_77/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q1 SLICE_77/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q1 SLICE_88/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_87/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_7/Q0 SLICE_88/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_8/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_68/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_69/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q1 SLICE_90/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_8/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_78/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_90/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_90/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_8/Q0 SLICE_94/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_9/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_14/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_18/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI i26\/SLICE_71/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_82/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_83/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_84/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_89/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_89/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_97/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[1\]_I/PADDI SLICE_99/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_9/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_14/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_18/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_76/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_82/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_84/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_89/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F1 SLICE_89/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_9/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI i26\/SLICE_71/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI i26\/SLICE_71/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI i26_adj_28\/SLICE_73/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI i26_adj_28\/SLICE_73/D0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_76/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_82/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_83/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_84/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_89/C0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_97/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[0\]_I/PADDI SLICE_98/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F1 SLICE_9/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 SLICE_9/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/Q0 i26\/SLICE_71/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F1 SLICE_9/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F1 SLICE_9/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F0 SLICE_9/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F0 SLICE_14/LSR (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_14/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_18/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_23/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_49/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_81/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_88/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_91/M1 (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_93/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_99/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_101/CLK (0:0:0)(0:0:0)) + (INTERCONNECT PHI2_I/PADDI SLICE_102/CLK (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_14/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_23/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_32/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_32/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI i26_adj_28\/SLICE_73/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI i26_adj_28\/SLICE_73/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_79/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_92/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_92/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_92/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[6\]_I/PADDI SLICE_99/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14/Q0 SLICE_14/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14/Q0 SLICE_14/C0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_14/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_76/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_82/A0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_85/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_86/B0 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_89/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_98/M1 (0:0:0)(0:0:0)) + (INTERCONNECT nFWE_I/PADDI SLICE_105/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_14/F1 i26\/SLICE_71/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_18/D1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_95/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[5\]_I/PADDI SLICE_103/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F0 SLICE_18/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_18/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_18/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_96/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[2\]_I/PADDI SLICE_101/B1 (0:0:0)(0:0:0)) + (INTERCONNECT i26_adj_28\/SLICE_73/OFX0 SLICE_18/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F0 SLICE_18/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F0 SLICE_79/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/F0 SLICE_18/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F1 SLICE_18/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/Q0 SLICE_83/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_18/Q0 SLICE_84/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_19/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_91/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q1 SLICE_100/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_19/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/Q0 SLICE_100/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q0 SLICE_19/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q0 SLICE_100/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F0 SLICE_19/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F0 SLICE_19/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F1 SLICE_67/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_19/F1 SLICE_87/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_23/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI i26\/SLICE_71/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI i26_adj_28\/SLICE_73/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_76/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_79/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_85/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_91/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_91/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_101/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[5\]_I/PADDI SLICE_105/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_23/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_32/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_86/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_92/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[7\]_I/PADDI SLICE_99/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F1 SLICE_23/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F1 SLICE_49/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F1 SLICE_84/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_23/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_49/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_76/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_83/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_85/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_86/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_91/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_101/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_105/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[4\]_I/PADDI SLICE_105/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/Q0 SLICE_23/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/Q0 SLICE_32/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_23/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_49/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_86/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_88/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_89/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[0\]_I/PADDI SLICE_93/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/F0 SLICE_23/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F0 SLICE_23/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_23/Q0 SLICE_56/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_25/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_36/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_58/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_60/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_61/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_63/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_67/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 RCKEEN_I_0_445\/SLICE_70/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 i2099\/SLICE_72/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 i2099\/SLICE_72/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_80/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q0 SLICE_104/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_25/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_34/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_35/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_35/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_58/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_60/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_63/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_65/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_65/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_66/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_68/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 RCKEEN_I_0_445\/SLICE_70/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_74/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q0 SLICE_100/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_25/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_34/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_34/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_43/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_44/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_56/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_60/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_63/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_65/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_69/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_75/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_78/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_87/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_95/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_100/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_100/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/Q0 SLICE_102/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_25/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_31/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_31/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_32/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_34/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_34/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_36/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_58/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_58/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_60/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_61/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_63/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 i2099\/SLICE_72/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 i2099\/SLICE_72/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_78/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_80/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_85/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_90/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_95/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_96/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_97/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_100/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/Q0 SLICE_104/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F1 SLICE_25/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_76/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_77/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_80/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_82/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_84/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_86/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_87/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_25/F1 SLICE_100/CE (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_26/C1 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_78/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_83/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_85/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_90/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_95/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_96/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_97/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCRAS_I/PADDI SLICE_98/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_26/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_58/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 RCKEEN_I_0_445\/SLICE_70/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 RCKEEN_I_0_445\/SLICE_70/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_74/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_74/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q0 SLICE_103/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_26/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/Q0 SLICE_49/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F1 SLICE_26/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_26/F1 LED_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_31/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_58/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_66/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_66/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 RCKEEN_I_0_445\/SLICE_70/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 i2099\/SLICE_72/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/Q0 SLICE_80/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 SLICE_31/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 SLICE_84/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 SLICE_102/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q1 SLICE_102/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F1 SLICE_31/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F1 SLICE_63/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_31/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_82/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q1 SLICE_102/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31/Q0 RA\[10\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_31/F1 SLICE_61/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49/Q0 SLICE_32/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/Q0 RA\[11\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_32/F1 SLICE_83/B0 (0:0:0)(0:0:0)) + (INTERCONNECT RCKEEN_I_0_445\/SLICE_70/OFX0 SLICE_34/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34/F0 SLICE_34/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 SLICE_34/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 SLICE_58/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F1 SLICE_60/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34/Q0 SLICE_35/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_34/F1 SLICE_60/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q0 SLICE_35/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q0 SLICE_60/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q0 RCKE_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/Q1 SLICE_35/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/Q0 SLICE_35/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/Q0 SLICE_74/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F0 SLICE_35/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/Q0 SLICE_35/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/F1 SLICE_104/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q1 SLICE_67/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q1 SLICE_68/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_35/Q1 SLICE_74/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/F0 SLICE_36/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F1 SLICE_36/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/F1 SLICE_64/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_36/F1 SLICE_66/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F1 SLICE_43/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F1 SLICE_44/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_43/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_69/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 SLICE_95/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/F1 SLICE_43/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q0 SLICE_43/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/F0 SLICE_43/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 SLICE_43/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F0 SLICE_44/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F0 SLICE_43/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F0 SLICE_44/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_43/Q0 UFMCLK_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F0 SLICE_44/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_44/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_75/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_78/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F1 SLICE_44/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F1 SLICE_78/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/Q0 SLICE_44/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F1 SLICE_44/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/F0 SLICE_44/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_44/Q0 UFMSDI_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_49/D1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_81/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_86/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_88/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[1\]_I/PADDI SLICE_89/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49/F1 SLICE_49/D0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_49/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI i26\/SLICE_71/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI i26_adj_28\/SLICE_73/C1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI i26_adj_28\/SLICE_73/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_79/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_81/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_92/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_102/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[2\]_I/PADDI SLICE_103/M0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_49/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI i26_adj_28\/SLICE_73/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI i26_adj_28\/SLICE_73/B0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_76/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_79/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_91/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_91/A0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_92/B1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_92/C0 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_102/M1 (0:0:0)(0:0:0)) + (INTERCONNECT Din\[3\]_I/PADDI SLICE_103/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_49/F0 SLICE_49/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F1 SLICE_49/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_56/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_78/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_95/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F1 SLICE_56/D0 (0:0:0)(0:0:0)) + (INTERCONNECT UFMSDO_I/PADDI SLICE_56/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F0 SLICE_56/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F0 SLICE_56/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F0 SLICE_58/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 SLICE_58/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F1 i2099\/SLICE_72/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58/OFX0 SLICE_58/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58/Q0 nRCAS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/F1 SLICE_60/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/F1 SLICE_61/B1 (0:0:0)(0:0:0)) + (INTERCONNECT i2099\/SLICE_72/OFX0 SLICE_60/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/F0 SLICE_60/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/Q0 nRCS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 SLICE_61/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 SLICE_63/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 i2099\/SLICE_72/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 i2099\/SLICE_72/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 SLICE_87/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/Q0 SLICE_102/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_61/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_64/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_65/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_65/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_66/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_66/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/Q0 SLICE_80/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/F1 SLICE_61/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/Q0 SLICE_61/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/Q0 nRRAS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/OFX0 SLICE_61/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_104/F0 SLICE_63/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F1 SLICE_63/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F0 SLICE_63/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F0 SLICE_63/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/Q0 nRWE_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_64/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_64/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_93/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_93/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_96/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_97/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_98/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_98/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_99/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_99/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_101/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_101/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/Q0 SLICE_103/C1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_64/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_90/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_93/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[9\]_I/PADDI SLICE_93/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q1 SLICE_64/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F0 SLICE_64/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_64/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_80/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F1 SLICE_104/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F0 SLICE_64/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F1 RA\[9\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/Q1 SLICE_65/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/Q1 SLICE_87/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_65/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_66/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_67/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_74/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_80/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/Q0 SLICE_100/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F0 SLICE_65/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_104/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F0 SLICE_66/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F0 SLICE_67/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/Q1 SLICE_67/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 SLICE_67/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/Q0 nUFMCS_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F0 RCKEEN_I_0_445\/SLICE_70/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_67/F1 SLICE_69/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/F0 SLICE_77/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q1 SLICE_74/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_68/Q1 SLICE_103/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F0 SLICE_69/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F0 SLICE_69/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F0 SLICE_69/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 RCKEEN_I_0_445\/SLICE_70/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 RCKEEN_I_0_445\/SLICE_70/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_74/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_74/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/Q1 SLICE_103/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F1 i26\/SLICE_71/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F1 SLICE_83/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 i26\/SLICE_71/B0 (0:0:0)(0:0:0)) + (INTERCONNECT i26\/SLICE_71/OFX0 SLICE_105/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F0 SLICE_74/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_74/F0 SLICE_104/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_75/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_87/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F1 SLICE_75/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F0 SLICE_76/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F0 SLICE_83/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_76/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F1 SLICE_91/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/Q0 SLICE_76/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/Q1 SLICE_76/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F0 SLICE_77/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/Q0 SLICE_77/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q1 SLICE_77/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/F1 SLICE_87/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_77/Q1 SLICE_80/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_78/M1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_96/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[7\]_I/PADDI SLICE_99/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_78/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_97/A0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[6\]_I/PADDI SLICE_101/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/Q0 SLICE_101/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/Q1 SLICE_99/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_79/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F0 SLICE_79/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/Q1 SLICE_79/M1 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_79/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_89/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_92/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_98/M0 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_103/CLK (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_105/A1 (0:0:0)(0:0:0)) + (INTERCONNECT nCCAS_I/PADDI SLICE_105/CLK (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/Q0 SLICE_80/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/Q1 SLICE_81/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/Q0 SLICE_81/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/Q1 SLICE_81/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F1 SLICE_81/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F0 SLICE_81/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/Q0 SLICE_81/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F1 SLICE_81/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F1 SLICE_93/CE (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F0 SLICE_82/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F0 SLICE_82/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F0 SLICE_83/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/Q0 SLICE_82/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F0 SLICE_84/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_84/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F0 SLICE_85/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q0 SLICE_84/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/Q1 SLICE_100/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F0 SLICE_85/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_85/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_86/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/F1 SLICE_105/A0 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[1\]_I/PADDI SLICE_85/M1 (0:0:0)(0:0:0)) + (INTERCONNECT CROW\[0\]_I/PADDI SLICE_85/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/Q0 RBA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/Q1 RBA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_86/Q0 SLICE_86/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/Q1 SLICE_86/M0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_87/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F0 SLICE_88/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/Q0 SLICE_97/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/Q1 SLICE_96/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q0 RD\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/Q1 RD\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_90/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[8\]_I/PADDI SLICE_98/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/Q0 SLICE_98/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/Q0 RD\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/Q1 RD\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F0 RDQMH_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F1 RDQML_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_95/M0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_97/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[4\]_I/PADDI SLICE_97/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/Q0 SLICE_97/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/Q1 SLICE_103/A1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_96/B1 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_96/B0 (0:0:0)(0:0:0)) + (INTERCONNECT MAin\[3\]_I/PADDI SLICE_96/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/Q1 SLICE_96/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/Q0 SLICE_96/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/Q0 SLICE_101/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F1 RA\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/Q1 SLICE_97/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/Q0 SLICE_98/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F1 RA\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/Q1 SLICE_99/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F0 RA\[8\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F1 RA\[0\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F0 RA\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F1 RA\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_100/Q0 SLICE_100/M1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F0 RA\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F1 RA\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/Q0 RD\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F1 RA\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/Q1 RD\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/Q0 RD\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[7\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[6\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[5\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[4\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[3\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[2\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[1\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 RD\[0\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/Q1 RD\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.vo b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.vo new file mode 100644 index 0000000..8cd98b1 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mapvo.vo @@ -0,0 +1,3678 @@ + +// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +// ldbanno -n Verilog -o RAM2GS_LCMXO640C_impl1_mapvo.vo -w -neg -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd +// Netlist created on Tue Aug 15 05:03:22 2023 +// Netlist written on Tue Aug 15 05:03:24 2023 +// Design is for device LCMXO640C +// Design is for package TQFP100 +// Design is for performance grade 3 + +`timescale 1 ns / 1 ps + +module RAM2GS ( PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, LED, RBA, RA, + RD, nRCS, RCLK, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, + UFMCLK, UFMSDI, UFMSDO ); + input PHI2; + input [9:0] MAin; + input [1:0] CROW; + input [7:0] Din; + input nCCAS, nCRAS, nFWE, RCLK, UFMSDO; + output [7:0] Dout; + output LED; + output [1:0] RBA; + output [11:0] RA; + output nRCS, RCKE, nRWE, nRRAS, nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI; + inout [7:0] RD; + wire FS_7, FS_6, RCLK_c, n2010, n2011, FS_15, FS_14, n2014, n2015, FS_5, + FS_4, n2009, FS_13, FS_12, n2013, FS_1, FS_0, n2008, FS_11, FS_10, + n2012, FS_3, FS_2, FS_9, FS_8, FS_17, FS_16, MAin_c_1, n1326, + MAin_c_0, n2263, ADSubmitted, n2242, n2459, n1413, C1Submitted_N_237, + PHI2_c, Din_c_6, C1Submitted, nFWE_c, n6_adj_3, n2284, MAin_c_5, + n2316, n26, MAin_c_2, n15, n2463, CmdEnable_N_248, + PHI2_N_120_enable_7, CmdEnable, PHI2r2, CmdSubmitted, PHI2r3, + \n2568\001/BUF1 , PHI2_N_120_enable_5, n2472, Din_c_5, Din_c_7, n1314, + Din_c_4, n8MEGEN, Din_c_0, Cmdn8MEGEN_N_264, PHI2_N_120_enable_4, + Cmdn8MEGEN, nRowColSel_N_35, RASr2, InitReady, Ready, + \n2568\000/BUF1 , RCLK_c_enable_25, RCLK_c_enable_23, nCRAS_c, CBR, + LEDEN, n2568, RCLK_c_enable_12, LED_N_84, nRowColSel_N_34, + nRCAS_N_165, n2208, n2209, nRWE_N_177, RA_0, n56, XOR8MEG, RA11_N_184, + RA_c, n2478, RCKEEN_N_122, RCKEEN_N_121, RCLK_c_enable_4, RCKEEN, + n2467, RCKE_c, RASr3, RASr, RCKE_N_132, CASr, nRWE_N_182, CASr2, + \n2568\002/BUF1 , Ready_N_292, n2469, n2462, n62, n1160, CmdUFMCLK, + UFMCLK_N_224, RCLK_c_enable_24, n1846, UFMCLK_c, n2470, n2272, n2471, + CmdUFMSDI, n2461, UFMSDI_N_231, UFMSDI_c, Din_c_1, n2324, Din_c_2, + Din_c_3, XOR8MEG_N_110, PHI2_N_120_enable_1, n2464, n1325, UFMSDO_c, + n8MEGEN_N_91, RCLK_c_enable_11, n2427, n15_adj_1, nRCAS_N_161, + nRCAS_c, n13, n2481, nRCS_N_136, nRCS_c, nRCS_N_139, nRowColSel_N_32, + n6, nRRAS_c, n2138, nRWE_N_178, n33, nRWE_N_171, RCLK_c_enable_3, + nRWE_c, nRowColSel, MAin_c_9, RowA_9, nRowColSel_N_28, n1502, n1410, + RA_1_9, Ready_N_296, nRowColSel_N_33, n1503, n2414, n1093, CmdUFMCS, + nUFMCS_c, n11, n1417, n2322, CASr3, n12, n2164, LEDEN_N_82, FWEr, + n2476, n2475, n13_adj_2, n1, n2214, n2328, n10, n2458, n732, n733, + n2290, n728, n729, n8, n727, MAin_c_7, MAin_c_6, RowA_6, RowA_7, + n2468, n1280, PHI2r, nCCAS_c, n726, Bank_3, Bank_6, Bank_5, n2278, + n2314, Bank_2, PHI2_N_120_enable_6, n14, n2460, n730, n2262, n2473, + n738, n737, n2474, n2253, CROW_c_1, CROW_c_0, RBA_c_0, RBA_c_1, n734, + n735, n7, n2451, Bank_0, Bank_1, WRD_0, WRD_1, MAin_c_8, RowA_8, + WRD_6, WRD_7, RDQMH_c, RDQML_c, MAin_c_4, RowA_4, RowA_5, MAin_c_3, + RowA_3, Bank_4, RowA_2, RA_1_3, Bank_7, RowA_0, RA_1_4, RowA_1, + RA_1_8, RA_1_0, RA_1_7, RA_1_1, n736, RA_1_6, RA_1_2, WRD_2, RA_1_5, + WRD_3, WRD_4, n984, WRD_5, Dout_c, Dout_0, Dout_1, Dout_2, Dout_3, + Dout_4, Dout_5, Dout_6, VCCI, GNDI_TSALL; + + SLICE_0 SLICE_0( .A1(FS_7), .A0(FS_6), .CLK(RCLK_c), .FCI(n2010), .Q0(FS_6), + .Q1(FS_7), .FCO(n2011)); + SLICE_1 SLICE_1( .A1(FS_15), .A0(FS_14), .CLK(RCLK_c), .FCI(n2014), + .Q0(FS_14), .Q1(FS_15), .FCO(n2015)); + SLICE_2 SLICE_2( .A1(FS_5), .A0(FS_4), .CLK(RCLK_c), .FCI(n2009), .Q0(FS_4), + .Q1(FS_5), .FCO(n2010)); + SLICE_3 SLICE_3( .A1(FS_13), .A0(FS_12), .CLK(RCLK_c), .FCI(n2013), + .Q0(FS_12), .Q1(FS_13), .FCO(n2014)); + SLICE_4 SLICE_4( .A1(FS_1), .A0(FS_0), .CLK(RCLK_c), .Q0(FS_0), .Q1(FS_1), + .FCO(n2008)); + SLICE_5 SLICE_5( .A1(FS_11), .A0(FS_10), .CLK(RCLK_c), .FCI(n2012), + .Q0(FS_10), .Q1(FS_11), .FCO(n2013)); + SLICE_6 SLICE_6( .A1(FS_3), .A0(FS_2), .CLK(RCLK_c), .FCI(n2008), .Q0(FS_2), + .Q1(FS_3), .FCO(n2009)); + SLICE_7 SLICE_7( .A1(FS_9), .A0(FS_8), .CLK(RCLK_c), .FCI(n2011), .Q0(FS_8), + .Q1(FS_9), .FCO(n2012)); + SLICE_8 SLICE_8( .A1(FS_17), .A0(FS_16), .CLK(RCLK_c), .FCI(n2015), + .Q0(FS_16), .Q1(FS_17)); + SLICE_9 SLICE_9( .C1(MAin_c_1), .B1(n1326), .A1(MAin_c_0), .D0(n2263), + .C0(ADSubmitted), .B0(n2242), .A0(n2459), .DI0(n1413), + .LSR(C1Submitted_N_237), .CLK(PHI2_c), .F0(n1413), .Q0(ADSubmitted), + .F1(n2263)); + SLICE_14 SLICE_14( .B1(Din_c_6), .A1(C1Submitted), .D0(MAin_c_1), + .C0(C1Submitted), .B0(n1326), .A0(nFWE_c), .DI0(n6_adj_3), + .LSR(C1Submitted_N_237), .CLK(PHI2_c), .F0(n6_adj_3), .Q0(C1Submitted), + .F1(n2284)); + SLICE_18 SLICE_18( .D1(MAin_c_5), .C1(n2316), .B1(n26), .A1(MAin_c_2), + .D0(n15), .C0(n1326), .B0(n2463), .A0(MAin_c_1), .DI0(CmdEnable_N_248), + .CE(PHI2_N_120_enable_7), .CLK(PHI2_c), .F0(CmdEnable_N_248), + .Q0(CmdEnable), .F1(n1326)); + SLICE_19 SLICE_19( .C1(PHI2r2), .B1(CmdSubmitted), .A1(PHI2r3), + .DI0(\n2568\001/BUF1 ), .CE(PHI2_N_120_enable_5), .CLK(PHI2_c), + .F0(\n2568\001/BUF1 ), .Q0(CmdSubmitted), .F1(n2472)); + SLICE_23 SLICE_23( .C1(Din_c_5), .B1(Din_c_7), .A1(Din_c_6), .D0(n1314), + .C0(Din_c_4), .B0(n8MEGEN), .A0(Din_c_0), .DI0(Cmdn8MEGEN_N_264), + .CE(PHI2_N_120_enable_4), .CLK(PHI2_c), .F0(Cmdn8MEGEN_N_264), + .Q0(Cmdn8MEGEN), .F1(n1314)); + SLICE_25 SLICE_25( .D1(nRowColSel_N_35), .C1(RASr2), .B1(InitReady), + .A1(Ready), .DI0(\n2568\000/BUF1 ), .CE(RCLK_c_enable_25), .CLK(RCLK_c), + .F0(\n2568\000/BUF1 ), .Q0(InitReady), .F1(RCLK_c_enable_23)); + SLICE_26 SLICE_26( .C1(nCRAS_c), .B1(CBR), .A1(LEDEN), .DI0(n2568), + .CE(RCLK_c_enable_12), .CLK(RCLK_c), .F0(n2568), .Q0(LEDEN), .F1(LED_N_84)); + SLICE_31 SLICE_31( .B1(nRowColSel_N_34), .A1(Ready), .C0(nRCAS_N_165), + .B0(Ready), .A0(n2208), .DI0(n2209), .LSR(nRWE_N_177), .CLK(RCLK_c), + .F0(n2209), .Q0(RA_0), .F1(n56)); + SLICE_32 SLICE_32( .B1(Din_c_7), .A1(Din_c_6), .C0(n8MEGEN), .B0(XOR8MEG), + .A0(Din_c_6), .DI0(RA11_N_184), .LSR(Ready), .CLK(PHI2_c), .F0(RA11_N_184), + .Q0(RA_c), .F1(n2478)); + SLICE_34 SLICE_34( .C1(Ready), .B1(InitReady), .A1(RASr2), .C0(Ready), + .B0(RCKEEN_N_122), .A0(InitReady), .DI0(RCKEEN_N_121), + .CE(RCLK_c_enable_4), .CLK(RCLK_c), .F0(RCKEEN_N_121), .Q0(RCKEEN), + .F1(n2467)); + SLICE_35 SLICE_35( .B1(RCKE_c), .A1(RASr2), .D0(RASr3), .C0(RASr2), + .B0(RCKEEN), .A0(RASr), .DI0(RCKE_N_132), .M1(CASr), .CLK(RCLK_c), + .F0(RCKE_N_132), .Q0(RCKE_c), .F1(nRWE_N_182), .Q1(CASr2)); + SLICE_36 SLICE_36( .B1(nRowColSel_N_35), .A1(Ready), .DI0(\n2568\002/BUF1 ), + .CE(Ready_N_292), .CLK(RCLK_c), .F0(\n2568\002/BUF1 ), .Q0(Ready), + .F1(n2469)); + SLICE_43 SLICE_43( .D1(FS_1), .C1(n2462), .B1(n62), .A1(FS_4), + .C0(InitReady), .B0(n1160), .A0(CmdUFMCLK), .DI0(UFMCLK_N_224), + .CE(RCLK_c_enable_24), .LSR(n1846), .CLK(RCLK_c), .F0(UFMCLK_N_224), + .Q0(UFMCLK_c), .F1(n1160)); + SLICE_44 SLICE_44( .D1(FS_11), .C1(n2470), .B1(n2272), .A1(n2471), + .D0(CmdUFMSDI), .C0(InitReady), .B0(n2462), .A0(n2461), .DI0(UFMSDI_N_231), + .CE(RCLK_c_enable_24), .LSR(n1846), .CLK(RCLK_c), .F0(UFMSDI_N_231), + .Q0(UFMSDI_c), .F1(n2462)); + SLICE_49 SLICE_49( .D1(Din_c_1), .C1(n1314), .B1(LEDEN), .A1(Din_c_4), + .D0(n2324), .C0(Din_c_2), .B0(Din_c_3), .A0(Din_c_0), .DI0(XOR8MEG_N_110), + .CE(PHI2_N_120_enable_1), .CLK(PHI2_c), .F0(XOR8MEG_N_110), .Q0(XOR8MEG), + .F1(n2324)); + SLICE_56 SLICE_56( .C1(FS_10), .B1(n2464), .A1(FS_11), .D0(n1325), + .C0(InitReady), .B0(Cmdn8MEGEN), .A0(UFMSDO_c), .DI0(n8MEGEN_N_91), + .CE(RCLK_c_enable_11), .CLK(RCLK_c), .F0(n8MEGEN_N_91), .Q0(n8MEGEN), + .F1(n1325)); + SLICE_58 SLICE_58( .D1(n2427), .C1(RASr2), .B1(CBR), .A1(Ready), .C0(Ready), + .B0(n15_adj_1), .A0(nRowColSel_N_34), .DI0(nRCAS_N_161), + .M0(nRowColSel_N_35), .CE(RCLK_c_enable_4), .CLK(RCLK_c), + .OFX0(nRCAS_N_161), .Q0(nRCAS_c)); + SLICE_60 SLICE_60( .D1(Ready), .C1(RCKE_c), .B1(InitReady), .A1(RASr2), + .D0(nRowColSel_N_35), .C0(n13), .B0(n2481), .A0(n2467), .DI0(nRCS_N_136), + .CE(RCLK_c_enable_4), .CLK(RCLK_c), .F0(nRCS_N_136), .Q0(nRCS_c), .F1(n13)); + SLICE_61 SLICE_61( .C1(nRCS_N_139), .B1(n13), .A1(Ready), + .D0(nRowColSel_N_32), .C0(n6), .B0(nRRAS_c), .A0(n56), .DI0(n2138), + .M0(nRowColSel_N_35), .CLK(RCLK_c), .OFX0(n2138), .Q0(nRRAS_c)); + SLICE_63 SLICE_63( .D1(nRCS_N_139), .C1(InitReady), .B1(RASr2), + .A1(nRowColSel_N_35), .D0(n2208), .C0(Ready), .B0(nRWE_N_178), .A0(n33), + .DI0(nRWE_N_171), .CE(RCLK_c_enable_3), .CLK(RCLK_c), .F0(nRWE_N_171), + .Q0(nRWE_c), .F1(n2208)); + SLICE_64 SLICE_64( .C1(nRowColSel), .B1(MAin_c_9), .A1(RowA_9), + .D0(nRowColSel_N_32), .C0(nRowColSel_N_28), .B0(n1502), .A0(nRowColSel), + .DI0(n1410), .LSR(n2469), .CLK(RCLK_c), .F0(n1410), .Q0(nRowColSel), + .F1(RA_1_9)); + SLICE_65 SLICE_65( .D1(InitReady), .C1(Ready_N_296), .B1(RASr2), + .A1(nRowColSel_N_32), .B0(nRowColSel_N_33), .A0(nRowColSel_N_32), + .DI0(n1503), .LSR(RASr2), .CLK(RCLK_c), .F0(n1503), .Q0(nRowColSel_N_32), + .F1(n2414)); + SLICE_66 SLICE_66( .D1(nRowColSel_N_33), .C1(nRowColSel_N_34), .B1(n2469), + .A1(nRowColSel_N_32), .B0(RASr2), .A0(nRowColSel_N_32), .DI0(n1093), + .LSR(nRowColSel_N_34), .CLK(RCLK_c), .F0(n1093), .Q0(nRowColSel_N_33), + .F1(RCLK_c_enable_4)); + SLICE_67 SLICE_67( .C1(n2472), .B1(CmdUFMCS), .A1(nUFMCS_c), .B0(CASr2), + .A0(nRowColSel_N_33), .M0(n1093), .LSR(nRowColSel_N_35), .CLK(RCLK_c), + .F0(n11), .Q0(nRowColSel_N_34), .F1(n1417)); + SLICE_68 SLICE_68( .B1(FS_12), .A1(FS_17), .D0(FS_3), .C0(FS_6), .B0(FS_1), + .A0(FS_0), .M1(CASr2), .M0(RASr2), .CLK(RCLK_c), .F0(n2322), + .Q0(nRowColSel_N_35), .F1(n2471), .Q1(CASr3)); + SLICE_69 SLICE_69( .D1(FS_14), .C1(FS_12), .B1(n12), .A1(FS_17), + .C0(InitReady), .B0(n1417), .A0(n62), .DI0(n2164), .LSR(LEDEN_N_82), + .CLK(RCLK_c), .F0(n2164), .Q0(nUFMCS_c), .F1(n62)); + RCKEEN_I_0_445_SLICE_70 \RCKEEN_I_0_445/SLICE_70 ( .C1(RASr2), .B1(FWEr), + .A1(CBR), .D0(nRowColSel_N_34), .C0(FWEr), .B0(n11), .A0(CBR), + .M0(nRowColSel_N_35), .OFX0(RCKEEN_N_122)); + i26_SLICE_71 \i26/SLICE_71 ( .D1(n2284), .C1(n2476), .B1(MAin_c_1), + .A1(MAin_c_0), .D0(ADSubmitted), .C0(MAin_c_0), .B0(n2475), .A0(Din_c_5), + .M0(Din_c_2), .OFX0(n13_adj_2)); + i2099_SLICE_72 \i2099/SLICE_72 ( .D1(nRowColSel_N_34), .C1(nRowColSel_N_35), + .B1(Ready), .A1(nRCS_N_139), .C0(nRowColSel_N_35), .B0(Ready), + .A0(nRCS_N_139), .M0(n15_adj_1), .OFX0(n2481)); + i26_adj_28_SLICE_73 \i26_adj_28/SLICE_73 ( .D1(MAin_c_0), .C1(Din_c_2), + .B1(Din_c_3), .A1(Din_c_6), .D0(MAin_c_0), .C0(Din_c_2), .B0(Din_c_3), + .A0(Din_c_6), .M0(Din_c_5), .OFX0(n15)); + SLICE_74 SLICE_74( .D1(n1), .C1(nRowColSel_N_33), .B1(CBR), .A1(FWEr), + .D0(CASr3), .C0(CASr2), .B0(FWEr), .A0(CBR), .M1(RASr2), .M0(RASr), + .CLK(RCLK_c), .F0(n1), .Q0(RASr2), .F1(n15_adj_1), .Q1(RASr3)); + SLICE_75 SLICE_75( .C1(InitReady), .B1(FS_11), .A1(n2214), .D0(FS_11), + .C0(n2272), .B0(n2328), .A0(FS_10), .F0(n2214), .F1(RCLK_c_enable_12)); + SLICE_76 SLICE_76( .D1(MAin_c_0), .C1(n10), .B1(n1326), .A1(nFWE_c), + .D0(n2458), .C0(Din_c_4), .B0(Din_c_5), .A0(Din_c_3), .M1(n732), .M0(n733), + .CE(RCLK_c_enable_23), .CLK(RCLK_c), .F0(PHI2_N_120_enable_4), .Q0(n732), + .F1(n2458), .Q1(nRWE_N_177)); + SLICE_77 SLICE_77( .D1(FS_7), .C1(n2322), .B1(FS_4), .A1(n2290), .C0(FS_9), + .B0(FS_5), .A0(FS_2), .M1(n728), .M0(n729), .CE(RCLK_c_enable_23), + .CLK(RCLK_c), .F0(n2290), .Q0(n728), .F1(n8), .Q1(n727)); + SLICE_78 SLICE_78( .D1(n2471), .C1(n2272), .B1(FS_14), .A1(FS_16), + .C0(InitReady), .B0(n2464), .A0(FS_11), .M1(MAin_c_7), .M0(MAin_c_6), + .LSR(Ready), .CLK(nCRAS_c), .F0(n1846), .Q0(RowA_6), .F1(n2464), + .Q1(RowA_7)); + SLICE_79 SLICE_79( .C1(Din_c_5), .B1(Din_c_3), .A1(Din_c_6), .D0(n2468), + .C0(n1280), .B0(n2463), .A0(Din_c_2), .M1(PHI2r), .M0(nCCAS_c), + .CLK(RCLK_c), .F0(C1Submitted_N_237), .Q0(CASr), .F1(n2468), .Q1(PHI2r2)); + SLICE_80 SLICE_80( .B1(nRowColSel_N_33), .A1(nRowColSel_N_34), + .D0(nRowColSel_N_35), .C0(n1502), .B0(nRowColSel_N_32), .A0(Ready), + .M1(n726), .M0(n727), .CE(RCLK_c_enable_23), .CLK(RCLK_c), + .F0(RCLK_c_enable_3), .Q0(n726), .F1(n1502), .Q1(Ready_N_296)); + SLICE_81 SLICE_81( .B1(Bank_3), .A1(Bank_6), .D0(Bank_5), .C0(n2278), + .B0(n2314), .A0(Bank_2), .M1(Din_c_2), .M0(Din_c_1), + .CE(PHI2_N_120_enable_6), .CLK(PHI2_c), .F0(n26), .Q0(CmdUFMCLK), + .F1(n2278), .Q1(CmdUFMCS)); + SLICE_82 SLICE_82( .D1(MAin_c_1), .C1(n14), .B1(n2460), .A1(MAin_c_0), + .B0(n1326), .A0(nFWE_c), .M1(n730), .M0(nRWE_N_177), .CE(RCLK_c_enable_23), + .CLK(RCLK_c), .F0(n2460), .Q0(n730), .F1(PHI2_N_120_enable_7), .Q1(n729)); + SLICE_83 SLICE_83( .D1(n2476), .C1(n2460), .B1(n10), .A1(MAin_c_0), + .D0(MAin_c_1), .C0(CmdEnable), .B0(n2478), .A0(Din_c_4), .M0(nCRAS_c), + .CLK(RCLK_c), .F0(n10), .Q0(RASr), .F1(PHI2_N_120_enable_6)); + SLICE_84 SLICE_84( .D1(n1314), .C1(n2262), .B1(CmdEnable), .A1(n2473), + .C0(MAin_c_1), .B0(n1326), .A0(MAin_c_0), .M1(n738), .M0(nRCAS_N_165), + .CE(RCLK_c_enable_23), .CLK(RCLK_c), .F0(n2262), .Q0(n738), + .F1(PHI2_N_120_enable_1), .Q1(n737)); + SLICE_85 SLICE_85( .D1(n2474), .C1(Din_c_5), .B1(n2253), .A1(n2473), + .B0(nFWE_c), .A0(Din_c_4), .M1(CROW_c_1), .M0(CROW_c_0), .LSR(Ready), + .CLK(nCRAS_c), .F0(n2473), .Q0(RBA_c_0), .F1(n2242), .Q1(RBA_c_1)); + SLICE_86 SLICE_86( .C1(Din_c_1), .B1(Din_c_0), .A1(Din_c_7), .C0(n2253), + .B0(nFWE_c), .A0(Din_c_4), .M1(n734), .M0(n735), .CE(RCLK_c_enable_23), + .CLK(RCLK_c), .F0(n2463), .Q0(n734), .F1(n2253), .Q1(n733)); + SLICE_87 SLICE_87( .B1(n2214), .A1(FS_8), .D0(n8), .C0(InitReady), + .B0(n2472), .A0(n7), .M1(nRCS_N_139), .M0(Ready_N_296), + .CE(RCLK_c_enable_23), .CLK(RCLK_c), .F0(RCLK_c_enable_11), + .Q0(nRCS_N_139), .F1(n7), .Q1(nRCAS_N_165)); + SLICE_88 SLICE_88( .C1(FS_10), .B1(FS_6), .A1(n2451), .D0(FS_8), .C0(FS_5), + .B0(FS_9), .A0(FS_7), .M1(Din_c_1), .M0(Din_c_0), .CLK(PHI2_c), .F0(n2451), + .Q0(Bank_0), .F1(n2461), .Q1(Bank_1)); + SLICE_89 SLICE_89( .C1(MAin_c_1), .B1(n1326), .A1(nFWE_c), .C0(MAin_c_0), + .B0(n1326), .A0(MAin_c_1), .M1(Din_c_1), .M0(Din_c_0), .CLK(nCCAS_c), + .F0(n1280), .Q0(WRD_0), .F1(n2459), .Q1(WRD_1)); + SLICE_90 SLICE_90( .D1(FS_16), .C1(FS_14), .B1(FS_12), .A1(FS_17), + .B0(FS_14), .A0(FS_16), .M1(MAin_c_9), .M0(MAin_c_8), .LSR(Ready), + .CLK(nCRAS_c), .F0(n2470), .Q0(RowA_8), .F1(n2328), .Q1(RowA_9)); + SLICE_91 SLICE_91( .B1(Din_c_5), .A1(Din_c_3), .D0(n2458), .C0(Din_c_5), + .B0(Din_c_4), .A0(Din_c_3), .M1(PHI2_c), .M0(PHI2r2), .CLK(RCLK_c), + .F0(PHI2_N_120_enable_5), .Q0(PHI2r3), .F1(n2476), .Q1(PHI2r)); + SLICE_92 SLICE_92( .B1(Din_c_3), .A1(Din_c_6), .C0(Din_c_3), .B0(Din_c_2), + .A0(Din_c_6), .M1(Din_c_7), .M0(Din_c_6), .CLK(nCCAS_c), .F0(n2474), + .Q0(WRD_6), .F1(n2475), .Q1(WRD_7)); + SLICE_93 SLICE_93( .B1(nRowColSel), .A1(MAin_c_9), .B0(nRowColSel), + .A0(MAin_c_9), .M0(Din_c_0), .CE(PHI2_N_120_enable_6), .CLK(PHI2_c), + .F0(RDQMH_c), .Q0(CmdUFMSDI), .F1(RDQML_c)); + SLICE_94 SLICE_94( .B1(FS_15), .A1(FS_13), .D0(FS_11), .C0(FS_16), + .B0(FS_13), .A0(FS_15), .F0(n12), .F1(n2272)); + SLICE_95 SLICE_95( .B1(FS_10), .A1(n62), .D0(InitReady), .C0(FS_10), + .B0(n2464), .A0(FS_11), .M1(MAin_c_5), .M0(MAin_c_4), .LSR(Ready), + .CLK(nCRAS_c), .F0(LEDEN_N_82), .Q0(RowA_4), .F1(RCLK_c_enable_25), + .Q1(RowA_5)); + SLICE_96 SLICE_96( .C1(nRowColSel), .B1(MAin_c_3), .A1(RowA_3), .D0(Bank_1), + .C0(Bank_4), .B0(MAin_c_3), .A0(MAin_c_7), .M1(MAin_c_3), .M0(MAin_c_2), + .LSR(Ready), .CLK(nCRAS_c), .F0(n2316), .Q0(RowA_2), .F1(RA_1_3), + .Q1(RowA_3)); + SLICE_97 SLICE_97( .C1(nRowColSel), .B1(MAin_c_4), .A1(RowA_4), .D0(Bank_0), + .C0(Bank_7), .B0(MAin_c_4), .A0(MAin_c_6), .M1(MAin_c_1), .M0(MAin_c_0), + .LSR(Ready), .CLK(nCRAS_c), .F0(n2314), .Q0(RowA_0), .F1(RA_1_4), + .Q1(RowA_1)); + SLICE_98 SLICE_98( .C1(nRowColSel), .B1(MAin_c_0), .A1(RowA_0), + .C0(nRowColSel), .B0(MAin_c_8), .A0(RowA_8), .M1(nFWE_c), .M0(nCCAS_c), + .CLK(nCRAS_c), .F0(RA_1_8), .Q0(CBR), .F1(RA_1_0), .Q1(FWEr)); + SLICE_99 SLICE_99( .C1(nRowColSel), .B1(MAin_c_1), .A1(RowA_1), + .C0(nRowColSel), .B0(MAin_c_7), .A0(RowA_7), .M1(Din_c_7), .M0(Din_c_6), + .CLK(PHI2_c), .F0(RA_1_7), .Q0(Bank_6), .F1(RA_1_1), .Q1(Bank_7)); + SLICE_100 SLICE_100( .D1(Ready), .C1(nRowColSel_N_33), .B1(InitReady), + .A1(RASr2), .D0(InitReady), .C0(PHI2r2), .B0(CmdSubmitted), .A0(PHI2r3), + .M1(n736), .M0(n737), .CE(RCLK_c_enable_23), .CLK(RCLK_c), + .F0(RCLK_c_enable_24), .Q0(n736), .F1(n6), .Q1(n735)); + SLICE_101 SLICE_101( .C1(nRowColSel), .B1(MAin_c_2), .A1(RowA_2), + .C0(nRowColSel), .B0(MAin_c_6), .A0(RowA_6), .M1(Din_c_5), .M0(Din_c_4), + .CLK(PHI2_c), .F0(RA_1_6), .Q0(Bank_4), .F1(RA_1_2), .Q1(Bank_5)); + SLICE_102 SLICE_102( .B1(nRWE_N_177), .A1(nRCAS_N_165), .C0(nRCAS_N_165), + .B0(nRCS_N_139), .A0(InitReady), .M1(Din_c_3), .M0(Din_c_2), .CLK(PHI2_c), + .F0(n2427), .Q0(Bank_2), .F1(n33), .Q1(Bank_3)); + SLICE_103 SLICE_103( .C1(nRowColSel), .B1(MAin_c_5), .A1(RowA_5), .C0(CBR), + .B0(CASr3), .A0(FWEr), .M1(Din_c_3), .M0(Din_c_2), .CLK(nCCAS_c), + .F0(nRowColSel_N_28), .Q0(WRD_2), .F1(RA_1_5), .Q1(WRD_3)); + SLICE_104 SLICE_104( .B1(Ready), .A1(n2414), .D0(nRowColSel_N_35), + .C0(nRWE_N_182), .B0(n1502), .A0(n1), .F0(nRWE_N_178), .F1(Ready_N_292)); + SLICE_105 SLICE_105( .B1(nFWE_c), .A1(nCCAS_c), .C0(n13_adj_2), .B0(Din_c_4), + .A0(n2253), .M1(Din_c_5), .M0(Din_c_4), .CLK(nCCAS_c), .F0(n14), + .Q0(WRD_4), .F1(n984), .Q1(WRD_5)); + RD_7_ \RD[7]_I ( .PADDI(Dout_c), .PADDT(n984), .PADDO(WRD_7), .RD7(RD[7])); + RD_6_ \RD[6]_I ( .PADDI(Dout_0), .PADDT(n984), .PADDO(WRD_6), .RD6(RD[6])); + RD_5_ \RD[5]_I ( .PADDI(Dout_1), .PADDT(n984), .PADDO(WRD_5), .RD5(RD[5])); + RD_4_ \RD[4]_I ( .PADDI(Dout_2), .PADDT(n984), .PADDO(WRD_4), .RD4(RD[4])); + RD_3_ \RD[3]_I ( .PADDI(Dout_3), .PADDT(n984), .PADDO(WRD_3), .RD3(RD[3])); + RD_2_ \RD[2]_I ( .PADDI(Dout_4), .PADDT(n984), .PADDO(WRD_2), .RD2(RD[2])); + RD_1_ \RD[1]_I ( .PADDI(Dout_5), .PADDT(n984), .PADDO(WRD_1), .RD1(RD[1])); + RD_0_ \RD[0]_I ( .PADDI(Dout_6), .PADDT(n984), .PADDO(WRD_0), .RD0(RD[0])); + Dout_7_ \Dout[7]_I ( .PADDO(Dout_c), .Dout7(Dout[7])); + Dout_6_ \Dout[6]_I ( .PADDO(Dout_0), .Dout6(Dout[6])); + Dout_5_ \Dout[5]_I ( .PADDO(Dout_1), .Dout5(Dout[5])); + Dout_4_ \Dout[4]_I ( .PADDO(Dout_2), .Dout4(Dout[4])); + Dout_3_ \Dout[3]_I ( .PADDO(Dout_3), .Dout3(Dout[3])); + Dout_2_ \Dout[2]_I ( .PADDO(Dout_4), .Dout2(Dout[2])); + Dout_1_ \Dout[1]_I ( .PADDO(Dout_5), .Dout1(Dout[1])); + Dout_0_ \Dout[0]_I ( .PADDO(Dout_6), .Dout0(Dout[0])); + LED LED_I( .PADDO(LED_N_84), .LED(LED)); + RBA_1_ \RBA[1]_I ( .PADDO(RBA_c_1), .RBA1(RBA[1])); + RBA_0_ \RBA[0]_I ( .PADDO(RBA_c_0), .RBA0(RBA[0])); + RA_11_ \RA[11]_I ( .PADDO(RA_c), .RA11(RA[11])); + RA_10_ \RA[10]_I ( .PADDO(RA_0), .RA10(RA[10])); + RA_9_ \RA[9]_I ( .PADDO(RA_1_9), .RA9(RA[9])); + RA_8_ \RA[8]_I ( .PADDO(RA_1_8), .RA8(RA[8])); + RA_7_ \RA[7]_I ( .PADDO(RA_1_7), .RA7(RA[7])); + RA_6_ \RA[6]_I ( .PADDO(RA_1_6), .RA6(RA[6])); + RA_5_ \RA[5]_I ( .PADDO(RA_1_5), .RA5(RA[5])); + RA_4_ \RA[4]_I ( .PADDO(RA_1_4), .RA4(RA[4])); + RA_3_ \RA[3]_I ( .PADDO(RA_1_3), .RA3(RA[3])); + RA_2_ \RA[2]_I ( .PADDO(RA_1_2), .RA2(RA[2])); + RA_1_ \RA[1]_I ( .PADDO(RA_1_1), .RA1(RA[1])); + RA_0_ \RA[0]_I ( .PADDO(RA_1_0), .RA0(RA[0])); + nRCS nRCS_I( .PADDO(nRCS_c), .nRCS(nRCS)); + RCKE RCKE_I( .PADDO(RCKE_c), .RCKE(RCKE)); + nRWE nRWE_I( .PADDO(nRWE_c), .nRWE(nRWE)); + nRRAS nRRAS_I( .PADDO(nRRAS_c), .nRRAS(nRRAS)); + nRCAS nRCAS_I( .PADDO(nRCAS_c), .nRCAS(nRCAS)); + RDQMH RDQMH_I( .PADDO(RDQMH_c), .RDQMH(RDQMH)); + RDQML RDQML_I( .PADDO(RDQML_c), .RDQML(RDQML)); + nUFMCS nUFMCS_I( .PADDO(nUFMCS_c), .nUFMCS(nUFMCS)); + UFMCLK UFMCLK_I( .PADDO(UFMCLK_c), .UFMCLK(UFMCLK)); + UFMSDI UFMSDI_I( .PADDO(UFMSDI_c), .UFMSDI(UFMSDI)); + PHI2 PHI2_I( .PADDI(PHI2_c), .PHI2(PHI2)); + MAin_9_ \MAin[9]_I ( .PADDI(MAin_c_9), .MAin9(MAin[9])); + MAin_8_ \MAin[8]_I ( .PADDI(MAin_c_8), .MAin8(MAin[8])); + MAin_7_ \MAin[7]_I ( .PADDI(MAin_c_7), .MAin7(MAin[7])); + MAin_6_ \MAin[6]_I ( .PADDI(MAin_c_6), .MAin6(MAin[6])); + MAin_5_ \MAin[5]_I ( .PADDI(MAin_c_5), .MAin5(MAin[5])); + MAin_4_ \MAin[4]_I ( .PADDI(MAin_c_4), .MAin4(MAin[4])); + MAin_3_ \MAin[3]_I ( .PADDI(MAin_c_3), .MAin3(MAin[3])); + MAin_2_ \MAin[2]_I ( .PADDI(MAin_c_2), .MAin2(MAin[2])); + MAin_1_ \MAin[1]_I ( .PADDI(MAin_c_1), .MAin1(MAin[1])); + MAin_0_ \MAin[0]_I ( .PADDI(MAin_c_0), .MAin0(MAin[0])); + CROW_1_ \CROW[1]_I ( .PADDI(CROW_c_1), .CROW1(CROW[1])); + CROW_0_ \CROW[0]_I ( .PADDI(CROW_c_0), .CROW0(CROW[0])); + Din_7_ \Din[7]_I ( .PADDI(Din_c_7), .Din7(Din[7])); + Din_6_ \Din[6]_I ( .PADDI(Din_c_6), .Din6(Din[6])); + Din_5_ \Din[5]_I ( .PADDI(Din_c_5), .Din5(Din[5])); + Din_4_ \Din[4]_I ( .PADDI(Din_c_4), .Din4(Din[4])); + Din_3_ \Din[3]_I ( .PADDI(Din_c_3), .Din3(Din[3])); + Din_2_ \Din[2]_I ( .PADDI(Din_c_2), .Din2(Din[2])); + Din_1_ \Din[1]_I ( .PADDI(Din_c_1), .Din1(Din[1])); + Din_0_ \Din[0]_I ( .PADDI(Din_c_0), .Din0(Din[0])); + nCCAS nCCAS_I( .PADDI(nCCAS_c), .nCCAS(nCCAS)); + nCRAS nCRAS_I( .PADDI(nCRAS_c), .nCRAS(nCRAS)); + nFWE nFWE_I( .PADDI(nFWE_c), .nFWE(nFWE)); + RCLK RCLK_I( .PADDI(RCLK_c), .RCLK(RCLK)); + UFMSDO UFMSDO_I( .PADDI(UFMSDO_c), .UFMSDO(UFMSDO)); + VHI VHI_INST( .Z(VCCI)); + PUR PUR_INST( .PUR(VCCI)); + GSR GSR_INST( .GSR(VCCI)); + VLO VLO_INST( .Z(GNDI_TSALL)); + TSALL TSALL_INST( .TSALL(GNDI_TSALL)); +endmodule + +module SLICE_0 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_0/FS_610_add_4_8_S1 , GNDI, \SLICE_0/FS_610_add_4_8_S0 , + A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i7( .D0(VCCI), .D1(\SLICE_0/FS_610_add_4_8_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i6( .D0(VCCI), .D1(\SLICE_0/FS_610_add_4_8_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_8( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_0/FS_610_add_4_8_S0 ), .S1(\SLICE_0/FS_610_add_4_8_S1 ), .CO0(), + .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module vcc ( output PWR1 ); + + VHI INST1( .Z(PWR1)); +endmodule + +module gnd ( output PWR0 ); + + VLO INST1( .Z(PWR0)); +endmodule + +module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, + CO1 ); + + CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1)); + defparam inst1.INIT0 = 16'hfaaa; + defparam inst1.INIT1 = 16'hfaaa; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_1 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_1/FS_610_add_4_16_S1 , GNDI, + \SLICE_1/FS_610_add_4_16_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i15( .D0(VCCI), .D1(\SLICE_1/FS_610_add_4_16_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i14( .D0(VCCI), .D1(\SLICE_1/FS_610_add_4_16_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_16( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_1/FS_610_add_4_16_S0 ), .S1(\SLICE_1/FS_610_add_4_16_S1 ), + .CO0(), .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_2 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_2/FS_610_add_4_6_S1 , GNDI, \SLICE_2/FS_610_add_4_6_S0 , + A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i5( .D0(VCCI), .D1(\SLICE_2/FS_610_add_4_6_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i4( .D0(VCCI), .D1(\SLICE_2/FS_610_add_4_6_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_6( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_2/FS_610_add_4_6_S0 ), .S1(\SLICE_2/FS_610_add_4_6_S1 ), .CO0(), + .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_3 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_3/FS_610_add_4_14_S1 , GNDI, + \SLICE_3/FS_610_add_4_14_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i13( .D0(VCCI), .D1(\SLICE_3/FS_610_add_4_14_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i12( .D0(VCCI), .D1(\SLICE_3/FS_610_add_4_14_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_14( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_3/FS_610_add_4_14_S0 ), .S1(\SLICE_3/FS_610_add_4_14_S1 ), + .CO0(), .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_4 ( input A1, A0, CLK, output Q0, Q1, FCO ); + wire VCCI, \SLICE_4/FS_610_add_4_2_S1 , GNDI, \SLICE_4/FS_610_add_4_2_S0 , + A1_dly, CLK_dly, A0_dly; + + vmuxregsre FS_610__i1( .D0(VCCI), .D1(\SLICE_4/FS_610_add_4_2_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i0( .D0(VCCI), .D1(\SLICE_4/FS_610_add_4_2_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 FS_610_add_4_2( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), + .S0(\SLICE_4/FS_610_add_4_2_S0 ), .S1(\SLICE_4/FS_610_add_4_2_S1 ), .CO0(), + .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + endspecify + +endmodule + +module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO0, + CO1 ); + + CCU2 inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT0(CO0), .COUT1(CO1)); + defparam inst1.INIT0 = 16'h0555; + defparam inst1.INIT1 = 16'hfaaa; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_5 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_5/FS_610_add_4_12_S1 , GNDI, + \SLICE_5/FS_610_add_4_12_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i11( .D0(VCCI), .D1(\SLICE_5/FS_610_add_4_12_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i10( .D0(VCCI), .D1(\SLICE_5/FS_610_add_4_12_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_12( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_5/FS_610_add_4_12_S0 ), .S1(\SLICE_5/FS_610_add_4_12_S1 ), + .CO0(), .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_6 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_6/FS_610_add_4_4_S1 , GNDI, \SLICE_6/FS_610_add_4_4_S0 , + A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i3( .D0(VCCI), .D1(\SLICE_6/FS_610_add_4_4_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i2( .D0(VCCI), .D1(\SLICE_6/FS_610_add_4_4_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_4( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_6/FS_610_add_4_4_S0 ), .S1(\SLICE_6/FS_610_add_4_4_S1 ), .CO0(), + .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_7 ( input A1, A0, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, \SLICE_7/FS_610_add_4_10_S1 , GNDI, + \SLICE_7/FS_610_add_4_10_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i9( .D0(VCCI), .D1(\SLICE_7/FS_610_add_4_10_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i8( .D0(VCCI), .D1(\SLICE_7/FS_610_add_4_10_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_10( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_7/FS_610_add_4_10_S0 ), .S1(\SLICE_7/FS_610_add_4_10_S1 ), + .CO0(), .CO1(FCO)); + + specify + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_8 ( input A1, A0, CLK, FCI, output Q0, Q1 ); + wire VCCI, \SLICE_8/FS_610_add_4_18_S1 , GNDI, + \SLICE_8/FS_610_add_4_18_S0 , A1_dly, CLK_dly, A0_dly, FCI_dly; + + vmuxregsre FS_610__i17( .D0(VCCI), .D1(\SLICE_8/FS_610_add_4_18_S1 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre FS_610__i16( .D0(VCCI), .D1(\SLICE_8/FS_610_add_4_18_S0 ), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 FS_610_add_4_18( .A0(A0_dly), .B0(GNDI), .C0(GNDI), .D0(GNDI), + .A1(A1_dly), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI_dly), + .S0(\SLICE_8/FS_610_add_4_18_S0 ), .S1(\SLICE_8/FS_610_add_4_18_S1 ), + .CO0(), .CO1()); + + specify + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, A1, 0:0:0, 0:0:0,,,, CLK_dly, A1_dly); + $setuphold (posedge CLK, A0, 0:0:0, 0:0:0,,,, CLK_dly, A0_dly); + $setuphold (posedge CLK, FCI, 0:0:0, 0:0:0,,,, CLK_dly, FCI_dly); + endspecify + +endmodule + +module SLICE_9 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut4 i1_2_lut_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40002 i1125_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 ADSubmitted_407( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut4 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40002 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h50DC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0003 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + +module SLICE_14 ( input B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40004 i1988_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40005 i2062_2_lut_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0006 C1Submitted_406( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40004 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40005 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hE0F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0006 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_18 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40007 i13_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40008 i3_4_lut_adj_21( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdEnable_405( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40007 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40008 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_19 ( input C1, B1, A1, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40009 i2_3_lut_rep_29( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 \n2568\001/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre CmdSubmitted_411( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40009 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40010 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_23 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40011 i1_2_lut_3_lut_adj_2( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 Cmdn8MEGEN_I_93_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Cmdn8MEGEN_410( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40011 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCC5C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_25 ( input D1, C1, B1, A1, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40013 i3_3_lut_4_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 \n2568\000/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre InitReady_394( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40013 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_26 ( input C1, B1, A1, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40014 i2049_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 m1_lut( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre LEDEN_419( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40014 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_31 ( input B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40015 i1_2_lut_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40011 i2_3_lut_adj_27( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0006 RA10_400( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40015 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_32 ( input B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40004 Din_7__I_0_462_i6_2_lut_rep_35( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40016 RA11_I_54_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 RA11_385( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40016 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hC6C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_34 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40017 i78_2_lut_rep_24_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 i1259_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre RCKEEN_401( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40018 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_35 ( input B1, A1, D0, C0, B0, A0, DI0, M1, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, M1_dly; + + lut40019 i1_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40020 RCKE_I_0_449_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CASr2_383( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre RCKE_395( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_36 ( input B1, A1, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40015 i771_2_lut_rep_26_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 \n2568\002/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre Ready_404( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_43 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40021 i919_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40022 i886_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 UFMCLK_416( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h3A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40022 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_44 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40023 i1_2_lut_rep_19_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40024 n2454_bdd_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 UFMSDI_417( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40025 i2028_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40026 i3_4_lut_adj_12( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre XOR8MEG_408( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40026 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_56 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut4 i1_2_lut_3_lut_adj_4( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40027 n8MEGEN_I_14_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre n8MEGEN_418( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCCC5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_58 ( input D1, C1, B1, A1, C0, B0, A0, DI0, M0, CE, CLK, output + OFX0, Q0 ); + wire \SLICE_58/SLICE_58_K1_H1 , GNDI, \SLICE_58/i2095/GATE_H0 , VCCI, + DI0_dly, CLK_dly, CE_dly; + + lut40028 SLICE_58_K1( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\SLICE_58/SLICE_58_K1_H1 )); + lut40029 \i2095/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\SLICE_58/i2095/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0030 nRCAS_398( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 SLICE_58_K0K1MUX( .D0(\SLICE_58/i2095/GATE_H0 ), + .D1(\SLICE_58/SLICE_58_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40028 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h7F2F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hBFBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0030 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module SLICE_60 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40031 i1234_4_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40032 i1_4_lut_adj_17( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0030 nRCS_396( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40031 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFA88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_61 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M0, CLK, output OFX0, + Q0 ); + wire GNDI, \SLICE_61/SLICE_61_K1_H1 , \SLICE_61/i16/GATE_H0 , VCCI, + DI0_dly, CLK_dly; + + lut40033 SLICE_61_K1( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\SLICE_61/SLICE_61_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 \i16/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\SLICE_61/i16/GATE_H0 )); + vmuxregsre0030 nRRAS_397( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 SLICE_61_K0K1MUX( .D0(\SLICE_61/i16/GATE_H0 ), + .D1(\SLICE_61/SLICE_61_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h7373) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40035 i2_3_lut_4_lut_adj_8( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40036 nRWE_I_0_455_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0030 nRWE_399( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40036 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFC5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40018 MAin_9__I_0_427_i10_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40037 i1_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 nRowColSel_402( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_65 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40038 Ready_bdd_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 i1_2_lut_adj_25( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 S_FSM_i4( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40038 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_66 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40039 i2_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 i2057_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 S_FSM_i3( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input C1, B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; + + lut40041 i1129_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40019 i1_2_lut_adj_23( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 S_FSM_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h3A3A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_68 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40004 i2024_2_lut_rep_28( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 i2026_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CASr3_384( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre S_FSM_i1( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_69 ( input D1, C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40042 i6_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40018 i11_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0006 nUFMCS_415( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40042 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RCKEEN_I_0_445_SLICE_70 ( input C1, B1, A1, D0, C0, B0, A0, M0, output + OFX0 ); + wire GNDI, \RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/SLICE_70_K1_H1 , + \RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/GATE_H0 ; + + lut40043 \RCKEEN_I_0_445/SLICE_70_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/SLICE_70_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40044 \RCKEEN_I_0_445/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/GATE_H0 )); + selmux2 \RCKEEN_I_0_445/SLICE_70_K0K1MUX ( + .D0(\RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/GATE_H0 ), + .D1(\RCKEEN_I_0_445/SLICE_70/RCKEEN_I_0_445/SLICE_70_K1_H1 ), .SD(M0), + .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40043 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1F1F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40044 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h5540) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module i26_SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); + wire \i26/SLICE_71/i26/SLICE_71_K1_H1 , \i26/SLICE_71/i26/GATE_H0 ; + + lut40045 \i26/SLICE_71_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\i26/SLICE_71/i26/SLICE_71_K1_H1 )); + lut40046 \i26/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\i26/SLICE_71/i26/GATE_H0 )); + selmux2 \i26/SLICE_71_K0K1MUX ( .D0(\i26/SLICE_71/i26/GATE_H0 ), + .D1(\i26/SLICE_71/i26/SLICE_71_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40046 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module i2099_SLICE_72 ( input D1, C1, B1, A1, C0, B0, A0, M0, output OFX0 ); + wire \i2099/SLICE_72/i2099/SLICE_72_K1_H1 , GNDI, + \i2099/SLICE_72/i2099/GATE_H0 ; + + lut40047 \i2099/SLICE_72_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\i2099/SLICE_72/i2099/SLICE_72_K1_H1 )); + lut40048 \i2099/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\i2099/SLICE_72/i2099/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + selmux2 \i2099/SLICE_72_K0K1MUX ( .D0(\i2099/SLICE_72/i2099/GATE_H0 ), + .D1(\i2099/SLICE_72/i2099/SLICE_72_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40047 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2F23) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2F2F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module i26_adj_28_SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output + OFX0 ); + wire \i26_adj_28/SLICE_73/i26_adj_28/SLICE_73_K1_H1 , + \i26_adj_28/SLICE_73/i26_adj_28/GATE_H0 ; + + lut40049 \i26_adj_28/SLICE_73_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\i26_adj_28/SLICE_73/i26_adj_28/SLICE_73_K1_H1 )); + lut40050 \i26_adj_28/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\i26_adj_28/SLICE_73/i26_adj_28/GATE_H0 )); + selmux2 \i26_adj_28/SLICE_73_K0K1MUX ( + .D0(\i26_adj_28/SLICE_73/i26_adj_28/GATE_H0 ), + .D1(\i26_adj_28/SLICE_73/i26_adj_28/SLICE_73_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_74 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly; + + lut40051 i35_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40052 i3_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr3_381( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre RASr2_380( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1F10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_75 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40009 i2_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40053 i7_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_76 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40054 i5_3_lut_rep_15_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40055 i1_4_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hB300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_77 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40056 i3_4_lut_adj_18( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40011 i1994_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i13( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i12( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40039 i5_3_lut_rep_21_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40057 i2065_2_lut_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 RowA_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40058 i1_2_lut_rep_25_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40059 i2_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre PHI2r2_377( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre CASr_382( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_80 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40004 i1_2_lut_adj_16( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40060 i1_2_lut_3_lut_4_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i15( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i14( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40060 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_81 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40061 i1982_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40062 i12_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdUFMCS_412( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CmdUFMCLK_413( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40061 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_82 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40063 i2052_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 i1990_2_lut_rep_17( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i11( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i10( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0302) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CLK, output F0, Q0, + F1 ); + wire M0_NOTIN, VCCI, GNDI, M0_dly, CLK_dly; + + lut40008 i1_2_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40026 i4_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RASr_379( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_84 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40056 i2_4_lut_adj_11( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40014 i1_2_lut_3_lut_adj_5( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_85 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40013 i2_3_lut_4_lut_adj_15( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 i2004_2_lut_rep_30( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 RBA__i2( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RBA__i1( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_86 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40009 i2_3_lut_adj_10( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40064 i1_2_lut_rep_20_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre IS_FSM__i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_87 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40040 i2_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40065 i17_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre IS_FSM__i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hCAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_88 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40009 n2452_bdd_2_lut_rep_18_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40066 FS_6__bdd_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre Bank_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0062) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40064 i1_2_lut_rep_16_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 i2_3_lut_adj_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre WRD_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_90 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40039 i2032_2_lut_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40004 i2_2_lut_rep_27( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0006 RowA_i9( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i8( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_91 ( input B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40061 i1_2_lut_rep_33( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40067 i2_4_lut_adj_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre PHI2r_376( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre PHI2r3_378( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h8C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40068 i1_2_lut_rep_32( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40069 i2_3_lut_rep_31( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre WRD_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40068 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40069 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_93 ( input B1, A1, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40070 i2060_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40019 i1512_2_lut( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre CmdUFMSDI_414( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40004 i1976_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 i5_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_95 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40061 i1_2_lut_adj_22( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 i2055_3_lut_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0006 RowA_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_96 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40018 MAin_9__I_0_427_i4_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 i2020_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 RowA_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_97 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40018 MAin_9__I_0_427_i5_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40042 i2018_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 RowA_i1( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 RowA_i0( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_98 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, M1_NOTIN, VCCI, CLK_NOTIN, M0_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40018 MAin_9__I_0_427_i1_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 MAin_9__I_0_427_i9_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre FWEr_389( .D0(M1_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + inverter M1_INVERTERIN( .I(M1_dly), .Z(M1_NOTIN)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre CBR_390( .D0(M0_NOTIN), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + inverter M0_INVERTERIN( .I(M0_dly), .Z(M0_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_99 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40018 MAin_9__I_0_427_i2_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 MAin_9__I_0_427_i8_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i7( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i6( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40072 i2_2_lut_3_lut_4_lut( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40073 i1_2_lut_4_lut_adj_7( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre IS_FSM__i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre IS_FSM__i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40072 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF0F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40073 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h08FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_101 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40018 MAin_9__I_0_427_i3_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 MAin_9__I_0_427_i7_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_102 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly; + + lut40004 i1_2_lut_adj_26( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 InitReady_bdd_3_lut( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre Bank_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre Bank_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_103 ( input C1, B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40018 MAin_9__I_0_427_i6_3_lut( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 i2_3_lut_adj_14( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre WRD_i3( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i2( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module SLICE_104 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40004 n2414_bdd_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40074 n1_bdd_4_lut( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40074 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'hF0DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_105 ( input B1, A1, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40004 i1513_2_lut( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40075 i2_3_lut_adj_20( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre WRD_i5( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre WRD_i4( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module lut40075 ( input A, B, C, D, output Z ); + + ROM16X1 #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); + + mjiobuf Dout_pad_7__713( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), + .PADI(RD7)); + + specify + (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD7) = (0:0:0,0:0:0); + (RD7 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD7, 0:0:0); + $width (negedge RD7, 0:0:0); + endspecify + +endmodule + +module mjiobuf ( input I, T, output Z, PAD, input PADI ); + + IBPU INST1( .I(PADI), .O(Z)); + OBZPU INST2( .I(I), .T(T), .O(PAD)); +endmodule + +module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); + + mjiobuf Dout_pad_6__714( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), + .PADI(RD6)); + + specify + (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD6) = (0:0:0,0:0:0); + (RD6 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD6, 0:0:0); + $width (negedge RD6, 0:0:0); + endspecify + +endmodule + +module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); + + mjiobuf Dout_pad_5__715( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), + .PADI(RD5)); + + specify + (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD5) = (0:0:0,0:0:0); + (RD5 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD5, 0:0:0); + $width (negedge RD5, 0:0:0); + endspecify + +endmodule + +module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); + + mjiobuf Dout_pad_4__716( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), + .PADI(RD4)); + + specify + (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD4) = (0:0:0,0:0:0); + (RD4 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD4, 0:0:0); + $width (negedge RD4, 0:0:0); + endspecify + +endmodule + +module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); + + mjiobuf Dout_pad_3__717( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), + .PADI(RD3)); + + specify + (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD3) = (0:0:0,0:0:0); + (RD3 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD3, 0:0:0); + $width (negedge RD3, 0:0:0); + endspecify + +endmodule + +module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); + + mjiobuf Dout_pad_2__718( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), + .PADI(RD2)); + + specify + (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD2) = (0:0:0,0:0:0); + (RD2 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD2, 0:0:0); + $width (negedge RD2, 0:0:0); + endspecify + +endmodule + +module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); + + mjiobuf Dout_pad_1__719( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), + .PADI(RD1)); + + specify + (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD1) = (0:0:0,0:0:0); + (RD1 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD1, 0:0:0); + $width (negedge RD1, 0:0:0); + endspecify + +endmodule + +module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); + + mjiobuf Dout_pad_0__720( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), + .PADI(RD0)); + + specify + (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD0) = (0:0:0,0:0:0); + (RD0 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD0, 0:0:0); + $width (negedge RD0, 0:0:0); + endspecify + +endmodule + +module Dout_7_ ( input PADDO, output Dout7 ); + wire GNDI; + + mjiobuf0076 Dout_pad_7( .I(PADDO), .T(GNDI), .PAD(Dout7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module mjiobuf0076 ( input I, T, output PAD ); + + OBZPU INST5( .I(I), .T(T), .O(PAD)); +endmodule + +module Dout_6_ ( input PADDO, output Dout6 ); + wire GNDI; + + mjiobuf0076 Dout_pad_6( .I(PADDO), .T(GNDI), .PAD(Dout6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_5_ ( input PADDO, output Dout5 ); + wire GNDI; + + mjiobuf0076 Dout_pad_5( .I(PADDO), .T(GNDI), .PAD(Dout5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_4_ ( input PADDO, output Dout4 ); + wire GNDI; + + mjiobuf0076 Dout_pad_4( .I(PADDO), .T(GNDI), .PAD(Dout4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_3_ ( input PADDO, output Dout3 ); + wire GNDI; + + mjiobuf0076 Dout_pad_3( .I(PADDO), .T(GNDI), .PAD(Dout3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_2_ ( input PADDO, output Dout2 ); + wire GNDI; + + mjiobuf0076 Dout_pad_2( .I(PADDO), .T(GNDI), .PAD(Dout2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_1_ ( input PADDO, output Dout1 ); + wire GNDI; + + mjiobuf0076 Dout_pad_1( .I(PADDO), .T(GNDI), .PAD(Dout1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_0_ ( input PADDO, output Dout0 ); + wire GNDI; + + mjiobuf0076 Dout_pad_0( .I(PADDO), .T(GNDI), .PAD(Dout0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => Dout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module LED ( input PADDO, output LED ); + wire GNDI; + + mjiobuf0076 LED_pad( .I(PADDO), .T(GNDI), .PAD(LED)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => LED) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_1_ ( input PADDO, output RBA1 ); + wire GNDI; + + mjiobuf0076 RBA_pad_1( .I(PADDO), .T(GNDI), .PAD(RBA1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RBA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RBA_0_ ( input PADDO, output RBA0 ); + wire GNDI; + + mjiobuf0076 RBA_pad_0( .I(PADDO), .T(GNDI), .PAD(RBA0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RBA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_11_ ( input PADDO, output RA11 ); + wire GNDI; + + mjiobuf0076 RA_pad_11( .I(PADDO), .T(GNDI), .PAD(RA11)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_10_ ( input PADDO, output RA10 ); + wire GNDI; + + mjiobuf0076 RA_pad_10( .I(PADDO), .T(GNDI), .PAD(RA10)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_9_ ( input PADDO, output RA9 ); + wire GNDI; + + mjiobuf0076 RA_pad_9( .I(PADDO), .T(GNDI), .PAD(RA9)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_8_ ( input PADDO, output RA8 ); + wire GNDI; + + mjiobuf0076 RA_pad_8( .I(PADDO), .T(GNDI), .PAD(RA8)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_7_ ( input PADDO, output RA7 ); + wire GNDI; + + mjiobuf0076 RA_pad_7( .I(PADDO), .T(GNDI), .PAD(RA7)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_6_ ( input PADDO, output RA6 ); + wire GNDI; + + mjiobuf0076 RA_pad_6( .I(PADDO), .T(GNDI), .PAD(RA6)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_5_ ( input PADDO, output RA5 ); + wire GNDI; + + mjiobuf0076 RA_pad_5( .I(PADDO), .T(GNDI), .PAD(RA5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_4_ ( input PADDO, output RA4 ); + wire GNDI; + + mjiobuf0076 RA_pad_4( .I(PADDO), .T(GNDI), .PAD(RA4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_3_ ( input PADDO, output RA3 ); + wire GNDI; + + mjiobuf0076 RA_pad_3( .I(PADDO), .T(GNDI), .PAD(RA3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2_ ( input PADDO, output RA2 ); + wire GNDI; + + mjiobuf0076 RA_pad_2( .I(PADDO), .T(GNDI), .PAD(RA2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_1_ ( input PADDO, output RA1 ); + wire GNDI; + + mjiobuf0076 RA_pad_1( .I(PADDO), .T(GNDI), .PAD(RA1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_0_ ( input PADDO, output RA0 ); + wire GNDI; + + mjiobuf0076 RA_pad_0( .I(PADDO), .T(GNDI), .PAD(RA0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCS ( input PADDO, output nRCS ); + wire GNDI; + + mjiobuf0076 nRCS_pad( .I(PADDO), .T(GNDI), .PAD(nRCS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RCKE ( input PADDO, output RCKE ); + wire GNDI; + + mjiobuf0076 RCKE_pad( .I(PADDO), .T(GNDI), .PAD(RCKE)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RCKE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRWE ( input PADDO, output nRWE ); + wire GNDI; + + mjiobuf0076 nRWE_pad( .I(PADDO), .T(GNDI), .PAD(nRWE)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRWE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRRAS ( input PADDO, output nRRAS ); + wire GNDI; + + mjiobuf0076 nRRAS_pad( .I(PADDO), .T(GNDI), .PAD(nRRAS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRRAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRCAS ( input PADDO, output nRCAS ); + wire GNDI; + + mjiobuf0076 nRCAS_pad( .I(PADDO), .T(GNDI), .PAD(nRCAS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nRCAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQMH ( input PADDO, output RDQMH ); + wire GNDI; + + mjiobuf0076 RDQMH_pad( .I(PADDO), .T(GNDI), .PAD(RDQMH)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RDQMH) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RDQML ( input PADDO, output RDQML ); + wire GNDI; + + mjiobuf0076 RDQML_pad( .I(PADDO), .T(GNDI), .PAD(RDQML)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => RDQML) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nUFMCS ( input PADDO, output nUFMCS ); + wire GNDI; + + mjiobuf0076 nUFMCS_pad( .I(PADDO), .T(GNDI), .PAD(nUFMCS)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => nUFMCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module UFMCLK ( input PADDO, output UFMCLK ); + wire GNDI; + + mjiobuf0076 UFMCLK_pad( .I(PADDO), .T(GNDI), .PAD(UFMCLK)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => UFMCLK) = (0:0:0,0:0:0); + endspecify + +endmodule + +module UFMSDI ( input PADDO, output UFMSDI ); + wire GNDI; + + mjiobuf0076 UFMSDI_pad( .I(PADDO), .T(GNDI), .PAD(UFMSDI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => UFMSDI) = (0:0:0,0:0:0); + endspecify + +endmodule + +module PHI2 ( output PADDI, input PHI2 ); + + mjiobuf0077 PHI2_pad( .Z(PADDI), .PAD(PHI2)); + + specify + (PHI2 => PADDI) = (0:0:0,0:0:0); + $width (posedge PHI2, 0:0:0); + $width (negedge PHI2, 0:0:0); + endspecify + +endmodule + +module mjiobuf0077 ( output Z, input PAD ); + + IBPU INST1( .I(PAD), .O(Z)); +endmodule + +module MAin_9_ ( output PADDI, input MAin9 ); + + mjiobuf0077 MAin_pad_9( .Z(PADDI), .PAD(MAin9)); + + specify + (MAin9 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin9, 0:0:0); + $width (negedge MAin9, 0:0:0); + endspecify + +endmodule + +module MAin_8_ ( output PADDI, input MAin8 ); + + mjiobuf0077 MAin_pad_8( .Z(PADDI), .PAD(MAin8)); + + specify + (MAin8 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin8, 0:0:0); + $width (negedge MAin8, 0:0:0); + endspecify + +endmodule + +module MAin_7_ ( output PADDI, input MAin7 ); + + mjiobuf0077 MAin_pad_7( .Z(PADDI), .PAD(MAin7)); + + specify + (MAin7 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin7, 0:0:0); + $width (negedge MAin7, 0:0:0); + endspecify + +endmodule + +module MAin_6_ ( output PADDI, input MAin6 ); + + mjiobuf0077 MAin_pad_6( .Z(PADDI), .PAD(MAin6)); + + specify + (MAin6 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin6, 0:0:0); + $width (negedge MAin6, 0:0:0); + endspecify + +endmodule + +module MAin_5_ ( output PADDI, input MAin5 ); + + mjiobuf0077 MAin_pad_5( .Z(PADDI), .PAD(MAin5)); + + specify + (MAin5 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin5, 0:0:0); + $width (negedge MAin5, 0:0:0); + endspecify + +endmodule + +module MAin_4_ ( output PADDI, input MAin4 ); + + mjiobuf0077 MAin_pad_4( .Z(PADDI), .PAD(MAin4)); + + specify + (MAin4 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin4, 0:0:0); + $width (negedge MAin4, 0:0:0); + endspecify + +endmodule + +module MAin_3_ ( output PADDI, input MAin3 ); + + mjiobuf0077 MAin_pad_3( .Z(PADDI), .PAD(MAin3)); + + specify + (MAin3 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin3, 0:0:0); + $width (negedge MAin3, 0:0:0); + endspecify + +endmodule + +module MAin_2_ ( output PADDI, input MAin2 ); + + mjiobuf0077 MAin_pad_2( .Z(PADDI), .PAD(MAin2)); + + specify + (MAin2 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin2, 0:0:0); + $width (negedge MAin2, 0:0:0); + endspecify + +endmodule + +module MAin_1_ ( output PADDI, input MAin1 ); + + mjiobuf0077 MAin_pad_1( .Z(PADDI), .PAD(MAin1)); + + specify + (MAin1 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin1, 0:0:0); + $width (negedge MAin1, 0:0:0); + endspecify + +endmodule + +module MAin_0_ ( output PADDI, input MAin0 ); + + mjiobuf0077 MAin_pad_0( .Z(PADDI), .PAD(MAin0)); + + specify + (MAin0 => PADDI) = (0:0:0,0:0:0); + $width (posedge MAin0, 0:0:0); + $width (negedge MAin0, 0:0:0); + endspecify + +endmodule + +module CROW_1_ ( output PADDI, input CROW1 ); + + mjiobuf0077 CROW_pad_1( .Z(PADDI), .PAD(CROW1)); + + specify + (CROW1 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW1, 0:0:0); + $width (negedge CROW1, 0:0:0); + endspecify + +endmodule + +module CROW_0_ ( output PADDI, input CROW0 ); + + mjiobuf0077 CROW_pad_0( .Z(PADDI), .PAD(CROW0)); + + specify + (CROW0 => PADDI) = (0:0:0,0:0:0); + $width (posedge CROW0, 0:0:0); + $width (negedge CROW0, 0:0:0); + endspecify + +endmodule + +module Din_7_ ( output PADDI, input Din7 ); + + mjiobuf0077 Din_pad_7( .Z(PADDI), .PAD(Din7)); + + specify + (Din7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din7, 0:0:0); + $width (negedge Din7, 0:0:0); + endspecify + +endmodule + +module Din_6_ ( output PADDI, input Din6 ); + + mjiobuf0077 Din_pad_6( .Z(PADDI), .PAD(Din6)); + + specify + (Din6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din6, 0:0:0); + $width (negedge Din6, 0:0:0); + endspecify + +endmodule + +module Din_5_ ( output PADDI, input Din5 ); + + mjiobuf0077 Din_pad_5( .Z(PADDI), .PAD(Din5)); + + specify + (Din5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din5, 0:0:0); + $width (negedge Din5, 0:0:0); + endspecify + +endmodule + +module Din_4_ ( output PADDI, input Din4 ); + + mjiobuf0077 Din_pad_4( .Z(PADDI), .PAD(Din4)); + + specify + (Din4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din4, 0:0:0); + $width (negedge Din4, 0:0:0); + endspecify + +endmodule + +module Din_3_ ( output PADDI, input Din3 ); + + mjiobuf0077 Din_pad_3( .Z(PADDI), .PAD(Din3)); + + specify + (Din3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din3, 0:0:0); + $width (negedge Din3, 0:0:0); + endspecify + +endmodule + +module Din_2_ ( output PADDI, input Din2 ); + + mjiobuf0077 Din_pad_2( .Z(PADDI), .PAD(Din2)); + + specify + (Din2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din2, 0:0:0); + $width (negedge Din2, 0:0:0); + endspecify + +endmodule + +module Din_1_ ( output PADDI, input Din1 ); + + mjiobuf0077 Din_pad_1( .Z(PADDI), .PAD(Din1)); + + specify + (Din1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din1, 0:0:0); + $width (negedge Din1, 0:0:0); + endspecify + +endmodule + +module Din_0_ ( output PADDI, input Din0 ); + + mjiobuf0077 Din_pad_0( .Z(PADDI), .PAD(Din0)); + + specify + (Din0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din0, 0:0:0); + $width (negedge Din0, 0:0:0); + endspecify + +endmodule + +module nCCAS ( output PADDI, input nCCAS ); + + mjiobuf0077 nCCAS_pad( .Z(PADDI), .PAD(nCCAS)); + + specify + (nCCAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCCAS, 0:0:0); + $width (negedge nCCAS, 0:0:0); + endspecify + +endmodule + +module nCRAS ( output PADDI, input nCRAS ); + + mjiobuf0077 nCRAS_pad( .Z(PADDI), .PAD(nCRAS)); + + specify + (nCRAS => PADDI) = (0:0:0,0:0:0); + $width (posedge nCRAS, 0:0:0); + $width (negedge nCRAS, 0:0:0); + endspecify + +endmodule + +module nFWE ( output PADDI, input nFWE ); + + mjiobuf0077 nFWE_pad( .Z(PADDI), .PAD(nFWE)); + + specify + (nFWE => PADDI) = (0:0:0,0:0:0); + $width (posedge nFWE, 0:0:0); + $width (negedge nFWE, 0:0:0); + endspecify + +endmodule + +module RCLK ( output PADDI, input RCLK ); + + mjiobuf0077 RCLK_pad( .Z(PADDI), .PAD(RCLK)); + + specify + (RCLK => PADDI) = (0:0:0,0:0:0); + $width (posedge RCLK, 0:0:0); + $width (negedge RCLK, 0:0:0); + endspecify + +endmodule + +module UFMSDO ( output PADDI, input UFMSDO ); + + mjiobuf0077 UFMSDO_pad( .Z(PADDI), .PAD(UFMSDO)); + + specify + (UFMSDO => PADDI) = (0:0:0,0:0:0); + $width (posedge UFMSDO, 0:0:0); + $width (negedge UFMSDO, 0:0:0); + endspecify + +endmodule diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html new file mode 100644 index 0000000..58e1c07 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_mrp.html @@ -0,0 +1,368 @@ + +Project Summary + + +
    
+            Lattice Mapping Report File for Design Module 'RAM2GS'
+
+
+
+Design Information
+
+Command line:   map -a MachXO -p LCMXO640C -t TQFP100 -s 3 -oc Commercial
+     RAM2GS_LCMXO640C_impl1.ngd -o RAM2GS_LCMXO640C_impl1_map.ncd -pr
+     RAM2GS_LCMXO640C_impl1.prf -mp RAM2GS_LCMXO640C_impl1.mrp -lpf D:/OneDrive/
+     Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf
+     -lpf
+     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf -c
+     0 -gui -msgset
+     D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO640CTQFP100
+Target Performance:   3
+Mapper:  mj5g00,  version:  Diamond (64-bit) 3.12.1.454
+Mapped on:  08/15/23  05:03:22
+
+
+Design Summary
+   Number of PFU registers:   102 out of   640 (16%)
+   Number of SLICEs:        71 out of   320 (22%)
+      SLICEs as Logic/ROM:     71 out of   320 (22%)
+      SLICEs as RAM:            0 out of   192 (0%)
+      SLICEs as Carry:          9 out of   320 (3%)
+   Number of LUT4s:        142 out of   640 (22%)
+      Number used as logic LUTs:        124
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       18
+      Number used as shift registers:     0
+   Number of external PIOs: 67 out of 74 (91%)
+   Number of GSRs:  0 out of 1 (0%)
+   JTAG used :      No
+   Readback used :  No
+   Oscillator used :  No
+   Startup used :   No
+   Number of TSALL: 0 out of 1 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  4
+     Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK )
+     Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
+     Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
+     Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
+   Number of Clock Enables:  13
+     Net PHI2_N_120_enable_4: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
+     Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
+     Net RCLK_c_enable_12: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_5: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_6: 2 loads, 2 LSLICEs
+     Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
+     Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs
+     Net Ready_N_292: 1 loads, 1 LSLICEs
+
+     Net RCLK_c_enable_11: 1 loads, 1 LSLICEs
+     Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs
+     Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
+   Number of LSRs:  9
+     Net RASr2: 1 loads, 1 LSLICEs
+     Net Ready: 7 loads, 7 LSLICEs
+     Net C1Submitted_N_237: 2 loads, 2 LSLICEs
+     Net n2469: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_35: 1 loads, 1 LSLICEs
+     Net n1846: 2 loads, 2 LSLICEs
+     Net LEDEN_N_82: 1 loads, 1 LSLICEs
+     Net nRowColSel_N_34: 1 loads, 1 LSLICEs
+     Net nRWE_N_177: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net Ready: 23 loads
+     Net InitReady: 17 loads
+     Net RASr2: 14 loads
+     Net nRowColSel: 13 loads
+     Net MAin_c_0: 12 loads
+     Net nRowColSel_N_35: 12 loads
+     Net Din_c_3: 11 loads
+     Net Din_c_6: 11 loads
+     Net MAin_c_1: 11 loads
+     Net Din_c_4: 10 loads
+
+
+
+
+   Number of warnings:  0
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+   No errors or warnings present.
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+------------+
+| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
+|                     |           |  IO_TYPE  | Register   |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[7]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[6]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[5]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[4]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[3]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[2]               | BIDIR     | LVCMOS33  |            |            |
+
++---------------------+-----------+-----------+------------+------------+
+| RD[1]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RD[0]               | BIDIR     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[7]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[6]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[5]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[4]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[3]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[2]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[1]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Dout[0]             | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| LED                 | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[1]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RBA[0]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[11]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[10]              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[9]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[8]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[7]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[6]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[5]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[4]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[3]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[2]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[1]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RA[0]               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCS                | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCKE                | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRWE                | OUTPUT    | LVCMOS33  |            |            |
+
++---------------------+-----------+-----------+------------+------------+
+| nRRAS               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nRCAS               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQMH               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RDQML               | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nUFMCS              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMCLK              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDI              | OUTPUT    | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| PHI2                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[9]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[8]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[7]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[6]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[5]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[4]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[3]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[2]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[1]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| MAin[0]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[1]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| CROW[0]             | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[7]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[6]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[5]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[4]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[3]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[2]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[1]              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| Din[0]              | INPUT     | LVCMOS33  |            |            |
+
++---------------------+-----------+-----------+------------+------------+
+| nCCAS               | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nCRAS               | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| nFWE                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| RCLK                | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+| UFMSDO              | INPUT     | LVCMOS33  |            |            |
++---------------------+-----------+-----------+------------+------------+
+
+
+
+Removed logic
+
+Block i2 undriven or does not drive anything - clipped.
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal nCRAS_N_9 was merged into signal nCRAS_c
+Signal nCCAS_N_3 was merged into signal nCCAS_c
+Signal PHI2_N_120 was merged into signal PHI2_c
+Signal RASr2_N_63 was merged into signal RASr2
+Signal n1426 was merged into signal nRowColSel_N_35
+Signal nRWE_N_176 was merged into signal nRWE_N_177
+Signal n1425 was merged into signal nRowColSel_N_34
+Signal nFWE_N_5 was merged into signal nFWE_c
+Signal n2477 was merged into signal Ready
+Signal GND_net undriven or does not drive anything - clipped.
+Signal VCC_net undriven or does not drive anything - clipped.
+Signal FS_610_add_4_18/CO1 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_18/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_10/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_4/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_12/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_2/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_14/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_6/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_16/CO0 undriven or does not drive anything - clipped.
+Signal FS_610_add_4_8/CO0 undriven or does not drive anything - clipped.
+Block i2135 was optimized away.
+Block i2134 was optimized away.
+Block i2136 was optimized away.
+Block RASr2_I_0_1_lut was optimized away.
+Block i1137_1_lut was optimized away.
+Block nRWE_I_50_1_lut was optimized away.
+Block i1136_1_lut was optimized away.
+Block i1_1_lut was optimized away.
+Block i637_1_lut_rep_34 was optimized away.
+Block i1 was optimized away.
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 30 MB
+        
+
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html new file mode 100644 index 0000000..3b975e0 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_pad.html @@ -0,0 +1,418 @@ + +PAD Specification File + + +
    PAD Specification File
+***************************
+
+PART TYPE:        LCMXO640C
+Performance Grade:      3
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.17
+
+Tue Aug 15 05:03:28 2023
+
+Pinout by Port Name:
++-----------+----------+---------------+-------+------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site  | Properties                   |
++-----------+----------+---------------+-------+------------------------------+
+| CROW[0]   | 32/2     | LVCMOS33_IN   | PB4C  | SLEW:FAST PULL:UP            |
+| CROW[1]   | 34/2     | LVCMOS33_IN   | PB4E  | SLEW:FAST PULL:UP            |
+| Din[0]    | 21/3     | LVCMOS33_IN   | PL10C | SLEW:FAST PULL:UP            |
+| Din[1]    | 15/3     | LVCMOS33_IN   | PL7B  | SLEW:FAST PULL:UP            |
+| Din[2]    | 14/3     | LVCMOS33_IN   | PL5B  | SLEW:FAST PULL:UP            |
+| Din[3]    | 16/3     | LVCMOS33_IN   | PL8C  | SLEW:FAST PULL:UP            |
+| Din[4]    | 18/3     | LVCMOS33_IN   | PL9A  | SLEW:FAST PULL:UP            |
+| Din[5]    | 17/3     | LVCMOS33_IN   | PL8D  | SLEW:FAST PULL:UP            |
+| Din[6]    | 20/3     | LVCMOS33_IN   | PL10A | SLEW:FAST PULL:UP            |
+| Din[7]    | 19/3     | LVCMOS33_IN   | PL9C  | SLEW:FAST PULL:UP            |
+| Dout[0]   | 1/3      | LVCMOS33_OUT  | PL2A  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[1]   | 7/3      | LVCMOS33_OUT  | PL3C  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[2]   | 8/3      | LVCMOS33_OUT  | PL3D  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[3]   | 6/3      | LVCMOS33_OUT  | PL3B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[4]   | 4/3      | LVCMOS33_OUT  | PL2D  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[5]   | 5/3      | LVCMOS33_OUT  | PL3A  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[6]   | 2/3      | LVCMOS33_OUT  | PL2C  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| Dout[7]   | 3/3      | LVCMOS33_OUT  | PL2B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| LED       | 57/1     | LVCMOS33_OUT  | PR10B | DRIVE:8mA SLEW:FAST PULL:UP  |
+| MAin[0]   | 23/3     | LVCMOS33_IN   | PL11C | SLEW:FAST PULL:UP            |
+| MAin[1]   | 38/2     | LVCMOS33_IN   | PB6B  | SLEW:FAST PULL:UP            |
+| MAin[2]   | 37/2     | LVCMOS33_IN   | PB5D  | SLEW:FAST PULL:UP            |
+| MAin[3]   | 47/2     | LVCMOS33_IN   | PB9C  | SLEW:FAST PULL:UP            |
+| MAin[4]   | 46/2     | LVCMOS33_IN   | PB9A  | SLEW:FAST PULL:UP            |
+| MAin[5]   | 45/2     | LVCMOS33_IN   | PB8D  | SLEW:FAST PULL:UP            |
+| MAin[6]   | 49/2     | LVCMOS33_IN   | PB9D  | SLEW:FAST PULL:UP            |
+| MAin[7]   | 44/2     | LVCMOS33_IN   | PB8C  | SLEW:FAST PULL:UP            |
+| MAin[8]   | 50/2     | LVCMOS33_IN   | PB9F  | SLEW:FAST PULL:UP            |
+| MAin[9]   | 51/1     | LVCMOS33_IN   | PR11D | SLEW:FAST PULL:UP            |
+| PHI2      | 39/2     | LVCMOS33_IN   | PB6C  | SLEW:FAST PULL:UP            |
+| RA[0]     | 98/0     | LVCMOS33_OUT  | PT2B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[10]    | 87/0     | LVCMOS33_OUT  | PT5A  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[11]    | 79/0     | LVCMOS33_OUT  | PT9A  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[1]     | 89/0     | LVCMOS33_OUT  | PT4F  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[2]     | 94/0     | LVCMOS33_OUT  | PT3B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[3]     | 97/0     | LVCMOS33_OUT  | PT2E  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[4]     | 99/0     | LVCMOS33_OUT  | PT2C  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[5]     | 95/0     | LVCMOS33_OUT  | PT3A  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[6]     | 91/0     | LVCMOS33_OUT  | PT3F  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[7]     | 100/0    | LVCMOS33_OUT  | PT2A  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[8]     | 96/0     | LVCMOS33_OUT  | PT2F  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RA[9]     | 85/0     | LVCMOS33_OUT  | PT6B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RBA[0]    | 63/1     | LVCMOS33_OUT  | PR7B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RBA[1]    | 83/0     | LVCMOS33_OUT  | PT7A  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RCKE      | 82/0     | LVCMOS33_OUT  | PT7E  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RCLK      | 86/0     | LVCMOS33_IN   | PT5B  | SLEW:FAST PULL:UP            |
+| RDQMH     | 76/0     | LVCMOS33_OUT  | PT9F  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RDQML     | 61/1     | LVCMOS33_OUT  | PR9B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[0]     | 64/1     | LVCMOS33_BIDI | PR6C  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[1]     | 65/1     | LVCMOS33_BIDI | PR6B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[2]     | 66/1     | LVCMOS33_BIDI | PR5D  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[3]     | 67/1     | LVCMOS33_BIDI | PR5B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[4]     | 68/1     | LVCMOS33_BIDI | PR4D  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[5]     | 69/1     | LVCMOS33_BIDI | PR4B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[6]     | 70/1     | LVCMOS33_BIDI | PR3D  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| RD[7]     | 71/1     | LVCMOS33_BIDI | PR3B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| UFMCLK    | 58/1     | LVCMOS33_OUT  | PR10A | DRIVE:8mA SLEW:FAST PULL:UP  |
+| UFMSDI    | 56/1     | LVCMOS33_OUT  | PR10C | DRIVE:8mA SLEW:FAST PULL:UP  |
+| UFMSDO    | 55/1     | LVCMOS33_IN   | PR10D | SLEW:FAST PULL:UP            |
+| nCCAS     | 27/2     | LVCMOS33_IN   | PB2C  | SLEW:FAST PULL:UP            |
+| nCRAS     | 43/2     | LVCMOS33_IN   | PB8B  | SLEW:FAST PULL:UP            |
+| nFWE      | 22/3     | LVCMOS33_IN   | PL11A | SLEW:FAST PULL:UP            |
+| nRCAS     | 78/0     | LVCMOS33_OUT  | PT9C  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| nRCS      | 77/0     | LVCMOS33_OUT  | PT9E  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| nRRAS     | 73/1     | LVCMOS33_OUT  | PR2B  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| nRWE      | 72/1     | LVCMOS33_OUT  | PR2D  | DRIVE:8mA SLEW:FAST PULL:UP  |
+| nUFMCS    | 53/1     | LVCMOS33_OUT  | PR11C | DRIVE:8mA SLEW:FAST PULL:UP  |
++-----------+----------+---------------+-------+------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    |       |
+| 3    | 3.3V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+---------------------+------------+---------------+-------+---------------+
+| Pin/Bank | Pin Info            | Preference | Buffer Type   | Site  | Dual Function |
++----------+---------------------+------------+---------------+-------+---------------+
+| 1/3      | Dout[0]             | LOCATED    | LVCMOS33_OUT  | PL2A  |               |
+| 2/3      | Dout[6]             | LOCATED    | LVCMOS33_OUT  | PL2C  |               |
+| 3/3      | Dout[7]             | LOCATED    | LVCMOS33_OUT  | PL2B  |               |
+| 4/3      | Dout[4]             | LOCATED    | LVCMOS33_OUT  | PL2D  |               |
+| 5/3      | Dout[5]             | LOCATED    | LVCMOS33_OUT  | PL3A  |               |
+| 6/3      | Dout[3]             | LOCATED    | LVCMOS33_OUT  | PL3B  |               |
+| 7/3      | Dout[1]             | LOCATED    | LVCMOS33_OUT  | PL3C  |               |
+| 8/3      | Dout[2]             | LOCATED    | LVCMOS33_OUT  | PL3D  |               |
+| 9/3      |     unused, PULL:UP |            |               | PL4A  |               |
+| 11/3     |     unused, PULL:UP |            |               | PL4C  |               |
+| 13/3     |     unused, PULL:UP |            |               | PL4D  |               |
+| 14/3     | Din[2]              | LOCATED    | LVCMOS33_IN   | PL5B  | GSR_PADN      |
+| 15/3     | Din[1]              | LOCATED    | LVCMOS33_IN   | PL7B  |               |
+| 16/3     | Din[3]              | LOCATED    | LVCMOS33_IN   | PL8C  | TSALLPAD      |
+| 17/3     | Din[5]              | LOCATED    | LVCMOS33_IN   | PL8D  |               |
+| 18/3     | Din[4]              | LOCATED    | LVCMOS33_IN   | PL9A  |               |
+| 19/3     | Din[7]              | LOCATED    | LVCMOS33_IN   | PL9C  |               |
+| 20/3     | Din[6]              | LOCATED    | LVCMOS33_IN   | PL10A |               |
+| 21/3     | Din[0]              | LOCATED    | LVCMOS33_IN   | PL10C |               |
+| 22/3     | nFWE                | LOCATED    | LVCMOS33_IN   | PL11A |               |
+| 23/3     | MAin[0]             | LOCATED    | LVCMOS33_IN   | PL11C |               |
+| 27/2     | nCCAS               | LOCATED    | LVCMOS33_IN   | PB2C  |               |
+| 32/2     | CROW[0]             | LOCATED    | LVCMOS33_IN   | PB4C  |               |
+| 34/2     | CROW[1]             | LOCATED    | LVCMOS33_IN   | PB4E  |               |
+| 36/2     |     unused, PULL:UP |            |               | PB5B  | PCLKT2_1      |
+| 37/2     | MAin[2]             | LOCATED    | LVCMOS33_IN   | PB5D  |               |
+| 38/2     | MAin[1]             | LOCATED    | LVCMOS33_IN   | PB6B  | PCLKT2_0      |
+| 39/2     | PHI2                | LOCATED    | LVCMOS33_IN   | PB6C  |               |
+| 43/2     | nCRAS               | LOCATED    | LVCMOS33_IN   | PB8B  |               |
+| 44/2     | MAin[7]             | LOCATED    | LVCMOS33_IN   | PB8C  |               |
+| 45/2     | MAin[5]             | LOCATED    | LVCMOS33_IN   | PB8D  |               |
+| 46/2     | MAin[4]             | LOCATED    | LVCMOS33_IN   | PB9A  |               |
+| 47/2     | MAin[3]             | LOCATED    | LVCMOS33_IN   | PB9C  |               |
+| 49/2     | MAin[6]             | LOCATED    | LVCMOS33_IN   | PB9D  |               |
+| 50/2     | MAin[8]             | LOCATED    | LVCMOS33_IN   | PB9F  |               |
+| 51/1     | MAin[9]             | LOCATED    | LVCMOS33_IN   | PR11D |               |
+| 52/1     |     unused, PULL:UP |            |               | PR11B |               |
+| 53/1     | nUFMCS              | LOCATED    | LVCMOS33_OUT  | PR11C |               |
+| 54/1     |     unused, PULL:UP |            |               | PR11A |               |
+| 55/1     | UFMSDO              | LOCATED    | LVCMOS33_IN   | PR10D |               |
+| 56/1     | UFMSDI              | LOCATED    | LVCMOS33_OUT  | PR10C |               |
+| 57/1     | LED                 | LOCATED    | LVCMOS33_OUT  | PR10B |               |
+| 58/1     | UFMCLK              | LOCATED    | LVCMOS33_OUT  | PR10A |               |
+| 59/1     |     unused, PULL:UP |            |               | PR9D  |               |
+| 61/1     | RDQML               | LOCATED    | LVCMOS33_OUT  | PR9B  |               |
+| 63/1     | RBA[0]              | LOCATED    | LVCMOS33_OUT  | PR7B  |               |
+| 64/1     | RD[0]               | LOCATED    | LVCMOS33_BIDI | PR6C  |               |
+| 65/1     | RD[1]               | LOCATED    | LVCMOS33_BIDI | PR6B  |               |
+| 66/1     | RD[2]               | LOCATED    | LVCMOS33_BIDI | PR5D  |               |
+| 67/1     | RD[3]               | LOCATED    | LVCMOS33_BIDI | PR5B  |               |
+| 68/1     | RD[4]               | LOCATED    | LVCMOS33_BIDI | PR4D  |               |
+| 69/1     | RD[5]               | LOCATED    | LVCMOS33_BIDI | PR4B  |               |
+| 70/1     | RD[6]               | LOCATED    | LVCMOS33_BIDI | PR3D  |               |
+| 71/1     | RD[7]               | LOCATED    | LVCMOS33_BIDI | PR3B  |               |
+| 72/1     | nRWE                | LOCATED    | LVCMOS33_OUT  | PR2D  |               |
+| 73/1     | nRRAS               | LOCATED    | LVCMOS33_OUT  | PR2B  |               |
+| 76/0     | RDQMH               | LOCATED    | LVCMOS33_OUT  | PT9F  |               |
+| 77/0     | nRCS                | LOCATED    | LVCMOS33_OUT  | PT9E  |               |
+| 78/0     | nRCAS               | LOCATED    | LVCMOS33_OUT  | PT9C  |               |
+| 79/0     | RA[11]              | LOCATED    | LVCMOS33_OUT  | PT9A  |               |
+| 82/0     | RCKE                | LOCATED    | LVCMOS33_OUT  | PT7E  | D7            |
+| 83/0     | RBA[1]              | LOCATED    | LVCMOS33_OUT  | PT7A  | D6            |
+| 85/0     | RA[9]               | LOCATED    | LVCMOS33_OUT  | PT6B  | PCLKT0_1      |
+| 86/0     | RCLK                | LOCATED    | LVCMOS33_IN   | PT5B  | PCLKT0_0      |
+| 87/0     | RA[10]              | LOCATED    | LVCMOS33_OUT  | PT5A  |               |
+| 89/0     | RA[1]               | LOCATED    | LVCMOS33_OUT  | PT4F  |               |
+| 91/0     | RA[6]               | LOCATED    | LVCMOS33_OUT  | PT3F  | D3            |
+| 94/0     | RA[2]               | LOCATED    | LVCMOS33_OUT  | PT3B  |               |
+| 95/0     | RA[5]               | LOCATED    | LVCMOS33_OUT  | PT3A  |               |
+| 96/0     | RA[8]               | LOCATED    | LVCMOS33_OUT  | PT2F  | D2            |
+| 97/0     | RA[3]               | LOCATED    | LVCMOS33_OUT  | PT2E  |               |
+| 98/0     | RA[0]               | LOCATED    | LVCMOS33_OUT  | PT2B  | D1            |
+| 99/0     | RA[4]               | LOCATED    | LVCMOS33_OUT  | PT2C  |               |
+| 100/0    | RA[7]               | LOCATED    | LVCMOS33_OUT  | PT2A  |               |
+| PB2A/2   |     unused, PULL:UP |            |               | PB2A  |               |
+| PB2B/2   |     unused, PULL:UP |            |               | PB2B  |               |
+| PB2D/2   |     unused, PULL:UP |            |               | PB2D  |               |
+| PB3A/2   |     unused, PULL:UP |            |               | PB3A  |               |
+| PB3B/2   |     unused, PULL:UP |            |               | PB3B  |               |
+| PB3C/2   |     unused, PULL:UP |            |               | PB3C  |               |
+| PB3D/2   |     unused, PULL:UP |            |               | PB3D  |               |
+| PB4A/2   |     unused, PULL:UP |            |               | PB4A  |               |
+| PB4B/2   |     unused, PULL:UP |            |               | PB4B  |               |
+| PB4D/2   |     unused, PULL:UP |            |               | PB4D  |               |
+| PB4F/2   |     unused, PULL:UP |            |               | PB4F  |               |
+| PB5A/2   |     unused, PULL:UP |            |               | PB5A  |               |
+| PB5C/2   |     unused, PULL:UP |            |               | PB5C  |               |
+| PB6A/2   |     unused, PULL:UP |            |               | PB6A  |               |
+| PB6D/2   |     unused, PULL:UP |            |               | PB6D  |               |
+| PB7A/2   |     unused, PULL:UP |            |               | PB7A  |               |
+| PB7B/2   |     unused, PULL:UP |            |               | PB7B  |               |
+| PB7C/2   |     unused, PULL:UP |            |               | PB7C  |               |
+| PB7D/2   |     unused, PULL:UP |            |               | PB7D  |               |
+| PB7E/2   |     unused, PULL:UP |            |               | PB7E  |               |
+| PB7F/2   |     unused, PULL:UP |            |               | PB7F  |               |
+| PB8A/2   |     unused, PULL:UP |            |               | PB8A  |               |
+| PB9B/2   |     unused, PULL:UP |            |               | PB9B  |               |
+| PB9E/0   |     unused, PULL:UP |            |               | PB9E  |               |
+| PL4B/3   |     unused, PULL:UP |            |               | PL4B  |               |
+| PL5A/3   |     unused, PULL:UP |            |               | PL5A  |               |
+| PL5C/3   |     unused, PULL:UP |            |               | PL5C  |               |
+| PL5D/3   |     unused, PULL:UP |            |               | PL5D  |               |
+| PL6A/3   |     unused, PULL:UP |            |               | PL6A  |               |
+| PL6B/3   |     unused, PULL:UP |            |               | PL6B  |               |
+| PL6C/3   |     unused, PULL:UP |            |               | PL6C  |               |
+| PL6D/3   |     unused, PULL:UP |            |               | PL6D  |               |
+| PL7A/3   |     unused, PULL:UP |            |               | PL7A  |               |
+| PL7C/3   |     unused, PULL:UP |            |               | PL7C  |               |
+| PL7D/3   |     unused, PULL:UP |            |               | PL7D  |               |
+| PL8A/3   |     unused, PULL:UP |            |               | PL8A  |               |
+| PL8B/3   |     unused, PULL:UP |            |               | PL8B  |               |
+| PL9B/3   |     unused, PULL:UP |            |               | PL9B  |               |
+| PL9D/3   |     unused, PULL:UP |            |               | PL9D  |               |
+| PL10B/3  |     unused, PULL:UP |            |               | PL10B |               |
+| PL10D/3  |     unused, PULL:UP |            |               | PL10D |               |
+| PL11B/3  |     unused, PULL:UP |            |               | PL11B |               |
+| PL11D/3  |     unused, PULL:UP |            |               | PL11D |               |
+| PR2A/1   |     unused, PULL:UP |            |               | PR2A  |               |
+| PR2C/1   |     unused, PULL:UP |            |               | PR2C  |               |
+| PR3A/1   |     unused, PULL:UP |            |               | PR3A  |               |
+| PR3C/1   |     unused, PULL:UP |            |               | PR3C  |               |
+| PR4A/1   |     unused, PULL:UP |            |               | PR4A  |               |
+| PR4C/1   |     unused, PULL:UP |            |               | PR4C  |               |
+| PR5A/1   |     unused, PULL:UP |            |               | PR5A  |               |
+| PR5C/1   |     unused, PULL:UP |            |               | PR5C  |               |
+| PR6A/1   |     unused, PULL:UP |            |               | PR6A  |               |
+| PR6D/1   |     unused, PULL:UP |            |               | PR6D  |               |
+| PR7A/1   |     unused, PULL:UP |            |               | PR7A  |               |
+| PR7C/1   |     unused, PULL:UP |            |               | PR7C  |               |
+| PR7D/1   |     unused, PULL:UP |            |               | PR7D  |               |
+| PR8A/1   |     unused, PULL:UP |            |               | PR8A  |               |
+| PR8B/1   |     unused, PULL:UP |            |               | PR8B  |               |
+| PR8C/1   |     unused, PULL:UP |            |               | PR8C  |               |
+| PR8D/1   |     unused, PULL:UP |            |               | PR8D  |               |
+| PR9A/1   |     unused, PULL:UP |            |               | PR9A  |               |
+| PR9C/1   |     unused, PULL:UP |            |               | PR9C  |               |
+| PT2D/0   |     unused, PULL:UP |            |               | PT2D  |               |
+| PT3C/0   |     unused, PULL:UP |            |               | PT3C  |               |
+| PT3D/0   |     unused, PULL:UP |            |               | PT3D  |               |
+| PT3E/0   |     unused, PULL:UP |            |               | PT3E  |               |
+| PT4A/0   |     unused, PULL:UP |            |               | PT4A  |               |
+| PT4B/0   |     unused, PULL:UP |            |               | PT4B  |               |
+| PT4C/0   |     unused, PULL:UP |            |               | PT4C  |               |
+| PT4D/0   |     unused, PULL:UP |            |               | PT4D  |               |
+| PT4E/0   |     unused, PULL:UP |            |               | PT4E  |               |
+| PT5C/0   |     unused, PULL:UP |            |               | PT5C  |               |
+| PT5D/0   |     unused, PULL:UP |            |               | PT5D  |               |
+| PT6A/0   |     unused, PULL:UP |            |               | PT6A  |               |
+| PT6C/0   |     unused, PULL:UP |            |               | PT6C  |               |
+| PT6D/0   |     unused, PULL:UP |            |               | PT6D  |               |
+| PT7B/0   |     unused, PULL:UP |            |               | PT7B  |               |
+| PT7C/0   |     unused, PULL:UP |            |               | PT7C  |               |
+| PT7D/0   |     unused, PULL:UP |            |               | PT7D  |               |
+| PT7F/0   |     unused, PULL:UP |            |               | PT7F  |               |
+| PT8A/0   |     unused, PULL:UP |            |               | PT8A  |               |
+| PT8B/0   |     unused, PULL:UP |            |               | PT8B  |               |
+| PT8C/0   |     unused, PULL:UP |            |               | PT8C  |               |
+| PT8D/0   |     unused, PULL:UP |            |               | PT8D  |               |
+| PT9B/0   |     unused, PULL:UP |            |               | PT9B  |               |
+| PT9D/0   |     unused, PULL:UP |            |               | PT9D  |               |
+| TCK/2    |                     |            |               | TCK   | TCK           |
+| TDI/2    |                     |            |               | TDI   | TDID0         |
+| TDO/2    |                     |            |               | TDO   | TDO           |
+| TMS/2    |                     |            |               | TMS   | TMS           |
++----------+---------------------+------------+---------------+-------+---------------+
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "CROW[0]"  SITE  "32";
+LOCATE  COMP  "CROW[1]"  SITE  "34";
+LOCATE  COMP  "Din[0]"  SITE  "21";
+LOCATE  COMP  "Din[1]"  SITE  "15";
+LOCATE  COMP  "Din[2]"  SITE  "14";
+LOCATE  COMP  "Din[3]"  SITE  "16";
+LOCATE  COMP  "Din[4]"  SITE  "18";
+LOCATE  COMP  "Din[5]"  SITE  "17";
+LOCATE  COMP  "Din[6]"  SITE  "20";
+LOCATE  COMP  "Din[7]"  SITE  "19";
+LOCATE  COMP  "Dout[0]"  SITE  "1";
+LOCATE  COMP  "Dout[1]"  SITE  "7";
+LOCATE  COMP  "Dout[2]"  SITE  "8";
+LOCATE  COMP  "Dout[3]"  SITE  "6";
+LOCATE  COMP  "Dout[4]"  SITE  "4";
+LOCATE  COMP  "Dout[5]"  SITE  "5";
+LOCATE  COMP  "Dout[6]"  SITE  "2";
+LOCATE  COMP  "Dout[7]"  SITE  "3";
+LOCATE  COMP  "LED"  SITE  "57";
+LOCATE  COMP  "MAin[0]"  SITE  "23";
+LOCATE  COMP  "MAin[1]"  SITE  "38";
+LOCATE  COMP  "MAin[2]"  SITE  "37";
+LOCATE  COMP  "MAin[3]"  SITE  "47";
+LOCATE  COMP  "MAin[4]"  SITE  "46";
+LOCATE  COMP  "MAin[5]"  SITE  "45";
+LOCATE  COMP  "MAin[6]"  SITE  "49";
+LOCATE  COMP  "MAin[7]"  SITE  "44";
+LOCATE  COMP  "MAin[8]"  SITE  "50";
+LOCATE  COMP  "MAin[9]"  SITE  "51";
+LOCATE  COMP  "PHI2"  SITE  "39";
+LOCATE  COMP  "RA[0]"  SITE  "98";
+LOCATE  COMP  "RA[10]"  SITE  "87";
+LOCATE  COMP  "RA[11]"  SITE  "79";
+LOCATE  COMP  "RA[1]"  SITE  "89";
+LOCATE  COMP  "RA[2]"  SITE  "94";
+LOCATE  COMP  "RA[3]"  SITE  "97";
+LOCATE  COMP  "RA[4]"  SITE  "99";
+LOCATE  COMP  "RA[5]"  SITE  "95";
+LOCATE  COMP  "RA[6]"  SITE  "91";
+LOCATE  COMP  "RA[7]"  SITE  "100";
+LOCATE  COMP  "RA[8]"  SITE  "96";
+LOCATE  COMP  "RA[9]"  SITE  "85";
+LOCATE  COMP  "RBA[0]"  SITE  "63";
+LOCATE  COMP  "RBA[1]"  SITE  "83";
+LOCATE  COMP  "RCKE"  SITE  "82";
+LOCATE  COMP  "RCLK"  SITE  "86";
+LOCATE  COMP  "RDQMH"  SITE  "76";
+LOCATE  COMP  "RDQML"  SITE  "61";
+LOCATE  COMP  "RD[0]"  SITE  "64";
+LOCATE  COMP  "RD[1]"  SITE  "65";
+LOCATE  COMP  "RD[2]"  SITE  "66";
+LOCATE  COMP  "RD[3]"  SITE  "67";
+LOCATE  COMP  "RD[4]"  SITE  "68";
+LOCATE  COMP  "RD[5]"  SITE  "69";
+LOCATE  COMP  "RD[6]"  SITE  "70";
+LOCATE  COMP  "RD[7]"  SITE  "71";
+LOCATE  COMP  "UFMCLK"  SITE  "58";
+LOCATE  COMP  "UFMSDI"  SITE  "56";
+LOCATE  COMP  "UFMSDO"  SITE  "55";
+LOCATE  COMP  "nCCAS"  SITE  "27";
+LOCATE  COMP  "nCRAS"  SITE  "43";
+LOCATE  COMP  "nFWE"  SITE  "22";
+LOCATE  COMP  "nRCAS"  SITE  "78";
+LOCATE  COMP  "nRCS"  SITE  "77";
+LOCATE  COMP  "nRRAS"  SITE  "73";
+LOCATE  COMP  "nRWE"  SITE  "72";
+LOCATE  COMP  "nUFMCS"  SITE  "53";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:28 2023
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html new file mode 100644 index 0000000..d480245 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_par.html @@ -0,0 +1,321 @@ + +Place & Route Report + + +
    PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:25 2023
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO640C_impl1.p2t
+RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir
+RAM2GS_LCMXO640C_impl1.prf -gui -msgset
+D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml
+
+
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            -9.822       909228       0.273        0            04           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 4 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd"
+Tue Aug 15 05:03:25 2023
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf
+Preference file: RAM2GS_LCMXO640C_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)      67/159          42% used
+                     67/74           90% bonded
+   SLICE             71/320          22% used
+
+
+
+Number of Signals: 262
+Number of Connections: 662
+
+Pin Constraint Summary:
+   67 out of 67 pins locked (100% locked).
+
+The following 2 signals are selected to use the primary clock routing resources:
+    RCLK_c (driver: RCLK, clk load #: 40)
+    PHI2_c (driver: PHI2, clk load #: 13)
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0)
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+.........
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+.........
+Placer score = 1223575.
+Finished Placer Phase 1.  REAL time: 3 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  1220793
+Finished Placer Phase 2.  REAL time: 3 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 1 out of 4 (25%)
+  General PIO: 1 out of 160 (0%)
+
+Global Clocks:
+  PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 40
+  PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 13
+  SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 7, ce load = 0, sr load = 0
+
+  PRIMARY  : 2 out of 4 (50%)
+  SECONDARY: 1 out of 4 (25%)
+
+
+
+
+I/O Usage Summary (final):
+   67 out of 159 (42.1%) PIO sites used.
+   67 out of 74 (90.5%) bonded PIO sites used.
+   Number of PIO comps: 67; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+------------+------------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
++----------+----------------+------------+------------+------------+
+| 0        | 18 / 18 (100%) | 3.3V       | -          | -          |
+| 1        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
+| 2        | 13 / 14 ( 92%) | -          | -          | -          |
+| 3        | 18 / 21 ( 85%) | 3.3V       | -          | -          |
++----------+----------------+------------+------------+------------+
+
+Total placer CPU time: 3 secs 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+0 connections routed; 662 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks.  This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
+WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks.  This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew.
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=7 clock_loads=4
+
+Completed router resource preassignment. Real time: 3 secs 
+
+Start NBR router at 05:03:28 08/15/23
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 05:03:28 08/15/23
+
+Start NBR section for initial routing at 05:03:28 08/15/23
+Level 1, iteration 1
+0(0.00%) conflict; 559(84.44%) untouched conns; 717961 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.776ns/-717.961ns; real time: 3 secs 
+Level 2, iteration 1
+7(0.03%) conflicts; 496(74.92%) untouched conns; 699022 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-699.022ns; real time: 3 secs 
+Level 3, iteration 1
+9(0.03%) conflicts; 252(38.07%) untouched conns; 765745 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-765.746ns; real time: 3 secs 
+Level 4, iteration 1
+9(0.03%) conflicts; 0(0.00%) untouched conn; 781820 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-781.821ns; real time: 4 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 05:03:29 08/15/23
+Level 4, iteration 1
+5(0.02%) conflicts; 0(0.00%) untouched conn; 781048 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-781.049ns; real time: 4 secs 
+Level 4, iteration 2
+4(0.01%) conflicts; 0(0.00%) untouched conn; 780690 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-780.691ns; real time: 4 secs 
+Level 4, iteration 3
+4(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-780.716ns; real time: 4 secs 
+Level 4, iteration 4
+2(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-780.716ns; real time: 4 secs 
+Level 4, iteration 5
+2(0.01%) conflicts; 0(0.00%) untouched conn; 783401 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-783.402ns; real time: 4 secs 
+Level 4, iteration 6
+0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-783.402ns; real time: 4 secs 
+
+Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-783.402ns; real time: 4 secs 
+
+Start NBR section for re-routing at 05:03:29 08/15/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 776978 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: -9.822ns/-776.979ns; real time: 4 secs 
+
+Start NBR section for post-routing at 05:03:29 08/15/23
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 260 (39.27%)
+  Estimated worst slack<setup> : -9.822ns
+  Timing score<setup> : 909228
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
+   Signal=nCCAS_c loads=7 clock_loads=4
+
+Total CPU time 4 secs 
+Total REAL time: 4 secs 
+Completely routed.
+End of route.  662 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 909228 
+
+Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = -9.822
+PAR_SUMMARY::Timing score<setup/<ns>> = 909.228
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.273
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 4 secs 
+Total REAL time to completion: 4 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html new file mode 100644 index 0000000..e2f5eb9 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_summary.html @@ -0,0 +1,83 @@ + +Project Summary + + +
    
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
    RAM2GS_LCMXO640C project summary
    Module Name:RAM2GS_LCMXO640CSynthesis:Lattice LSE
    Implementation Name:impl1Strategy Name:Strategy1
    Last Process:JEDEC FileState:Passed
    Target Device:LCMXO640C-3T100CDevice Family:MachXO
    Device Type:LCMXO640CPackage Type:TQFP100
    Performance grade:3Operating conditions:COM
    Logic preference file:RAM2GS_LCMXO640C.lpf
    Physical Preference file:impl1/RAM2GS_LCMXO640C_impl1.prf
    Product Version:3.12.1.454Patch Version:
    Updated:2023/08/15 05:03:36
    Implementation Location:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1
    Project File:D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html new file mode 100644 index 0000000..4f20fac --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_tw1.html @@ -0,0 +1,434 @@ + +Lattice Map TRACE Report + + +
    Map TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo640c_impl1_map.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:23 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1_map.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,3
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 283.768000 MHz (213 errors)
    • 
+                383 items scored, 213 timing errors detected.
+Warning: 116.104MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY NET "PHI2_c" 120.077000 MHz (97 errors)
    • 
+                106 items scored, 97 timing errors detected.
+Warning:  42.739MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+            383 items scored, 213 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 5.089ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i14  (from RCLK_c +)
+   Destination:    FF         Data in        n8MEGEN_418  (to RCLK_c +)
+
+   Delay:               8.369ns  (24.4% logic, 75.6% route), 5 logic levels.
+
+ Constraint Details:
+
+      8.369ns physical path delay SLICE_1 to SLICE_56 exceeds
+      3.524ns delay constraint less
+      0.244ns CE_SET requirement (totaling 3.280ns) by 5.089ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_56:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560    SLICE_1.CLK to     SLICE_1.Q0 SLICE_1 (from RCLK_c)
+ROUTE         5   e 1.441     SLICE_1.Q0 to    SLICE_90.C1 FS_14
+CTOF_DEL    ---     0.371    SLICE_90.C1 to    SLICE_90.F1 SLICE_90
+ROUTE         1   e 1.441    SLICE_90.F1 to    SLICE_75.B0 n2328
+CTOF_DEL    ---     0.371    SLICE_75.B0 to    SLICE_75.F0 SLICE_75
+ROUTE         2   e 1.441    SLICE_75.F0 to    SLICE_87.B1 n2214
+CTOF_DEL    ---     0.371    SLICE_87.B1 to    SLICE_87.F1 SLICE_87
+ROUTE         1   e 0.561    SLICE_87.F1 to    SLICE_87.A0 n7
+CTOF_DEL    ---     0.371    SLICE_87.A0 to    SLICE_87.F0 SLICE_87
+ROUTE         1   e 1.441    SLICE_87.F0 to    SLICE_56.CE RCLK_c_enable_11 (to RCLK_c)
+                  --------
+                    8.369   (24.4% logic, 75.6% route), 5 logic levels.
+
+Warning: 116.104MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+            106 items scored, 97 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 7.535ns (weighted slack = -15.070ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:              11.061ns  (21.8% logic, 78.2% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.061ns physical path delay SLICE_88 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 7.535ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560   SLICE_88.CLK to    SLICE_88.Q0 SLICE_88 (from PHI2_c)
+ROUTE         1   e 1.441    SLICE_88.Q0 to    SLICE_97.D0 Bank_0
+CTOF_DEL    ---     0.371    SLICE_97.D0 to    SLICE_97.F0 SLICE_97
+ROUTE         1   e 1.441    SLICE_97.F0 to    SLICE_81.B0 n2314
+CTOF_DEL    ---     0.371    SLICE_81.B0 to    SLICE_81.F0 SLICE_81
+ROUTE         1   e 1.441    SLICE_81.F0 to    SLICE_18.B1 n26
+CTOF_DEL    ---     0.371    SLICE_18.B1 to    SLICE_18.F1 SLICE_18
+ROUTE         8   e 1.441    SLICE_18.F1 to    SLICE_89.B0 n1326
+CTOF_DEL    ---     0.371    SLICE_89.B0 to    SLICE_89.F0 SLICE_89
+ROUTE         1   e 1.441    SLICE_89.F0 to    SLICE_79.C0 n1280
+CTOF_DEL    ---     0.371    SLICE_79.C0 to    SLICE_79.F0 SLICE_79
+ROUTE         2   e 1.441    SLICE_79.F0 to   SLICE_14.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                   11.061   (21.8% logic, 78.2% route), 6 logic levels.
+
+Warning:  42.739MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 283.768000 MHz ; |  283.768 MHz|  116.104 MHz|   5 *
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 120.077000 MHz ; |  120.077 MHz|   42.739 MHz|   6 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+2 preferences(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+n1326                                   |       8|      96|     30.97%
+                                        |        |        |
+n26                                     |       1|      72|     23.23%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 310  Score: 1346529
+Cumulative negative slack: 874289
+
+Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:23 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1_map.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 283.768000 MHz (0 errors)
    •             383 items scored, 0 timing errors detected.
+
+
  • FREQUENCY NET "PHI2_c" 120.077000 MHz (0 errors)
    •             106 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+            383 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.342ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.325ns  (38.8% logic, 61.2% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.325ns physical path delay SLICE_100 to SLICE_100 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns
+
+ Physical Path Details:
+
+      Data path SLICE_100 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126  SLICE_100.CLK to   SLICE_100.Q0 SLICE_100 (from RCLK_c)
+ROUTE         1   e 0.199   SLICE_100.Q0 to   SLICE_100.M1 n736 (to RCLK_c)
+                  --------
+                    0.325   (38.8% logic, 61.2% route), 1 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+            106 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.430ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.411ns  (51.3% logic, 48.7% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.411ns physical path delay SLICE_14 to SLICE_14 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.019ns) by 0.430ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137   SLICE_14.CLK to    SLICE_14.Q0 SLICE_14 (from PHI2_c)
+ROUTE         2   e 0.199    SLICE_14.Q0 to    SLICE_14.C0 C1Submitted
+CTOF_DEL    ---     0.074    SLICE_14.C0 to    SLICE_14.F0 SLICE_14
+ROUTE         1   e 0.001    SLICE_14.F0 to   SLICE_14.DI0 n6_adj_3 (to PHI2_c)
+                  --------
+                    0.411   (51.3% logic, 48.7% route), 2 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 283.768000 MHz ; |     0.000 ns|     0.342 ns|   1  
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 120.077000 MHz ; |     0.000 ns|     0.430 ns|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 310 (setup), 0 (hold)
+Score: 1346529 (setup), 0 (hold)
+Cumulative negative slack: 874289 (874289+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html new file mode 100644 index 0000000..eb0175c --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1_twr.html @@ -0,0 +1,2242 @@ + +Lattice TRACE Report + + +
    Place & Route TRACE Report
+
+Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd.
+Design name: RAM2GS
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO640C
+Package:     TQFP100
+Performance: 3
+Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Performance Hardware Data Status: Version 1.124.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:29 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,3
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 283.768000 MHz (233 errors)
    • 
+                383 items scored, 233 timing errors detected.
+Warning: 116.198MHz is the maximum frequency for this preference.
+
+
  • FREQUENCY NET "PHI2_c" 120.077000 MHz (95 errors)
    • 
+                106 items scored, 95 timing errors detected.
+Warning:  55.096MHz is the maximum frequency for this preference.
+
+Report Type:     based on TRACE automatically generated preferences
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+            383 items scored, 233 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 5.082ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i13  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI_417  (to RCLK_c +)
+
+   Delay:               7.980ns  (21.0% logic, 79.0% route), 4 logic levels.
+
+ Constraint Details:
+
+      7.980ns physical path delay SLICE_3 to SLICE_44 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.626ns LSR_SET requirement (totaling 2.898ns) by 5.082ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5C.CLK to       R3C5C.Q1 SLICE_3 (from RCLK_c)
+ROUTE         3     1.372       R3C5C.Q1 to       R3C2D.C1 FS_13
+CTOF_DEL    ---     0.371       R3C2D.C1 to       R3C2D.F1 SLICE_94
+ROUTE         3     1.278       R3C2D.F1 to       R4C5B.D1 n2272
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_78
+ROUTE         3     0.528       R4C5B.F1 to       R4C5B.C0 n2464
+CTOF_DEL    ---     0.371       R4C5B.C0 to       R4C5B.F0 SLICE_78
+ROUTE         2     3.129       R4C5B.F0 to      R9C9C.LSR n1846 (to RCLK_c)
+                  --------
+                    7.980   (21.0% logic, 79.0% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C5C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R9C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.998ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI_417  (to RCLK_c +)
+
+   Delay:               7.896ns  (21.2% logic, 78.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      7.896ns physical path delay SLICE_3 to SLICE_44 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.626ns LSR_SET requirement (totaling 2.898ns) by 4.998ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5C.CLK to       R3C5C.Q0 SLICE_3 (from RCLK_c)
+ROUTE         4     1.063       R3C5C.Q0 to       R3C6C.A1 FS_12
+CTOF_DEL    ---     0.371       R3C6C.A1 to       R3C6C.F1 SLICE_68
+ROUTE         2     1.503       R3C6C.F1 to       R4C5B.A1 n2471
+CTOF_DEL    ---     0.371       R4C5B.A1 to       R4C5B.F1 SLICE_78
+ROUTE         3     0.528       R4C5B.F1 to       R4C5B.C0 n2464
+CTOF_DEL    ---     0.371       R4C5B.C0 to       R4C5B.F0 SLICE_78
+ROUTE         2     3.129       R4C5B.F0 to      R9C9C.LSR n1846 (to RCLK_c)
+                  --------
+                    7.896   (21.2% logic, 78.8% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C5C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R9C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.889ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI_417  (to RCLK_c +)
+
+   Delay:               7.787ns  (21.5% logic, 78.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      7.787ns physical path delay SLICE_1 to SLICE_44 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.626ns LSR_SET requirement (totaling 2.898ns) by 4.889ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5D.CLK to       R3C5D.Q1 SLICE_1 (from RCLK_c)
+ROUTE         3     1.179       R3C5D.Q1 to       R3C2D.D1 FS_15
+CTOF_DEL    ---     0.371       R3C2D.D1 to       R3C2D.F1 SLICE_94
+ROUTE         3     1.278       R3C2D.F1 to       R4C5B.D1 n2272
+CTOF_DEL    ---     0.371       R4C5B.D1 to       R4C5B.F1 SLICE_78
+ROUTE         3     0.528       R4C5B.F1 to       R4C5B.C0 n2464
+CTOF_DEL    ---     0.371       R4C5B.C0 to       R4C5B.F0 SLICE_78
+ROUTE         2     3.129       R4C5B.F0 to      R9C9C.LSR n1846 (to RCLK_c)
+                  --------
+                    7.787   (21.5% logic, 78.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C5D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R9C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.800ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i17  (from RCLK_c +)
+   Destination:    FF         Data in        UFMSDI_417  (to RCLK_c +)
+
+   Delay:               7.698ns  (21.7% logic, 78.3% route), 4 logic levels.
+
+ Constraint Details:
+
+      7.698ns physical path delay SLICE_8 to SLICE_44 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.626ns LSR_SET requirement (totaling 2.898ns) by 4.800ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C6A.CLK to       R3C6A.Q1 SLICE_8 (from RCLK_c)
+ROUTE         4     0.865       R3C6A.Q1 to       R3C6C.C1 FS_17
+CTOF_DEL    ---     0.371       R3C6C.C1 to       R3C6C.F1 SLICE_68
+ROUTE         2     1.503       R3C6C.F1 to       R4C5B.A1 n2471
+CTOF_DEL    ---     0.371       R4C5B.A1 to       R4C5B.F1 SLICE_78
+ROUTE         3     0.528       R4C5B.F1 to       R4C5B.C0 n2464
+CTOF_DEL    ---     0.371       R4C5B.C0 to       R4C5B.F0 SLICE_78
+ROUTE         2     3.129       R4C5B.F0 to      R9C9C.LSR n1846 (to RCLK_c)
+                  --------
+                    7.698   (21.7% logic, 78.3% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_44:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R9C9C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.458ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i13  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               7.801ns  (26.2% logic, 73.8% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.801ns physical path delay SLICE_3 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 4.458ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5C.CLK to       R3C5C.Q1 SLICE_3 (from RCLK_c)
+ROUTE         3     1.372       R3C5C.Q1 to       R3C2D.C1 FS_13
+CTOF_DEL    ---     0.371       R3C2D.C1 to       R3C2D.F1 SLICE_94
+ROUTE         3     1.777       R3C2D.F1 to       R9C9C.D1 n2272
+CTOF_DEL    ---     0.371       R9C9C.D1 to       R9C9C.F1 SLICE_44
+ROUTE         2     2.111       R9C9C.F1 to       R3C2B.A1 n2462
+CTOF_DEL    ---     0.371       R3C2B.A1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    7.801   (26.2% logic, 73.8% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C5C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.352ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i13  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_419  (to RCLK_c +)
+
+   Delay:               7.632ns  (21.9% logic, 78.1% route), 4 logic levels.
+
+ Constraint Details:
+
+      7.632ns physical path delay SLICE_3 to SLICE_26 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 3.280ns) by 4.352ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5C.CLK to       R3C5C.Q1 SLICE_3 (from RCLK_c)
+ROUTE         3     1.372       R3C5C.Q1 to       R3C2D.C1 FS_13
+CTOF_DEL    ---     0.371       R3C2D.C1 to       R3C2D.F1 SLICE_94
+ROUTE         3     1.471       R3C2D.F1 to       R4C5C.C0 n2272
+CTOF_DEL    ---     0.371       R4C5C.C0 to       R4C5C.F0 SLICE_75
+ROUTE         2     0.513       R4C5C.F0 to       R4C5C.C1 n2214
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_75
+ROUTE         1     2.603       R4C5C.F1 to       R9C9B.CE RCLK_c_enable_12 (to RCLK_c)
+                  --------
+                    7.632   (21.9% logic, 78.1% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C5C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R9C9B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.293ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i12  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               7.636ns  (26.8% logic, 73.2% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.636ns physical path delay SLICE_3 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 4.293ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5C.CLK to       R3C5C.Q0 SLICE_3 (from RCLK_c)
+ROUTE         4     1.063       R3C5C.Q0 to       R3C6C.A1 FS_12
+CTOF_DEL    ---     0.371       R3C6C.A1 to       R3C6C.F1 SLICE_68
+ROUTE         2     1.921       R3C6C.F1 to       R9C9C.C1 n2471
+CTOF_DEL    ---     0.371       R9C9C.C1 to       R9C9C.F1 SLICE_44
+ROUTE         2     2.111       R9C9C.F1 to       R3C2B.A1 n2462
+CTOF_DEL    ---     0.371       R3C2B.A1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    7.636   (26.8% logic, 73.2% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C5C.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.265ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               7.608ns  (26.9% logic, 73.1% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.608ns physical path delay SLICE_1 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 4.265ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5D.CLK to       R3C5D.Q1 SLICE_1 (from RCLK_c)
+ROUTE         3     1.179       R3C5D.Q1 to       R3C2D.D1 FS_15
+CTOF_DEL    ---     0.371       R3C2D.D1 to       R3C2D.F1 SLICE_94
+ROUTE         3     1.777       R3C2D.F1 to       R9C9C.D1 n2272
+CTOF_DEL    ---     0.371       R9C9C.D1 to       R9C9C.F1 SLICE_44
+ROUTE         2     2.111       R9C9C.F1 to       R3C2B.A1 n2462
+CTOF_DEL    ---     0.371       R3C2B.A1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    7.608   (26.9% logic, 73.1% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C5D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.226ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i16  (from RCLK_c +)
+   Destination:    FF         Data in        UFMCLK_416  (to RCLK_c +)
+
+   Delay:               7.569ns  (27.0% logic, 73.0% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.569ns physical path delay SLICE_8 to SLICE_43 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.181ns DIN_SET requirement (totaling 3.343ns) by 4.226ns
+
+ Physical Path Details:
+
+      Data path SLICE_8 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C6A.CLK to       R3C6A.Q0 SLICE_8 (from RCLK_c)
+ROUTE         5     0.873       R3C6A.Q0 to       R3C6B.C0 FS_16
+CTOF_DEL    ---     0.371       R3C6B.C0 to       R3C6B.F0 SLICE_90
+ROUTE         1     2.044       R3C6B.F0 to       R9C9C.A1 n2470
+CTOF_DEL    ---     0.371       R9C9C.A1 to       R9C9C.F1 SLICE_44
+ROUTE         2     2.111       R9C9C.F1 to       R3C2B.A1 n2462
+CTOF_DEL    ---     0.371       R3C2B.A1 to       R3C2B.F1 SLICE_43
+ROUTE         1     0.497       R3C2B.F1 to       R3C2B.C0 n1160
+CTOF_DEL    ---     0.371       R3C2B.C0 to       R3C2B.F0 SLICE_43
+ROUTE         1     0.000       R3C2B.F0 to      R3C2B.DI0 UFMCLK_N_224 (to RCLK_c)
+                  --------
+                    7.569   (27.0% logic, 73.0% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_8:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C6A.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C2B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.159ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        LEDEN_419  (to RCLK_c +)
+
+   Delay:               7.439ns  (22.5% logic, 77.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      7.439ns physical path delay SLICE_1 to SLICE_26 exceeds
+      3.524ns delay constraint less
+      0.000ns skew and
+      0.244ns CE_SET requirement (totaling 3.280ns) by 4.159ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R3C5D.CLK to       R3C5D.Q1 SLICE_1 (from RCLK_c)
+ROUTE         3     1.179       R3C5D.Q1 to       R3C2D.D1 FS_15
+CTOF_DEL    ---     0.371       R3C2D.D1 to       R3C2D.F1 SLICE_94
+ROUTE         3     1.471       R3C2D.F1 to       R4C5C.C0 n2272
+CTOF_DEL    ---     0.371       R4C5C.C0 to       R4C5C.F0 SLICE_75
+ROUTE         2     0.513       R4C5C.F0 to       R4C5C.C1 n2214
+CTOF_DEL    ---     0.371       R4C5C.C1 to       R4C5C.F1 SLICE_75
+ROUTE         1     2.603       R4C5C.F1 to       R9C9B.CE RCLK_c_enable_12 (to RCLK_c)
+                  --------
+                    7.439   (22.5% logic, 77.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R3C5D.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_26:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     1.425       86.PADDI to      R9C9B.CLK RCLK_c
+                  --------
+                    1.425   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning: 116.198MHz is the maximum frequency for this preference.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+            106 items scored, 95 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error: The following path exceeds requirements by 4.911ns (weighted slack = -9.822ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               8.437ns  (28.6% logic, 71.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.437ns physical path delay SLICE_99 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.911ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     2.159       R2C2A.Q1 to       R7C9A.D0 Bank_7
+CTOF_DEL    ---     0.371       R7C9A.D0 to       R7C9A.F0 SLICE_97
+ROUTE         1     1.026       R7C9A.F0 to       R5C9C.A0 n2314
+CTOF_DEL    ---     0.371       R5C9C.A0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.947       R5C9D.F1 to       R6C9B.C0 n1326
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_89
+ROUTE         1     0.497       R6C9B.F0 to       R6C9D.C0 n1280
+CTOF_DEL    ---     0.371       R6C9D.C0 to       R6C9D.F0 SLICE_79
+ROUTE         2     1.089       R6C9D.F0 to      R6C7A.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    8.437   (28.6% logic, 71.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R6C7A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.644ns (weighted slack = -9.288ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
+                   FF                        CmdUFMCLK_413
+
+   Delay:               8.543ns  (28.3% logic, 71.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.543ns physical path delay SLICE_99 to SLICE_81 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.644ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     2.159       R2C2A.Q1 to       R7C9A.D0 Bank_7
+CTOF_DEL    ---     0.371       R7C9A.D0 to       R7C9A.F0 SLICE_97
+ROUTE         1     1.026       R7C9A.F0 to       R5C9C.A0 n2314
+CTOF_DEL    ---     0.371       R5C9C.A0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.945       R5C9D.F1 to       R7C9D.C0 n1326
+CTOF_DEL    ---     0.371       R7C9D.C0 to       R7C9D.F0 SLICE_82
+ROUTE         2     0.513       R7C9D.F0 to       R7C9C.C1 n2460
+CTOF_DEL    ---     0.371       R7C9C.C1 to       R7C9C.F1 SLICE_83
+ROUTE         2     1.181       R7C9C.F1 to       R5C9C.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    8.543   (28.3% logic, 71.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R5C9C.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.644ns (weighted slack = -9.288ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:               8.543ns  (28.3% logic, 71.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.543ns physical path delay SLICE_99 to SLICE_93 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.644ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     2.159       R2C2A.Q1 to       R7C9A.D0 Bank_7
+CTOF_DEL    ---     0.371       R7C9A.D0 to       R7C9A.F0 SLICE_97
+ROUTE         1     1.026       R7C9A.F0 to       R5C9C.A0 n2314
+CTOF_DEL    ---     0.371       R5C9C.A0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.945       R5C9D.F1 to       R7C9D.C0 n1326
+CTOF_DEL    ---     0.371       R7C9D.C0 to       R7C9D.F0 SLICE_82
+ROUTE         2     0.513       R7C9D.F0 to       R7C9C.C1 n2460
+CTOF_DEL    ---     0.371       R7C9C.C1 to       R7C9C.F1 SLICE_83
+ROUTE         2     1.181       R7C9C.F1 to      R10C9A.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    8.543   (28.3% logic, 71.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to     R10C9A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.536ns (weighted slack = -9.072ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               8.435ns  (28.6% logic, 71.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.435ns physical path delay SLICE_99 to SLICE_18 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.536ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     2.159       R2C2A.Q1 to       R7C9A.D0 Bank_7
+CTOF_DEL    ---     0.371       R7C9A.D0 to       R7C9A.F0 SLICE_97
+ROUTE         1     1.026       R7C9A.F0 to       R5C9C.A0 n2314
+CTOF_DEL    ---     0.371       R5C9C.A0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.945       R5C9D.F1 to       R7C9D.C0 n1326
+CTOF_DEL    ---     0.371       R7C9D.C0 to       R7C9D.F0 SLICE_82
+ROUTE         2     0.513       R7C9D.F0 to       R7C9D.C1 n2460
+CTOF_DEL    ---     0.371       R7C9D.C1 to       R7C9D.F1 SLICE_82
+ROUTE         1     1.073       R7C9D.F1 to       R5C9D.CE PHI2_N_120_enable_7 (to PHI2_c)
+                  --------
+                    8.435   (28.6% logic, 71.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.485ns (weighted slack = -8.970ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               8.011ns  (30.1% logic, 69.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.011ns physical path delay SLICE_99 to SLICE_9 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.485ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     2.159       R2C2A.Q1 to       R7C9A.D0 Bank_7
+CTOF_DEL    ---     0.371       R7C9A.D0 to       R7C9A.F0 SLICE_97
+ROUTE         1     1.026       R7C9A.F0 to       R5C9C.A0 n2314
+CTOF_DEL    ---     0.371       R5C9C.A0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.947       R5C9D.F1 to       R6C9B.C0 n1326
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_89
+ROUTE         1     0.497       R6C9B.F0 to       R6C9D.C0 n1280
+CTOF_DEL    ---     0.371       R6C9D.C0 to       R6C9D.F0 SLICE_79
+ROUTE         2     0.663       R6C9D.F0 to      R6C9C.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    8.011   (30.1% logic, 69.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R6C9C.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.400ns (weighted slack = -8.800ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        CmdSubmitted_411  (to PHI2_c -)
+
+   Delay:               8.299ns  (29.1% logic, 70.9% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.299ns physical path delay SLICE_99 to SLICE_19 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.400ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     2.159       R2C2A.Q1 to       R7C9A.D0 Bank_7
+CTOF_DEL    ---     0.371       R7C9A.D0 to       R7C9A.F0 SLICE_97
+ROUTE         1     1.026       R7C9A.F0 to       R5C9C.A0 n2314
+CTOF_DEL    ---     0.371       R5C9C.A0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.680       R5C9D.F1 to       R5C9B.D1 n1326
+CTOF_DEL    ---     0.371       R5C9B.D1 to       R5C9B.F1 SLICE_76
+ROUTE         2     1.068       R5C9B.F1 to       R5C7C.D0 n2458
+CTOF_DEL    ---     0.371       R5C7C.D0 to       R5C7C.F0 SLICE_91
+ROUTE         1     0.647       R5C7C.F0 to       R5C7D.CE PHI2_N_120_enable_5 (to PHI2_c)
+                  --------
+                    8.299   (29.1% logic, 70.9% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R5C7D.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.271ns (weighted slack = -8.542ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i7  (from PHI2_c +)
+   Destination:    FF         Data in        Cmdn8MEGEN_410  (to PHI2_c -)
+
+   Delay:               8.170ns  (29.6% logic, 70.4% route), 6 logic levels.
+
+ Constraint Details:
+
+      8.170ns physical path delay SLICE_99 to SLICE_23 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.265ns CE_SET requirement (totaling 3.899ns) by 4.271ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q1 SLICE_99 (from PHI2_c)
+ROUTE         1     2.159       R2C2A.Q1 to       R7C9A.D0 Bank_7
+CTOF_DEL    ---     0.371       R7C9A.D0 to       R7C9A.F0 SLICE_97
+ROUTE         1     1.026       R7C9A.F0 to       R5C9C.A0 n2314
+CTOF_DEL    ---     0.371       R5C9C.A0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.680       R5C9D.F1 to       R5C9B.D1 n1326
+CTOF_DEL    ---     0.371       R5C9B.D1 to       R5C9B.F1 SLICE_76
+ROUTE         2     0.513       R5C9B.F1 to       R5C9B.C0 n2458
+CTOF_DEL    ---     0.371       R5C9B.C0 to       R5C9B.F0 SLICE_76
+ROUTE         1     1.073       R5C9B.F0 to       R5C8B.CE PHI2_N_120_enable_4 (to PHI2_c)
+                  --------
+                    8.170   (29.6% logic, 70.4% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R5C8B.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.250ns (weighted slack = -8.500ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i1  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               7.776ns  (26.3% logic, 73.7% route), 5 logic levels.
+
+ Constraint Details:
+
+      7.776ns physical path delay SLICE_88 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.250ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R9C3B.CLK to       R9C3B.Q1 SLICE_88 (from PHI2_c)
+ROUTE         1     1.616       R9C3B.Q1 to       R9C9A.D0 Bank_1
+CTOF_DEL    ---     0.371       R9C9A.D0 to       R9C9A.F0 SLICE_96
+ROUTE         1     1.583       R9C9A.F0 to       R5C9D.A1 n2316
+CTOF_DEL    ---     0.371       R5C9D.A1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.947       R5C9D.F1 to       R6C9B.C0 n1326
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_89
+ROUTE         1     0.497       R6C9B.F0 to       R6C9D.C0 n1280
+CTOF_DEL    ---     0.371       R6C9D.C0 to       R6C9D.F0 SLICE_79
+ROUTE         2     1.089       R6C9D.F0 to      R6C7A.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    7.776   (26.3% logic, 73.7% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R9C3B.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R6C7A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.196ns (weighted slack = -8.392ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i0  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               7.722ns  (31.3% logic, 68.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.722ns physical path delay SLICE_88 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.196ns
+
+ Physical Path Details:
+
+      Data path SLICE_88 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R9C3B.CLK to       R9C3B.Q0 SLICE_88 (from PHI2_c)
+ROUTE         1     1.444       R9C3B.Q0 to       R7C9A.C0 Bank_0
+CTOF_DEL    ---     0.371       R7C9A.C0 to       R7C9A.F0 SLICE_97
+ROUTE         1     1.026       R7C9A.F0 to       R5C9C.A0 n2314
+CTOF_DEL    ---     0.371       R5C9C.A0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.947       R5C9D.F1 to       R6C9B.C0 n1326
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_89
+ROUTE         1     0.497       R6C9B.F0 to       R6C9D.C0 n1280
+CTOF_DEL    ---     0.371       R6C9D.C0 to       R6C9D.F0 SLICE_79
+ROUTE         2     1.089       R6C9D.F0 to      R6C7A.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    7.722   (31.3% logic, 68.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_88:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R9C3B.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R6C7A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Error: The following path exceeds requirements by 4.179ns (weighted slack = -8.358ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Bank_i6  (from PHI2_c +)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               7.705ns  (31.3% logic, 68.7% route), 6 logic levels.
+
+ Constraint Details:
+
+      7.705ns physical path delay SLICE_99 to SLICE_14 exceeds
+      4.164ns delay constraint less
+      0.000ns skew and
+      0.638ns LSR_SET requirement (totaling 3.526ns) by 4.179ns
+
+ Physical Path Details:
+
+      Data path SLICE_99 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.560      R2C2A.CLK to       R2C2A.Q0 SLICE_99 (from PHI2_c)
+ROUTE         1     1.956       R2C2A.Q0 to       R5C9C.C1 Bank_6
+CTOF_DEL    ---     0.371       R5C9C.C1 to       R5C9C.F1 SLICE_81
+ROUTE         1     0.497       R5C9C.F1 to       R5C9C.C0 n2278
+CTOF_DEL    ---     0.371       R5C9C.C0 to       R5C9C.F0 SLICE_81
+ROUTE         1     0.304       R5C9C.F0 to       R5C9D.D1 n26
+CTOF_DEL    ---     0.371       R5C9D.D1 to       R5C9D.F1 SLICE_18
+ROUTE         8     0.947       R5C9D.F1 to       R6C9B.C0 n1326
+CTOF_DEL    ---     0.371       R6C9B.C0 to       R6C9B.F0 SLICE_89
+ROUTE         1     0.497       R6C9B.F0 to       R6C9D.C0 n1280
+CTOF_DEL    ---     0.371       R6C9D.C0 to       R6C9D.F0 SLICE_79
+ROUTE         2     1.089       R6C9D.F0 to      R6C7A.LSR C1Submitted_N_237 (to PHI2_c)
+                  --------
+                    7.705   (31.3% logic, 68.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_99:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R2C2A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     3.668       39.PADDI to      R6C7A.CLK PHI2_c
+                  --------
+                    3.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+Warning:  55.096MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 283.768000 MHz ; |  283.768 MHz|  116.198 MHz|   4 *
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 120.077000 MHz ; |  120.077 MHz|   55.096 MHz|   6 *
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+2 preferences(marked by "*" above) not met.
+
+----------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+----------------------------------------------------------------------------
+n1326                                   |       8|      94|     28.66%
+                                        |        |        |
+n26                                     |       1|      70|     21.34%
+                                        |        |        |
+----------------------------------------------------------------------------
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 328  Score: 909228
+Cumulative negative slack: 648187
+
+Constraints cover 489 paths, 2 nets, and 415 connections (62.69% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Tue Aug 15 05:03:30 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf 
+Design file:     ram2gs_lcmxo640c_impl1.ncd
+Preference file: ram2gs_lcmxo640c_impl1.prf
+Device,speed:    LCMXO640C,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY NET "RCLK_c" 283.768000 MHz (0 errors)
    •             383 items scored, 0 timing errors detected.
+
+
  • FREQUENCY NET "PHI2_c" 120.077000 MHz (0 errors)
    •             106 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+            383 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i4  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i5  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_100 to SLICE_100 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_100 to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R4C8B.CLK to       R4C8B.Q0 SLICE_100 (from RCLK_c)
+ROUTE         1     0.130       R4C8B.Q0 to       R4C8B.M1 n736 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R4C8B.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_100:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R4C8B.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i8  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i9  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_76 to SLICE_76 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_76 to SLICE_76:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R5C9B.CLK to       R5C9B.Q0 SLICE_76 (from RCLK_c)
+ROUTE         1     0.130       R5C9B.Q0 to       R5C9B.M1 n732 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_76:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R5C9B.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_76:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R5C9B.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i12  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i13  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_77 to SLICE_77 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_77 to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R3C6D.CLK to       R3C6D.Q0 SLICE_77 (from RCLK_c)
+ROUTE         1     0.130       R3C6D.Q0 to       R3C6D.M1 n728 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R3C6D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_77:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R3C6D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i14  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i15  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_80 to SLICE_80 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_80 to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R3C8C.CLK to       R3C8C.Q0 SLICE_80 (from RCLK_c)
+ROUTE         1     0.130       R3C8C.Q0 to       R3C8C.M1 n726 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R3C8C.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_80:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R3C8C.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i10  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i11  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_82 to SLICE_82 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_82 to SLICE_82:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R7C9D.CLK to       R7C9D.Q0 SLICE_82 (from RCLK_c)
+ROUTE         1     0.130       R7C9D.Q0 to       R7C9D.M1 n730 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_82:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R7C9D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_82:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R7C9D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i2  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i3  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_84 to SLICE_84 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_84 to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R5C8C.CLK to       R5C8C.Q0 SLICE_84 (from RCLK_c)
+ROUTE         1     0.130       R5C8C.Q0 to       R5C8C.M1 n738 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R5C8C.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_84:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R5C8C.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.273ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i6  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i7  (to RCLK_c +)
+
+   Delay:               0.256ns  (49.2% logic, 50.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.256ns physical path delay SLICE_86 to SLICE_86 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.273ns
+
+ Physical Path Details:
+
+      Data path SLICE_86 to SLICE_86:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R5C8D.CLK to       R5C8D.Q0 SLICE_86 (from RCLK_c)
+ROUTE         1     0.130       R5C8D.Q0 to       R5C8D.M1 n734 (to RCLK_c)
+                  --------
+                    0.256   (49.2% logic, 50.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_86:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R5C8D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_86:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R5C8D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.277ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              IS_FSM__i0  (from RCLK_c +)
+   Destination:    FF         Data in        IS_FSM__i1  (to RCLK_c +)
+
+   Delay:               0.260ns  (48.5% logic, 51.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.260ns physical path delay SLICE_87 to SLICE_87 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.277ns
+
+ Physical Path Details:
+
+      Data path SLICE_87 to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R4C5A.CLK to       R4C5A.Q0 SLICE_87 (from RCLK_c)
+ROUTE         6     0.134       R4C5A.Q0 to       R4C5A.M1 nRCS_N_139 (to RCLK_c)
+                  --------
+                    0.260   (48.5% logic, 51.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R4C5A.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_87:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R4C5A.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.290ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              RASr2_380  (from RCLK_c +)
+   Destination:    FF         Data in        RASr3_381  (to RCLK_c +)
+
+   Delay:               0.273ns  (46.2% logic, 53.8% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.273ns physical path delay SLICE_74 to SLICE_74 meets
+     -0.017ns M_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.017ns) by 0.290ns
+
+ Physical Path Details:
+
+      Data path SLICE_74 to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R4C7A.CLK to       R4C7A.Q0 SLICE_74 (from RCLK_c)
+ROUTE        14     0.147       R4C7A.Q0 to       R4C7A.M1 RASr2 (to RCLK_c)
+                  --------
+                    0.273   (46.2% logic, 53.8% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R4C7A.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_74:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R4C7A.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.301ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS_610__i15  (from RCLK_c +)
+   Destination:    FF         Data in        FS_610_add_4_16  (to RCLK_c +)
+                   FF                        FS_610__i15
+                   FF                        FS_610__i14
+
+   Delay:               0.257ns  (49.0% logic, 51.0% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.257ns physical path delay SLICE_1 to SLICE_1 meets
+     -0.044ns LUT_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.044ns) by 0.301ns
+
+ Physical Path Details:
+
+      Data path SLICE_1 to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.126      R3C5D.CLK to       R3C5D.Q1 SLICE_1 (from RCLK_c)
+ROUTE         3     0.131       R3C5D.Q1 to       R3C5D.A1 FS_15 (to RCLK_c)
+                  --------
+                    0.257   (49.0% logic, 51.0% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R3C5D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path RCLK to SLICE_1:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        40     0.351       86.PADDI to      R3C5D.CLK RCLK_c
+                  --------
+                    0.351   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+================================================================================
+Preference: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+            106 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.361ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        C1Submitted_406  (to PHI2_c -)
+
+   Delay:               0.342ns  (61.7% logic, 38.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.342ns physical path delay SLICE_14 to SLICE_14 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.361ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R6C7A.CLK to       R6C7A.Q0 SLICE_14 (from PHI2_c)
+ROUTE         2     0.131       R6C7A.Q0 to       R6C7A.A0 C1Submitted
+CTOF_DEL    ---     0.074       R6C7A.A0 to       R6C7A.F0 SLICE_14
+ROUTE         1     0.000       R6C7A.F0 to      R6C7A.DI0 n6_adj_3 (to PHI2_c)
+                  --------
+                    0.342   (61.7% logic, 38.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R6C7A.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R6C7A.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.361ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_407  (from PHI2_c -)
+   Destination:    FF         Data in        ADSubmitted_407  (to PHI2_c -)
+
+   Delay:               0.342ns  (61.7% logic, 38.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.342ns physical path delay SLICE_9 to SLICE_9 meets
+     -0.019ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.019ns) by 0.361ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R6C9C.CLK to       R6C9C.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.131       R6C9C.Q0 to       R6C9C.A0 ADSubmitted
+CTOF_DEL    ---     0.074       R6C9C.A0 to       R6C9C.F0 SLICE_9
+ROUTE         1     0.000       R6C9C.F0 to      R6C9C.DI0 n1413 (to PHI2_c)
+                  --------
+                    0.342   (61.7% logic, 38.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R6C9C.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R6C9C.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.585ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        XOR8MEG_408  (to PHI2_c -)
+
+   Delay:               0.562ns  (37.5% logic, 62.5% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.562ns physical path delay SLICE_18 to SLICE_49 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.585ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_49:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R5C9D.CLK to       R5C9D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.221       R5C9D.Q0 to       R5C8C.B1 CmdEnable
+CTOF_DEL    ---     0.074       R5C8C.B1 to       R5C8C.F1 SLICE_84
+ROUTE         1     0.130       R5C8C.F1 to       R5C8A.CE PHI2_N_120_enable_1 (to PHI2_c)
+                  --------
+                    0.562   (37.5% logic, 62.5% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_49:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.885ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMCS_412  (to PHI2_c -)
+                   FF                        CmdUFMCLK_413
+
+   Delay:               0.862ns  (33.1% logic, 66.9% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.862ns physical path delay SLICE_18 to SLICE_81 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.885ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R5C9D.CLK to       R5C9D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.145       R5C9D.Q0 to       R7C9C.D0 CmdEnable
+CTOF_DEL    ---     0.074       R7C9C.D0 to       R7C9C.F0 SLICE_83
+ROUTE         2     0.196       R7C9C.F0 to       R7C9C.A1 n10
+CTOF_DEL    ---     0.074       R7C9C.A1 to       R7C9C.F1 SLICE_83
+ROUTE         2     0.236       R7C9C.F1 to       R5C9C.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    0.862   (33.1% logic, 66.9% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_81:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C9C.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.885ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:               0.862ns  (33.1% logic, 66.9% route), 3 logic levels.
+
+ Constraint Details:
+
+      0.862ns physical path delay SLICE_18 to SLICE_93 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 0.885ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R5C9D.CLK to       R5C9D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.145       R5C9D.Q0 to       R7C9C.D0 CmdEnable
+CTOF_DEL    ---     0.074       R7C9C.D0 to       R7C9C.F0 SLICE_83
+ROUTE         2     0.196       R7C9C.F0 to       R7C9C.A1 n10
+CTOF_DEL    ---     0.074       R7C9C.A1 to       R7C9C.F1 SLICE_83
+ROUTE         2     0.236       R7C9C.F1 to      R10C9A.CE PHI2_N_120_enable_6 (to PHI2_c)
+                  --------
+                    0.862   (33.1% logic, 66.9% route), 3 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_93:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to     R10C9A.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.146ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        Cmdn8MEGEN_410  (to PHI2_c -)
+
+   Delay:               1.123ns  (32.0% logic, 68.0% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.123ns physical path delay SLICE_18 to SLICE_23 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 1.146ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R5C9D.CLK to       R5C9D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.145       R5C9D.Q0 to       R7C9C.D0 CmdEnable
+CTOF_DEL    ---     0.074       R7C9C.D0 to       R7C9C.F0 SLICE_83
+ROUTE         2     0.300       R7C9C.F0 to       R5C9B.A1 n10
+CTOF_DEL    ---     0.074       R5C9B.A1 to       R5C9B.F1 SLICE_76
+ROUTE         2     0.103       R5C9B.F1 to       R5C9B.C0 n2458
+CTOF_DEL    ---     0.074       R5C9B.C0 to       R5C9B.F0 SLICE_76
+ROUTE         1     0.216       R5C9B.F0 to       R5C8B.CE PHI2_N_120_enable_4 (to PHI2_c)
+                  --------
+                    1.123   (32.0% logic, 68.0% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_23:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C8B.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.173ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdEnable_405  (from PHI2_c -)
+   Destination:    FF         Data in        CmdSubmitted_411  (to PHI2_c -)
+
+   Delay:               1.150ns  (31.2% logic, 68.8% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.150ns physical path delay SLICE_18 to SLICE_19 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 1.173ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R5C9D.CLK to       R5C9D.Q0 SLICE_18 (from PHI2_c)
+ROUTE         2     0.145       R5C9D.Q0 to       R7C9C.D0 CmdEnable
+CTOF_DEL    ---     0.074       R7C9C.D0 to       R7C9C.F0 SLICE_83
+ROUTE         2     0.300       R7C9C.F0 to       R5C9B.A1 n10
+CTOF_DEL    ---     0.074       R5C9B.A1 to       R5C9B.F1 SLICE_76
+ROUTE         2     0.216       R5C9B.F1 to       R5C7C.D0 n2458
+CTOF_DEL    ---     0.074       R5C7C.D0 to       R5C7C.F0 SLICE_91
+ROUTE         1     0.130       R5C7C.F0 to       R5C7D.CE PHI2_N_120_enable_5 (to PHI2_c)
+                  --------
+                    1.150   (31.2% logic, 68.8% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_19:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C7D.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.573ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              ADSubmitted_407  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               1.550ns  (26.5% logic, 73.5% route), 4 logic levels.
+
+ Constraint Details:
+
+      1.550ns physical path delay SLICE_9 to SLICE_18 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 1.573ns
+
+ Physical Path Details:
+
+      Data path SLICE_9 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R6C9C.CLK to       R6C9C.Q0 SLICE_9 (from PHI2_c)
+ROUTE         2     0.310       R6C9C.Q0 to       R5C7A.A0 ADSubmitted
+CTOOFX_DEL  ---     0.125       R5C7A.A0 to     R5C7A.OFX0 i26/SLICE_71
+ROUTE         1     0.296     R5C7A.OFX0 to       R4C9A.A0 n13_adj_2
+CTOF_DEL    ---     0.074       R4C9A.A0 to       R4C9A.F0 SLICE_105
+ROUTE         1     0.318       R4C9A.F0 to       R7C9D.B1 n14
+CTOF_DEL    ---     0.074       R7C9D.B1 to       R7C9D.F1 SLICE_82
+ROUTE         1     0.216       R7C9D.F1 to       R5C9D.CE PHI2_N_120_enable_7 (to PHI2_c)
+                  --------
+                    1.550   (26.5% logic, 73.5% route), 4 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_9:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R6C9C.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 1.708ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              C1Submitted_406  (from PHI2_c -)
+   Destination:    FF         Data in        CmdEnable_405  (to PHI2_c -)
+
+   Delay:               1.685ns  (28.5% logic, 71.5% route), 5 logic levels.
+
+ Constraint Details:
+
+      1.685ns physical path delay SLICE_14 to SLICE_18 meets
+     -0.023ns CE_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.023ns) by 1.708ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R6C7A.CLK to       R6C7A.Q0 SLICE_14 (from PHI2_c)
+ROUTE         2     0.196       R6C7A.Q0 to       R6C7A.A1 C1Submitted
+CTOF_DEL    ---     0.074       R6C7A.A1 to       R6C7A.F1 SLICE_14
+ROUTE         1     0.179       R6C7A.F1 to       R5C7A.C1 n2284
+CTOOFX_DEL  ---     0.121       R5C7A.C1 to     R5C7A.OFX0 i26/SLICE_71
+ROUTE         1     0.296     R5C7A.OFX0 to       R4C9A.A0 n13_adj_2
+CTOF_DEL    ---     0.074       R4C9A.A0 to       R4C9A.F0 SLICE_105
+ROUTE         1     0.318       R4C9A.F0 to       R7C9D.B1 n14
+CTOF_DEL    ---     0.074       R7C9D.B1 to       R7C9D.F1 SLICE_82
+ROUTE         1     0.216       R7C9D.F1 to       R5C9D.CE PHI2_N_120_enable_7 (to PHI2_c)
+                  --------
+                    1.685   (28.5% logic, 71.5% route), 5 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R6C7A.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C9D.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 4.684ns (weighted slack = 9.368ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              XOR8MEG_408  (from PHI2_c -)
+   Destination:    FF         Data in        RA11_385  (to PHI2_c +)
+
+   Delay:               0.512ns  (41.2% logic, 58.8% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.512ns physical path delay SLICE_49 to SLICE_32 meets
+     -0.008ns DIN_HLD and
+     -4.164ns delay constraint less
+      0.000ns skew requirement (totaling -4.172ns) by 4.684ns
+
+ Physical Path Details:
+
+      Data path SLICE_49 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.137      R5C8A.CLK to       R5C8A.Q0 SLICE_49 (from PHI2_c)
+ROUTE         1     0.301       R5C8A.Q0 to       R2C9A.C0 XOR8MEG
+CTOF_DEL    ---     0.074       R2C9A.C0 to       R2C9A.F0 SLICE_32
+ROUTE         1     0.000       R2C9A.F0 to      R2C9A.DI0 RA11_N_184 (to PHI2_c)
+                  --------
+                    0.512   (41.2% logic, 58.8% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path PHI2 to SLICE_49:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R5C8A.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path PHI2 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        14     0.903       39.PADDI to      R2C9A.CLK PHI2_c
+                  --------
+                    0.903   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY NET "RCLK_c" 283.768000 MHz ; |     0.000 ns|     0.273 ns|   1  
+                                        |             |             |
+FREQUENCY NET "PHI2_c" 120.077000 MHz ; |     0.000 ns|     0.361 ns|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 4 clocks:
+
+Clock Domain: nCRAS_c   Source: nCRAS.PAD   Loads: 9
+   No transfer within this clock domain is found
+
+Clock Domain: nCCAS_c   Source: nCCAS.PAD   Loads: 7
+   No transfer within this clock domain is found
+
+Clock Domain: RCLK_c   Source: RCLK.PAD   Loads: 40
+   Covered under: FREQUENCY NET "RCLK_c" 283.768000 MHz ;
+
+   Data transfers from:
+   Clock Domain: nCRAS_c   Source: nCRAS.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+   Clock Domain: PHI2_c   Source: PHI2.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+Clock Domain: PHI2_c   Source: PHI2.PAD   Loads: 14
+   Covered under: FREQUENCY NET "PHI2_c" 120.077000 MHz ;
+
+   Data transfers from:
+   Clock Domain: RCLK_c   Source: RCLK.PAD
+      Not reported because source and destination domains are unrelated.
+      To report these transfers please refer to preference CLKSKEWDIFF to define
+      external clock skew between clock ports.
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 489 paths, 2 nets, and 415 connections (62.69% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 328 (setup), 0 (hold)
+Score: 909228 (setup), 0 (hold)
+Cumulative negative slack: 648187 (648187+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_drc.log b/CPLD/LCMXO640C/impl1/RAM2GS_drc.log new file mode 100644 index 0000000..60696e6 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_drc.log @@ -0,0 +1,15 @@ +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 318 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO640C_impl1.ngd. diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_lse.twr b/CPLD/LCMXO640C/impl1/RAM2GS_lse.twr new file mode 100644 index 0000000..4779f7d --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_lse.twr @@ -0,0 +1,291 @@ +-------------------------------------------------------------------------------- +Lattice Synthesis Timing Report, Version +Tue Aug 15 05:03:22 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Design: RAM2GS +Constraint file: +Report level: verbose report, limited to 3 items per constraint +-------------------------------------------------------------------------------- + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c] + 0 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c] + 115 items scored, 112 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 8.575ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i3 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMCS_412 (to PHI2_c -) + + Delay: 10.811ns (23.7% logic, 76.3% route), 6 logic levels. + + Constraint Details: + + 10.811ns data_path Bank_i3 to CmdUFMCS_412 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns + + Path Details: Bank_i3 to CmdUFMCS_412 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i3 (from PHI2_c) +Route 1 e 1.220 Bank[3] +LUT4 --- 0.390 B to Z i1982_2_lut +Route 1 e 1.220 n2278 +LUT4 --- 0.390 C to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 8 e 1.719 n1326 +LUT4 --- 0.390 B to Z i1990_2_lut_rep_17 +Route 2 e 1.386 n2460 +LUT4 --- 0.390 C to Z i1_2_lut_4_lut +Route 3 e 1.483 PHI2_N_120_enable_6 + -------- + 10.811 (23.7% logic, 76.3% route), 6 logic levels. + + +Error: The following path violates requirements by 8.575ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i3 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMSDI_414 (to PHI2_c -) + + Delay: 10.811ns (23.7% logic, 76.3% route), 6 logic levels. + + Constraint Details: + + 10.811ns data_path Bank_i3 to CmdUFMSDI_414 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns + + Path Details: Bank_i3 to CmdUFMSDI_414 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i3 (from PHI2_c) +Route 1 e 1.220 Bank[3] +LUT4 --- 0.390 B to Z i1982_2_lut +Route 1 e 1.220 n2278 +LUT4 --- 0.390 C to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 8 e 1.719 n1326 +LUT4 --- 0.390 B to Z i1990_2_lut_rep_17 +Route 2 e 1.386 n2460 +LUT4 --- 0.390 C to Z i1_2_lut_4_lut +Route 3 e 1.483 PHI2_N_120_enable_6 + -------- + 10.811 (23.7% logic, 76.3% route), 6 logic levels. + + +Error: The following path violates requirements by 8.575ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK Bank_i3 (from PHI2_c +) + Destination: FD1P3AX SP CmdUFMCLK_413 (to PHI2_c -) + + Delay: 10.811ns (23.7% logic, 76.3% route), 6 logic levels. + + Constraint Details: + + 10.811ns data_path Bank_i3 to CmdUFMCLK_413 violates + 2.500ns delay constraint less + 0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns + + Path Details: Bank_i3 to CmdUFMCLK_413 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q Bank_i3 (from PHI2_c) +Route 1 e 1.220 Bank[3] +LUT4 --- 0.390 B to Z i1982_2_lut +Route 1 e 1.220 n2278 +LUT4 --- 0.390 C to Z i12_4_lut +Route 1 e 1.220 n26 +LUT4 --- 0.390 B to Z i13_4_lut +Route 8 e 1.719 n1326 +LUT4 --- 0.390 B to Z i1990_2_lut_rep_17 +Route 2 e 1.386 n2460 +LUT4 --- 0.390 C to Z i1_2_lut_4_lut +Route 3 e 1.483 PHI2_N_120_enable_6 + -------- + 10.811 (23.7% logic, 76.3% route), 6 logic levels. + +Warning: 11.075 ns is the maximum delay for this constraint. + + + +================================================================================ +Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c] + 357 items scored, 234 timing errors detected. +-------------------------------------------------------------------------------- + + +Error: The following path violates requirements by 4.364ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i13 (from RCLK_c +) + Destination: FD1P3AX D n8MEGEN_418 (to RCLK_c +) + + Delay: 9.182ns (23.7% logic, 76.3% route), 5 logic levels. + + Constraint Details: + + 9.182ns data_path FS_610__i13 to n8MEGEN_418 violates + 5.000ns delay constraint less + 0.182ns L_S requirement (totaling 4.818ns) by 4.364ns + + Path Details: FS_610__i13 to n8MEGEN_418 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_610__i13 (from RCLK_c) +Route 3 e 1.603 FS[13] +LUT4 --- 0.390 A to Z i1976_2_lut +Route 3 e 1.483 n2272 +LUT4 --- 0.390 C to Z i5_3_lut_rep_21_4_lut +Route 3 e 1.483 n2464 +LUT4 --- 0.390 B to Z i1_2_lut_3_lut_adj_4 +Route 1 e 1.220 n1325 +LUT4 --- 0.390 D to Z n8MEGEN_I_14_4_lut +Route 1 e 1.220 n8MEGEN_N_91 + -------- + 9.182 (23.7% logic, 76.3% route), 5 logic levels. + + +Error: The following path violates requirements by 4.364ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i15 (from RCLK_c +) + Destination: FD1P3AX D n8MEGEN_418 (to RCLK_c +) + + Delay: 9.182ns (23.7% logic, 76.3% route), 5 logic levels. + + Constraint Details: + + 9.182ns data_path FS_610__i15 to n8MEGEN_418 violates + 5.000ns delay constraint less + 0.182ns L_S requirement (totaling 4.818ns) by 4.364ns + + Path Details: FS_610__i15 to n8MEGEN_418 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_610__i15 (from RCLK_c) +Route 3 e 1.603 FS[15] +LUT4 --- 0.390 B to Z i1976_2_lut +Route 3 e 1.483 n2272 +LUT4 --- 0.390 C to Z i5_3_lut_rep_21_4_lut +Route 3 e 1.483 n2464 +LUT4 --- 0.390 B to Z i1_2_lut_3_lut_adj_4 +Route 1 e 1.220 n1325 +LUT4 --- 0.390 D to Z n8MEGEN_I_14_4_lut +Route 1 e 1.220 n8MEGEN_N_91 + -------- + 9.182 (23.7% logic, 76.3% route), 5 logic levels. + + +Error: The following path violates requirements by 4.349ns + + Logical Details: Cell type Pin type Cell name (clock net +/-) + + Source: FD1S3AX CK FS_610__i13 (from RCLK_c +) + Destination: FD1P3AX SP n8MEGEN_418 (to RCLK_c +) + + Delay: 9.085ns (23.9% logic, 76.1% route), 5 logic levels. + + Constraint Details: + + 9.085ns data_path FS_610__i13 to n8MEGEN_418 violates + 5.000ns delay constraint less + 0.264ns LCE_S requirement (totaling 4.736ns) by 4.349ns + + Path Details: FS_610__i13 to n8MEGEN_418 + + Name Fanout Delay (ns) Pins Resource(Cell.Net) +L_CO --- 0.613 CK to Q FS_610__i13 (from RCLK_c) +Route 3 e 1.603 FS[13] +LUT4 --- 0.390 A to Z i1976_2_lut +Route 3 e 1.483 n2272 +LUT4 --- 0.390 C to Z i7_4_lut +Route 2 e 1.386 n2214 +LUT4 --- 0.390 B to Z i2_2_lut +Route 1 e 1.220 n7 +LUT4 --- 0.390 A to Z i17_4_lut +Route 1 e 1.220 RCLK_c_enable_11 + -------- + 9.085 (23.9% logic, 76.1% route), 5 logic levels. + +Warning: 9.364 ns is the maximum delay for this constraint. + + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 5.000 ns| 22.150 ns| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 5.000 ns| 9.364 ns| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + +-------------------------------------------------------------------------------- +Critical Nets | Loads| Errors| % of total +-------------------------------------------------------------------------------- +n1326 | 8| 104| 30.06% + | | | +n26 | 1| 78| 22.54% + | | | +RCLK_c_enable_23 | 16| 64| 18.50% + | | | +-------------------------------------------------------------------------------- + + +Timing summary: +--------------- + +Timing errors: 346 Score: 1874657 + +Constraints cover 476 paths, 187 nets, and 480 connections (64.3% coverage) + + +Peak memory: 53284864 bytes, TRCE: 1122304 bytes, DLYMAN: 167936 bytes +CPU_TIME_REPORT: 0 secs diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html b/CPLD/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html new file mode 100644 index 0000000..d5f78c7 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_lse_lsetwr.html @@ -0,0 +1,356 @@ + +Lattice Synthesis Timing Report + + +
    Lattice Synthesis Timing Report
+--------------------------------------------------------------------------------
+Lattice Synthesis Timing Report, Version  
+Tue Aug 15 05:03:22 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Design:     RAM2GS
+Constraint file:  
+Report level:    verbose report, limited to 3 items per constraint
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
+            0 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
+            115 items scored, 112 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 8.575ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCS_412  (to PHI2_c -)
+
+   Delay:                  10.811ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.811ns data_path Bank_i3 to CmdUFMCS_412 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns
+
+ Path Details: Bank_i3 to CmdUFMCS_412
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 1.220                                  Bank[3]
+LUT4        ---     0.390              B to Z              i1982_2_lut
+Route         1   e 1.220                                  n2278
+LUT4        ---     0.390              C to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         8   e 1.719                                  n1326
+LUT4        ---     0.390              B to Z              i1990_2_lut_rep_17
+Route         2   e 1.386                                  n2460
+LUT4        ---     0.390              C to Z              i1_2_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_120_enable_6
+                  --------
+                   10.811  (23.7% logic, 76.3% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 8.575ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMSDI_414  (to PHI2_c -)
+
+   Delay:                  10.811ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.811ns data_path Bank_i3 to CmdUFMSDI_414 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns
+
+ Path Details: Bank_i3 to CmdUFMSDI_414
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 1.220                                  Bank[3]
+LUT4        ---     0.390              B to Z              i1982_2_lut
+Route         1   e 1.220                                  n2278
+LUT4        ---     0.390              C to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         8   e 1.719                                  n1326
+LUT4        ---     0.390              B to Z              i1990_2_lut_rep_17
+Route         2   e 1.386                                  n2460
+LUT4        ---     0.390              C to Z              i1_2_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_120_enable_6
+                  --------
+                   10.811  (23.7% logic, 76.3% route), 6 logic levels.
+
+
+Error:  The following path violates requirements by 8.575ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             Bank_i3  (from PHI2_c +)
+   Destination:    FD1P3AX    SP             CmdUFMCLK_413  (to PHI2_c -)
+
+   Delay:                  10.811ns  (23.7% logic, 76.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.811ns data_path Bank_i3 to CmdUFMCLK_413 violates
+      2.500ns delay constraint less
+      0.264ns LCE_S requirement (totaling 2.236ns) by 8.575ns
+
+ Path Details: Bank_i3 to CmdUFMCLK_413
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              Bank_i3 (from PHI2_c)
+Route         1   e 1.220                                  Bank[3]
+LUT4        ---     0.390              B to Z              i1982_2_lut
+Route         1   e 1.220                                  n2278
+LUT4        ---     0.390              C to Z              i12_4_lut
+Route         1   e 1.220                                  n26
+LUT4        ---     0.390              B to Z              i13_4_lut
+Route         8   e 1.719                                  n1326
+LUT4        ---     0.390              B to Z              i1990_2_lut_rep_17
+Route         2   e 1.386                                  n2460
+LUT4        ---     0.390              C to Z              i1_2_lut_4_lut
+Route         3   e 1.483                                  PHI2_N_120_enable_6
+                  --------
+                   10.811  (23.7% logic, 76.3% route), 6 logic levels.
+
+Warning: 11.075 ns is the maximum delay for this constraint.
+
+
+
+================================================================================
+Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
+            357 items scored, 234 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Error:  The following path violates requirements by 4.364ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i13  (from RCLK_c +)
+   Destination:    FD1P3AX    D              n8MEGEN_418  (to RCLK_c +)
+
+   Delay:                   9.182ns  (23.7% logic, 76.3% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.182ns data_path FS_610__i13 to n8MEGEN_418 violates
+      5.000ns delay constraint less
+      0.182ns L_S requirement (totaling 4.818ns) by 4.364ns
+
+ Path Details: FS_610__i13 to n8MEGEN_418
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_610__i13 (from RCLK_c)
+Route         3   e 1.603                                  FS[13]
+LUT4        ---     0.390              A to Z              i1976_2_lut
+Route         3   e 1.483                                  n2272
+LUT4        ---     0.390              C to Z              i5_3_lut_rep_21_4_lut
+Route         3   e 1.483                                  n2464
+LUT4        ---     0.390              B to Z              i1_2_lut_3_lut_adj_4
+Route         1   e 1.220                                  n1325
+LUT4        ---     0.390              D to Z              n8MEGEN_I_14_4_lut
+Route         1   e 1.220                                  n8MEGEN_N_91
+                  --------
+                    9.182  (23.7% logic, 76.3% route), 5 logic levels.
+
+
+Error:  The following path violates requirements by 4.364ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i15  (from RCLK_c +)
+   Destination:    FD1P3AX    D              n8MEGEN_418  (to RCLK_c +)
+
+   Delay:                   9.182ns  (23.7% logic, 76.3% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.182ns data_path FS_610__i15 to n8MEGEN_418 violates
+      5.000ns delay constraint less
+      0.182ns L_S requirement (totaling 4.818ns) by 4.364ns
+
+ Path Details: FS_610__i15 to n8MEGEN_418
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_610__i15 (from RCLK_c)
+Route         3   e 1.603                                  FS[15]
+LUT4        ---     0.390              B to Z              i1976_2_lut
+Route         3   e 1.483                                  n2272
+LUT4        ---     0.390              C to Z              i5_3_lut_rep_21_4_lut
+Route         3   e 1.483                                  n2464
+LUT4        ---     0.390              B to Z              i1_2_lut_3_lut_adj_4
+Route         1   e 1.220                                  n1325
+LUT4        ---     0.390              D to Z              n8MEGEN_I_14_4_lut
+Route         1   e 1.220                                  n8MEGEN_N_91
+                  --------
+                    9.182  (23.7% logic, 76.3% route), 5 logic levels.
+
+
+Error:  The following path violates requirements by 4.349ns
+
+ Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)
+
+   Source:         FD1S3AX    CK             FS_610__i13  (from RCLK_c +)
+   Destination:    FD1P3AX    SP             n8MEGEN_418  (to RCLK_c +)
+
+   Delay:                   9.085ns  (23.9% logic, 76.1% route), 5 logic levels.
+
+ Constraint Details:
+
+      9.085ns data_path FS_610__i13 to n8MEGEN_418 violates
+      5.000ns delay constraint less
+      0.264ns LCE_S requirement (totaling 4.736ns) by 4.349ns
+
+ Path Details: FS_610__i13 to n8MEGEN_418
+
+   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
+L_CO        ---     0.613             CK to Q              FS_610__i13 (from RCLK_c)
+Route         3   e 1.603                                  FS[13]
+LUT4        ---     0.390              A to Z              i1976_2_lut
+Route         3   e 1.483                                  n2272
+LUT4        ---     0.390              C to Z              i7_4_lut
+Route         2   e 1.386                                  n2214
+LUT4        ---     0.390              B to Z              i2_2_lut
+Route         1   e 1.220                                  n7
+LUT4        ---     0.390              A to Z              i17_4_lut
+Route         1   e 1.220                                  RCLK_c_enable_11
+                  --------
+                    9.085  (23.9% logic, 76.1% route), 5 logic levels.
+
+Warning: 9.364 ns is the maximum delay for this constraint.
+
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |     5.000 ns|    22.150 ns|     6 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |     5.000 ns|     9.364 ns|     5 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+--------------------------------------------------------------------------------
+Critical Nets                           |   Loads|  Errors| % of total
+--------------------------------------------------------------------------------
+n1326                                   |       8|     104|     30.06%
+                                        |        |        |
+n26                                     |       1|      78|     22.54%
+                                        |        |        |
+RCLK_c_enable_23                        |      16|      64|     18.50%
+                                        |        |        |
+--------------------------------------------------------------------------------
+
+
+Timing summary:
+---------------
+
+Timing errors: 346  Score: 1874657
+
+Constraints cover  476 paths, 187 nets, and 480 connections (64.3% coverage)
+
+
+Peak memory: 53284864 bytes, TRCE: 1122304 bytes, DLYMAN: 167936 bytes
+CPU_TIME_REPORT: 0 secs 
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/RAM2GS_prim.v b/CPLD/LCMXO640C/impl1/RAM2GS_prim.v new file mode 100644 index 0000000..d45f192 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/RAM2GS_prim.v @@ -0,0 +1,819 @@ +// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.12.1.454 +// Netlist written on Tue Aug 15 05:03:22 2023 +// +// Verilog Description of module RAM2GS +// + +module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE, + LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS, + nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1[8:14]) + input PHI2; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + input [9:0]MAin; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + input [1:0]CROW; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + input [7:0]Din; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + output [7:0]Dout; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + input nCCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + input nCRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + input nFWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) + output LED; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) + output [1:0]RBA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + output [11:0]RA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + inout [7:0]RD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + output nRCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) + input RCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + output RCKE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) + output nRWE; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) + output nRRAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) + output nRCAS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) + output RDQMH; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) + output RDQML; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) + output nUFMCS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) + output UFMCLK; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) + output UFMSDI; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) + input UFMSDO; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) + + wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + wire nCCAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + wire nCRAS_c /* synthesis is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + wire nCRAS_N_9 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + wire PHI2_N_120 /* synthesis is_inv_clock=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(38[6:13]) + + wire GND_net, VCC_net, PHI2r, PHI2r2, PHI2r3, RASr, RASr2, + RASr3, CASr, CASr2, CASr3, FWEr, CBR, LEDEN, Din_c_7, + Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, Din_c_0; + wire [7:0]Bank; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(31[12:16]) + + wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6, + MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0, + nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c, + nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, RA_0; + wire [9:0]RowA; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(51[12:16]) + + wire RA_1_9, RA_1_8, RA_1_7, RA_1_6, RA_1_5, RA_1_4, RA_1_3, + RA_1_2, RA_1_1, RA_1_0, RDQML_c, RDQMH_c; + wire [7:0]WRD; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(59[12:15]) + + wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted, + CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI, + CmdUFMCS, InitReady, Ready; + wire [17:0]FS; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(86[13:15]) + + wire LED_N_84, nFWE_N_5, n2414, RA11_N_184, n15, n2262, PHI2_N_120_enable_6, + n2257, n7, RASr2_N_63, RCKE_N_132, nRowColSel_N_35, n2011, + nRWE_N_182, RCKEEN_N_130, nRowColSel_N_34, nRowColSel_N_33, + n2015, nRowColSel_N_32, nRowColSel_N_28, n1426, n6, n2328, + n2457, n1425, RCKEEN_N_123, nRWE_N_178, RCKEEN_N_122, n2324, + nRCS_N_139, nRCAS_N_165, nRWE_N_177, nRWE_N_176, n2322, Ready_N_296, + n2316, n2314, Ready_N_292, nRCS_N_136, nRCAS_N_161, nRWE_N_171, + RCKEEN_N_121, n2336, PHI2_N_120_enable_5, n2209, CmdEnable_N_248, + C1Submitted_N_237, n2478, n2477, n2138, n1410, n2290, Cmdn8MEGEN_N_264, + XOR8MEG_N_110, n2208, LEDEN_N_82, n2243, RCLK_c_enable_24, + n2476, n2475, n8MEGEN_N_91, UFMCLK_N_224, UFMSDI_N_231, n2460, + n2227, n2253, n726, n727, n728, n729, n730, n1502, n732, + n733, n734, n735, n736, n737, n738, n2284, n2463, n2164, + PHI2_N_120_enable_4, n1325, n2278, n1503, n2214, n1417, + n2010, n2474, n2009, n1280, n33, n2473, n2263, n56, + PHI2_N_120_enable_1, n12, n10, n13, n2272, Dout_c, n78, + n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, + n89, n90, n91, n92, n93, n94, n95, n15_adj_1, n1, + n2462, n2472, n2471, n1093, RCLK_c_enable_11, n62, RCLK_c_enable_25, + n2470, n2242, n2461, RCLK_c_enable_23, RCLK_c_enable_12, n2451, + n2014, n14, n13_adj_2, n2568, n2245, PHI2_N_120_enable_7, + RCLK_c_enable_4, n2469, n1413, n1846, Dout_0, Dout_1, n984, + Dout_2, Dout_3, Dout_4, n1314, Dout_5, Dout_6, n2468, + n1160, n2337, n2008, n2013, n6_adj_3, RCLK_c_enable_3, n2467, + n2012, n2479, n1326, n2464, n8, n2481, n2430, n2459, + n2458, n2427, n2480, n11, n26; + + VHI i2 (.Z(VCC_net)); + INV i2136 (.A(PHI2_c), .Z(PHI2_N_120)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + ORCALUT4 i6_4_lut (.A(FS[17]), .B(n12), .C(FS[12]), .D(FS[14]), + .Z(n62)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i6_4_lut.init = 16'h8000; + ORCALUT4 i1_4_lut_4_lut (.A(Din_c_3), .B(Din_c_5), .C(Din_c_4), .D(n2458), + .Z(PHI2_N_120_enable_4)) /* synthesis lut_function=(A (B (C (D))+!B (D))+!A !(B+!(D))) */ ; + defparam i1_4_lut_4_lut.init = 16'hb300; + FD1S3AX PHI2r2_377 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r2_377.GSR = "ENABLED"; + ORCALUT4 i1994_3_lut (.A(FS[2]), .B(FS[5]), .C(FS[9]), .Z(n2290)) /* synthesis lut_function=(A+(B+(C))) */ ; + defparam i1994_3_lut.init = 16'hfefe; + ORCALUT4 i1_2_lut_3_lut (.A(MAin_c_0), .B(n1326), .C(MAin_c_1), .Z(n2263)) /* synthesis lut_function=((B+!(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(80[15:31]) + defparam i1_2_lut_3_lut.init = 16'hdfdf; + FD1S3AX PHI2r3_378 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r3_378.GSR = "ENABLED"; + FD1S3AX RASr_379 (.D(nCRAS_N_9), .CK(RCLK_c), .Q(RASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr_379.GSR = "ENABLED"; + FD1S3AX RASr2_380 (.D(RASr), .CK(RCLK_c), .Q(RASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr2_380.GSR = "ENABLED"; + FD1S3AX RASr3_381 (.D(RASr2), .CK(RCLK_c), .Q(RASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam RASr3_381.GSR = "ENABLED"; + FD1S3AX CASr_382 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr_382.GSR = "ENABLED"; + FD1S3AX CASr2_383 (.D(CASr), .CK(RCLK_c), .Q(CASr2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr2_383.GSR = "ENABLED"; + FD1S3AX CASr3_384 (.D(CASr2), .CK(RCLK_c), .Q(CASr3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam CASr3_384.GSR = "ENABLED"; + FD1S3IX RA11_385 (.D(RA11_N_184), .CK(PHI2_c), .CD(n2477), .Q(RA_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam RA11_385.GSR = "ENABLED"; + FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i0.GSR = "ENABLED"; + ORCALUT4 i637_1_lut_rep_34 (.A(Ready), .Z(n2477)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i637_1_lut_rep_34.init = 16'h5555; + FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i0.GSR = "ENABLED"; + FD1S3AX FWEr_389 (.D(nFWE_N_5), .CK(nCRAS_N_9), .Q(FWEr)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam FWEr_389.GSR = "ENABLED"; + FD1S3AX CBR_390 (.D(nCCAS_N_3), .CK(nCRAS_N_9), .Q(CBR)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam CBR_390.GSR = "ENABLED"; + FD1S3IX ADSubmitted_407 (.D(n1413), .CK(PHI2_N_120), .CD(C1Submitted_N_237), + .Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam ADSubmitted_407.GSR = "ENABLED"; + ORCALUT4 i2026_4_lut (.A(FS[0]), .B(FS[1]), .C(FS[6]), .D(FS[3]), + .Z(n2322)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i2026_4_lut.init = 16'hfffe; + FD1S3AX RCKE_395 (.D(RCKE_N_132), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(141[9] 144[5]) + defparam RCKE_395.GSR = "ENABLED"; + FD1P3AY nRCS_396 (.D(nRCS_N_136), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(nRCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRCS_396.GSR = "ENABLED"; + FD1S3IX nRowColSel_402 (.D(n1410), .CK(RCLK_c), .CD(n2469), .Q(nRowColSel)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRowColSel_402.GSR = "ENABLED"; + ORCALUT4 n8MEGEN_I_14_4_lut (.A(UFMSDO_c), .B(Cmdn8MEGEN), .C(InitReady), + .D(n1325), .Z(n8MEGEN_N_91)) /* synthesis lut_function=(A (B (C+(D)))+!A (B+!(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(394[12] 409[6]) + defparam n8MEGEN_I_14_4_lut.init = 16'hccc5; + ORCALUT4 i771_2_lut_rep_26_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2469)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i771_2_lut_rep_26_2_lut.init = 16'hdddd; + ORCALUT4 i7_4_lut (.A(FS[10]), .B(n2328), .C(n2272), .D(FS[11]), + .Z(n2214)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i7_4_lut.init = 16'h0200; + ORCALUT4 i2062_2_lut_3_lut_4_lut (.A(nFWE_c), .B(n1326), .C(C1Submitted), + .D(MAin_c_1), .Z(n6_adj_3)) /* synthesis lut_function=(A (C)+!A (B (C)+!B !((D)+!C))) */ ; + defparam i2062_2_lut_3_lut_4_lut.init = 16'he0f0; + ORCALUT4 i2046_1_lut_2_lut_3_lut_3_lut (.A(Ready), .B(n13), .C(nRCS_N_139), + .Z(n2337)) /* synthesis lut_function=(!(A (B)+!A !((C)+!B))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i2046_1_lut_2_lut_3_lut_3_lut.init = 16'h7373; + ORCALUT4 i3_3_lut_4_lut_4_lut (.A(Ready), .B(InitReady), .C(RASr2), + .D(nRowColSel_N_35), .Z(RCLK_c_enable_23)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i3_3_lut_4_lut_4_lut.init = 16'h4000; + ORCALUT4 i2065_2_lut_3_lut (.A(FS[11]), .B(n2464), .C(InitReady), + .Z(n1846)) /* synthesis lut_function=(!(A+(B+(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i2065_2_lut_3_lut.init = 16'h0101; + ORCALUT4 i2055_3_lut_4_lut (.A(FS[11]), .B(n2464), .C(FS[10]), .D(InitReady), + .Z(LEDEN_N_82)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i2055_3_lut_4_lut.init = 16'h0001; + ORCALUT4 i2_3_lut (.A(n2214), .B(FS[11]), .C(InitReady), .Z(RCLK_c_enable_12)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam i2_3_lut.init = 16'h0808; + CCU2 FS_610_add_4_8 (.A0(FS[6]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[7]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2010), + .COUT1(n2011), .S0(n89), .S1(n88)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_8.INIT0 = 16'hfaaa; + defparam FS_610_add_4_8.INIT1 = 16'hfaaa; + defparam FS_610_add_4_8.INJECT1_0 = "NO"; + defparam FS_610_add_4_8.INJECT1_1 = "NO"; + FD1S3IX S_FSM_i3 (.D(n1093), .CK(RCLK_c), .CD(n1425), .Q(nRowColSel_N_33)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i3.GSR = "ENABLED"; + ORCALUT4 Ready_bdd_4_lut (.A(nRowColSel_N_32), .B(RASr2), .C(Ready_N_296), + .D(InitReady), .Z(n2414)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ; + defparam Ready_bdd_4_lut.init = 16'h2000; + FD1S3AY nRRAS_397 (.D(n2138), .CK(RCLK_c), .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRRAS_397.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_2_lut (.A(Ready), .B(nRowColSel_N_34), .Z(n56)) /* synthesis lut_function=((B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i1_2_lut_2_lut.init = 16'hdddd; + ORCALUT4 i2_4_lut (.A(Din_c_2), .B(n2463), .C(n1280), .D(n2468), + .Z(C1Submitted_N_237)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ; + defparam i2_4_lut.init = 16'h0400; + ORCALUT4 i1_2_lut_3_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_32), + .C(n1502), .D(nRowColSel_N_35), .Z(RCLK_c_enable_3)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam i1_2_lut_3_lut_4_lut_4_lut.init = 16'hfffd; + ORCALUT4 Din_7__I_0_462_i6_2_lut_rep_35 (.A(Din_c_6), .B(Din_c_7), .Z(n2478)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) + defparam Din_7__I_0_462_i6_2_lut_rep_35.init = 16'heeee; + BB Dout_pad_7__713 (.I(WRD[7]), .T(n984), .B(RD[7]), .O(Dout_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + FD1P3AY nRCAS_398 (.D(nRCAS_N_161), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRCAS_398.GSR = "ENABLED"; + FD1P3AY nRWE_399 (.D(nRWE_N_171), .SP(RCLK_c_enable_3), .CK(RCLK_c), + .Q(nRWE_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam nRWE_399.GSR = "ENABLED"; + FD1S3JX RA10_400 (.D(n2209), .CK(RCLK_c), .PD(nRWE_N_176), .Q(RA_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam RA10_400.GSR = "ENABLED"; + FD1P3AX RCKEEN_401 (.D(RCKEEN_N_121), .SP(RCLK_c_enable_4), .CK(RCLK_c), + .Q(RCKEEN)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam RCKEEN_401.GSR = "ENABLED"; + FD1S3AX FS_610__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i0.GSR = "ENABLED"; + ORCALUT4 i13_4_lut (.A(MAin_c_2), .B(n26), .C(n2316), .D(MAin_c_5), + .Z(n1326)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; + defparam i13_4_lut.init = 16'hdfff; + ORCALUT4 i12_4_lut (.A(Bank[2]), .B(n2314), .C(n2278), .D(Bank[5]), + .Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ; + defparam i12_4_lut.init = 16'hbfff; + ORCALUT4 i2_3_lut_adj_1 (.A(MAin_c_1), .B(n1326), .C(MAin_c_0), .Z(n1280)) /* synthesis lut_function=((B+(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(80[15:31]) + defparam i2_3_lut_adj_1.init = 16'hfdfd; + FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_N_9), .CD(n2477), .Q(RBA_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RBA__i1.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_3_lut_adj_2 (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5), + .Z(n1314)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(315[17:31]) + defparam i1_2_lut_3_lut_adj_2.init = 16'hfefe; + ORCALUT4 i2020_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]), + .Z(n2316)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i2020_4_lut.init = 16'h8000; + ORCALUT4 i1990_2_lut_rep_17 (.A(nFWE_c), .B(n1326), .Z(n2460)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1990_2_lut_rep_17.init = 16'heeee; + ORCALUT4 i1125_4_lut (.A(n2459), .B(n2242), .C(ADSubmitted), .D(n2263), + .Z(n1413)) /* synthesis lut_function=(!(A ((D)+!B)+!A !(B (C+!(D))+!B (C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam i1125_4_lut.init = 16'h50dc; + ORCALUT4 i2018_4_lut (.A(MAin_c_6), .B(MAin_c_4), .C(Bank[7]), .D(Bank[0]), + .Z(n2314)) /* synthesis lut_function=(A (B (C (D)))) */ ; + defparam i2018_4_lut.init = 16'h8000; + ORCALUT4 i4_4_lut (.A(Din_c_4), .B(n2478), .C(CmdEnable), .D(MAin_c_1), + .Z(n10)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; + defparam i4_4_lut.init = 16'h0020; + ORCALUT4 i2_2_lut_rep_27 (.A(FS[16]), .B(FS[14]), .Z(n2470)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i2_2_lut_rep_27.init = 16'heeee; + ORCALUT4 i2_3_lut_4_lut (.A(nRowColSel_N_32), .B(n2469), .C(nRowColSel_N_34), + .D(nRowColSel_N_33), .Z(RCLK_c_enable_4)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i2_3_lut_4_lut.init = 16'hfffe; + ORCALUT4 Cmdn8MEGEN_I_93_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_4), + .D(n1314), .Z(Cmdn8MEGEN_N_264)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(321[13] 335[7]) + defparam Cmdn8MEGEN_I_93_4_lut.init = 16'hcc5c; + ORCALUT4 i1982_2_lut (.A(Bank[6]), .B(Bank[3]), .Z(n2278)) /* synthesis lut_function=(A (B)) */ ; + defparam i1982_2_lut.init = 16'h8888; + ORCALUT4 i2_4_lut_adj_3 (.A(Din_c_3), .B(Din_c_4), .C(Din_c_5), .D(n2458), + .Z(PHI2_N_120_enable_5)) /* synthesis lut_function=(A (B (D))+!A !((C+!(D))+!B)) */ ; + defparam i2_4_lut_adj_3.init = 16'h8c00; + FD1P3AX IS_FSM__i0 (.D(Ready_N_296), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRCS_N_139)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i0.GSR = "ENABLED"; + FD1S3JX C1Submitted_406 (.D(n6_adj_3), .CK(PHI2_N_120), .PD(C1Submitted_N_237), + .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam C1Submitted_406.GSR = "ENABLED"; + FD1S3JX nUFMCS_415 (.D(n2164), .CK(RCLK_c), .PD(LEDEN_N_82), .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam nUFMCS_415.GSR = "ENABLED"; + ORCALUT4 i2049_3_lut (.A(LEDEN), .B(CBR), .C(nCRAS_c), .Z(LED_N_84)) /* synthesis lut_function=((B+(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[15:41]) + defparam i2049_3_lut.init = 16'hfdfd; + ORCALUT4 MAin_9__I_0_427_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel), + .Z(RA_1_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i10_3_lut.init = 16'hcaca; + FD1S3AX S_FSM_i1 (.D(RASr2_N_63), .CK(RCLK_c), .Q(nRowColSel_N_35)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i1.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_3_lut_adj_4 (.A(FS[11]), .B(n2464), .C(FS[10]), + .Z(n1325)) /* synthesis lut_function=((B+!(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_3_lut_adj_4.init = 16'hdfdf; + ORCALUT4 MAin_9__I_0_427_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel), + .Z(RA_1_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i9_3_lut.init = 16'hcaca; + ORCALUT4 MAin_9__I_0_427_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel), + .Z(RA_1_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i8_3_lut.init = 16'hcaca; + ORCALUT4 i1209_4_lut_else_4_lut (.A(nRCS_N_139), .B(Ready), .C(nRowColSel_N_35), + .Z(n2479)) /* synthesis lut_function=(!(A (B (C))+!A (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(48[6:16]) + defparam i1209_4_lut_else_4_lut.init = 16'h2f2f; + ORCALUT4 i1_2_lut_3_lut_adj_5 (.A(MAin_c_0), .B(n1326), .C(MAin_c_1), + .Z(n2262)) /* synthesis lut_function=((B+(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(80[15:31]) + defparam i1_2_lut_3_lut_adj_5.init = 16'hfdfd; + ORCALUT4 i2045_1_lut_4_lut (.A(n56), .B(nRRAS_c), .C(n6), .D(nRowColSel_N_32), + .Z(n2336)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i2045_1_lut_4_lut.init = 16'hfffe; + FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i0.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_4_lut (.A(MAin_c_0), .B(n10), .C(n2460), .D(n2476), + .Z(PHI2_N_120_enable_6)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i1_2_lut_4_lut.init = 16'h0800; + ORCALUT4 i2_3_lut_rep_29 (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), + .Z(n2472)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) + defparam i2_3_lut_rep_29.init = 16'h0808; + ORCALUT4 nRowColSel_N_34_bdd_3_lut_2115 (.A(nRowColSel_N_34), .B(n15_adj_1), + .C(Ready), .Z(n2430)) /* synthesis lut_function=(A+!(B (C))) */ ; + defparam nRowColSel_N_34_bdd_3_lut_2115.init = 16'hbfbf; + ORCALUT4 i4_4_lut_adj_6 (.A(MAin_c_1), .B(n2476), .C(MAin_c_0), .D(n2284), + .Z(n2257)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ; + defparam i4_4_lut_adj_6.init = 16'h0080; + FD1S3AX PHI2r_376 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam PHI2r_376.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_4_lut_adj_7 (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2), + .D(InitReady), .Z(RCLK_c_enable_24)) /* synthesis lut_function=(!(A (B (C (D))+!B (D))+!A (D))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(402[16:47]) + defparam i1_2_lut_4_lut_adj_7.init = 16'h08ff; + ORCALUT4 i2024_2_lut_rep_28 (.A(FS[17]), .B(FS[12]), .Z(n2471)) /* synthesis lut_function=(A+(B)) */ ; + defparam i2024_2_lut_rep_28.init = 16'heeee; + FD1S3IX S_FSM_i4 (.D(n1503), .CK(RCLK_c), .CD(RASr2_N_63), .Q(nRowColSel_N_32)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i4.GSR = "ENABLED"; + CCU2 FS_610_add_4_16 (.A0(FS[14]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[15]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2014), + .COUT1(n2015), .S0(n81), .S1(n80)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_16.INIT0 = 16'hfaaa; + defparam FS_610_add_4_16.INIT1 = 16'hfaaa; + defparam FS_610_add_4_16.INJECT1_0 = "NO"; + defparam FS_610_add_4_16.INJECT1_1 = "NO"; + ORCALUT4 i2_3_lut_4_lut_adj_8 (.A(nRowColSel_N_35), .B(RASr2), .C(InitReady), + .D(nRCS_N_139), .Z(n2208)) /* synthesis lut_function=((((D)+!C)+!B)+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i2_3_lut_4_lut_adj_8.init = 16'hff7f; + ORCALUT4 i1_4_lut_4_lut_adj_9 (.A(CBR), .B(n11), .C(FWEr), .D(nRowColSel_N_34), + .Z(RCKEEN_N_123)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(23[27:31]) + defparam i1_4_lut_4_lut_adj_9.init = 16'h5540; + ORCALUT4 i3_4_lut (.A(CBR), .B(FWEr), .C(CASr2), .D(CASr3), .Z(n1)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ; + defparam i3_4_lut.init = 16'h0040; + PFUMX i2095 (.BLUT(n2430), .ALUT(n2457), .C0(nRowColSel_N_35), .Z(nRCAS_N_161)); + ORCALUT4 MAin_9__I_0_427_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel), + .Z(RA_1_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i7_3_lut.init = 16'hcaca; + ORCALUT4 i1_4_lut (.A(nRowColSel), .B(n1502), .C(nRowColSel_N_28), + .D(nRowColSel_N_32), .Z(n1410)) /* synthesis lut_function=(A (B+!(C (D)))+!A (B+!(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1_4_lut.init = 16'hcfee; + ORCALUT4 i1_2_lut (.A(RASr2), .B(RCKE_c), .Z(nRWE_N_182)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(91[9] 95[5]) + defparam i1_2_lut.init = 16'hbbbb; + ORCALUT4 i2004_2_lut_rep_30 (.A(Din_c_4), .B(nFWE_c), .Z(n2473)) /* synthesis lut_function=(A+(B)) */ ; + defparam i2004_2_lut_rep_30.init = 16'heeee; + ORCALUT4 i1_2_lut_rep_20_3_lut (.A(Din_c_4), .B(nFWE_c), .C(n2253), + .Z(n2463)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; + defparam i1_2_lut_rep_20_3_lut.init = 16'h1010; + ORCALUT4 i2_3_lut_adj_10 (.A(Din_c_7), .B(Din_c_0), .C(Din_c_1), .Z(n2253)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; + defparam i2_3_lut_adj_10.init = 16'h0808; + CCU2 FS_610_add_4_6 (.A0(FS[4]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[5]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2009), + .COUT1(n2010), .S0(n91), .S1(n90)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_6.INIT0 = 16'hfaaa; + defparam FS_610_add_4_6.INIT1 = 16'hfaaa; + defparam FS_610_add_4_6.INJECT1_0 = "NO"; + defparam FS_610_add_4_6.INJECT1_1 = "NO"; + ORCALUT4 i2_4_lut_adj_11 (.A(n2473), .B(CmdEnable), .C(n2262), .D(n1314), + .Z(PHI2_N_120_enable_1)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; + defparam i2_4_lut_adj_11.init = 16'h0004; + ORCALUT4 MAin_9__I_0_427_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel), + .Z(RA_1_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i6_3_lut.init = 16'hcaca; + ORCALUT4 i3_4_lut_adj_12 (.A(Din_c_0), .B(Din_c_3), .C(Din_c_2), .D(n2324), + .Z(XOR8MEG_N_110)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; + defparam i3_4_lut_adj_12.init = 16'h0020; + ORCALUT4 MAin_9__I_0_427_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel), + .Z(RA_1_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i5_3_lut.init = 16'hcaca; + ORCALUT4 i2028_4_lut (.A(Din_c_4), .B(LEDEN), .C(n1314), .D(Din_c_1), + .Z(n2324)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ; + defparam i2028_4_lut.init = 16'hfefa; + ORCALUT4 MAin_9__I_0_427_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel), + .Z(RA_1_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i4_3_lut.init = 16'hcaca; + ORCALUT4 i2_3_lut_rep_31 (.A(Din_c_6), .B(Din_c_2), .C(Din_c_3), .Z(n2474)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i2_3_lut_rep_31.init = 16'h4040; + FD1P3IX UFMSDI_417 (.D(UFMSDI_N_231), .SP(RCLK_c_enable_24), .CD(n1846), + .CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam UFMSDI_417.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_4_lut_adj_13 (.A(Din_c_6), .B(Din_c_2), .C(Din_c_3), + .D(MAin_c_0), .Z(n2243)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i1_2_lut_4_lut_adj_13.init = 16'h4000; + ORCALUT4 MAin_9__I_0_427_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel), + .Z(RA_1_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i3_3_lut.init = 16'hcaca; + ORCALUT4 n2427_bdd_4_lut_4_lut (.A(CBR), .B(RASr2), .C(Ready), .D(n2427), + .Z(n2457)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A !((C+(D))+!B))) */ ; + defparam n2427_bdd_4_lut_4_lut.init = 16'h7f73; + GSR GSR_INST (.GSR(VCC_net)); + ORCALUT4 i2_3_lut_adj_14 (.A(FWEr), .B(CASr3), .C(CBR), .Z(nRowColSel_N_28)) /* synthesis lut_function=((B+(C))+!A) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(230[16:37]) + defparam i2_3_lut_adj_14.init = 16'hfdfd; + ORCALUT4 InitReady_bdd_3_lut (.A(InitReady), .B(nRCS_N_139), .C(nRCAS_N_165), + .Z(n2427)) /* synthesis lut_function=((B+(C))+!A) */ ; + defparam InitReady_bdd_3_lut.init = 16'hfdfd; + ORCALUT4 i35_3_lut_4_lut (.A(FWEr), .B(CBR), .C(nRowColSel_N_33), + .D(n1), .Z(n15_adj_1)) /* synthesis lut_function=(!(A (C+!(D))+!A (B (C+!(D))+!B !(C+(D))))) */ ; + defparam i35_3_lut_4_lut.init = 16'h1f10; + ORCALUT4 MAin_9__I_0_427_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel), + .Z(RA_1_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i2_3_lut.init = 16'hcaca; + CCU2 FS_610_add_4_14 (.A0(FS[12]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[13]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2013), + .COUT1(n2014), .S0(n83), .S1(n82)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_14.INIT0 = 16'hfaaa; + defparam FS_610_add_4_14.INIT1 = 16'hfaaa; + defparam FS_610_add_4_14.INJECT1_0 = "NO"; + defparam FS_610_add_4_14.INJECT1_1 = "NO"; + ORCALUT4 i2_3_lut_4_lut_adj_15 (.A(n2473), .B(n2253), .C(Din_c_5), + .D(n2474), .Z(n2242)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; + defparam i2_3_lut_4_lut_adj_15.init = 16'h4000; + ORCALUT4 n2414_bdd_2_lut (.A(n2414), .B(Ready), .Z(Ready_N_292)) /* synthesis lut_function=(A+(B)) */ ; + defparam n2414_bdd_2_lut.init = 16'heeee; + ORCALUT4 i1_2_lut_adj_16 (.A(nRowColSel_N_34), .B(nRowColSel_N_33), + .Z(n1502)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1_2_lut_adj_16.init = 16'heeee; + ORCALUT4 RCKE_I_0_449_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3), + .Z(RCKE_N_132)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[11:55]) + defparam RCKE_I_0_449_4_lut.init = 16'hcfc8; + ORCALUT4 i1_4_lut_adj_17 (.A(n2467), .B(n2481), .C(n13), .D(nRowColSel_N_35), + .Z(nRCS_N_136)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B+!(C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(48[6:16]) + defparam i1_4_lut_adj_17.init = 16'hcfdd; + FD1P3AX IS_FSM__i15 (.D(n726), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(Ready_N_296)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i15.GSR = "ENABLED"; + ORCALUT4 MAin_9__I_0_427_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel), + .Z(RA_1_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(55[19:54]) + defparam MAin_9__I_0_427_i1_3_lut.init = 16'hcaca; + ORCALUT4 i1558_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(RCKEEN_N_130)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ; + defparam i1558_2_lut_3_lut.init = 16'h1f1f; + ORCALUT4 RA11_I_54_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_184)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(99[22:51]) + defparam RA11_I_54_3_lut.init = 16'hc6c6; + ORCALUT4 i17_4_lut (.A(n7), .B(n2472), .C(InitReady), .D(n8), .Z(RCLK_c_enable_11)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B (C))) */ ; + defparam i17_4_lut.init = 16'hcac0; + ORCALUT4 i1234_4_lut_4_lut (.A(RASr2), .B(InitReady), .C(RCKE_c), + .D(Ready), .Z(n13)) /* synthesis lut_function=(A (B+(D))+!A (C (D))) */ ; + defparam i1234_4_lut_4_lut.init = 16'hfa88; + ORCALUT4 i2_2_lut (.A(FS[8]), .B(n2214), .Z(n7)) /* synthesis lut_function=(!(A+!(B))) */ ; + defparam i2_2_lut.init = 16'h4444; + ORCALUT4 i78_2_lut_rep_24_3_lut (.A(RASr2), .B(InitReady), .C(Ready), + .Z(n2467)) /* synthesis lut_function=(A (B+(C))+!A (C)) */ ; + defparam i78_2_lut_rep_24_3_lut.init = 16'hf8f8; + FD1P3AX IS_FSM__i14 (.D(n727), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n726)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i14.GSR = "ENABLED"; + FD1P3AX IS_FSM__i13 (.D(n728), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n727)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i13.GSR = "ENABLED"; + ORCALUT4 i2_2_lut_3_lut_4_lut (.A(RASr2), .B(InitReady), .C(nRowColSel_N_33), + .D(Ready), .Z(n6)) /* synthesis lut_function=(A (B (C)+!B (C+!(D)))+!A (C+!(D))) */ ; + defparam i2_2_lut_3_lut_4_lut.init = 16'hf0f7; + ORCALUT4 i1512_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(58[17:46]) + defparam i1512_2_lut.init = 16'hbbbb; + ORCALUT4 i1_1_lut (.A(nFWE_c), .Z(nFWE_N_5)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam i1_1_lut.init = 16'h5555; + FD1P3AX IS_FSM__i12 (.D(n729), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n728)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i12.GSR = "ENABLED"; + FD1P3AX XOR8MEG_408 (.D(XOR8MEG_N_110), .SP(PHI2_N_120_enable_1), .CK(PHI2_N_120), + .Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam XOR8MEG_408.GSR = "ENABLED"; + FD1P3AX n8MEGEN_418 (.D(n8MEGEN_N_91), .SP(RCLK_c_enable_11), .CK(RCLK_c), + .Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam n8MEGEN_418.GSR = "ENABLED"; + FD1P3AX LEDEN_419 (.D(n2568), .SP(RCLK_c_enable_12), .CK(RCLK_c), + .Q(LEDEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam LEDEN_419.GSR = "ENABLED"; + PFUMX i16 (.BLUT(n2336), .ALUT(n2337), .C0(nRowColSel_N_35), .Z(n2138)); + FD1P3AX Ready_404 (.D(n2568), .SP(Ready_N_292), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(147[9] 285[5]) + defparam Ready_404.GSR = "ENABLED"; + FD1P3AX CmdUFMCLK_413 (.D(Din_c_1), .SP(PHI2_N_120_enable_6), .CK(PHI2_N_120), + .Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMCLK_413.GSR = "ENABLED"; + FD1P3AX CmdUFMSDI_414 (.D(Din_c_0), .SP(PHI2_N_120_enable_6), .CK(PHI2_N_120), + .Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMSDI_414.GSR = "ENABLED"; + FD1P3AX Cmdn8MEGEN_410 (.D(Cmdn8MEGEN_N_264), .SP(PHI2_N_120_enable_4), + .CK(PHI2_N_120), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam Cmdn8MEGEN_410.GSR = "ENABLED"; + FD1P3AX CmdSubmitted_411 (.D(n2568), .SP(PHI2_N_120_enable_5), .CK(PHI2_N_120), + .Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdSubmitted_411.GSR = "ENABLED"; + FD1P3AX CmdUFMCS_412 (.D(Din_c_2), .SP(PHI2_N_120_enable_6), .CK(PHI2_N_120), + .Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdUFMCS_412.GSR = "ENABLED"; + FD1P3AX IS_FSM__i11 (.D(n730), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n729)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i11.GSR = "ENABLED"; + ORCALUT4 i2060_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ; + defparam i2060_2_lut.init = 16'h7777; + ORCALUT4 i1_2_lut_rep_32 (.A(Din_c_6), .B(Din_c_3), .Z(n2475)) /* synthesis lut_function=(!((B)+!A)) */ ; + defparam i1_2_lut_rep_32.init = 16'h2222; + FD1P3AX IS_FSM__i10 (.D(nRWE_N_177), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n730)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i10.GSR = "ENABLED"; + ORCALUT4 i3_4_lut_adj_18 (.A(n2290), .B(FS[4]), .C(n2322), .D(FS[7]), + .Z(n8)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; + defparam i3_4_lut_adj_18.init = 16'h0004; + ORCALUT4 i886_3_lut (.A(CmdUFMCLK), .B(n1160), .C(InitReady), .Z(UFMCLK_N_224)) /* synthesis lut_function=(A (B+(C))+!A !((C)+!B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(386[12] 409[6]) + defparam i886_3_lut.init = 16'hacac; + FD1P3AX IS_FSM__i9 (.D(n732), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRWE_N_177)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i9.GSR = "ENABLED"; + ORCALUT4 i2_3_lut_4_lut_adj_19 (.A(Din_c_6), .B(Din_c_3), .C(Din_c_2), + .D(MAin_c_0), .Z(n2245)) /* synthesis lut_function=(!((B+(C+(D)))+!A)) */ ; + defparam i2_3_lut_4_lut_adj_19.init = 16'h0002; + ORCALUT4 i919_4_lut (.A(FS[4]), .B(n62), .C(n2462), .D(FS[1]), .Z(n1160)) /* synthesis lut_function=(!(A (B (C)+!B !((D)+!C))+!A (B+!(C (D))))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(386[12] 409[6]) + defparam i919_4_lut.init = 16'h3a0a; + ORCALUT4 i2052_4_lut (.A(MAin_c_0), .B(n2460), .C(n14), .D(MAin_c_1), + .Z(PHI2_N_120_enable_7)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C+!(D))))) */ ; + defparam i2052_4_lut.init = 16'h0302; + ORCALUT4 i2_3_lut_adj_20 (.A(n2253), .B(Din_c_4), .C(n13_adj_2), .Z(n14)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ; + defparam i2_3_lut_adj_20.init = 16'h2020; + ORCALUT4 i1136_1_lut (.A(nRowColSel_N_34), .Z(n1425)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1136_1_lut.init = 16'h5555; + FD1P3AX IS_FSM__i8 (.D(n733), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n732)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i8.GSR = "ENABLED"; + FD1P3AX IS_FSM__i7 (.D(n734), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n733)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i7.GSR = "ENABLED"; + FD1P3AX IS_FSM__i6 (.D(n735), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n734)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i6.GSR = "ENABLED"; + FD1P3AX IS_FSM__i5 (.D(n736), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n735)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i5.GSR = "ENABLED"; + FD1P3AX IS_FSM__i4 (.D(n737), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n736)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i4.GSR = "ENABLED"; + FD1P3AX IS_FSM__i3 (.D(n738), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n737)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i3.GSR = "ENABLED"; + FD1P3AX IS_FSM__i2 (.D(nRCAS_N_165), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(n738)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i2.GSR = "ENABLED"; + FD1P3AX IS_FSM__i1 (.D(nRCS_N_139), .SP(RCLK_c_enable_23), .CK(RCLK_c), + .Q(nRCAS_N_165)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263[11:15]) + defparam IS_FSM__i1.GSR = "ENABLED"; + FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_N_9), .CD(n2477), .Q(RBA_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RBA__i2.GSR = "ENABLED"; + FD1S3AX FS_610__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i17.GSR = "ENABLED"; + FD1S3AX FS_610__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i16.GSR = "ENABLED"; + FD1S3AX FS_610__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i15.GSR = "ENABLED"; + FD1S3AX FS_610__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i14.GSR = "ENABLED"; + FD1S3AX FS_610__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i13.GSR = "ENABLED"; + FD1S3AX FS_610__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i12.GSR = "ENABLED"; + FD1S3AX FS_610__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i11.GSR = "ENABLED"; + FD1S3AX FS_610__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i10.GSR = "ENABLED"; + FD1S3AX FS_610__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i9.GSR = "ENABLED"; + FD1S3AX FS_610__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i8.GSR = "ENABLED"; + FD1S3AX FS_610__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i7.GSR = "ENABLED"; + FD1S3AX FS_610__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i6.GSR = "ENABLED"; + FD1S3AX FS_610__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i5.GSR = "ENABLED"; + FD1S3AX FS_610__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i4.GSR = "ENABLED"; + FD1S3AX FS_610__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i3.GSR = "ENABLED"; + FD1S3AX FS_610__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i2.GSR = "ENABLED"; + FD1S3AX FS_610__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610__i1.GSR = "ENABLED"; + FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i7.GSR = "ENABLED"; + ORCALUT4 i3_4_lut_adj_21 (.A(MAin_c_1), .B(n2463), .C(n1326), .D(n15), + .Z(CmdEnable_N_248)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ; + defparam i3_4_lut_adj_21.init = 16'h0800; + FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i6.GSR = "ENABLED"; + FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i5.GSR = "ENABLED"; + FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i4.GSR = "ENABLED"; + FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i3.GSR = "ENABLED"; + FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i2.GSR = "ENABLED"; + FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(123[9] 125[5]) + defparam WRD_i1.GSR = "ENABLED"; + FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_N_9), .PD(n2477), .Q(RowA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i9.GSR = "ENABLED"; + FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i8.GSR = "ENABLED"; + FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i7.GSR = "ENABLED"; + FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i6.GSR = "ENABLED"; + FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_N_9), .PD(n2477), .Q(RowA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i5.GSR = "ENABLED"; + FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i4.GSR = "ENABLED"; + FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i3.GSR = "ENABLED"; + FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i2.GSR = "ENABLED"; + FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_N_9), .CD(n2477), .Q(RowA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(105[9] 120[5]) + defparam RowA_i1.GSR = "ENABLED"; + FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i7.GSR = "ENABLED"; + ORCALUT4 i1_2_lut_rep_25_3_lut (.A(Din_c_6), .B(Din_c_3), .C(Din_c_5), + .Z(n2468)) /* synthesis lut_function=(!((B+(C))+!A)) */ ; + defparam i1_2_lut_rep_25_3_lut.init = 16'h0202; + ORCALUT4 i5_3_lut_rep_15_4_lut (.A(nFWE_c), .B(n1326), .C(n10), .D(MAin_c_0), + .Z(n2458)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; + defparam i5_3_lut_rep_15_4_lut.init = 16'h1000; + FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i6.GSR = "ENABLED"; + FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i5.GSR = "ENABLED"; + FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i4.GSR = "ENABLED"; + FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i3.GSR = "ENABLED"; + FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i2.GSR = "ENABLED"; + FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(98[9] 102[5]) + defparam Bank_i1.GSR = "ENABLED"; + ORCALUT4 FS_6__bdd_4_lut (.A(FS[7]), .B(FS[9]), .C(FS[5]), .D(FS[8]), + .Z(n2451)) /* synthesis lut_function=(!(A (B+(D))+!A (((D)+!C)+!B))) */ ; + defparam FS_6__bdd_4_lut.init = 16'h0062; + BB Dout_pad_6__714 (.I(WRD[6]), .T(n984), .B(RD[6]), .O(Dout_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_5__715 (.I(WRD[5]), .T(n984), .B(RD[5]), .O(Dout_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + ORCALUT4 i1_2_lut_rep_16_3_lut (.A(nFWE_c), .B(n1326), .C(MAin_c_1), + .Z(n2459)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ; + defparam i1_2_lut_rep_16_3_lut.init = 16'h1010; + BB Dout_pad_4__716 (.I(WRD[4]), .T(n984), .B(RD[4]), .O(Dout_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_3__717 (.I(WRD[3]), .T(n984), .B(RD[3]), .O(Dout_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_2__718 (.I(WRD[2]), .T(n984), .B(RD[2]), .O(Dout_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + ORCALUT4 i1_2_lut_rep_33 (.A(Din_c_3), .B(Din_c_5), .Z(n2476)) /* synthesis lut_function=(A (B)) */ ; + defparam i1_2_lut_rep_33.init = 16'h8888; + BB Dout_pad_1__719 (.I(WRD[1]), .T(n984), .B(RD[1]), .O(Dout_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + BB Dout_pad_0__720 (.I(WRD[0]), .T(n984), .B(RD[0]), .O(Dout_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(60[14:16]) + OB Dout_pad_7 (.I(Dout_c), .O(Dout[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_6 (.I(Dout_0), .O(Dout[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_5 (.I(Dout_1), .O(Dout[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_4 (.I(Dout_2), .O(Dout[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_3 (.I(Dout_3), .O(Dout[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_2 (.I(Dout_4), .O(Dout[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_1 (.I(Dout_5), .O(Dout[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB Dout_pad_0 (.I(Dout_6), .O(Dout[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(27[15:19]) + OB LED_pad (.I(LED_N_84), .O(LED)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(22[9:12]) + OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(47[19:22]) + OB RA_pad_11 (.I(RA_c), .O(RA[11])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_10 (.I(RA_0), .O(RA[10])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_9 (.I(RA_1_9), .O(RA[9])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_8 (.I(RA_1_8), .O(RA[8])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_7 (.I(RA_1_7), .O(RA[7])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_6 (.I(RA_1_6), .O(RA[6])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_5 (.I(RA_1_5), .O(RA[5])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_4 (.I(RA_1_4), .O(RA[4])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_3 (.I(RA_1_3), .O(RA[3])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_2 (.I(RA_1_2), .O(RA[2])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_1 (.I(RA_1_1), .O(RA[1])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB RA_pad_0 (.I(RA_1_0), .O(RA[0])); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(52[16:18]) + OB nRCS_pad (.I(nRCS_c), .O(nRCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[13:17]) + OB RCKE_pad (.I(RCKE_c), .O(RCKE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(45[13:17]) + OB nRWE_pad (.I(nRWE_c), .O(nRWE)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[45:49]) + OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[23:28]) + OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(46[34:39]) + OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[16:21]) + OB RDQML_pad (.I(RDQML_c), .O(RDQML)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(56[9:14]) + OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(63[13:19]) + OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(64[13:19]) + OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(65[13:19]) + IB PHI2_pad (.I(PHI2), .O(PHI2_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(8[8:12]) + IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(35[14:18]) + IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(34[14:18]) + IB Din_pad_7 (.I(Din[7]), .O(Din_c_7)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_6 (.I(Din[6]), .O(Din_c_6)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_5 (.I(Din[5]), .O(Din_c_5)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_4 (.I(Din[4]), .O(Din_c_4)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_3 (.I(Din[3]), .O(Din_c_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_2 (.I(Din[2]), .O(Din_c_2)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_1 (.I(Din[1]), .O(Din_c_1)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB Din_pad_0 (.I(Din[0]), .O(Din_c_0)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(26[14:17]) + IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + IB nFWE_pad (.I(nFWE), .O(nFWE_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(36[8:12]) + IB RCLK_pad (.I(RCLK), .O(RCLK_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(41[8:12]) + IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(66[8:14]) + ORCALUT4 i1_2_lut_rep_19_4_lut (.A(n2471), .B(n2272), .C(n2470), .D(FS[11]), + .Z(n2462)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_rep_19_4_lut.init = 16'hfeff; + CCU2 FS_610_add_4_2 (.A0(FS[0]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[1]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(GND_net), + .COUT1(n2008), .S0(n95), .S1(n94)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_2.INIT0 = 16'h0555; + defparam FS_610_add_4_2.INIT1 = 16'hfaaa; + defparam FS_610_add_4_2.INJECT1_0 = "NO"; + defparam FS_610_add_4_2.INJECT1_1 = "NO"; + ORCALUT4 i2057_2_lut (.A(nRowColSel_N_32), .B(RASr2), .Z(n1093)) /* synthesis lut_function=(!(A+!(B))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i2057_2_lut.init = 16'h4444; + ORCALUT4 n2454_bdd_3_lut_4_lut (.A(n2461), .B(n2462), .C(InitReady), + .D(CmdUFMSDI), .Z(UFMSDI_N_231)) /* synthesis lut_function=(A (B (C (D))+!B ((D)+!C))+!A (C (D))) */ ; + defparam n2454_bdd_3_lut_4_lut.init = 16'hf202; + FD1P3IX UFMCLK_416 (.D(UFMCLK_N_224), .SP(RCLK_c_enable_24), .CD(n1846), + .CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam UFMCLK_416.GSR = "ENABLED"; + FD1P3AX CmdEnable_405 (.D(CmdEnable_N_248), .SP(PHI2_N_120_enable_7), + .CK(PHI2_N_120), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(288[9] 337[5]) + defparam CmdEnable_405.GSR = "ENABLED"; + ORCALUT4 i1513_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n984)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1513_2_lut.init = 16'heeee; + ORCALUT4 n1_bdd_4_lut (.A(n1), .B(n1502), .C(nRWE_N_182), .D(nRowColSel_N_35), + .Z(nRWE_N_178)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ; + defparam n1_bdd_4_lut.init = 16'hf0dd; + CCU2 FS_610_add_4_12 (.A0(FS[10]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[11]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2012), + .COUT1(n2013), .S0(n85), .S1(n84)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_12.INIT0 = 16'hfaaa; + defparam FS_610_add_4_12.INIT1 = 16'hfaaa; + defparam FS_610_add_4_12.INJECT1_0 = "NO"; + defparam FS_610_add_4_12.INJECT1_1 = "NO"; + ORCALUT4 i1_2_lut_adj_22 (.A(n62), .B(FS[10]), .Z(RCLK_c_enable_25)) /* synthesis lut_function=(A (B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i1_2_lut_adj_22.init = 16'h8888; + ORCALUT4 i1209_4_lut_then_4_lut (.A(nRCS_N_139), .B(Ready), .C(nRowColSel_N_35), + .D(nRowColSel_N_34), .Z(n2480)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A (B (C+!(D))+!B (C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(48[6:16]) + defparam i1209_4_lut_then_4_lut.init = 16'h2f23; + ORCALUT4 nRWE_I_0_455_4_lut (.A(n33), .B(nRWE_N_178), .C(Ready), .D(n2208), + .Z(nRWE_N_171)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(232[12] 284[6]) + defparam nRWE_I_0_455_4_lut.init = 16'hcfc5; + ORCALUT4 nRWE_I_50_1_lut (.A(nRWE_N_177), .Z(nRWE_N_176)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(255[14] 262[8]) + defparam nRWE_I_50_1_lut.init = 16'h5555; + CCU2 FS_610_add_4_4 (.A0(FS[2]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[3]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2008), + .COUT1(n2009), .S0(n93), .S1(n92)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_4.INIT0 = 16'hfaaa; + defparam FS_610_add_4_4.INIT1 = 16'hfaaa; + defparam FS_610_add_4_4.INJECT1_0 = "NO"; + defparam FS_610_add_4_4.INJECT1_1 = "NO"; + CCU2 FS_610_add_4_10 (.A0(FS[8]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[9]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2011), + .COUT1(n2012), .S0(n87), .S1(n86)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_10.INIT0 = 16'hfaaa; + defparam FS_610_add_4_10.INIT1 = 16'hfaaa; + defparam FS_610_add_4_10.INJECT1_0 = "NO"; + defparam FS_610_add_4_10.INJECT1_1 = "NO"; + ORCALUT4 i1_2_lut_adj_23 (.A(nRowColSel_N_33), .B(CASr2), .Z(n11)) /* synthesis lut_function=(A+!(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(48[6:16]) + defparam i1_2_lut_adj_23.init = 16'hbbbb; + CCU2 FS_610_add_4_18 (.A0(FS[16]), .B0(GND_net), .C0(GND_net), .D0(GND_net), + .A1(FS[17]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n2015), + .S0(n79), .S1(n78)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam FS_610_add_4_18.INIT0 = 16'hfaaa; + defparam FS_610_add_4_18.INIT1 = 16'hfaaa; + defparam FS_610_add_4_18.INJECT1_0 = "NO"; + defparam FS_610_add_4_18.INJECT1_1 = "NO"; + ORCALUT4 i5_3_lut_rep_21_4_lut (.A(FS[16]), .B(FS[14]), .C(n2272), + .D(n2471), .Z(n2464)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i5_3_lut_rep_21_4_lut.init = 16'hfffe; + ORCALUT4 i1137_1_lut (.A(nRowColSel_N_35), .Z(n1426)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1137_1_lut.init = 16'h5555; + ORCALUT4 RASr2_I_0_1_lut (.A(RASr2), .Z(RASr2_N_63)) /* synthesis lut_function=(!(A)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(143[40:46]) + defparam RASr2_I_0_1_lut.init = 16'h5555; + ORCALUT4 n2452_bdd_2_lut_rep_18_3_lut (.A(n2451), .B(FS[6]), .C(FS[10]), + .Z(n2461)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ; + defparam n2452_bdd_2_lut_rep_18_3_lut.init = 16'h0808; + ORCALUT4 i2_3_lut_4_lut_adj_24 (.A(Din_c_5), .B(n2475), .C(MAin_c_0), + .D(ADSubmitted), .Z(n2227)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(309[7:24]) + defparam i2_3_lut_4_lut_adj_24.init = 16'h0004; + ORCALUT4 i1_2_lut_adj_25 (.A(nRowColSel_N_32), .B(nRowColSel_N_33), + .Z(n1503)) /* synthesis lut_function=(A+(B)) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i1_2_lut_adj_25.init = 16'heeee; + ORCALUT4 i5_4_lut (.A(FS[15]), .B(FS[13]), .C(FS[16]), .D(FS[11]), + .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136[9:13]) + defparam i5_4_lut.init = 16'h8000; + ORCALUT4 i1_2_lut_adj_26 (.A(nRCAS_N_165), .B(nRWE_N_177), .Z(n33)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1_2_lut_adj_26.init = 16'heeee; + ORCALUT4 i1259_3_lut (.A(InitReady), .B(RCKEEN_N_122), .C(Ready), + .Z(RCKEEN_N_121)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(84[6:11]) + defparam i1259_3_lut.init = 16'hcaca; + FD1P3AX InitReady_394 (.D(n2568), .SP(RCLK_c_enable_25), .CK(RCLK_c), + .Q(InitReady)) /* synthesis lse_init_val=0 */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(134[9] 138[5]) + defparam InitReady_394.GSR = "ENABLED"; + ORCALUT4 i11_3_lut (.A(n62), .B(n1417), .C(InitReady), .Z(n2164)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(21[6:11]) + defparam i11_3_lut.init = 16'hcaca; + PFUMX RCKEEN_I_0_445 (.BLUT(RCKEEN_N_123), .ALUT(RCKEEN_N_130), .C0(nRowColSel_N_35), + .Z(RCKEEN_N_122)); + ORCALUT4 i1129_3_lut (.A(nUFMCS_c), .B(CmdUFMCS), .C(n2472), .Z(n1417)) /* synthesis lut_function=(!(A (B (C))+!A (B+!(C)))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(340[9] 410[5]) + defparam i1129_3_lut.init = 16'h3a3a; + FD1S3IX S_FSM_i2 (.D(n1093), .CK(RCLK_c), .CD(n1426), .Q(nRowColSel_N_34)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam S_FSM_i2.GSR = "ENABLED"; + INV i2134 (.A(nCCAS_c), .Z(nCCAS_N_3)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[8:13]) + ORCALUT4 i1988_2_lut (.A(C1Submitted), .B(Din_c_6), .Z(n2284)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1988_2_lut.init = 16'heeee; + PFUMX i26 (.BLUT(n2227), .ALUT(n2257), .C0(Din_c_2), .Z(n13_adj_2)); + INV i2135 (.A(nCRAS_c), .Z(nCRAS_N_9)); // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(11[15:20]) + VLO i1 (.Z(GND_net)); + TSALL TSALL_INST (.TSALL(GND_net)); + ORCALUT4 i2_3_lut_adj_27 (.A(n2208), .B(Ready), .C(nRCAS_N_165), .Z(n2209)) /* synthesis lut_function=(A+(B+(C))) */ ; // d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131[13:16]) + defparam i2_3_lut_adj_27.init = 16'hfefe; + PUR PUR_INST (.PUR(VCC_net)); + defparam PUR_INST.RST_PULSE = 1; + ORCALUT4 i2032_2_lut_3_lut_4_lut (.A(FS[17]), .B(FS[12]), .C(FS[14]), + .D(FS[16]), .Z(n2328)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; + defparam i2032_2_lut_3_lut_4_lut.init = 16'hfffe; + ORCALUT4 i1976_2_lut (.A(FS[13]), .B(FS[15]), .Z(n2272)) /* synthesis lut_function=(A+(B)) */ ; + defparam i1976_2_lut.init = 16'heeee; + ORCALUT4 m1_lut (.Z(n2568)) /* synthesis lut_function=1, syn_instantiated=1 */ ; + defparam m1_lut.init = 16'hffff; + PFUMX i2099 (.BLUT(n2479), .ALUT(n2480), .C0(n15_adj_1), .Z(n2481)); + PFUMX i26_adj_28 (.BLUT(n2245), .ALUT(n2243), .C0(Din_c_5), .Z(n15)); + +endmodule +// +// Verilog Description of module TSALL +// module not written out since it is a black-box. +// + +// +// Verilog Description of module PUR +// module not written out since it is a black-box. +// + diff --git a/CPLD/LCMXO640C/impl1/automake.log b/CPLD/LCMXO640C/impl1/automake.log new file mode 100644 index 0000000..ba3df24 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/automake.log @@ -0,0 +1,1016 @@ + +synthesis -f "RAM2GS_LCMXO640C_impl1_lattice.synproj" +synthesis: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:21 2023 + + +Command Line: synthesis -f RAM2GS_LCMXO640C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml + + +Synthesis options: +The -a option is MachXO. +The -s option is 3. +The -t option is TQFP100. +The -d option is LCMXO640C. +Using package TQFP100. +Using performance grade 3. + + +########################################################## + +### Lattice Family : MachXO + +### Device : LCMXO640C + +### Package : TQFP100 + +### Speed : 3 + +########################################################## + + + + +Optimization goal = Balanced +Top-level module name = RAM2GS. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C (searchpath added) +-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1 (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C (searchpath added) +Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v +NGD file = RAM2GS_LCMXO640C_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 +Compile design. +Compile Design Begin +Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 +Top module name (Verilog): RAM2GS + + + + +Last elaborated design is RAM2GS() +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Top-level module name = RAM2GS. + +original encoding -> new encoding (one-hot encoding) + + 0000 -> 0000000000000001 + + 0001 -> 0000000000000010 + + 0010 -> 0000000000000100 + + 0011 -> 0000000000001000 + + 0100 -> 0000000000010000 + + 0101 -> 0000000000100000 + + 0110 -> 0000000001000000 + + 0111 -> 0000000010000000 + + 1000 -> 0000000100000000 + + 1001 -> 0000001000000000 + + 1010 -> 0000010000000000 + + 1011 -> 0000100000000000 + + 1100 -> 0001000000000000 + + 1101 -> 0010000000000000 + + 1110 -> 0100000000000000 + + 1111 -> 1000000000000000 + + +original encoding -> new encoding (one-hot encoding) + + 00 -> 0001 + + 01 -> 0010 + + 10 -> 0100 + + 11 -> 1000 + + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. + +Applying 200.000000 MHz constraint to all clocks + + +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... + + +Running DRC... + +DRC complete with no errors or warnings + +Design Results: + 318 blocks expanded +completed the first expansion +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO640C_impl1.ngd. + +################### Begin Area Report (RAM2GS)###################### +Number of register bits => 102 of 862 (11 % ) +BB => 8 +CCU2 => 9 +FD1P3AX => 28 +FD1P3AY => 3 +FD1P3IX => 2 +FD1S3AX => 47 +FD1S3AY => 1 +FD1S3IX => 16 +FD1S3JX => 5 +GSR => 1 +IB => 26 +INV => 3 +OB => 33 +ORCALUT4 => 127 +PFUMX => 6 +################### End Area Report ################## + +################### Begin BlackBox Report ###################### +TSALL => 1 +################### End BlackBox Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 4 + Net : RCLK_c, loads : 62 + Net : PHI2_c, loads : 11 + Net : nCCAS_c, loads : 2 + Net : nCRAS_c, loads : 2 +Clock Enable Nets +Number of Clock Enables: 13 +Top 10 highest fanout Clock Enables: + Net : RCLK_c_enable_23, loads : 16 + Net : RCLK_c_enable_4, loads : 3 + Net : PHI2_N_120_enable_6, loads : 3 + Net : RCLK_c_enable_24, loads : 2 + Net : RCLK_c_enable_12, loads : 1 + Net : PHI2_N_120_enable_1, loads : 1 + Net : PHI2_N_120_enable_4, loads : 1 + Net : RCLK_c_enable_3, loads : 1 + Net : PHI2_N_120_enable_5, loads : 1 + Net : RCLK_c_enable_11, loads : 1 +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : InitReady, loads : 17 + Net : Ready, loads : 17 + Net : RCLK_c_enable_23, loads : 16 + Net : nCRAS_N_9, loads : 15 + Net : RASr2, loads : 13 + Net : nRowColSel, loads : 13 + Net : n2477, loads : 13 + Net : MAin_c_0, loads : 12 + Net : nRowColSel_N_35, loads : 12 + Net : Din_c_6, loads : 11 +################### End Clock Report ################## + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 200.000 MHz| 45.147 MHz| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 200.000 MHz| 106.792 MHz| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + + +Peak Memory Usage: 51.215 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 0.609 secs +-------------------------------------------------------------- + +map -a "MachXO" -p LCMXO640C -t TQFP100 -s 3 -oc Commercial "RAM2GS_LCMXO640C_impl1.ngd" -o "RAM2GS_LCMXO640C_impl1_map.ncd" -pr "RAM2GS_LCMXO640C_impl1.prf" -mp "RAM2GS_LCMXO640C_impl1.mrp" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.lpf" -lpf "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.lpf" -c 0 +map: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + Process the file: RAM2GS_LCMXO640C_impl1.ngd + Picdevice="LCMXO640C" + + Pictype="TQFP100" + + Picspeed=3 + + Remove unused logic + + Do not produce over sized NCDs. + +Part used: LCMXO640CTQFP100, Performance used: 3. + +Loading device for application map from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Running general design DRC... + +Removing unused logic... + +Optimizing... + + + + +Design Summary: + Number of PFU registers: 102 out of 640 (16%) + Number of SLICEs: 71 out of 320 (22%) + SLICEs as Logic/ROM: 71 out of 320 (22%) + SLICEs as RAM: 0 out of 192 (0%) + SLICEs as Carry: 9 out of 320 (3%) + Number of LUT4s: 142 out of 640 (22%) + Number used as logic LUTs: 124 + Number used as distributed RAM: 0 + Number used as ripple logic: 18 + Number used as shift registers: 0 + Number of external PIOs: 67 out of 74 (91%) + Number of GSRs: 0 out of 1 (0%) + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + Number of TSALL: 0 out of 1 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. + Number of clocks: 4 + Net RCLK_c: 40 loads, 40 rising, 0 falling (Driver: PIO RCLK ) + Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 ) + Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS ) + Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS ) + Number of Clock Enables: 13 + Net PHI2_N_120_enable_4: 1 loads, 1 LSLICEs + Net RCLK_c_enable_4: 3 loads, 3 LSLICEs + Net RCLK_c_enable_23: 8 loads, 8 LSLICEs + Net RCLK_c_enable_12: 1 loads, 1 LSLICEs + Net RCLK_c_enable_3: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_5: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_6: 2 loads, 2 LSLICEs + Net RCLK_c_enable_24: 2 loads, 2 LSLICEs + Net PHI2_N_120_enable_1: 1 loads, 1 LSLICEs + Net Ready_N_292: 1 loads, 1 LSLICEs + Net RCLK_c_enable_11: 1 loads, 1 LSLICEs + Net PHI2_N_120_enable_7: 1 loads, 1 LSLICEs + Net RCLK_c_enable_25: 1 loads, 1 LSLICEs + Number of LSRs: 9 + Net RASr2: 1 loads, 1 LSLICEs + Net Ready: 7 loads, 7 LSLICEs + Net C1Submitted_N_237: 2 loads, 2 LSLICEs + Net n2469: 1 loads, 1 LSLICEs + Net nRowColSel_N_35: 1 loads, 1 LSLICEs + Net n1846: 2 loads, 2 LSLICEs + Net LEDEN_N_82: 1 loads, 1 LSLICEs + Net nRowColSel_N_34: 1 loads, 1 LSLICEs + Net nRWE_N_177: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net Ready: 23 loads + Net InitReady: 17 loads + Net RASr2: 14 loads + Net nRowColSel: 13 loads + Net MAin_c_0: 12 loads + Net nRowColSel_N_35: 12 loads + Net Din_c_3: 11 loads + Net Din_c_6: 11 loads + Net MAin_c_1: 11 loads + Net Din_c_4: 10 loads + + + Number of warnings: 0 + Number of errors: 0 + + + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 30 MB + +Dumping design to file RAM2GS_LCMXO640C_impl1_map.ncd. + +ncd2vdb "RAM2GS_LCMXO640C_impl1_map.ncd" ".vdbs/RAM2GS_LCMXO640C_impl1_map.vdb" + +Loading device for application ncd2vdb from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. + +ncd2eqn "RAM2GS_LCMXO640C_impl1_map.ncd" +ncd2eqn: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Start loading RAM2GS_LCMXO640C_impl1_map.ncd. + +Loading design for application ncd2eqn from file RAM2GS_LCMXO640C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application ncd2eqn from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Finish loading RAM2GS_LCMXO640C_impl1_map.ncd. +ncd2eqn runs successfully. + +trce -f "RAM2GS_LCMXO640C_impl1.mt" -o "RAM2GS_LCMXO640C_impl1.tw1" "RAM2GS_LCMXO640C_impl1_map.ncd" "RAM2GS_LCMXO640C_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file ram2gs_lcmxo640c_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:23 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf +Design file: ram2gs_lcmxo640c_impl1_map.ncd +Preference file: ram2gs_lcmxo640c_impl1.prf +Device,speed: LCMXO640C,3 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 310 Score: 1346529 +Cumulative negative slack: 874289 + +Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:23 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO640C_impl1.tw1 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.prf +Design file: ram2gs_lcmxo640c_impl1_map.ncd +Preference file: ram2gs_lcmxo640c_impl1.prf +Device,speed: LCMXO640C,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 489 paths, 2 nets, and 407 connections (61.48% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 310 (setup), 0 (hold) +Score: 1346529 (setup), 0 (hold) +Cumulative negative slack: 874289 (874289+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 33 MB + + +ldbanno "RAM2GS_LCMXO640C_impl1_map.ncd" -n Verilog -o "RAM2GS_LCMXO640C_impl1_mapvo.vo" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a Verilog netlist using the orca library type based on the RAM2GS_LCMXO640C_impl1_map design file. + + +Loading design for application ldbanno from file RAM2GS_LCMXO640C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application ldbanno from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Converting design RAM2GS_LCMXO640C_impl1_map.ncd into .ldb format. +Writing Verilog netlist to file RAM2GS_LCMXO640C_impl1_mapvo.vo +Writing SDF timing to file RAM2GS_LCMXO640C_impl1_mapvo.sdf + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 30 MB + +ldbanno "RAM2GS_LCMXO640C_impl1_map.ncd" -n VHDL -o "RAM2GS_LCMXO640C_impl1_mapvho.vho" -w -neg +ldbanno: version Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Writing a VHDL netlist using the orca library type based on the RAM2GS_LCMXO640C_impl1_map design file. + + +Loading design for application ldbanno from file RAM2GS_LCMXO640C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application ldbanno from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Converting design RAM2GS_LCMXO640C_impl1_map.ncd into .ldb format. +Writing VHDL netlist to file RAM2GS_LCMXO640C_impl1_mapvho.vho +Writing SDF timing to file RAM2GS_LCMXO640C_impl1_mapvho.sdf + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 30 MB + +mpartrce -p "RAM2GS_LCMXO640C_impl1.p2t" -f "RAM2GS_LCMXO640C_impl1.p3t" -tf "RAM2GS_LCMXO640C_impl1.pt" "RAM2GS_LCMXO640C_impl1_map.ncd" "RAM2GS_LCMXO640C_impl1.ncd" + +---- MParTrce Tool ---- +Removing old design directory at request of -rem command line option to this program. +Running par. Please wait . . . + +Lattice Place and Route Report for Design "RAM2GS_LCMXO640C_impl1_map.ncd" +Tue Aug 15 05:03:25 2023 + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO640C_impl1_map.ncd RAM2GS_LCMXO640C_impl1.dir/5_1.ncd RAM2GS_LCMXO640C_impl1.prf +Preference file: RAM2GS_LCMXO640C_impl1.prf. +Placement level-cost: 5-1. +Routing Iterations: 6 + +Loading design for application par from file RAM2GS_LCMXO640C_impl1_map.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application par from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +License checked out. + + +Ignore Preference Error(s): True +Device utilization summary: + + PIO (prelim) 67/159 42% used + 67/74 90% bonded + SLICE 71/320 22% used + + + +Number of Signals: 262 +Number of Connections: 662 + +Pin Constraint Summary: + 67 out of 67 pins locked (100% locked). + +The following 2 signals are selected to use the primary clock routing resources: + RCLK_c (driver: RCLK, clk load #: 40) + PHI2_c (driver: PHI2, clk load #: 13) + +The following 1 signal is selected to use the secondary clock routing resources: + nCRAS_c (driver: nCRAS, clk load #: 7, sr load #: 0, ce load #: 0) + +No signal is selected as Global Set/Reset. +Starting Placer Phase 0. +......... +Finished Placer Phase 0. REAL time: 0 secs + +Starting Placer Phase 1. +......... +Placer score = 1223575. +Finished Placer Phase 1. REAL time: 3 secs + +Starting Placer Phase 2. +. +Placer score = 1220793 +Finished Placer Phase 2. REAL time: 3 secs + + +------------------ Clock Report ------------------ + +Global Clock Resources: + CLK_PIN : 1 out of 4 (25%) + General PIO: 1 out of 160 (0%) + +Global Clocks: + PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT5B)", clk load = 40 + PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB6C)", clk load = 13 + SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB8B)", clk load = 7, ce load = 0, sr load = 0 + + PRIMARY : 2 out of 4 (50%) + SECONDARY: 1 out of 4 (25%) + +--------------- End of Clock Report --------------- + + +I/O Usage Summary (final): + 67 out of 159 (42.1%) PIO sites used. + 67 out of 74 (90.5%) bonded PIO sites used. + Number of PIO comps: 67; differential: 0. + Number of Vref pins used: 0. + +I/O Bank Usage Summary: ++----------+----------------+------------+------------+------------+ +| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | ++----------+----------------+------------+------------+------------+ +| 0 | 18 / 18 (100%) | 3.3V | - | - | +| 1 | 18 / 21 ( 85%) | 3.3V | - | - | +| 2 | 13 / 14 ( 92%) | - | - | - | +| 3 | 18 / 21 ( 85%) | 3.3V | - | - | ++----------+----------------+------------+------------+------------+ + +Total placer CPU time: 3 secs + +Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd. + +0 connections routed; 662 unrouted. +Starting router resource preassignment + + + + + +Completed router resource preassignment. Real time: 3 secs + +Start NBR router at 05:03:28 08/15/23 + +***************************************************************** +Info: NBR allows conflicts(one node used by more than one signal) + in the earlier iterations. In each iteration, it tries to + solve the conflicts while keeping the critical connections + routed as short as possible. The routing process is said to + be completed when no conflicts exist and all connections + are routed. +Note: NBR uses a different method to calculate timing slacks. The + worst slack and total negative slack may not be the same as + that in TRCE report. You should always run TRCE to verify + your design. +***************************************************************** + +Start NBR special constraint process at 05:03:28 08/15/23 + +Start NBR section for initial routing at 05:03:28 08/15/23 +Level 1, iteration 1 +0(0.00%) conflict; 559(84.44%) untouched conns; 717961 (nbr) score; +Estimated worst slack/total negative slack: -9.776ns/-717.961ns; real time: 3 secs +Level 2, iteration 1 +7(0.03%) conflicts; 496(74.92%) untouched conns; 699022 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-699.022ns; real time: 3 secs +Level 3, iteration 1 +9(0.03%) conflicts; 252(38.07%) untouched conns; 765745 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-765.746ns; real time: 3 secs +Level 4, iteration 1 +9(0.03%) conflicts; 0(0.00%) untouched conn; 781820 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-781.821ns; real time: 4 secs + +Info: Initial congestion level at 75% usage is 0 +Info: Initial congestion area at 75% usage is 0 (0.00%) + +Start NBR section for normal routing at 05:03:29 08/15/23 +Level 4, iteration 1 +5(0.02%) conflicts; 0(0.00%) untouched conn; 781048 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-781.049ns; real time: 4 secs +Level 4, iteration 2 +4(0.01%) conflicts; 0(0.00%) untouched conn; 780690 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.691ns; real time: 4 secs +Level 4, iteration 3 +4(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs +Level 4, iteration 4 +2(0.01%) conflicts; 0(0.00%) untouched conn; 780715 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-780.716ns; real time: 4 secs +Level 4, iteration 5 +2(0.01%) conflicts; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs +Level 4, iteration 6 +0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs + +Start NBR section for performance tuning (iteration 1) at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 783401 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-783.402ns; real time: 4 secs + +Start NBR section for re-routing at 05:03:29 08/15/23 +Level 4, iteration 1 +0(0.00%) conflict; 0(0.00%) untouched conn; 776978 (nbr) score; +Estimated worst slack/total negative slack: -9.822ns/-776.979ns; real time: 4 secs + +Start NBR section for post-routing at 05:03:29 08/15/23 + +End NBR router with 0 unrouted connection + +NBR Summary +----------- + Number of unrouted connections : 0 (0.00%) + Number of connections with timing violations : 260 (39.27%) + Estimated worst slack : -9.822ns + Timing score : 909228 +----------- +Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. + + + + + +Total CPU time 4 secs +Total REAL time: 4 secs +Completely routed. +End of route. 662 routed (100.00%); 0 unrouted. + +Hold time timing score: 0, hold timing errors: 0 + +Timing score: 909228 + +Dumping design to file RAM2GS_LCMXO640C_impl1.dir/5_1.ncd. + + +PAR_SUMMARY::Run status = Completed +PAR_SUMMARY::Number of unrouted conns = 0 +PAR_SUMMARY::Worst slack> = -9.822 +PAR_SUMMARY::Timing score> = 909.228 +PAR_SUMMARY::Worst slack> = 0.273 +PAR_SUMMARY::Timing score> = 0.000 +PAR_SUMMARY::Number of errors = 0 + +Total CPU time to completion: 4 secs +Total REAL time to completion: 4 secs + +par done! + +Note: user must run 'Trace' for timing closure signoff. + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Exiting par with exit code 0 +Exiting mpartrce with exit code 0 + +trce -f "RAM2GS_LCMXO640C_impl1.pt" -o "RAM2GS_LCMXO640C_impl1.twr" "RAM2GS_LCMXO640C_impl1.ncd" "RAM2GS_LCMXO640C_impl1.prf" +trce: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application trce from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application trce from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:29 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf +Design file: ram2gs_lcmxo640c_impl1.ncd +Preference file: ram2gs_lcmxo640c_impl1.prf +Device,speed: LCMXO640C,3 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +Report Type: based on TRACE automatically generated preferences +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Setup): +--------------- + +Timing errors: 328 Score: 909228 +Cumulative negative slack: 648187 + +Constraints cover 489 paths, 2 nets, and 415 connections (62.69% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Tue Aug 15 05:03:30 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 3 -sphld m -o RAM2GS_LCMXO640C_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf +Design file: ram2gs_lcmxo640c_impl1.ncd +Preference file: ram2gs_lcmxo640c_impl1.prf +Device,speed: LCMXO640C,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 489 paths, 2 nets, and 415 connections (62.69% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 328 (setup), 0 (hold) +Score: 909228 (setup), 0 (hold) +Cumulative negative slack: 648187 (648187+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 32 MB + + +iotiming "RAM2GS_LCMXO640C_impl1.ncd" "RAM2GS_LCMXO640C_impl1.prf" +I/O Timing Report: +: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application iotiming from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Running Performance Grade: 3 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 4 +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Running Performance Grade: 4 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Running Performance Grade: 5 +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... + +Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: M +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Running Performance Grade: M +Computing Setup Time ... +Computing Max Clock to Output Delay ... +Computing Hold Time ... +Computing Min Clock to Output Delay ... +Done. + +tmcheck -par "RAM2GS_LCMXO640C_impl1.par" + +bitgen -w "RAM2GS_LCMXO640C_impl1.ncd" -f "RAM2GS_LCMXO640C_impl1.t2b" "RAM2GS_LCMXO640C_impl1.prf" + + +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + + +Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 3 +Loading device for application Bitgen from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2GS_LCMXO640C_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| ES | No** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... +Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit". +Total CPU Time: 0 secs +Total REAL Time: 0 secs +Peak Memory Usage: 46 MB + +ddtcmd -dev LCMXO640C-XXT100 -if "RAM2GS_LCMXO640C_impl1.bit" -oft -jed -of "RAM2GS_LCMXO640C_impl1.jed" -comment "RAM2GS_LCMXO640C_impl1.alt" +Lattice Diamond Deployment Tool 3.12 Command Line + +Loading Programmer Device Database... + +Generating JED..... +Device Name: LCMXO640C-XXT100 +Reading Input File: RAM2GS_LCMXO640C_impl1.bit +Output File: RAM2GS_LCMXO640C_impl1.jed +Comment file RAM2GS_LCMXO640C_impl1.alt. +Generating JEDEC..... +File RAM2GS_LCMXO640C_impl1.jed generated successfully. +Lattice Diamond Deployment Tool has exited successfully. + diff --git a/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html new file mode 100644 index 0000000..8e04933 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html @@ -0,0 +1,9 @@ + 
    Setting log file to 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v'
+(VERI-1482) Analyzing Verilog file 'D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
+INFO - D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-411,10) (VERI-9000) elaborating module 'RAM2GS'
+Done: design load finished with (0) errors, and (0) warnings
+
+
    \ No newline at end of file diff --git a/CPLD/LCMXO640C/impl1/impl1.xcf b/CPLD/LCMXO640C/impl1/impl1.xcf new file mode 100644 index 0000000..262d62b --- /dev/null +++ b/CPLD/LCMXO640C/impl1/impl1.xcf @@ -0,0 +1,50 @@ + + + + + + JTAG + + + 1 + Lattice + MachXO + LCMXO640C + 0x01285043 + All + LCMXO640C + + 8 + 11111111 + 1 + 0 + + D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1/RAM2GS_LCMXO640C_impl1.jed + 08/15/23 04:37:09 + 0x4B06 + FLASH Erase,Program,Verify + + + + + SEQUENTIAL + ENTIRED CHAIN + No Override + TLR + TLR + + 1 + + + USB + EzUSB-0 + \\?\usb#vid_1134&amp;pid_8001#5&amp;887acb0&amp;0&amp;13# + + diff --git a/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior b/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior new file mode 100644 index 0000000..bf3668f --- /dev/null +++ b/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1.ior @@ -0,0 +1,138 @@ +Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 4 +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +Loading design for application iotiming from file ram2gs_lcmxo640c_impl1.ncd. +Design name: RAM2GS +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO640C +Package: TQFP100 +Performance: M +Package Status: Final Version 1.17. +Performance Hardware Data Status: Version 1.124. +// Design: RAM2GS +// Package: TQFP100 +// ncd File: ram2gs_lcmxo640c_impl1.ncd +// Version: Diamond (64-bit) 3.12.1.454 +// Written on Tue Aug 15 05:03:31 2023 +// M: Minimum Performance Grade +// iotiming RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml + +I/O Timing Report (All units are in ns) + +Worst Case Results across Performance Grades (M, 5, 4, 3): + +// Input Setup and Hold Times + +Port Clock Edge Setup Performance_Grade Hold Performance_Grade +---------------------------------------------------------------------- +CROW[0] nCRAS F -0.236 M 3.076 3 +CROW[1] nCRAS F -0.216 M 2.985 3 +Din[0] PHI2 F 6.373 3 2.684 3 +Din[0] nCCAS F 1.094 3 0.245 3 +Din[1] PHI2 F 5.890 3 2.684 3 +Din[1] nCCAS F 1.106 3 0.247 3 +Din[2] PHI2 F 4.774 3 2.292 3 +Din[2] nCCAS F 1.207 3 0.231 3 +Din[3] PHI2 F 8.665 3 1.537 3 +Din[3] nCCAS F 0.786 3 0.612 3 +Din[4] PHI2 F 5.483 3 1.881 3 +Din[4] nCCAS F 1.180 3 0.282 3 +Din[5] PHI2 F 7.162 3 1.124 3 +Din[5] nCCAS F 0.802 3 0.635 3 +Din[6] PHI2 F 8.125 3 1.435 3 +Din[6] nCCAS F 1.142 3 0.086 3 +Din[7] PHI2 F 8.015 3 1.300 3 +Din[7] nCCAS F 1.259 3 -0.010 M +MAin[0] PHI2 F 6.577 3 0.639 3 +MAin[0] nCRAS F -0.004 M 2.291 3 +MAin[1] PHI2 F 6.880 3 1.958 3 +MAin[1] nCRAS F 1.424 3 1.006 3 +MAin[2] PHI2 F 4.559 3 0.456 3 +MAin[2] nCRAS F -0.209 M 2.966 3 +MAin[3] PHI2 F 5.604 3 -0.096 M +MAin[3] nCRAS F -0.323 M 3.369 3 +MAin[4] PHI2 F 6.263 3 -0.211 M +MAin[4] nCRAS F -0.086 M 2.536 3 +MAin[5] PHI2 F 4.291 3 0.703 3 +MAin[5] nCRAS F 1.052 3 1.326 3 +MAin[6] PHI2 F 5.837 3 -0.133 M +MAin[6] nCRAS F -0.017 M 2.334 3 +MAin[7] PHI2 F 6.302 3 -0.241 M +MAin[7] nCRAS F -0.106 M 2.631 3 +MAin[8] nCRAS F -0.086 M 2.542 3 +MAin[9] nCRAS F 0.549 3 1.796 3 +PHI2 RCLK R 4.937 3 -0.562 M +UFMSDO RCLK R 2.296 3 -0.152 M +nCCAS RCLK R 1.639 3 -0.029 M +nCCAS nCRAS F -0.229 M 3.059 3 +nCRAS RCLK R 1.104 3 0.341 3 +nFWE PHI2 F 5.086 3 1.672 3 +nFWE nCRAS F 0.037 3 2.231 3 + + +// Clock to Output Delay + +Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade +------------------------------------------------------------------------ +LED RCLK R 7.152 3 1.423 M +LED nCRAS F 12.128 3 2.429 M +RA[0] RCLK R 9.839 3 1.974 M +RA[0] nCRAS F 12.557 3 2.494 M +RA[10] RCLK R 5.747 3 1.141 M +RA[11] PHI2 R 7.990 3 1.574 M +RA[1] RCLK R 10.012 3 2.010 M +RA[1] nCRAS F 12.750 3 2.545 M +RA[2] RCLK R 10.522 3 2.116 M +RA[2] nCRAS F 12.564 3 2.494 M +RA[3] RCLK R 10.341 3 2.077 M +RA[3] nCRAS F 11.973 3 2.372 M +RA[4] RCLK R 9.672 3 1.940 M +RA[4] nCRAS F 13.443 3 2.679 M +RA[5] RCLK R 9.440 3 1.890 M +RA[5] nCRAS F 10.958 3 2.155 M +RA[6] RCLK R 10.605 3 2.138 M +RA[6] nCRAS F 13.114 3 2.628 M +RA[7] RCLK R 8.842 3 1.782 M +RA[7] nCRAS F 10.779 3 2.148 M +RA[8] RCLK R 10.258 3 2.067 M +RA[8] nCRAS F 12.925 3 2.579 M +RA[9] RCLK R 7.160 3 1.425 M +RA[9] nCRAS F 9.857 3 1.950 M +RBA[0] nCRAS F 10.935 3 2.169 M +RBA[1] nCRAS F 10.976 3 2.184 M +RCKE RCLK R 5.747 3 1.141 M +RDQMH RCLK R 9.890 3 1.991 M +RDQML RCLK R 9.338 3 1.859 M +RD[0] nCCAS F 7.488 3 1.591 M +RD[1] nCCAS F 8.012 3 1.701 M +RD[2] nCCAS F 8.965 3 1.912 M +RD[3] nCCAS F 8.965 3 1.912 M +RD[4] nCCAS F 7.951 3 1.691 M +RD[5] nCCAS F 7.951 3 1.691 M +RD[6] nCCAS F 8.012 3 1.701 M +RD[7] nCCAS F 8.384 3 1.785 M +UFMCLK RCLK R 7.986 3 1.598 M +UFMSDI RCLK R 5.747 3 1.141 M +nRCAS RCLK R 5.747 3 1.141 M +nRCS RCLK R 5.747 3 1.141 M +nRRAS RCLK R 6.929 3 1.373 M +nRWE RCLK R 7.375 3 1.459 M +nUFMCS RCLK R 7.996 3 1.601 M +WARNING: you must also run trce with hold speed: 3 +WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd b/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd new file mode 100644 index 0000000..80934ca --- /dev/null +++ b/CPLD/LCMXO640C/impl1/ram2gs_lcmxo640c_impl1_trce.asd @@ -0,0 +1,13 @@ +[ActiveSupport TRCE] +; Setup Analysis +Fmax_0 = 116.198 MHz (283.768 MHz); +Fmax_1 = 55.096 MHz (120.077 MHz); +Failed = 2 (Total 2); +Clock_ports = 4; +Clock_nets = 4; +; Hold Analysis +Fmax_0 = 0.273 ns (0.000 ns); +Fmax_1 = 0.361 ns (0.000 ns); +Failed = 0 (Total 2); +Clock_ports = 4; +Clock_nets = 4; diff --git a/CPLD/LCMXO640C/impl1/synthesis.log b/CPLD/LCMXO640C/impl1/synthesis.log new file mode 100644 index 0000000..ece5a9b --- /dev/null +++ b/CPLD/LCMXO640C/impl1/synthesis.log @@ -0,0 +1,238 @@ +synthesis: version Diamond (64-bit) 3.12.1.454 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Tue Aug 15 05:03:21 2023 + + +Command Line: synthesis -f RAM2GS_LCMXO640C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml + +Synthesis options: +The -a option is MachXO. +The -s option is 3. +The -t option is TQFP100. +The -d option is LCMXO640C. +Using package TQFP100. +Using performance grade 3. + + +########################################################## + +### Lattice Family : MachXO + +### Device : LCMXO640C + +### Package : TQFP100 + +### Speed : 3 + +########################################################## + + + +INFO - synthesis: User-Selected Strategy Settings +Optimization goal = Balanced +Top-level module name = RAM2GS. +Target frequency = 200.000000 MHz. +Maximum fanout = 1000. +Timing path count = 3 +BRAM utilization = 100.000000 % +DSP usage = true +DSP utilization = 100.000000 % +fsm_encoding_style = auto +resolve_mixed_drivers = 0 +fix_gated_clocks = 1 + +Mux style = Auto +Use Carry Chain = true +carry_chain_length = 0 +Loop Limit = 1950. +Use IO Insertion = TRUE +Use IO Reg = AUTO + +Resource Sharing = TRUE +Propagate Constants = TRUE +Remove Duplicate Registers = TRUE +force_gsr = auto +ROM style = auto +RAM style = auto +The -comp option is FALSE. +The -syn option is FALSE. +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C (searchpath added) +-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1 (searchpath added) +-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C (searchpath added) +Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v +NGD file = RAM2GS_LCMXO640C_impl1.ngd +-sdc option: SDC file input not used. +-lpf option: Output file option is ON. +Hardtimer checking is enabled (default). The -dt option is not used. +The -r option is OFF. [ Remove LOC Properties is OFF. ] +Technology check ok... + +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 +Compile design. +Compile Design Begin +Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482 +Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482 +Top module name (Verilog): RAM2GS +INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209 +WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209 +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +Loading device for application map from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.17. +Top-level module name = RAM2GS. +INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding +original encoding -> new encoding (one-hot encoding) + + 0000 -> 0000000000000001 + + 0001 -> 0000000000000010 + + 0010 -> 0000000000000100 + + 0011 -> 0000000000001000 + + 0100 -> 0000000000010000 + + 0101 -> 0000000000100000 + + 0110 -> 0000000001000000 + + 0111 -> 0000000010000000 + + 1000 -> 0000000100000000 + + 1001 -> 0000001000000000 + + 1010 -> 0000010000000000 + + 1011 -> 0000100000000000 + + 1100 -> 0001000000000000 + + 1101 -> 0010000000000000 + + 1110 -> 0100000000000000 + + 1111 -> 1000000000000000 + +INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding +original encoding -> new encoding (one-hot encoding) + + 00 -> 0001 + + 01 -> 0010 + + 10 -> 0100 + + 11 -> 1000 + + + + +GSR will not be inferred because no asynchronous signal was found in the netlist. +WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored. +Applying 200.000000 MHz constraint to all clocks + +WARNING - synthesis: No user .sdc file. +Results of NGD DRC are available in RAM2GS_drc.log. +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'... +Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'... +All blocks are expanded and NGD expansion is successful. +Writing NGD file RAM2GS_LCMXO640C_impl1.ngd. + +################### Begin Area Report (RAM2GS)###################### +Number of register bits => 102 of 862 (11 % ) +BB => 8 +CCU2 => 9 +FD1P3AX => 28 +FD1P3AY => 3 +FD1P3IX => 2 +FD1S3AX => 47 +FD1S3AY => 1 +FD1S3IX => 16 +FD1S3JX => 5 +GSR => 1 +IB => 26 +INV => 3 +OB => 33 +ORCALUT4 => 127 +PFUMX => 6 +################### End Area Report ################## + +################### Begin BlackBox Report ###################### +TSALL => 1 +################### End BlackBox Report ################## + +################### Begin Clock Report ###################### +Clock Nets +Number of Clocks: 4 + Net : RCLK_c, loads : 62 + Net : PHI2_c, loads : 11 + Net : nCCAS_c, loads : 2 + Net : nCRAS_c, loads : 2 +Clock Enable Nets +Number of Clock Enables: 13 +Top 10 highest fanout Clock Enables: + Net : RCLK_c_enable_23, loads : 16 + Net : RCLK_c_enable_4, loads : 3 + Net : PHI2_N_120_enable_6, loads : 3 + Net : RCLK_c_enable_24, loads : 2 + Net : RCLK_c_enable_12, loads : 1 + Net : PHI2_N_120_enable_1, loads : 1 + Net : PHI2_N_120_enable_4, loads : 1 + Net : RCLK_c_enable_3, loads : 1 + Net : PHI2_N_120_enable_5, loads : 1 + Net : RCLK_c_enable_11, loads : 1 +Highest fanout non-clock nets +Top 10 highest fanout non-clock nets: + Net : InitReady, loads : 17 + Net : Ready, loads : 17 + Net : RCLK_c_enable_23, loads : 16 + Net : nCRAS_N_9, loads : 15 + Net : RASr2, loads : 13 + Net : nRowColSel, loads : 13 + Net : n2477, loads : 13 + Net : MAin_c_0, loads : 12 + Net : nRowColSel_N_35, loads : 12 + Net : Din_c_6, loads : 11 +################### End Clock Report ################## + +Timing Report Summary +-------------- +-------------------------------------------------------------------------------- +Constraint | Constraint| Actual|Levels +-------------------------------------------------------------------------------- + | | | +create_clock -period 5.000000 -name | | | +clk3 [get_nets nCCAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk2 [get_nets nCRAS_c] | -| -| 0 + | | | +create_clock -period 5.000000 -name | | | +clk1 [get_nets PHI2_c] | 200.000 MHz| 45.147 MHz| 6 * + | | | +create_clock -period 5.000000 -name | | | +clk0 [get_nets RCLK_c] | 200.000 MHz| 106.792 MHz| 5 * + | | | +-------------------------------------------------------------------------------- + + +2 constraints not met. + + +Peak Memory Usage: 51.215 MB + +-------------------------------------------------------------- +Elapsed CPU time for LSE flow : 0.609 secs +-------------------------------------------------------------- diff --git a/CPLD/LCMXO640C/impl1/synthesis_lse.html b/CPLD/LCMXO640C/impl1/synthesis_lse.html new file mode 100644 index 0000000..5a4ea61 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/synthesis_lse.html @@ -0,0 +1,303 @@ + +Synthesis and Ngdbuild Report + + +
    Synthesis and Ngdbuild  Report
+synthesis:  version Diamond (64-bit) 3.12.1.454
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Tue Aug 15 05:03:21 2023
+
+
+Command Line:  synthesis -f RAM2GS_LCMXO640C_impl1_lattice.synproj -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/promote.xml 
+
+Synthesis options:
+The -a option is MachXO.
+The -s option is 3.
+The -t option is TQFP100.
+The -d option is LCMXO640C.
+Using package TQFP100.
+Using performance grade 3.
+                                                          
+
+##########################################################
+
+### Lattice Family : MachXO
+
+### Device  : LCMXO640C
+
+### Package : TQFP100
+
+### Speed   : 3
+
+##########################################################
+
+                                                          
+
+INFO - synthesis: User-Selected Strategy Settings
+Optimization goal = Balanced
+Top-level module name = RAM2GS.
+Target frequency = 200.000000 MHz.
+Maximum fanout = 1000.
+Timing path count = 3
+BRAM utilization = 100.000000 %
+DSP usage = true
+DSP utilization = 100.000000 %
+fsm_encoding_style = auto
+resolve_mixed_drivers = 0
+fix_gated_clocks = 1
+
+Mux style = Auto
+Use Carry Chain = true
+carry_chain_length = 0
+Loop Limit = 1950.
+Use IO Insertion = TRUE
+Use IO Reg = AUTO
+
+Resource Sharing = TRUE
+Propagate Constants = TRUE
+Remove Duplicate Registers = TRUE
+force_gsr = auto
+ROM style = auto
+RAM style = auto
+The -comp option is FALSE.
+The -syn option is FALSE.
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C (searchpath added)
+-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C/impl1 (searchpath added)
+-p D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO640C (searchpath added)
+Verilog design file = D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-SPI.v
+NGD file = RAM2GS_LCMXO640C_impl1.ngd
+-sdc option: SDC file input not used.
+-lpf option: Output file option is ON.
+Hardtimer checking is enabled (default). The -dt option is not used.
+The -r option is OFF. [ Remove LOC Properties is OFF. ]
+Technology check ok...
+
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Compile design.
+Compile Design Begin
+Analyzing Verilog file d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v. VERI-1482
+Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
+Top module name (Verilog): RAM2GS
+INFO - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(1): compiling module RAM2GS. VERI-1018
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
+WARNING - synthesis: d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+Loading device for application map from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.17.
+Top-level module name = RAM2GS.
+INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 0000 -> 0000000000000001
+
+ 0001 -> 0000000000000010
+
+ 0010 -> 0000000000000100
+
+ 0011 -> 0000000000001000
+
+ 0100 -> 0000000000010000
+
+ 0101 -> 0000000000100000
+
+ 0110 -> 0000000001000000
+
+ 0111 -> 0000000010000000
+
+ 1000 -> 0000000100000000
+
+ 1001 -> 0000001000000000
+
+ 1010 -> 0000010000000000
+
+ 1011 -> 0000100000000000
+
+ 1100 -> 0001000000000000
+
+ 1101 -> 0010000000000000
+
+ 1110 -> 0100000000000000
+
+ 1111 -> 1000000000000000
+
+INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
+original encoding -> new encoding (one-hot encoding)
+
+ 00 -> 0001
+
+ 01 -> 0010
+
+ 10 -> 0100
+
+ 11 -> 1000
+
+
+
+
+GSR will not be inferred because no asynchronous signal was found in the netlist.
+WARNING - synthesis: Initial value found on instance C1Submitted_406 will be ignored.
+Applying 200.000000 MHz constraint to all clocks
+
+WARNING - synthesis: No user .sdc file.
+Results of NGD DRC are available in RAM2GS_drc.log.
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
+Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
+All blocks are expanded and NGD expansion is successful.
+Writing NGD file RAM2GS_LCMXO640C_impl1.ngd.
+
+################### Begin Area Report (RAM2GS)######################
+Number of register bits => 102 of 862 (11 % )
+BB => 8
+CCU2 => 9
+FD1P3AX => 28
+FD1P3AY => 3
+FD1P3IX => 2
+FD1S3AX => 47
+FD1S3AY => 1
+FD1S3IX => 16
+FD1S3JX => 5
+GSR => 1
+IB => 26
+INV => 3
+OB => 33
+ORCALUT4 => 127
+PFUMX => 6
+################### End Area Report ##################
+
+################### Begin BlackBox Report ######################
+TSALL => 1
+################### End BlackBox Report ##################
+
+################### Begin Clock Report ######################
+Clock Nets
+Number of Clocks: 4
+  Net : RCLK_c, loads : 62
+  Net : PHI2_c, loads : 11
+  Net : nCCAS_c, loads : 2
+  Net : nCRAS_c, loads : 2
+Clock Enable Nets
+Number of Clock Enables: 13
+Top 10 highest fanout Clock Enables:
+  Net : RCLK_c_enable_23, loads : 16
+  Net : RCLK_c_enable_4, loads : 3
+  Net : PHI2_N_120_enable_6, loads : 3
+  Net : RCLK_c_enable_24, loads : 2
+  Net : RCLK_c_enable_12, loads : 1
+  Net : PHI2_N_120_enable_1, loads : 1
+  Net : PHI2_N_120_enable_4, loads : 1
+  Net : RCLK_c_enable_3, loads : 1
+  Net : PHI2_N_120_enable_5, loads : 1
+  Net : RCLK_c_enable_11, loads : 1
+Highest fanout non-clock nets
+Top 10 highest fanout non-clock nets:
+  Net : InitReady, loads : 17
+  Net : Ready, loads : 17
+  Net : RCLK_c_enable_23, loads : 16
+  Net : nCRAS_N_9, loads : 15
+  Net : RASr2, loads : 13
+  Net : nRowColSel, loads : 13
+  Net : n2477, loads : 13
+  Net : MAin_c_0, loads : 12
+  Net : nRowColSel_N_35, loads : 12
+  Net : Din_c_6, loads : 11
+################### End Clock Report ##################
+
+Timing Report Summary
+--------------
+--------------------------------------------------------------------------------
+Constraint                              |   Constraint|       Actual|Levels
+--------------------------------------------------------------------------------
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk3 [get_nets nCCAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk2 [get_nets nCRAS_c]                 |            -|            -|     0  
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk1 [get_nets PHI2_c]                  |  200.000 MHz|   45.147 MHz|     6 *
+                                        |             |             |
+create_clock -period 5.000000 -name     |             |             |
+clk0 [get_nets RCLK_c]                  |  200.000 MHz|  106.792 MHz|     5 *
+                                        |             |             |
+--------------------------------------------------------------------------------
+
+
+2 constraints not met.
+
+
+Peak Memory Usage: 51.215  MB
+
+--------------------------------------------------------------
+Elapsed CPU time for LSE flow : 0.609  secs
+--------------------------------------------------------------
+
+
+
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    
+
    + + diff --git a/CPLD/LCMXO640C/impl1/xxx_lse_cp_file_list b/CPLD/LCMXO640C/impl1/xxx_lse_cp_file_list new file mode 100644 index 0000000..1c1a02c --- /dev/null +++ b/CPLD/LCMXO640C/impl1/xxx_lse_cp_file_list @@ -0,0 +1,250 @@ +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v +3 d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v diff --git a/CPLD/LCMXO640C/impl1/xxx_lse_sign_file b/CPLD/LCMXO640C/impl1/xxx_lse_sign_file new file mode 100644 index 0000000..15202f1 --- /dev/null +++ b/CPLD/LCMXO640C/impl1/xxx_lse_sign_file @@ -0,0 +1,250 @@ +LSE_CPS_ID_1 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" +LSE_CPS_ID_2 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_3 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_4 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:80[15:31]" +LSE_CPS_ID_5 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_6 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_7 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_8 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_9 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_10 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_11 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_12 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_13 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_14 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_15 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_16 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_17 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_18 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_19 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:141[9] 144[5]" +LSE_CPS_ID_20 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_21 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_22 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:394[12] 409[6]" +LSE_CPS_ID_23 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_24 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_25 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_26 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_27 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_28 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_29 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_30 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_31 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_32 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_33 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_34 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_35 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" +LSE_CPS_ID_36 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_37 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_38 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_39 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_40 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_41 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_42 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:80[15:31]" +LSE_CPS_ID_43 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_44 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:315[17:31]" +LSE_CPS_ID_45 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_46 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_47 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_48 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:321[13] 335[7]" +LSE_CPS_ID_49 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_50 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_51 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_52 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[15:41]" +LSE_CPS_ID_53 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_54 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_55 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_56 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_57 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_58 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:48[6:16]" +LSE_CPS_ID_59 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:80[15:31]" +LSE_CPS_ID_60 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_61 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" +LSE_CPS_ID_62 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_63 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:402[16:47]" +LSE_CPS_ID_64 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_65 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_66 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_67 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:23[27:31]" +LSE_CPS_ID_68 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_69 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_70 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:91[9] 95[5]" +LSE_CPS_ID_71 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_72 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_73 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_74 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_75 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_76 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_77 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_78 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_79 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:230[16:37]" +LSE_CPS_ID_80 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_81 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_82 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_83 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[11:55]" +LSE_CPS_ID_84 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:48[6:16]" +LSE_CPS_ID_85 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_86 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:55[19:54]" +LSE_CPS_ID_87 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:99[22:51]" +LSE_CPS_ID_88 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_89 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_90 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:58[17:46]" +LSE_CPS_ID_91 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_92 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_93 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_94 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_95 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_96 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:147[9] 285[5]" +LSE_CPS_ID_97 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_98 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_99 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_100 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_101 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_102 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_103 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_104 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:386[12] 409[6]" +LSE_CPS_ID_105 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_106 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:386[12] 409[6]" +LSE_CPS_ID_107 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_108 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_109 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_110 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_111 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_112 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_113 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_114 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_115 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:263[11:15]" +LSE_CPS_ID_116 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_117 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_118 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_119 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_120 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_121 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_122 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_123 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_124 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_125 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_126 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_127 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_128 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_129 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_130 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_131 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_132 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_133 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_134 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_135 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_136 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_137 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_138 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_139 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_140 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:123[9] 125[5]" +LSE_CPS_ID_141 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_142 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_143 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_144 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_145 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_146 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_147 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_148 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_149 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:105[9] 120[5]" +LSE_CPS_ID_150 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_151 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_152 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_153 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_154 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_155 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_156 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:98[9] 102[5]" +LSE_CPS_ID_157 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_158 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_159 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_160 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_161 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_162 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_163 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:60[14:16]" +LSE_CPS_ID_164 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_165 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_166 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_167 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_168 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_169 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_170 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_171 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:27[15:19]" +LSE_CPS_ID_172 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:22[9:12]" +LSE_CPS_ID_173 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" +LSE_CPS_ID_174 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:47[19:22]" +LSE_CPS_ID_175 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_176 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_177 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_178 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_179 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_180 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_181 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_182 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_183 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_184 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_185 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_186 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:52[16:18]" +LSE_CPS_ID_187 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[13:17]" +LSE_CPS_ID_188 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:45[13:17]" +LSE_CPS_ID_189 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[45:49]" +LSE_CPS_ID_190 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[23:28]" +LSE_CPS_ID_191 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:46[34:39]" +LSE_CPS_ID_192 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[16:21]" +LSE_CPS_ID_193 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:56[9:14]" +LSE_CPS_ID_194 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:63[13:19]" +LSE_CPS_ID_195 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:64[13:19]" +LSE_CPS_ID_196 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:65[13:19]" +LSE_CPS_ID_197 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:8[8:12]" +LSE_CPS_ID_198 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_199 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_200 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_201 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_202 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_203 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_204 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_205 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_206 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_207 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:35[14:18]" +LSE_CPS_ID_208 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" +LSE_CPS_ID_209 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:34[14:18]" +LSE_CPS_ID_210 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_211 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_212 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_213 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_214 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_215 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_216 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_217 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:26[14:17]" +LSE_CPS_ID_218 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" +LSE_CPS_ID_219 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" +LSE_CPS_ID_220 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:36[8:12]" +LSE_CPS_ID_221 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:41[8:12]" +LSE_CPS_ID_222 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:66[8:14]" +LSE_CPS_ID_223 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_224 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_225 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_226 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_227 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:288[9] 337[5]" +LSE_CPS_ID_228 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_229 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_230 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:48[6:16]" +LSE_CPS_ID_231 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:232[12] 284[6]" +LSE_CPS_ID_232 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:255[14] 262[8]" +LSE_CPS_ID_233 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_234 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_235 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:48[6:16]" +LSE_CPS_ID_236 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_237 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_238 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_239 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:143[40:46]" +LSE_CPS_ID_240 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:309[7:24]" +LSE_CPS_ID_241 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_242 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:136[9:13]" +LSE_CPS_ID_243 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:84[6:11]" +LSE_CPS_ID_244 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:134[9] 138[5]" +LSE_CPS_ID_245 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:21[6:11]" +LSE_CPS_ID_246 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:340[9] 410[5]" +LSE_CPS_ID_247 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" +LSE_CPS_ID_248 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[8:13]" +LSE_CPS_ID_249 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:11[15:20]" +LSE_CPS_ID_250 "d:/onedrive/documents/github/ram2gs/cpld/ram2gs-spi.v:131[13:16]" diff --git a/CPLD/MAXII/RAM2GS.qws b/CPLD/MAXII/RAM2GS.qws index c95d0a6..0162b06 100644 Binary files a/CPLD/MAXII/RAM2GS.qws and b/CPLD/MAXII/RAM2GS.qws differ diff --git a/CPLD/MAXII/db/RAM2GS.(0).cnf.cdb b/CPLD/MAXII/db/RAM2GS.(0).cnf.cdb index 44fdc4e..98161d8 100644 Binary files a/CPLD/MAXII/db/RAM2GS.(0).cnf.cdb and b/CPLD/MAXII/db/RAM2GS.(0).cnf.cdb differ diff --git a/CPLD/MAXII/db/RAM2GS.(0).cnf.hdb b/CPLD/MAXII/db/RAM2GS.(0).cnf.hdb index 2874700..178a749 100644 Binary files a/CPLD/MAXII/db/RAM2GS.(0).cnf.hdb and b/CPLD/MAXII/db/RAM2GS.(0).cnf.hdb differ diff --git a/CPLD/MAXII/db/RAM2GS.asm.qmsg b/CPLD/MAXII/db/RAM2GS.asm.qmsg index a0fa0f7..70abc3a 100644 --- a/CPLD/MAXII/db/RAM2GS.asm.qmsg +++ b/CPLD/MAXII/db/RAM2GS.asm.qmsg @@ -1,7 +1,7 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691916642301 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691916642301 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:50:42 2023 " "Processing started: Sun Aug 13 04:50:42 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691916642301 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691916642301 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691916642301 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691916642519 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691916642535 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691916642535 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4663 " "Peak virtual memory: 4663 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916642660 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:42 2023 " "Processing ended: Sun Aug 13 04:50:42 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916642660 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916642660 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916642660 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691916642660 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691922993004 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922993004 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:36:32 2023 " "Processing started: Sun Aug 13 06:36:32 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922993004 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691922993004 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691922993004 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691922993222 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691922993238 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691922993254 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4663 " "Peak virtual memory: 4663 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922993363 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:36:33 2023 " "Processing ended: Sun Aug 13 06:36:33 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922993363 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922993363 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922993363 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691922993363 ""} diff --git a/CPLD/MAXII/db/RAM2GS.asm.rdb b/CPLD/MAXII/db/RAM2GS.asm.rdb index f655ea9..a761141 100644 Binary files a/CPLD/MAXII/db/RAM2GS.asm.rdb and b/CPLD/MAXII/db/RAM2GS.asm.rdb differ diff --git a/CPLD/MAXII/db/RAM2GS.asm_labs.ddb b/CPLD/MAXII/db/RAM2GS.asm_labs.ddb index a36c071..3aa9131 100644 Binary files a/CPLD/MAXII/db/RAM2GS.asm_labs.ddb and b/CPLD/MAXII/db/RAM2GS.asm_labs.ddb differ diff --git a/CPLD/MAXII/db/RAM2GS.cmp.cdb b/CPLD/MAXII/db/RAM2GS.cmp.cdb index 0503533..1da8483 100644 Binary files a/CPLD/MAXII/db/RAM2GS.cmp.cdb and b/CPLD/MAXII/db/RAM2GS.cmp.cdb differ diff --git a/CPLD/MAXII/db/RAM2GS.cmp.hdb b/CPLD/MAXII/db/RAM2GS.cmp.hdb index 83869b3..eb3829b 100644 Binary files a/CPLD/MAXII/db/RAM2GS.cmp.hdb and b/CPLD/MAXII/db/RAM2GS.cmp.hdb differ diff --git a/CPLD/MAXII/db/RAM2GS.cmp.idb b/CPLD/MAXII/db/RAM2GS.cmp.idb index 7b9abaa..3ff160d 100644 Binary files a/CPLD/MAXII/db/RAM2GS.cmp.idb and b/CPLD/MAXII/db/RAM2GS.cmp.idb differ diff --git a/CPLD/MAXII/db/RAM2GS.cmp.rdb b/CPLD/MAXII/db/RAM2GS.cmp.rdb index 4c7511a..9a4dd89 100644 Binary files a/CPLD/MAXII/db/RAM2GS.cmp.rdb and b/CPLD/MAXII/db/RAM2GS.cmp.rdb differ diff --git a/CPLD/MAXII/db/RAM2GS.cmp0.ddb b/CPLD/MAXII/db/RAM2GS.cmp0.ddb index e75f5b3..835d779 100644 Binary files a/CPLD/MAXII/db/RAM2GS.cmp0.ddb and b/CPLD/MAXII/db/RAM2GS.cmp0.ddb differ diff --git a/CPLD/MAXII/db/RAM2GS.db_info b/CPLD/MAXII/db/RAM2GS.db_info index ec93250..791ee53 100644 --- a/CPLD/MAXII/db/RAM2GS.db_info +++ b/CPLD/MAXII/db/RAM2GS.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition Version_Index = 503488000 -Creation_Time = Sun Aug 13 04:50:24 2023 +Creation_Time = Sun Aug 13 05:45:46 2023 diff --git a/CPLD/MAXII/db/RAM2GS.fit.qmsg b/CPLD/MAXII/db/RAM2GS.fit.qmsg index fb060a4..2c68733 100644 --- a/CPLD/MAXII/db/RAM2GS.fit.qmsg +++ b/CPLD/MAXII/db/RAM2GS.fit.qmsg @@ -1,45 +1,45 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691916639926 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691916639926 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691916639926 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691916639973 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691916639973 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691916639988 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691916640004 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916640098 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916640098 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916640098 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916640098 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916640098 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691916640098 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691916640144 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691916640160 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691916640160 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691916640160 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916640160 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691916640160 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691916640160 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691916640160 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691916640160 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 340 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916640176 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691916640176 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691916640191 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691916640223 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691916640223 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691916640223 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691916640223 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916640238 ""} -{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691916640254 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691916640332 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916640441 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691916640441 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691916640816 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916640816 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691916640832 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "22 " "Router estimated average interconnect usage is 22% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "22 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691916640957 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691916640957 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691916641098 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691916641098 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916641098 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.25 " "Total time spent on timing analysis during the Fitter is 0.25 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691916641113 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916641113 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691916641144 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691916641176 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916641207 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:41 2023 " "Processing ended: Sun Aug 13 04:50:41 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916641207 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916641207 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916641207 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691916641207 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691922990504 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691922990504 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691922990504 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691922990551 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691922990551 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691922990582 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691922990582 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922990707 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922990707 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922990707 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922990707 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922990707 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691922990707 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691922990770 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691922990770 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691922990770 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691922990770 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922990770 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922990770 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922990770 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922990770 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922990770 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922990770 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922990770 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922990770 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691922990770 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691922990785 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691922990785 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691922990785 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922990801 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 336 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922990801 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922990801 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922990801 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922990801 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922990801 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691922990801 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691922990816 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691922990832 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691922990832 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691922990832 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691922990832 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922990863 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691922990863 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691922990957 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922991066 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691922991066 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691922991457 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922991457 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691922991473 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691922991598 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691922991598 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691922991754 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691922991754 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922991754 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.25 " "Total time spent on timing analysis during the Fitter is 0.25 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691922991769 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922991769 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691922991816 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691922991848 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922991879 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:36:31 2023 " "Processing ended: Sun Aug 13 06:36:31 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922991879 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922991879 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922991879 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691922991879 ""} diff --git a/CPLD/MAXII/db/RAM2GS.hier_info b/CPLD/MAXII/db/RAM2GS.hier_info index c65e494..1fe70d4 100644 --- a/CPLD/MAXII/db/RAM2GS.hier_info +++ b/CPLD/MAXII/db/RAM2GS.hier_info @@ -88,25 +88,25 @@ Din[2] => WRD[2].DATAIN Din[2] => Bank[2].DATAIN Din[2] => Equal14.IN6 Din[2] => Equal15.IN3 -Din[2] => Equal17.IN1 +Din[2] => Equal16.IN1 Din[3] => CmdUFMErase.DATAB Din[3] => WRD[3].DATAIN Din[3] => Bank[3].DATAIN Din[3] => Equal14.IN5 Din[3] => Equal15.IN2 -Din[3] => Equal17.IN0 +Din[3] => Equal16.IN0 Din[4] => WRD[4].DATAIN Din[4] => Bank[4].DATAIN Din[4] => Equal14.IN4 Din[4] => Equal15.IN6 -Din[4] => Equal16.IN3 +Din[4] => Equal17.IN3 Din[4] => Equal18.IN0 Din[4] => Equal19.IN3 Din[5] => WRD[5].DATAIN Din[5] => Bank[5].DATAIN Din[5] => Equal14.IN3 Din[5] => Equal15.IN1 -Din[5] => Equal16.IN2 +Din[5] => Equal17.IN2 Din[5] => Equal18.IN3 Din[5] => Equal19.IN0 Din[6] => RA11.IN1 @@ -114,24 +114,24 @@ Din[6] => WRD[6].DATAIN Din[6] => Bank[6].DATAIN Din[6] => Equal14.IN1 Din[6] => Equal15.IN5 -Din[6] => Equal16.IN1 +Din[6] => Equal17.IN1 Din[6] => Equal18.IN2 Din[6] => Equal19.IN2 Din[7] => WRD[7].DATAIN Din[7] => Bank[7].DATAIN Din[7] => Equal14.IN0 Din[7] => Equal15.IN0 -Din[7] => Equal16.IN0 +Din[7] => Equal17.IN0 Din[7] => Equal18.IN1 Din[7] => Equal19.IN1 -Dout[0] <= Dout[0].DB_MAX_OUTPUT_PORT_TYPE -Dout[1] <= Dout[1].DB_MAX_OUTPUT_PORT_TYPE -Dout[2] <= Dout[2].DB_MAX_OUTPUT_PORT_TYPE -Dout[3] <= Dout[3].DB_MAX_OUTPUT_PORT_TYPE -Dout[4] <= Dout[4].DB_MAX_OUTPUT_PORT_TYPE -Dout[5] <= Dout[5].DB_MAX_OUTPUT_PORT_TYPE -Dout[6] <= Dout[6].DB_MAX_OUTPUT_PORT_TYPE -Dout[7] <= Dout[7].DB_MAX_OUTPUT_PORT_TYPE +Dout[0] << Dout[0].DB_MAX_OUTPUT_PORT_TYPE +Dout[1] << Dout[1].DB_MAX_OUTPUT_PORT_TYPE +Dout[2] << Dout[2].DB_MAX_OUTPUT_PORT_TYPE +Dout[3] << Dout[3].DB_MAX_OUTPUT_PORT_TYPE +Dout[4] << Dout[4].DB_MAX_OUTPUT_PORT_TYPE +Dout[5] << Dout[5].DB_MAX_OUTPUT_PORT_TYPE +Dout[6] << Dout[6].DB_MAX_OUTPUT_PORT_TYPE +Dout[7] << Dout[7].DB_MAX_OUTPUT_PORT_TYPE nCCAS => WRD[0].CLK nCCAS => WRD[1].CLK nCCAS => WRD[2].CLK @@ -164,21 +164,21 @@ nFWE => CMDWR.IN1 nFWE => ADWR.IN1 nFWE => C1WR.IN1 nFWE => FWEr.DATAIN -LED <= LED.DB_MAX_OUTPUT_PORT_TYPE -RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE -RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE -RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE -RA[10] <= RA10.DB_MAX_OUTPUT_PORT_TYPE -RA[11] <= RA11.DB_MAX_OUTPUT_PORT_TYPE +LED << LED.DB_MAX_OUTPUT_PORT_TYPE +RBA[0] << RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RBA[1] << RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[0] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[1] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[2] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[3] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[4] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[5] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[6] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[7] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[8] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[9] << RA.DB_MAX_OUTPUT_PORT_TYPE +RA[10] << RA10.DB_MAX_OUTPUT_PORT_TYPE +RA[11] << RA11.DB_MAX_OUTPUT_PORT_TYPE RD[0] <> RD[0] RD[1] <> RD[1] RD[2] <> RD[2] @@ -187,7 +187,7 @@ RD[4] <> RD[4] RD[5] <> RD[5] RD[6] <> RD[6] RD[7] <> RD[7] -nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRCS << nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE RCLK => UFMProgram.CLK RCLK => UFMErase.CLK RCLK => UFMReqErase.CLK @@ -243,12 +243,12 @@ RCLK => RASr.CLK RCLK => PHI2r3.CLK RCLK => PHI2r2.CLK RCLK => PHI2r.CLK -RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE -nRWE <= nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE -nRRAS <= nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE -nRCAS <= nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE -RDQMH <= RDQMH.DB_MAX_OUTPUT_PORT_TYPE -RDQML <= RDQML.DB_MAX_OUTPUT_PORT_TYPE +RCKE << RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRWE << nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRRAS << nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRCAS << nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE +RDQMH << RDQMH.DB_MAX_OUTPUT_PORT_TYPE +RDQML << RDQML.DB_MAX_OUTPUT_PORT_TYPE |RAM2GS|UFM:UFM_inst diff --git a/CPLD/MAXII/db/RAM2GS.hif b/CPLD/MAXII/db/RAM2GS.hif index bbe8de7..26016a1 100644 Binary files a/CPLD/MAXII/db/RAM2GS.hif and b/CPLD/MAXII/db/RAM2GS.hif differ diff --git a/CPLD/MAXII/db/RAM2GS.map.cdb b/CPLD/MAXII/db/RAM2GS.map.cdb index 5bfcc19..04f5b07 100644 Binary files a/CPLD/MAXII/db/RAM2GS.map.cdb and b/CPLD/MAXII/db/RAM2GS.map.cdb differ diff --git a/CPLD/MAXII/db/RAM2GS.map.hdb b/CPLD/MAXII/db/RAM2GS.map.hdb index 1299fdd..8581f2f 100644 Binary files a/CPLD/MAXII/db/RAM2GS.map.hdb and b/CPLD/MAXII/db/RAM2GS.map.hdb differ diff --git a/CPLD/MAXII/db/RAM2GS.map.qmsg b/CPLD/MAXII/db/RAM2GS.map.qmsg index 6b440fd..2adcb52 100644 --- a/CPLD/MAXII/db/RAM2GS.map.qmsg +++ b/CPLD/MAXII/db/RAM2GS.map.qmsg @@ -1,27 +1,27 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691916629644 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691916629644 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:50:29 2023 " "Processing started: Sun Aug 13 04:50:29 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691916629644 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916629644 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916629644 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691916629957 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691916629957 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691916638098 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691916638098 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916638098 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691916638129 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691916638129 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_unv " "Found entity 1: UFM_altufm_none_unv" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691916638129 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691916638129 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916638129 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691916638160 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691916638160 "|RAM2GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691916638160 "|RAM2GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691916638160 "|RAM2GS"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691916638176 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_unv UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component " "Elaborating entity \"UFM_altufm_none_unv\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component\"" { } { { "UFM.v" "UFM_altufm_none_unv_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691916638192 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916638457 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916638457 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916638457 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916638457 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916638457 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916638457 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916638457 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916638457 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691916638488 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691916638488 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691916638488 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691916638488 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691916638488 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691916638488 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916638535 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4700 " "Peak virtual memory: 4700 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916638551 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:38 2023 " "Processing ended: Sun Aug 13 04:50:38 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916638551 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916638551 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916638551 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916638551 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691922978582 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922978582 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:36:18 2023 " "Processing started: Sun Aug 13 06:36:18 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922978582 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922978582 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922978582 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691922979047 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691922979047 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691922988629 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691922988629 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922988629 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691922988676 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691922988676 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_unv " "Found entity 1: UFM_altufm_none_unv" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691922988676 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691922988676 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922988676 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691922988707 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691922988707 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691922988707 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691922988707 "|RAM2GS"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691922988723 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_unv UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component " "Elaborating entity \"UFM_altufm_none_unv\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component\"" { } { { "UFM.v" "UFM_altufm_none_unv_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691922988723 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922989020 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922989020 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922989020 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922989020 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922989020 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922989020 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922989020 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922989020 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691922989051 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691922989051 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691922989051 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691922989051 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691922989051 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691922989051 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922989113 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4702 " "Peak virtual memory: 4702 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922989129 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:36:29 2023 " "Processing ended: Sun Aug 13 06:36:29 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922989129 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922989129 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922989129 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922989129 ""} diff --git a/CPLD/MAXII/db/RAM2GS.map.rdb b/CPLD/MAXII/db/RAM2GS.map.rdb index 01cb887..9f27e69 100644 Binary files a/CPLD/MAXII/db/RAM2GS.map.rdb and b/CPLD/MAXII/db/RAM2GS.map.rdb differ diff --git a/CPLD/MAXII/db/RAM2GS.pre_map.hdb b/CPLD/MAXII/db/RAM2GS.pre_map.hdb index 821c5d9..ded3a08 100644 Binary files a/CPLD/MAXII/db/RAM2GS.pre_map.hdb and b/CPLD/MAXII/db/RAM2GS.pre_map.hdb differ diff --git a/CPLD/MAXII/db/RAM2GS.routing.rdb b/CPLD/MAXII/db/RAM2GS.routing.rdb index a15b7e9..42882b4 100644 Binary files a/CPLD/MAXII/db/RAM2GS.routing.rdb and b/CPLD/MAXII/db/RAM2GS.routing.rdb differ diff --git a/CPLD/MAXII/db/RAM2GS.rtlv.hdb b/CPLD/MAXII/db/RAM2GS.rtlv.hdb index fe91131..ec8c72a 100644 Binary files a/CPLD/MAXII/db/RAM2GS.rtlv.hdb and b/CPLD/MAXII/db/RAM2GS.rtlv.hdb differ diff --git a/CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb b/CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb index 621c2e4..11638fe 100644 Binary files a/CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb and b/CPLD/MAXII/db/RAM2GS.rtlv_sg.cdb differ diff --git a/CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb b/CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb index cbc0bb7..de7e9e6 100644 Binary files a/CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb and b/CPLD/MAXII/db/RAM2GS.rtlv_sg_swap.cdb differ diff --git a/CPLD/MAXII/db/RAM2GS.sta.qmsg b/CPLD/MAXII/db/RAM2GS.sta.qmsg index 9e58fc7..d84743f 100644 --- a/CPLD/MAXII/db/RAM2GS.sta.qmsg +++ b/CPLD/MAXII/db/RAM2GS.sta.qmsg @@ -1,25 +1,25 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691916643769 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691916643769 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:50:43 2023 " "Processing started: Sun Aug 13 04:50:43 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691916643769 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691916643769 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691916643769 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691916643863 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691916643988 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691916643988 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644019 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644019 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691916644066 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691916644207 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691916644254 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644254 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916644270 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691916644270 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691916644270 ""} -{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691916644270 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691916644285 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.541 -253.391 RCLK " " -8.541 -253.391 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.503 -92.361 PHI2 " " -8.503 -92.361 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.149 -5.683 nCRAS " " -1.149 -5.683 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644285 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -17.185 " "Worst-case hold slack is -17.185" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -17.185 -17.185 DRCLK " " -17.185 -17.185 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.694 -16.694 ARCLK " " -16.694 -16.694 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.367 -1.096 nCRAS " " -0.367 -1.096 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.107 -0.165 PHI2 " " -0.107 -0.165 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.163 0.000 RCLK " " 1.163 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644285 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644285 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691916644285 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691916644301 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916644301 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916644301 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691916644379 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691916644395 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691916644395 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4677 " "Peak virtual memory: 4677 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916644441 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:44 2023 " "Processing ended: Sun Aug 13 04:50:44 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916644441 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916644441 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916644441 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691916644441 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691922994535 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922994535 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:36:34 2023 " "Processing started: Sun Aug 13 06:36:34 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922994535 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691922994535 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691922994535 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691922994645 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691922994769 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691922994769 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922994801 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922994801 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691922994832 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691922994973 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691922995020 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922995020 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922995020 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922995020 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922995020 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922995020 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922995020 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922995020 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691922995020 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691922995020 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691922995035 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691922995035 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.675 -99.463 PHI2 " " -8.675 -99.463 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.924 -256.499 RCLK " " -7.924 -256.499 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.977 -1.340 nCRAS " " -0.977 -1.340 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922995035 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.324 " "Worst-case hold slack is -16.324" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.324 -16.324 DRCLK " " -16.324 -16.324 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.276 -16.276 ARCLK " " -16.276 -16.276 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.015 -1.898 PHI2 " " -1.015 -1.898 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.103 -0.198 nCRAS " " -0.103 -0.198 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.151 0.000 RCLK " " 1.151 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995035 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922995035 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691922995035 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691922995051 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922995051 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922995051 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691922995113 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691922995144 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691922995144 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922995191 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:36:35 2023 " "Processing ended: Sun Aug 13 06:36:35 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922995191 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922995191 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922995191 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691922995191 ""} diff --git a/CPLD/MAXII/db/RAM2GS.sta.rdb b/CPLD/MAXII/db/RAM2GS.sta.rdb index 5d1ccf6..1894210 100644 Binary files a/CPLD/MAXII/db/RAM2GS.sta.rdb and b/CPLD/MAXII/db/RAM2GS.sta.rdb differ diff --git a/CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb b/CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb index 142a18c..0b26e7f 100644 Binary files a/CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb and b/CPLD/MAXII/db/RAM2GS.sta_cmp.5_slow.tdb differ diff --git a/CPLD/MAXII/db/RAM2GS.tmw_info b/CPLD/MAXII/db/RAM2GS.tmw_info index b1dda52..abb47a1 100644 --- a/CPLD/MAXII/db/RAM2GS.tmw_info +++ b/CPLD/MAXII/db/RAM2GS.tmw_info @@ -1,6 +1,6 @@ -start_full_compilation:s:00:00:16 -start_analysis_synthesis:s:00:00:10-start_full_compilation +start_full_compilation:s:00:00:18 +start_analysis_synthesis:s:00:00:12-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:02-start_full_compilation -start_assembler:s:00:00:02-start_full_compilation +start_fitter:s:00:00:03-start_full_compilation +start_assembler:s:00:00:01-start_full_compilation start_timing_analyzer:s:00:00:02-start_full_compilation diff --git a/CPLD/MAXII/db/RAM2GS.vpr.ammdb b/CPLD/MAXII/db/RAM2GS.vpr.ammdb index 04358f8..3ca426c 100644 Binary files a/CPLD/MAXII/db/RAM2GS.vpr.ammdb and b/CPLD/MAXII/db/RAM2GS.vpr.ammdb differ diff --git a/CPLD/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg b/CPLD/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg index c4ddaa7..abcb803 100644 --- a/CPLD/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg +++ b/CPLD/MAXII/db/prev_cmp_RAM2GS-MAXII.qmsg @@ -1,115 +1,112 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691903436765 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903436781 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:36 2023 " "Processing started: Sun Aug 13 01:10:36 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903436781 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903436781 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903436781 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691903437078 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691903437078 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691903445963 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903445963 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903445963 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691903446010 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691903446010 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_unv " "Found entity 1: UFM_altufm_none_unv" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903446010 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691903446010 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903446010 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691903446041 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903446041 "|RAM2GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903446041 "|RAM2GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691903446041 "|RAM2GS"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691903446072 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_unv UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component " "Elaborating entity \"UFM_altufm_none_unv\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component\"" { } { { "UFM.v" "UFM_altufm_none_unv_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691903446088 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903446478 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903446478 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903446478 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903446478 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903446478 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903446478 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903446478 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691903446478 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "247 " "Implemented 247 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691903446525 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691903446525 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691903446525 ""} { "Info" "ICUT_CUT_TM_LCELLS" "183 " "Implemented 183 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691903446525 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691903446525 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691903446525 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903446572 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4700 " "Peak virtual memory: 4700 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903446588 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:46 2023 " "Processing ended: Sun Aug 13 01:10:46 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903446588 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903446588 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:25 " "Total CPU time (on all processors): 00:00:25" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903446588 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691903446588 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1691903447931 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903447947 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:47 2023 " "Processing started: Sun Aug 13 01:10:47 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903447947 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1691903447947 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1691903447947 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1691903448056 ""} -{ "Info" "0" "" "Project = RAM2GS-MAXII" { } { } 0 0 "Project = RAM2GS-MAXII" 0 0 "Fitter" 0 0 1691903448056 ""} -{ "Info" "0" "" "Revision = RAM2GS" { } { } 0 0 "Revision = RAM2GS" 0 0 "Fitter" 0 0 1691903448056 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691903448103 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691903448103 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691903448103 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691903448150 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691903448150 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691903448187 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691903448193 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903448318 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903448318 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903448318 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903448318 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691903448318 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691903448318 ""} -{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 63 " "No exact pin location assignment(s) for 1 pins of 63 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1691903448334 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691903448365 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691903448365 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691903448365 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691903448365 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903448365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903448365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903448365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903448365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903448365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903448365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903448365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691903448365 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691903448365 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691903448365 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691903448365 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691903448380 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903448380 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903448380 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903448380 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903448380 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903448380 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903448380 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903448380 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903448380 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903448380 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903448380 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691903448380 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691903448380 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691903448380 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691903448380 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691903448380 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691903448396 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691903448443 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691903448443 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691903448443 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691903448443 ""} -{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "1 unused 3.3V 0 1 0 " "Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1691903448459 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1691903448459 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1691903448459 ""} -{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 38 0 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 38 total pin(s) used -- 0 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1691903448459 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 24 18 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 24 total pin(s) used -- 18 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1691903448459 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1691903448459 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1691903448459 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903448490 ""} -{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691903448490 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691903448584 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903448724 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691903448724 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691903449219 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903449219 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691903449235 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691903449344 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691903449344 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691903449485 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691903449485 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903449485 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.26 " "Total time spent on timing analysis during the Fitter is 0.26 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691903449500 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691903449500 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691903449532 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691903449563 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5344 " "Peak virtual memory: 5344 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903449578 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:49 2023 " "Processing ended: Sun Aug 13 01:10:49 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903449578 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903449578 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903449578 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691903449578 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1691903450625 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903450625 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:50 2023 " "Processing started: Sun Aug 13 01:10:50 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903450625 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691903450625 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691903450625 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691903450891 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691903450907 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691903450922 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903451020 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:51 2023 " "Processing ended: Sun Aug 13 01:10:51 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903451020 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903451020 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903451020 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691903451020 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1691903451629 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1691903452426 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691903452426 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 01:10:52 2023 " "Processing started: Sun Aug 13 01:10:52 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691903452426 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691903452426 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691903452426 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691903452582 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691903452910 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691903452910 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903452942 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903452942 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691903452988 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691903453145 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691903453176 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903453176 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903453176 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903453176 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903453176 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903453176 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903453176 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691903453176 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691903453176 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691903453176 ""} -{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691903453191 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691903453191 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.855 -98.476 PHI2 " " -8.855 -98.476 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.999 -266.939 RCLK " " -7.999 -266.939 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.973 -1.155 nCRAS " " -0.973 -1.155 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903453223 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.789 " "Worst-case hold slack is -16.789" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.789 -16.789 DRCLK " " -16.789 -16.789 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.423 -16.423 ARCLK " " -16.423 -16.423 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.008 -2.101 PHI2 " " -1.008 -2.101 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.397 -1.578 nCRAS " " -0.397 -1.578 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.107 0.000 RCLK " " 1.107 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453223 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903453223 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691903453238 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691903453238 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691903453254 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691903453254 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691903453301 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691903453332 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691903453332 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691903453379 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 01:10:53 2023 " "Processing ended: Sun Aug 13 01:10:53 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691903453379 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691903453379 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691903453379 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691903453379 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 21 s " "Quartus Prime Full Compilation was successful. 0 errors, 21 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691903454016 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691922467363 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922467363 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:27:47 2023 " "Processing started: Sun Aug 13 06:27:47 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922467363 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922467363 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922467363 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691922467957 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691922467957 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691922477879 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691922477879 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922477879 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691922477926 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691922477926 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_unv " "Found entity 1: UFM_altufm_none_unv" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691922477926 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691922477926 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922477926 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691922477972 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691922477972 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691922477972 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691922477972 "|RAM2GS"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691922478004 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_unv UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component " "Elaborating entity \"UFM_altufm_none_unv\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_unv:UFM_altufm_none_unv_component\"" { } { { "UFM.v" "UFM_altufm_none_unv_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691922478019 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922478332 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922478332 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922478332 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922478332 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922478332 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922478332 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922478332 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922478332 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691922478363 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691922478363 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691922478363 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691922478363 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691922478363 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691922478363 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922478426 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4703 " "Peak virtual memory: 4703 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922478441 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:27:58 2023 " "Processing ended: Sun Aug 13 06:27:58 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922478441 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922478441 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922478441 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922478441 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1691922479832 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922479832 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:27:59 2023 " "Processing started: Sun Aug 13 06:27:59 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922479832 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1691922479832 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1691922479832 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1691922479941 ""} +{ "Info" "0" "" "Project = RAM2GS-MAXII" { } { } 0 0 "Project = RAM2GS-MAXII" 0 0 "Fitter" 0 0 1691922479941 ""} +{ "Info" "0" "" "Revision = RAM2GS" { } { } 0 0 "Revision = RAM2GS" 0 0 "Fitter" 0 0 1691922479941 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691922480004 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691922480004 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691922480004 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691922480035 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691922480035 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691922480082 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691922480082 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922480223 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922480223 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922480223 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922480223 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922480223 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691922480223 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691922480269 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691922480269 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691922480269 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691922480269 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922480269 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922480269 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922480269 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922480269 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922480269 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922480269 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922480269 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922480269 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691922480269 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691922480269 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691922480269 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691922480285 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922480285 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922480285 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922480285 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691922480285 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922480285 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922480285 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922480285 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691922480285 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922480285 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922480285 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922480285 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922480285 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691922480285 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691922480285 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691922480285 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691922480301 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691922480316 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691922480316 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691922480316 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691922480316 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922480347 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691922480347 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691922480426 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922480535 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691922480535 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691922480910 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922480910 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691922480926 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691922481066 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691922481066 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691922481238 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691922481238 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922481238 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.26 " "Total time spent on timing analysis during the Fitter is 0.26 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691922481254 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922481269 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691922481285 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691922481316 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5343 " "Peak virtual memory: 5343 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922481348 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:28:01 2023 " "Processing ended: Sun Aug 13 06:28:01 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922481348 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922481348 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922481348 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691922481348 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1691922482426 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922482426 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:28:02 2023 " "Processing started: Sun Aug 13 06:28:02 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922482426 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691922482426 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691922482426 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691922482644 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691922482676 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691922482676 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4663 " "Peak virtual memory: 4663 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922482785 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:28:02 2023 " "Processing ended: Sun Aug 13 06:28:02 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922482785 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922482785 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922482785 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691922482785 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1691922483488 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1691922484019 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922484019 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:28:03 2023 " "Processing started: Sun Aug 13 06:28:03 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922484019 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691922484019 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXII -c RAM2GS " "Command: quartus_sta RAM2GS-MAXII -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691922484019 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691922484129 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691922484269 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691922484269 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922484301 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922484301 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691922484332 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691922484488 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691922484519 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922484519 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922484519 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922484519 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922484519 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922484519 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922484519 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922484519 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691922484519 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691922484519 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691922484535 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691922484535 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -8.675 -99.463 PHI2 " " -8.675 -99.463 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.924 -256.499 RCLK " " -7.924 -256.499 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.977 -1.340 nCRAS " " -0.977 -1.340 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484535 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922484535 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.324 " "Worst-case hold slack is -16.324" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.324 -16.324 DRCLK " " -16.324 -16.324 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.276 -16.276 ARCLK " " -16.276 -16.276 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.015 -1.898 PHI2 " " -1.015 -1.898 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.103 -0.198 nCRAS " " -0.103 -0.198 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.151 0.000 RCLK " " 1.151 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484551 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922484551 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691922484551 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691922484566 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922484566 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922484566 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691922484629 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691922484660 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691922484660 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922484707 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:28:04 2023 " "Processing ended: Sun Aug 13 06:28:04 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922484707 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922484707 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922484707 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691922484707 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 20 s " "Quartus Prime Full Compilation was successful. 0 errors, 20 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691922485379 ""} diff --git a/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt b/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt index d73dff3..d0e06bd 100644 Binary files a/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt and b/CPLD/MAXII/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt differ diff --git a/CPLD/MAXII/output_files/RAM2GS.asm.rpt b/CPLD/MAXII/output_files/RAM2GS.asm.rpt index 8878de3..ddbf78b 100644 --- a/CPLD/MAXII/output_files/RAM2GS.asm.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.asm.rpt @@ -1,5 +1,5 @@ Assembler report for RAM2GS -Sun Aug 13 04:50:42 2023 +Sun Aug 13 06:36:33 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sun Aug 13 04:50:42 2023 ; +; Assembler Status ; Successful - Sun Aug 13 06:36:33 2023 ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX II ; @@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula. +----------------+---------------------------------------------------------------------------------+ ; Option ; Setting ; +----------------+---------------------------------------------------------------------------------+ -; JTAG usercode ; 0x00171C35 ; -; Checksum ; 0x00172025 ; +; JTAG usercode ; 0x00173373 ; +; Checksum ; 0x001735EB ; +----------------+---------------------------------------------------------------------------------+ @@ -78,15 +78,15 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sun Aug 13 04:50:42 2023 + Info: Processing started: Sun Aug 13 06:36:32 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning Info: Peak virtual memory: 4663 megabytes - Info: Processing ended: Sun Aug 13 04:50:42 2023 - Info: Elapsed time: 00:00:00 + Info: Processing ended: Sun Aug 13 06:36:33 2023 + Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:00 diff --git a/CPLD/MAXII/output_files/RAM2GS.done b/CPLD/MAXII/output_files/RAM2GS.done index 15ad0a9..d4305d5 100644 --- a/CPLD/MAXII/output_files/RAM2GS.done +++ b/CPLD/MAXII/output_files/RAM2GS.done @@ -1 +1 @@ -Sun Aug 13 04:50:45 2023 +Sun Aug 13 06:36:35 2023 diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.rpt b/CPLD/MAXII/output_files/RAM2GS.fit.rpt index e04858d..e60bbb4 100644 --- a/CPLD/MAXII/output_files/RAM2GS.fit.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.fit.rpt @@ -1,5 +1,5 @@ Fitter report for RAM2GS -Sun Aug 13 04:50:41 2023 +Sun Aug 13 06:36:31 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -59,7 +59,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Fitter Summary ; +-----------------------+---------------------------------------------+ -; Fitter Status ; Successful - Sun Aug 13 04:50:41 2023 ; +; Fitter Status ; Successful - Sun Aug 13 06:36:31 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -135,8 +135,8 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 1.8% ; -; Processors 3-4 ; 1.5% ; +; Processor 2 ; 2.0% ; +; Processors 3-4 ; 1.3% ; +----------------------------+-------------+ @@ -157,9 +157,9 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ ; -- Combinational with a register ; 77 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 56 ; -; -- 3 input functions ; 48 ; -; -- 2 input functions ; 41 ; +; -- 4 input functions ; 57 ; +; -- 3 input functions ; 46 ; +; -- 2 input functions ; 42 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; @@ -168,11 +168,11 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ ; -- arithmetic mode ; 16 ; ; -- qfbk mode ; 7 ; ; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 29 ; +; -- synchronous clear/load mode ; 25 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; ; Total registers ; 98 / 240 ( 41 % ) ; -; Total LABs ; 23 / 24 ( 96 % ) ; +; Total LABs ; 21 / 24 ( 88 % ) ; ; Logic elements in carry chains ; 17 ; ; Virtual pins ; 0 ; ; I/O pins ; 63 / 80 ( 79 % ) ; @@ -186,8 +186,8 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ ; Global signals ; 4 ; ; -- Global clocks ; 4 / 4 ( 100 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 26.5% / 24.7% / 28.5% ; -; Peak interconnect usage (total/H/V) ; 26.5% / 24.7% / 28.5% ; +; Average interconnect usage (total/H/V) ; 23.8% / 26.2% / 21.3% ; +; Peak interconnect usage (total/H/V) ; 23.8% / 26.2% / 21.3% ; ; Maximum fan-out ; 55 ; ; Highest non-global fan-out ; 41 ; ; Total fan-out ; 661 ; @@ -204,20 +204,20 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ ; CROW[1] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[1] ; 36 ; 1 ; 4 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[6] ; 41 ; 1 ; 5 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[7] ; 40 ; 1 ; 5 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[1] ; 51 ; 1 ; 7 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[1] ; 51 ; 1 ; 7 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[2] ; 50 ; 1 ; 7 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[3] ; 71 ; 2 ; 8 ; 4 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[4] ; 70 ; 2 ; 8 ; 4 ; 4 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[5] ; 69 ; 2 ; 8 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[6] ; 72 ; 2 ; 8 ; 4 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[7] ; 68 ; 2 ; 8 ; 3 ; 1 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[6] ; 72 ; 2 ; 8 ; 4 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[7] ; 68 ; 2 ; 8 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[8] ; 73 ; 2 ; 8 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[9] ; 74 ; 2 ; 8 ; 4 ; 0 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 22 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; @@ -245,18 +245,18 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ ; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; ; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; ; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; RBA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RDQMH ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RDQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; @@ -272,12 +272,12 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; -; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; -; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; +; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ; +; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ; ; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; ; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; -; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; -; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; +; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ; +; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ; ; RD[7] ; 97 ; 2 ; 3 ; 5 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -491,8 +491,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Din[6] ; Input ; (1) ; ; nFWE ; Input ; (1) ; ; Din[0] ; Input ; (1) ; -; Din[1] ; Input ; (1) ; ; Din[7] ; Input ; (1) ; +; Din[1] ; Input ; (1) ; ; Din[4] ; Input ; (1) ; ; Din[2] ; Input ; (1) ; ; Din[3] ; Input ; (1) ; @@ -505,14 +505,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ -; CmdDRDIn~2 ; LC_X5_Y3_N9 ; 4 ; Clock enable ; no ; -- ; -- ; -; CmdLEDEN~1 ; LC_X5_Y3_N3 ; 3 ; Clock enable ; no ; -- ; -- ; -; DRDIn~1 ; LC_X6_Y4_N1 ; 2 ; Clock enable ; no ; -- ; -- ; +; CmdDRDIn~1 ; LC_X6_Y1_N6 ; 4 ; Clock enable ; no ; -- ; -- ; +; CmdLEDEN~1 ; LC_X5_Y1_N9 ; 3 ; Clock enable ; no ; -- ; -- ; +; DRDIn~1 ; LC_X5_Y1_N0 ; 2 ; Clock enable ; no ; -- ; -- ; ; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK3 ; ; RCLK ; PIN_12 ; 55 ; Clock ; yes ; Global Clock ; GCLK0 ; -; Ready ; LC_X6_Y2_N8 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ; -; always8~7 ; LC_X7_Y3_N8 ; 3 ; Clock enable ; no ; -- ; -- ; -; comb~0 ; LC_X7_Y1_N6 ; 8 ; Output enable ; no ; -- ; -- ; +; Ready ; LC_X3_Y2_N5 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; always8~6 ; LC_X6_Y3_N1 ; 3 ; Clock enable ; no ; -- ; -- ; +; comb~0 ; LC_X3_Y4_N5 ; 8 ; Output enable ; no ; -- ; -- ; ; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ; ; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK1 ; +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ @@ -535,112 +535,115 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------+--------------------+ ; Routing Resource Type ; Usage ; +-----------------------+--------------------+ -; C4s ; 175 / 784 ( 22 % ) ; -; Direct links ; 36 / 888 ( 4 % ) ; +; C4s ; 146 / 784 ( 19 % ) ; +; Direct links ; 45 / 888 ( 5 % ) ; ; Global clocks ; 4 / 4 ( 100 % ) ; ; LAB clocks ; 14 / 32 ( 44 % ) ; -; LUT chains ; 20 / 216 ( 9 % ) ; -; Local interconnects ; 274 / 888 ( 31 % ) ; -; R4s ; 148 / 704 ( 21 % ) ; +; LUT chains ; 27 / 216 ( 13 % ) ; +; Local interconnects ; 266 / 888 ( 30 % ) ; +; R4s ; 149 / 704 ( 21 % ) ; +-----------------------+--------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 7.61) ; Number of LABs (Total = 23) ; +; Number of Logic Elements (Average = 8.33) ; Number of LABs (Total = 21) ; +--------------------------------------------+------------------------------+ -; 1 ; 2 ; -; 2 ; 2 ; -; 3 ; 0 ; -; 4 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 1 ; ; 5 ; 1 ; ; 6 ; 1 ; ; 7 ; 1 ; -; 8 ; 2 ; -; 9 ; 5 ; -; 10 ; 9 ; +; 8 ; 0 ; +; 9 ; 2 ; +; 10 ; 13 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.43) ; Number of LABs (Total = 23) ; +; LAB-wide Signals (Average = 1.33) ; Number of LABs (Total = 21) ; +------------------------------------+------------------------------+ -; 1 Clock ; 17 ; -; 1 Clock enable ; 2 ; -; 1 Sync. clear ; 5 ; -; 1 Sync. load ; 3 ; -; 2 Clocks ; 6 ; +; 1 Clock ; 10 ; +; 1 Clock enable ; 3 ; +; 1 Sync. clear ; 3 ; +; 1 Sync. load ; 2 ; +; 2 Clocks ; 10 ; +------------------------------------+------------------------------+ +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +---------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 7.87) ; Number of LABs (Total = 23) ; +; Number of Signals Sourced (Average = 8.62) ; Number of LABs (Total = 21) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 2 ; +; 1 ; 0 ; ; 2 ; 1 ; ; 3 ; 1 ; -; 4 ; 0 ; +; 4 ; 1 ; ; 5 ; 1 ; ; 6 ; 1 ; ; 7 ; 1 ; -; 8 ; 1 ; -; 9 ; 5 ; -; 10 ; 8 ; -; 11 ; 1 ; -; 12 ; 1 ; +; 8 ; 0 ; +; 9 ; 2 ; +; 10 ; 9 ; +; 11 ; 2 ; +; 12 ; 2 ; +---------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 5.57) ; Number of LABs (Total = 23) ; +; Number of Signals Sourced Out (Average = 5.57) ; Number of LABs (Total = 21) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 3 ; -; 2 ; 2 ; -; 3 ; 1 ; -; 4 ; 2 ; -; 5 ; 5 ; -; 6 ; 1 ; -; 7 ; 1 ; -; 8 ; 3 ; -; 9 ; 2 ; -; 10 ; 3 ; +; 1 ; 0 ; +; 2 ; 3 ; +; 3 ; 2 ; +; 4 ; 1 ; +; 5 ; 3 ; +; 6 ; 5 ; +; 7 ; 3 ; +; 8 ; 2 ; +; 9 ; 1 ; +; 10 ; 1 ; +-------------------------------------------------+------------------------------+ -+----------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+---------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 9.74) ; Number of LABs (Total = 23) ; -+---------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 1 ; -; 2 ; 0 ; -; 3 ; 1 ; -; 4 ; 0 ; -; 5 ; 1 ; -; 6 ; 3 ; -; 7 ; 3 ; -; 8 ; 2 ; -; 9 ; 0 ; -; 10 ; 3 ; -; 11 ; 2 ; -; 12 ; 1 ; -; 13 ; 0 ; -; 14 ; 1 ; -; 15 ; 1 ; -; 16 ; 2 ; -; 17 ; 1 ; -; 18 ; 1 ; -+---------------------------------------------+------------------------------+ ++-----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 10.71) ; Number of LABs (Total = 21) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 1 ; +; 8 ; 3 ; +; 9 ; 3 ; +; 10 ; 3 ; +; 11 ; 0 ; +; 12 ; 1 ; +; 13 ; 1 ; +; 14 ; 1 ; +; 15 ; 0 ; +; 16 ; 2 ; +; 17 ; 2 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 1 ; ++----------------------------------------------+------------------------------+ +-------------------------------------------------------------------------+ @@ -662,8 +665,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------+----------------------+-------------------+ ; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; +-----------------+----------------------+-------------------+ -; I/O ; nCRAS ; 4.0 ; -; I/O ; RCLK ; 3.7 ; +; I/O ; RCLK ; 4.0 ; +; I/O ; nCRAS ; 2.5 ; +-----------------+----------------------+-------------------+ Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer. @@ -674,9 +677,9 @@ This will disable optimization of problematic paths and expose them for further +-----------------+----------------------+-------------------+ ; Source Register ; Destination Register ; Delay Added in ns ; +-----------------+----------------------+-------------------+ -; nCCAS ; CBR ; 4.013 ; +; nCCAS ; CBR ; 2.469 ; ; PHI2 ; PHI2r ; 1.523 ; -; nCRAS ; RASr ; 0.916 ; +; nCRAS ; RASr ; 1.214 ; +-----------------+----------------------+-------------------+ Note: This table only shows the top 3 path(s) that have the largest delay added for hold. @@ -737,8 +740,8 @@ Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 22% of the available device resources - Info (170196): Router estimated peak interconnect usage is 22% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170195): Router estimated average interconnect usage is 19% of the available device resources + Info (170196): Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 @@ -748,8 +751,8 @@ Warning (169174): The Reserve All Unused Pins setting has not been specified, an Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings Info: Peak virtual memory: 5345 megabytes - Info: Processing ended: Sun Aug 13 04:50:41 2023 - Info: Elapsed time: 00:00:02 + Info: Processing ended: Sun Aug 13 06:36:31 2023 + Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:03 diff --git a/CPLD/MAXII/output_files/RAM2GS.fit.summary b/CPLD/MAXII/output_files/RAM2GS.fit.summary index 9858dbb..952fe86 100644 --- a/CPLD/MAXII/output_files/RAM2GS.fit.summary +++ b/CPLD/MAXII/output_files/RAM2GS.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Sun Aug 13 04:50:41 2023 +Fitter Status : Successful - Sun Aug 13 06:36:31 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS diff --git a/CPLD/MAXII/output_files/RAM2GS.flow.rpt b/CPLD/MAXII/output_files/RAM2GS.flow.rpt index 0c4d2e3..fc55790 100644 --- a/CPLD/MAXII/output_files/RAM2GS.flow.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.flow.rpt @@ -1,5 +1,5 @@ Flow report for RAM2GS -Sun Aug 13 04:50:44 2023 +Sun Aug 13 06:36:35 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+---------------------------------------------+ -; Flow Status ; Successful - Sun Aug 13 04:50:42 2023 ; +; Flow Status ; Successful - Sun Aug 13 06:36:33 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 08/13/2023 04:50:29 ; +; Start date & time ; 08/13/2023 06:36:18 ; ; Main task ; Compilation ; ; Revision Name ; RAM2GS ; +-------------------+---------------------+ @@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------+---------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +---------------------------------------+---------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 207120313862967.169191662914016 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 207120313862967.169192297814284 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; @@ -85,11 +85,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4700 MB ; 00:00:23 ; -; Fitter ; 00:00:02 ; 1.0 ; 5345 MB ; 00:00:03 ; -; Assembler ; 00:00:00 ; 1.0 ; 4662 MB ; 00:00:00 ; -; Timing Analyzer ; 00:00:01 ; 1.0 ; 4677 MB ; 00:00:01 ; -; Total ; 00:00:12 ; -- ; -- ; 00:00:27 ; +; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 4702 MB ; 00:00:26 ; +; Fitter ; 00:00:01 ; 1.0 ; 5345 MB ; 00:00:03 ; +; Assembler ; 00:00:01 ; 1.0 ; 4662 MB ; 00:00:00 ; +; Timing Analyzer ; 00:00:01 ; 1.0 ; 4676 MB ; 00:00:01 ; +; Total ; 00:00:14 ; -- ; -- ; 00:00:30 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/CPLD/MAXII/output_files/RAM2GS.map.rpt b/CPLD/MAXII/output_files/RAM2GS.map.rpt index c5bf80d..5cba882 100644 --- a/CPLD/MAXII/output_files/RAM2GS.map.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for RAM2GS -Sun Aug 13 04:50:38 2023 +Sun Aug 13 06:36:29 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sun Aug 13 04:50:38 2023 ; +; Analysis & Synthesis Status ; Successful - Sun Aug 13 06:36:29 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -167,9 +167,9 @@ https://fpgasoftware.intel.com/eula. ; -- Combinational with a register ; 68 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 56 ; -; -- 3 input functions ; 48 ; -; -- 2 input functions ; 41 ; +; -- 4 input functions ; 57 ; +; -- 3 input functions ; 46 ; +; -- 2 input functions ; 42 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; @@ -270,7 +270,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sun Aug 13 04:50:29 2023 + Info: Processing started: Sun Aug 13 06:36:18 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected @@ -301,10 +301,10 @@ Info (21057): Implemented 248 device resources after synthesis - the final resou Info (21070): Implemented 1 User Flash Memory blocks Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings - Info: Peak virtual memory: 4700 megabytes - Info: Processing ended: Sun Aug 13 04:50:38 2023 - Info: Elapsed time: 00:00:09 - Info: Total CPU time (on all processors): 00:00:23 + Info: Peak virtual memory: 4702 megabytes + Info: Processing ended: Sun Aug 13 06:36:29 2023 + Info: Elapsed time: 00:00:11 + Info: Total CPU time (on all processors): 00:00:26 +------------------------------------------+ diff --git a/CPLD/MAXII/output_files/RAM2GS.map.summary b/CPLD/MAXII/output_files/RAM2GS.map.summary index add9d2e..061e4cf 100644 --- a/CPLD/MAXII/output_files/RAM2GS.map.summary +++ b/CPLD/MAXII/output_files/RAM2GS.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Sun Aug 13 04:50:38 2023 +Analysis & Synthesis Status : Successful - Sun Aug 13 06:36:29 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS diff --git a/CPLD/MAXII/output_files/RAM2GS.pof b/CPLD/MAXII/output_files/RAM2GS.pof index 69bb0b3..5f10bb4 100644 Binary files a/CPLD/MAXII/output_files/RAM2GS.pof and b/CPLD/MAXII/output_files/RAM2GS.pof differ diff --git a/CPLD/MAXII/output_files/RAM2GS.sta.rpt b/CPLD/MAXII/output_files/RAM2GS.sta.rpt index 19d7096..59ebfc9 100644 --- a/CPLD/MAXII/output_files/RAM2GS.sta.rpt +++ b/CPLD/MAXII/output_files/RAM2GS.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for RAM2GS -Sun Aug 13 04:50:44 2023 +Sun Aug 13 06:36:35 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -18,13 +18,13 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition 10. Minimum Pulse Width Summary 11. Setup: 'ARCLK' 12. Setup: 'DRCLK' - 13. Setup: 'RCLK' - 14. Setup: 'PHI2' + 13. Setup: 'PHI2' + 14. Setup: 'RCLK' 15. Setup: 'nCRAS' 16. Hold: 'DRCLK' 17. Hold: 'ARCLK' - 18. Hold: 'nCRAS' - 19. Hold: 'PHI2' + 18. Hold: 'PHI2' + 19. Hold: 'nCRAS' 20. Hold: 'RCLK' 21. Setup Transfers 22. Hold Transfers @@ -87,7 +87,7 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.2% ; +; Processor 2 ; 0.0% ; +----------------------------+-------------+ @@ -112,8 +112,8 @@ https://fpgasoftware.intel.com/eula. +------------+-----------------+------------+------+ ; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; ; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; -; 55.54 MHz ; 55.54 MHz ; PHI2 ; ; -; 114.17 MHz ; 114.17 MHz ; RCLK ; ; +; 54.5 MHz ; 54.5 MHz ; PHI2 ; ; +; 119.76 MHz ; 119.76 MHz ; RCLK ; ; +------------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -125,9 +125,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+---------+---------------+ ; ARCLK ; -99.000 ; -99.000 ; ; DRCLK ; -99.000 ; -99.000 ; -; RCLK ; -8.541 ; -253.391 ; -; PHI2 ; -8.503 ; -92.361 ; -; nCRAS ; -1.149 ; -5.683 ; +; PHI2 ; -8.675 ; -99.463 ; +; RCLK ; -7.924 ; -256.499 ; +; nCRAS ; -0.977 ; -1.340 ; +-------+---------+---------------+ @@ -136,11 +136,11 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+---------+---------------+ -; DRCLK ; -17.185 ; -17.185 ; -; ARCLK ; -16.694 ; -16.694 ; -; nCRAS ; -0.367 ; -1.096 ; -; PHI2 ; -0.107 ; -0.165 ; -; RCLK ; 1.163 ; 0.000 ; +; DRCLK ; -16.324 ; -16.324 ; +; ARCLK ; -16.276 ; -16.276 ; +; PHI2 ; -1.015 ; -1.898 ; +; nCRAS ; -0.103 ; -0.198 ; +; RCLK ; 1.151 ; 0.000 ; +-------+---------+---------------+ @@ -176,7 +176,7 @@ No paths to report. ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; -99.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ; -; -22.306 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -1.732 ; 1.574 ; +; -22.724 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -2.195 ; 1.529 ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ @@ -186,246 +186,246 @@ No paths to report. ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; -99.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ; -; -22.695 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -0.773 ; 2.922 ; -; -21.815 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -0.773 ; 2.042 ; +; -22.707 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.658 ; 2.049 ; +; -22.676 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.658 ; 2.018 ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'RCLK' ; -+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ -; -8.541 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.580 ; 6.128 ; -; -8.532 ; FWEr ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.580 ; 6.119 ; -; -8.528 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.580 ; 6.115 ; -; -8.039 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.580 ; 5.626 ; -; -8.035 ; FWEr ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.580 ; 5.622 ; -; -8.002 ; CBR ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.580 ; 5.589 ; -; -7.967 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.580 ; 5.554 ; -; -7.852 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.314 ; 4.705 ; -; -7.759 ; FS[0] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.426 ; -; -7.570 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.314 ; 4.423 ; -; -7.509 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.580 ; 5.096 ; -; -7.505 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.580 ; 5.092 ; -; -7.443 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.314 ; 4.296 ; -; -7.380 ; CmdLEDEN ; LEDEN ; PHI2 ; RCLK ; 0.500 ; -3.314 ; 4.233 ; -; -7.265 ; CmdSubmitted ; LEDEN ; PHI2 ; RCLK ; 0.500 ; -3.314 ; 4.118 ; -; -7.255 ; FS[2] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.922 ; -; -7.175 ; Ready ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.842 ; -; -7.160 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.827 ; -; -7.120 ; Cmdn8MEGEN ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.314 ; 3.973 ; -; -7.095 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.580 ; 4.682 ; -; -7.019 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.686 ; -; -7.009 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.676 ; -; -6.997 ; S[0] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.664 ; -; -6.961 ; FS[16] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.628 ; -; -6.931 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; LEDEN ; DRCLK ; RCLK ; 1.000 ; 0.773 ; 8.371 ; -; -6.887 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.554 ; -; -6.881 ; FS[1] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.548 ; -; -6.846 ; S[1] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.513 ; -; -6.829 ; FS[17] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.496 ; -; -6.773 ; FS[16] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.440 ; -; -6.772 ; FS[13] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.439 ; -; -6.768 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.435 ; -; -6.762 ; FS[3] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.429 ; -; -6.668 ; RASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.335 ; -; -6.653 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.320 ; -; -6.641 ; FS[17] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.308 ; -; -6.636 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.303 ; -; -6.629 ; FS[0] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.296 ; -; -6.530 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; n8MEGEN ; DRCLK ; RCLK ; 1.000 ; 0.773 ; 7.970 ; -; -6.510 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; UFMD ; DRCLK ; RCLK ; 1.000 ; 0.773 ; 7.950 ; -; -6.448 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.115 ; -; -6.396 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.063 ; -; -6.395 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.062 ; -; -6.362 ; FS[6] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.029 ; -; -6.356 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.023 ; -; -6.329 ; FS[16] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.996 ; -; -6.325 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.992 ; -; -6.321 ; IS[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.988 ; -; -6.309 ; FS[6] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.976 ; -; -6.285 ; InitReady ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.952 ; -; -6.267 ; FS[4] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.934 ; -; -6.264 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.931 ; -; -6.263 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.930 ; -; -6.257 ; FS[11] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.924 ; -; -6.256 ; FS[4] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.923 ; -; -6.251 ; FS[6] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.918 ; -; -6.207 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.874 ; -; -6.197 ; FS[17] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.864 ; -; -6.181 ; FS[10] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.848 ; -; -6.177 ; RASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.844 ; -; -6.162 ; FS[3] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.829 ; -; -6.145 ; FS[8] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.812 ; -; -6.125 ; FS[2] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.792 ; -; -6.116 ; IS[3] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.783 ; -; -6.093 ; IS[2] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.760 ; -; -6.073 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.314 ; 2.926 ; -; -6.045 ; Ready ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.712 ; -; -6.006 ; FS[14] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.673 ; -; -5.993 ; FS[5] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.660 ; -; -5.988 ; FS[5] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.655 ; -; -5.976 ; FS[7] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.643 ; -; -5.972 ; S[0] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.639 ; -; -5.955 ; Ready ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.622 ; -; -5.947 ; IS[0] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.614 ; -; -5.928 ; FS[6] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.595 ; -; -5.918 ; FS[7] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.585 ; -; -5.862 ; FS[7] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.529 ; -; -5.857 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.524 ; -; -5.839 ; Ready ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.506 ; -; -5.826 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.493 ; -; -5.791 ; UFMInitDone ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.458 ; -; -5.753 ; S[1] ; RCKEEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.420 ; -; -5.751 ; FS[1] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.418 ; -; -5.733 ; UFMInitDone ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.400 ; -; -5.702 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.369 ; -; -5.701 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.368 ; -; -5.686 ; FS[6] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.353 ; -; -5.685 ; FS[6] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.352 ; -; -5.671 ; CmdDRCLK ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.314 ; 2.524 ; -; -5.638 ; FS[16] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.305 ; -; -5.632 ; FS[3] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.299 ; -; -5.592 ; IS[2] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.259 ; -; -5.591 ; IS[1] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.258 ; -; -5.548 ; FS[5] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.215 ; -; -5.546 ; Ready ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.213 ; -; -5.545 ; UFMInitDone ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.212 ; -; -5.540 ; UFMInitDone ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.207 ; -; -5.506 ; FS[17] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.173 ; -; -5.495 ; Ready ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.162 ; -; -5.490 ; FS[16] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.157 ; -+--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ - - +---------------------------------------------------------------------------------------------------------+ ; Setup: 'PHI2' ; +--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ -; -8.503 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.670 ; -; -8.349 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.516 ; -; -8.052 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.219 ; -; -8.052 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.219 ; -; -7.898 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.065 ; -; -7.898 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.065 ; -; -7.828 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.995 ; -; -7.810 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.977 ; -; -7.731 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.898 ; -; -7.674 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.841 ; -; -7.581 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.748 ; -; -7.536 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.703 ; -; -7.442 ; Bank[6] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.609 ; -; -7.442 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.609 ; -; -7.442 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.609 ; -; -7.382 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.549 ; -; -7.359 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.526 ; -; -7.359 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.526 ; -; -7.292 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.459 ; -; -7.288 ; Bank[5] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.455 ; -; -7.288 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.455 ; -; -7.288 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.455 ; -; -7.280 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.447 ; -; -7.280 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.447 ; -; -7.135 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.302 ; -; -7.130 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.297 ; -; -7.130 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.297 ; -; -7.056 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.223 ; -; -7.024 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.191 ; -; -7.015 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.182 ; -; -7.015 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.182 ; -; -6.906 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.073 ; -; -6.861 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.028 ; -; -6.861 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.028 ; -; -6.843 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.010 ; -; -6.841 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.008 ; -; -6.841 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.008 ; -; -6.764 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.931 ; -; -6.749 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.916 ; -; -6.749 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.916 ; -; -6.749 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.916 ; -; -6.670 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.837 ; -; -6.670 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.837 ; -; -6.670 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.837 ; -; -6.618 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.785 ; -; -6.618 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.785 ; -; -6.617 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.784 ; -; -6.614 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.781 ; -; -6.573 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.740 ; -; -6.573 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.740 ; -; -6.524 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.691 ; -; -6.520 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.687 ; -; -6.520 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.687 ; -; -6.520 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.687 ; -; -6.464 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.631 ; -; -6.464 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.631 ; -; -6.349 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.516 ; -; -6.325 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.492 ; -; -6.322 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.489 ; -; -6.322 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.489 ; -; -6.243 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.410 ; -; -6.243 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.410 ; -; -6.231 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.398 ; -; -6.231 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.398 ; -; -6.231 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.398 ; -; -6.093 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.260 ; -; -6.093 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.260 ; -; -6.073 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.240 ; -; -6.073 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.240 ; -; -6.057 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.224 ; -; -5.963 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.130 ; -; -5.963 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.130 ; -; -5.963 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.130 ; -; -5.925 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.092 ; -; -5.925 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.092 ; -; -5.849 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.016 ; -; -5.846 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.013 ; -; -5.846 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.013 ; -; -5.804 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.971 ; -; -5.804 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.971 ; -; -5.696 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.863 ; -; -5.696 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.863 ; -; -5.578 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.245 ; -; -5.578 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.245 ; -; -5.557 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.724 ; -; -5.536 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.703 ; -; -5.536 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.703 ; -; -5.463 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.630 ; -; -5.463 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.630 ; -; -5.463 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.630 ; -; -5.407 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.574 ; -; -5.407 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.574 ; -; -5.139 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.306 ; -; -5.139 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.306 ; -; -5.062 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.729 ; -; -5.036 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.203 ; -; -5.036 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 5.203 ; -; -4.968 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.635 ; -; -4.968 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.635 ; -; -4.968 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 5.635 ; +; -8.675 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.842 ; +; -8.632 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.799 ; +; -8.529 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.696 ; +; -8.479 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.646 ; +; -8.426 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.593 ; +; -8.426 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.593 ; +; -8.383 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.550 ; +; -8.383 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.550 ; +; -8.280 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.447 ; +; -8.280 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.447 ; +; -8.234 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.401 ; +; -8.234 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.401 ; +; -8.230 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.397 ; +; -8.230 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.397 ; +; -8.191 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.358 ; +; -8.191 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.358 ; +; -8.088 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.255 ; +; -8.088 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.255 ; +; -8.038 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.205 ; +; -8.038 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.205 ; +; -8.014 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.181 ; +; -8.014 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.181 ; +; -8.014 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.181 ; +; -8.008 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.175 ; +; -7.996 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.163 ; +; -7.971 ; Bank[6] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.138 ; +; -7.971 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.138 ; +; -7.971 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.138 ; +; -7.965 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.132 ; +; -7.930 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.097 ; +; -7.868 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.035 ; +; -7.868 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.035 ; +; -7.868 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.035 ; +; -7.862 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.029 ; +; -7.818 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.985 ; +; -7.818 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.985 ; +; -7.818 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.985 ; +; -7.812 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.979 ; +; -7.747 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.914 ; +; -7.747 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.914 ; +; -7.681 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.848 ; +; -7.681 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.848 ; +; -7.555 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.722 ; +; -7.555 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.722 ; +; -7.512 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.679 ; +; -7.512 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.679 ; +; -7.489 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.656 ; +; -7.489 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.656 ; +; -7.481 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.648 ; +; -7.469 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.636 ; +; -7.469 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.636 ; +; -7.425 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.592 ; +; -7.366 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.533 ; +; -7.366 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.533 ; +; -7.335 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.502 ; +; -7.335 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.502 ; +; -7.335 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.502 ; +; -7.329 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.496 ; +; -7.316 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.483 ; +; -7.316 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.483 ; +; -7.269 ; Bank[5] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.436 ; +; -7.269 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.436 ; +; -7.269 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.436 ; +; -7.263 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.430 ; +; -7.232 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.399 ; +; -7.232 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.399 ; +; -7.176 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.343 ; +; -7.176 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.343 ; +; -7.040 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.207 ; +; -7.040 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.207 ; +; -6.984 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.151 ; +; -6.984 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.151 ; +; -6.833 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.000 ; +; -6.833 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.000 ; +; -6.820 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.987 ; +; -6.820 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.987 ; +; -6.820 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.987 ; +; -6.814 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.981 ; +; -6.767 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.934 ; +; -6.767 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.934 ; +; -6.764 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.931 ; +; -6.764 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.931 ; +; -6.764 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.931 ; +; -6.758 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.925 ; +; -6.641 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.808 ; +; -6.598 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.765 ; +; -6.495 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.662 ; +; -6.445 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.612 ; +; -6.318 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.485 ; +; -6.318 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.485 ; +; -6.262 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.429 ; +; -6.262 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.429 ; +; -5.962 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.129 ; +; -5.896 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.063 ; +; -5.868 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.535 ; +; -5.868 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.535 ; +; -5.676 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.343 ; +; -5.676 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.343 ; +; -5.456 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.123 ; +; -5.456 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.123 ; +--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'RCLK' ; ++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ +; -7.924 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.615 ; 5.476 ; +; -7.664 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.615 ; 5.216 ; +; -7.383 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.615 ; 4.935 ; +; -7.350 ; FS[16] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.017 ; +; -7.334 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.615 ; 4.886 ; +; -7.222 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.615 ; 4.774 ; +; -7.139 ; FS[17] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.806 ; +; -6.999 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.615 ; 4.551 ; +; -6.975 ; Cmdn8MEGEN ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.190 ; 3.952 ; +; -6.874 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.190 ; 3.851 ; +; -6.874 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.190 ; 3.851 ; +; -6.785 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.615 ; 4.337 ; +; -6.710 ; FWEr ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.615 ; 4.262 ; +; -6.637 ; UFMInitDone ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.304 ; +; -6.533 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.200 ; +; -6.454 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.121 ; +; -6.433 ; FS[12] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.100 ; +; -6.427 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.094 ; +; -6.426 ; S[0] ; RCKEEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.093 ; +; -6.420 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.190 ; 3.397 ; +; -6.418 ; CmdSubmitted ; LEDEN ; PHI2 ; RCLK ; 0.500 ; -3.190 ; 3.395 ; +; -6.411 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.078 ; +; -6.389 ; CBR ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.615 ; 3.941 ; +; -6.380 ; FS[4] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.047 ; +; -6.338 ; Ready ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.005 ; +; -6.322 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.989 ; +; -6.286 ; FS[10] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.953 ; +; -6.280 ; FS[10] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.947 ; +; -6.244 ; FWEr ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.615 ; 3.796 ; +; -6.243 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.910 ; +; -6.211 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.878 ; +; -6.180 ; S[0] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.847 ; +; -6.176 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.843 ; +; -6.169 ; S[0] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.836 ; +; -6.160 ; S[1] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.827 ; +; -6.107 ; IS[1] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.774 ; +; -6.105 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.772 ; +; -6.101 ; S[0] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.768 ; +; -6.099 ; FS[13] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.766 ; +; -6.080 ; FS[7] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.747 ; +; -6.071 ; FS[16] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.738 ; +; -6.060 ; FS[17] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.727 ; +; -6.025 ; FS[2] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.692 ; +; -6.018 ; IS[3] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.685 ; +; -5.980 ; InitReady ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.647 ; +; -5.969 ; InitReady ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.636 ; +; -5.964 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.190 ; 2.941 ; +; -5.958 ; FS[4] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.625 ; +; -5.955 ; IS[0] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.622 ; +; -5.952 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.619 ; +; -5.948 ; FS[1] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.615 ; +; -5.921 ; FS[4] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.588 ; +; -5.914 ; S[0] ; nRowColSel ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.581 ; +; -5.901 ; InitReady ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.568 ; +; -5.901 ; FS[16] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.568 ; +; -5.876 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.543 ; +; -5.860 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.527 ; +; -5.860 ; FS[17] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.527 ; +; -5.820 ; UFMInitDone ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.487 ; +; -5.814 ; FS[6] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.481 ; +; -5.784 ; CmdDRCLK ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.190 ; 2.761 ; +; -5.775 ; Ready ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.442 ; +; -5.774 ; CmdLEDEN ; LEDEN ; PHI2 ; RCLK ; 0.500 ; -3.190 ; 2.751 ; +; -5.751 ; RASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.418 ; +; -5.747 ; FS[11] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.414 ; +; -5.741 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.408 ; +; -5.741 ; FS[11] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.408 ; +; -5.741 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.408 ; +; -5.733 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; n8MEGEN ; DRCLK ; RCLK ; 1.000 ; 1.658 ; 8.058 ; +; -5.719 ; FS[12] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.386 ; +; -5.718 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; LEDEN ; DRCLK ; RCLK ; 1.000 ; 1.658 ; 8.043 ; +; -5.708 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.375 ; +; -5.677 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.344 ; +; -5.671 ; FS[3] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.338 ; +; -5.658 ; FS[7] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.325 ; +; -5.611 ; RCKE~reg0 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.278 ; +; -5.583 ; S[1] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.250 ; +; -5.579 ; Ready ; IS[2] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.246 ; +; -5.572 ; FS[10] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.239 ; +; -5.556 ; FS[16] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.223 ; +; -5.548 ; IS[2] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.215 ; +; -5.516 ; RASr2 ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.183 ; +; -5.484 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.151 ; +; -5.477 ; S[1] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.144 ; +; -5.475 ; FS[5] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.142 ; +; -5.466 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.133 ; +; -5.466 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.133 ; +; -5.462 ; FS[2] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.129 ; +; -5.432 ; RASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.099 ; +; -5.400 ; Ready ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.067 ; +; -5.394 ; FS[7] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.061 ; +; -5.391 ; FS[13] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.058 ; +; -5.385 ; FS[1] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.052 ; +; -5.358 ; UFMInitDone ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.025 ; +; -5.345 ; FS[17] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.012 ; +; -5.337 ; FS[16] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 6.004 ; +; -5.329 ; Ready ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.996 ; +; -5.291 ; FS[4] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.958 ; +; -5.291 ; FS[5] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.958 ; +; -5.239 ; UFMInitDone ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 5.906 ; ++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ + + +--------------------------------------------------------------------------------------------------------+ ; Setup: 'nCRAS' ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -1.149 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 5.928 ; 7.244 ; -; -0.869 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.580 ; 3.616 ; -; -0.755 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 2.580 ; 3.502 ; -; -0.754 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 2.580 ; 3.501 ; -; -0.753 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 2.580 ; 3.500 ; -; -0.749 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 2.580 ; 3.496 ; -; -0.649 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 5.928 ; 7.244 ; -; -0.222 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 2.580 ; 2.969 ; -; -0.221 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 2.580 ; 2.968 ; -; -0.211 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.580 ; 2.958 ; -; 0.085 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 2.580 ; 2.662 ; -; 0.809 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 2.580 ; 1.938 ; -; 0.812 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 2.580 ; 1.935 ; -; 0.813 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 2.580 ; 1.934 ; +; -0.977 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 5.963 ; 7.107 ; +; -0.477 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 5.963 ; 7.107 ; +; -0.363 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.615 ; 3.145 ; +; 0.202 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 2.615 ; 2.580 ; +; 0.203 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 2.615 ; 2.579 ; +; 0.211 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 2.615 ; 2.571 ; +; 0.236 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 2.615 ; 2.546 ; +; 0.237 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.615 ; 2.545 ; +; 0.238 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 2.615 ; 2.544 ; +; 0.240 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 2.615 ; 2.542 ; +; 0.250 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 2.615 ; 2.532 ; +; 0.262 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 2.615 ; 2.520 ; +; 0.541 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 2.615 ; 2.241 ; +; 0.549 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 2.615 ; 2.233 ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ @@ -434,8 +434,8 @@ No paths to report. +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -17.185 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -0.773 ; 2.042 ; -; -16.305 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -0.773 ; 2.922 ; +; -16.324 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.658 ; 2.018 ; +; -16.293 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.658 ; 2.049 ; ; 60.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ @@ -445,246 +445,246 @@ No paths to report. +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -16.694 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -1.732 ; 1.574 ; +; -16.276 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -2.195 ; 1.529 ; ; 60.000 ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -+--------------------------------------------------------------------------------------------------------+ -; Hold: 'nCRAS' ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -0.367 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 2.580 ; 1.934 ; -; -0.366 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 2.580 ; 1.935 ; -; -0.363 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 2.580 ; 1.938 ; -; 0.361 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 2.580 ; 2.662 ; -; 0.657 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.580 ; 2.958 ; -; 0.667 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 2.580 ; 2.968 ; -; 0.668 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 2.580 ; 2.969 ; -; 1.095 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 5.928 ; 7.244 ; -; 1.195 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 2.580 ; 3.496 ; -; 1.199 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 2.580 ; 3.500 ; -; 1.200 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 2.580 ; 3.501 ; -; 1.201 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 2.580 ; 3.502 ; -; 1.315 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.580 ; 3.616 ; -; 1.595 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 5.928 ; 7.244 ; -+--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ - - +-----------------------------------------------------------------------------------------------------------+ ; Hold: 'PHI2' ; +--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -; -0.107 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.314 ; 3.428 ; -; -0.098 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.314 ; 3.437 ; -; -0.058 ; LEDEN ; CmdLEDEN ; RCLK ; PHI2 ; -0.500 ; 3.314 ; 2.977 ; -; 0.023 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 3.314 ; 3.058 ; -; 0.130 ; LEDEN ; XOR8MEG ; RCLK ; PHI2 ; -0.500 ; 3.314 ; 3.165 ; -; 2.127 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.348 ; -; 2.238 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.459 ; -; 3.126 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.347 ; -; 3.128 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.349 ; -; 3.244 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 2.965 ; -; 3.264 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.485 ; -; 3.556 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.777 ; -; 3.692 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.913 ; -; 4.057 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.778 ; -; 4.488 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.209 ; -; 4.557 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.278 ; -; 4.825 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.546 ; -; 4.987 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.208 ; -; 4.987 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.208 ; -; 4.988 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.709 ; -; 5.067 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.788 ; -; 5.114 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.835 ; -; 5.256 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.977 ; -; 5.264 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.985 ; -; 5.343 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.064 ; -; 5.414 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.635 ; -; 5.414 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.635 ; -; 5.414 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.635 ; -; 5.482 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.203 ; -; 5.482 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.203 ; -; 5.495 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.216 ; -; 5.508 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.729 ; -; 5.545 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.266 ; -; 5.567 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.288 ; -; 5.695 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.416 ; -; 5.774 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.495 ; -; 5.835 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.556 ; -; 5.882 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.603 ; -; 5.909 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.630 ; -; 5.909 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.630 ; -; 5.909 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.630 ; -; 5.982 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.703 ; -; 5.982 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.703 ; -; 5.995 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.716 ; -; 6.003 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.724 ; -; 6.024 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.245 ; -; 6.024 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.245 ; -; 6.036 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.757 ; -; 6.124 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.845 ; -; 6.250 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.971 ; -; 6.250 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.971 ; -; 6.263 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.984 ; -; 6.274 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.995 ; -; 6.313 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.034 ; -; 6.353 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.074 ; -; 6.409 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.130 ; -; 6.409 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.130 ; -; 6.409 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.130 ; -; 6.467 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.188 ; -; 6.503 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.224 ; -; 6.519 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.240 ; -; 6.519 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.240 ; -; 6.539 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.260 ; -; 6.539 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.260 ; -; 6.552 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.273 ; -; 6.677 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.398 ; -; 6.677 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.398 ; -; 6.677 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.398 ; -; 6.689 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.410 ; -; 6.689 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.410 ; -; 6.702 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.423 ; -; 6.768 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.489 ; -; 6.768 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.489 ; -; 6.771 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.492 ; -; 6.781 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.502 ; -; 6.892 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.613 ; -; 6.966 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.687 ; -; 6.966 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.687 ; -; 6.966 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.687 ; -; 7.019 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.740 ; -; 7.019 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.740 ; -; 7.046 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.767 ; -; 7.060 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.781 ; -; 7.116 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.837 ; -; 7.116 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.837 ; -; 7.116 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.837 ; -; 7.195 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.916 ; -; 7.195 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.916 ; -; 7.195 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.916 ; -; 7.210 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.931 ; -; 7.287 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.008 ; -; 7.287 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.008 ; -; 7.289 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.010 ; -; 7.307 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.028 ; -; 7.307 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.028 ; -; 7.320 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.041 ; -; 7.461 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.182 ; -; 7.461 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.182 ; -; 7.474 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.195 ; -; 7.576 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.297 ; +; -1.015 ; LEDEN ; CmdLEDEN ; RCLK ; PHI2 ; -0.500 ; 3.190 ; 1.896 ; +; -0.752 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 3.190 ; 2.159 ; +; -0.131 ; LEDEN ; XOR8MEG ; RCLK ; PHI2 ; -0.500 ; 3.190 ; 2.780 ; +; 0.082 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.190 ; 3.493 ; +; 0.268 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.190 ; 3.679 ; +; 2.319 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.540 ; +; 2.357 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.578 ; +; 2.583 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.804 ; +; 3.233 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.454 ; +; 3.661 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.882 ; +; 3.882 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.103 ; +; 4.199 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.920 ; +; 4.310 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.531 ; +; 4.529 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.750 ; +; 5.312 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.033 ; +; 5.313 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.034 ; +; 5.368 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.089 ; +; 5.369 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.090 ; +; 5.817 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.538 ; +; 5.818 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.539 ; +; 5.837 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.558 ; +; 5.883 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.604 ; +; 5.884 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.605 ; +; 5.893 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.614 ; +; 5.902 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.123 ; +; 5.902 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.123 ; +; 5.902 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.123 ; +; 6.122 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.343 ; +; 6.122 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.343 ; +; 6.314 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.535 ; +; 6.314 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.535 ; +; 6.342 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.063 ; +; 6.366 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.087 ; +; 6.367 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.088 ; +; 6.408 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.129 ; +; 6.416 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.137 ; +; 6.417 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.138 ; +; 6.420 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.141 ; +; 6.476 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.197 ; +; 6.519 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.240 ; +; 6.520 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.241 ; +; 6.562 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.283 ; +; 6.563 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.284 ; +; 6.848 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.569 ; +; 6.891 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.612 ; +; 6.904 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.625 ; +; 6.925 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.646 ; +; 6.941 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.662 ; +; 6.991 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.712 ; +; 7.044 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.765 ; +; 7.087 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.808 ; +; 7.210 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.931 ; +; 7.210 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.931 ; +; 7.210 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.931 ; +; 7.266 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.987 ; +; 7.266 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.987 ; +; 7.266 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.987 ; +; 7.353 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.074 ; +; 7.419 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.140 ; +; 7.430 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.151 ; +; 7.430 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.151 ; +; 7.474 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.195 ; +; 7.486 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.207 ; +; 7.486 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.207 ; +; 7.524 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.245 ; +; 7.622 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.343 ; +; 7.622 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.343 ; +; 7.627 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.348 ; +; 7.670 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.391 ; +; 7.678 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.399 ; +; 7.678 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.399 ; +; 7.715 ; Bank[5] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.436 ; +; 7.715 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.436 ; +; 7.715 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.436 ; +; 7.781 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.502 ; +; 7.781 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.502 ; +; 7.781 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.502 ; +; 7.902 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.623 ; +; 7.935 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.656 ; +; 7.935 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.656 ; +; 7.952 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.673 ; +; 8.001 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.722 ; +; 8.001 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.722 ; +; 8.055 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.776 ; +; 8.098 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.819 ; +; 8.127 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.848 ; +; 8.127 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.848 ; +; 8.193 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.914 ; +; 8.193 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.914 ; +; 8.264 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.985 ; +; 8.264 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.985 ; +; 8.264 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.985 ; +; 8.314 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.035 ; +; 8.314 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.035 ; +; 8.314 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.035 ; +; 8.417 ; Bank[6] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.138 ; +; 8.417 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.138 ; +; 8.417 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.138 ; +; 8.460 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.181 ; +; 8.460 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.181 ; +--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ ++--------------------------------------------------------------------------------------------------------+ +; Hold: 'nCRAS' ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; -0.103 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 2.615 ; 2.233 ; +; -0.095 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 2.615 ; 2.241 ; +; 0.184 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 2.615 ; 2.520 ; +; 0.196 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 2.615 ; 2.532 ; +; 0.206 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 2.615 ; 2.542 ; +; 0.208 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 2.615 ; 2.544 ; +; 0.209 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.615 ; 2.545 ; +; 0.210 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 2.615 ; 2.546 ; +; 0.235 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 2.615 ; 2.571 ; +; 0.243 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 2.615 ; 2.579 ; +; 0.244 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 2.615 ; 2.580 ; +; 0.809 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.615 ; 3.145 ; +; 0.923 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 5.963 ; 7.107 ; +; 1.423 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 5.963 ; 7.107 ; ++--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ + + +---------------------------------------------------------------------------------------------------------+ ; Hold: 'RCLK' ; +-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ -; 1.163 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 3.348 ; 4.732 ; -; 1.221 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 3.348 ; 4.790 ; -; 1.404 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 3.348 ; 4.973 ; -; 1.649 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.870 ; -; 1.663 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 3.348 ; 4.732 ; -; 1.667 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.888 ; -; 1.721 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 3.348 ; 4.790 ; -; 1.732 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.953 ; -; 1.735 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.956 ; -; 1.822 ; CASr2 ; CASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.043 ; -; 1.904 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 3.348 ; 4.973 ; -; 1.926 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.147 ; -; 1.979 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.200 ; -; 1.986 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.207 ; -; 1.989 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.210 ; -; 1.995 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.216 ; +; 1.151 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 3.348 ; 4.720 ; +; 1.330 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 3.348 ; 4.899 ; +; 1.361 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 3.348 ; 4.930 ; +; 1.640 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.861 ; +; 1.651 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 3.348 ; 4.720 ; +; 1.659 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.880 ; +; 1.708 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.929 ; +; 1.711 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.932 ; +; 1.718 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 1.939 ; +; 1.830 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 3.348 ; 4.899 ; +; 1.861 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 3.348 ; 4.930 ; +; 1.973 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.194 ; +; 1.976 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.197 ; +; 1.993 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.214 ; +; 2.010 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.231 ; ; 2.108 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.329 ; ; 2.116 ; FS[9] ; FS[9] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.337 ; +; 2.117 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; ; 2.117 ; FS[16] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; -; 2.117 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; -; 2.126 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.347 ; -; 2.127 ; LEDEN ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.348 ; -; 2.127 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.348 ; -; 2.138 ; FS[0] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.359 ; -; 2.153 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.374 ; -; 2.154 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.375 ; -; 2.216 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.437 ; -; 2.221 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.442 ; -; 2.230 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.451 ; -; 2.230 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.451 ; +; 2.117 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.338 ; +; 2.126 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.347 ; +; 2.129 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.350 ; +; 2.135 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.356 ; +; 2.136 ; LEDEN ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.357 ; +; 2.143 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.364 ; +; 2.143 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.364 ; +; 2.144 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.365 ; +; 2.145 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.366 ; +; 2.146 ; n8MEGEN ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.367 ; +; 2.151 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.372 ; +; 2.190 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.411 ; +; 2.198 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.419 ; +; 2.221 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.442 ; +; 2.221 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.442 ; +; 2.228 ; IS[1] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.449 ; +; 2.230 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.451 ; +; 2.231 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; ; 2.231 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; -; 2.231 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.452 ; -; 2.233 ; UFMD ; UFMD ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.454 ; -; 2.240 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.461 ; -; 2.253 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.474 ; -; 2.274 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.495 ; -; 2.283 ; UFMReqErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.504 ; -; 2.284 ; UFMReqErase ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.505 ; -; 2.289 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.510 ; -; 2.296 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.517 ; -; 2.300 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.521 ; -; 2.306 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.527 ; -; 2.357 ; PHI2r2 ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.578 ; -; 2.431 ; RASr ; RASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.652 ; -; 2.435 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.656 ; -; 2.502 ; RCKEEN ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.723 ; -; 2.530 ; n8MEGEN ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.751 ; -; 2.621 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.842 ; -; 2.656 ; PHI2r3 ; DRDIn ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.877 ; -; 2.662 ; PHI2r2 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.883 ; -; 2.664 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.885 ; -; 2.688 ; PHI2r2 ; PHI2r3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.909 ; -; 2.704 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.925 ; -; 2.710 ; nRowColSel ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.931 ; -; 2.753 ; RASr2 ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.974 ; -; 2.759 ; RASr2 ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.980 ; +; 2.239 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.460 ; +; 2.239 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.460 ; +; 2.241 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.462 ; +; 2.250 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.471 ; +; 2.275 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.496 ; +; 2.341 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.562 ; +; 2.359 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.580 ; +; 2.421 ; CASr2 ; CASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.642 ; +; 2.517 ; PHI2r2 ; PHI2r3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.738 ; +; 2.547 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.768 ; +; 2.550 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.771 ; +; 2.573 ; RASr2 ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.794 ; +; 2.590 ; CASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.811 ; +; 2.654 ; PHI2r2 ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.875 ; +; 2.656 ; PHI2r2 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.877 ; +; 2.656 ; CASr3 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.877 ; +; 2.671 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.892 ; +; 2.673 ; UFMD ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.894 ; +; 2.681 ; RASr2 ; RASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.902 ; +; 2.795 ; IS[0] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.016 ; +; 2.828 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.049 ; +; 2.840 ; RASr2 ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.061 ; +; 2.904 ; IS[2] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.125 ; ; 2.940 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.161 ; ; 2.948 ; FS[9] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.169 ; ; 2.949 ; FS[16] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.170 ; -; 2.949 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.170 ; -; 2.970 ; FS[0] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.191 ; +; 2.958 ; FS[1] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.179 ; +; 2.967 ; RASr ; RASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.188 ; +; 2.969 ; UFMD ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.190 ; +; 2.975 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.196 ; +; 2.977 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.198 ; +; 2.990 ; InitReady ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.211 ; +; 3.028 ; Ready ; DRDIn ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.249 ; +; 3.046 ; UFMD ; UFMD ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.267 ; +; 3.048 ; RASr2 ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.269 ; ; 3.051 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.272 ; +; 3.052 ; CASr3 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.273 ; ; 3.059 ; FS[9] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.280 ; -; 3.060 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.281 ; -; 3.060 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.281 ; -; 3.065 ; PHI2r3 ; DRCLK ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.286 ; -; 3.066 ; RASr ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.287 ; -; 3.081 ; FS[0] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.302 ; -; 3.105 ; Ready ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.326 ; -; 3.161 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.382 ; -; 3.170 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; -; 3.170 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; +; 3.069 ; FS[1] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.290 ; +; 3.086 ; CASr ; CASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.307 ; +; 3.086 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.307 ; +; 3.088 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.309 ; +; 3.095 ; CASr3 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.316 ; +; 3.109 ; PHI2r3 ; DRDIn ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.330 ; +; 3.109 ; PHI2r3 ; DRCLK ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.330 ; +; 3.146 ; S[1] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.367 ; +; 3.161 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.382 ; +; 3.161 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.382 ; +; 3.170 ; FS[4] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; ; 3.170 ; FS[9] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.391 ; -; 3.171 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; -; 3.171 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; -; 3.171 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; -; 3.180 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.401 ; -; 3.198 ; UFMD ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.419 ; -; 3.245 ; RASr2 ; RASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.466 ; -; 3.252 ; IS[1] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.473 ; -; 3.257 ; RASr2 ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.478 ; -; 3.263 ; RASr2 ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.484 ; -; 3.268 ; RASr2 ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.489 ; -; 3.281 ; FS[5] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.502 ; -; 3.281 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.502 ; -; 3.281 ; FS[9] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.502 ; -; 3.282 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.503 ; -; 3.392 ; FS[5] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.613 ; -; 3.392 ; FS[14] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.613 ; -; 3.492 ; FS[13] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.713 ; -; 3.492 ; FS[13] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.713 ; -; 3.492 ; FS[3] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.713 ; -; 3.492 ; FS[3] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.713 ; -; 3.492 ; FS[3] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.713 ; -; 3.492 ; FS[3] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.713 ; -; 3.492 ; FS[13] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.713 ; +; 3.171 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; +; 3.179 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ; +; 3.179 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.400 ; +; 3.181 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.402 ; +; 3.197 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.418 ; +; 3.207 ; RASr2 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.428 ; +; 3.210 ; FS[5] ; DRShift ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.431 ; +; 3.222 ; RASr ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.443 ; +; 3.233 ; RCKEEN ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.454 ; +; 3.265 ; Ready ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.486 ; +; 3.269 ; RCKEEN ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.490 ; +; 3.281 ; FS[4] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.502 ; +-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ @@ -752,7 +752,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 31 ; 31 ; -; Unconstrained Input Port Paths ; 255 ; 255 ; +; Unconstrained Input Port Paths ; 249 ; 249 ; ; Unconstrained Output Ports ; 38 ; 38 ; ; Unconstrained Output Port Paths ; 78 ; 78 ; +---------------------------------+-------+------+ @@ -948,7 +948,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sun Aug 13 04:50:43 2023 + Info: Processing started: Sun Aug 13 06:36:34 2023 Info: Command: quartus_sta RAM2GS-MAXII -c RAM2GS Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -974,17 +974,17 @@ Info (332146): Worst-case setup slack is -99.000 Info (332119): ========= =================== ===================== Info (332119): -99.000 -99.000 ARCLK Info (332119): -99.000 -99.000 DRCLK - Info (332119): -8.541 -253.391 RCLK - Info (332119): -8.503 -92.361 PHI2 - Info (332119): -1.149 -5.683 nCRAS -Info (332146): Worst-case hold slack is -17.185 + Info (332119): -8.675 -99.463 PHI2 + Info (332119): -7.924 -256.499 RCLK + Info (332119): -0.977 -1.340 nCRAS +Info (332146): Worst-case hold slack is -16.324 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -17.185 -17.185 DRCLK - Info (332119): -16.694 -16.694 ARCLK - Info (332119): -0.367 -1.096 nCRAS - Info (332119): -0.107 -0.165 PHI2 - Info (332119): 1.163 0.000 RCLK + Info (332119): -16.324 -16.324 DRCLK + Info (332119): -16.276 -16.276 ARCLK + Info (332119): -1.015 -1.898 PHI2 + Info (332119): -0.103 -0.198 nCRAS + Info (332119): 1.151 0.000 RCLK Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -29.500 @@ -1000,8 +1000,8 @@ Info (332001): The selected device family is not supported by the report_metasta Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings - Info: Peak virtual memory: 4677 megabytes - Info: Processing ended: Sun Aug 13 04:50:44 2023 + Info: Peak virtual memory: 4676 megabytes + Info: Processing ended: Sun Aug 13 06:36:35 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXII/output_files/RAM2GS.sta.summary b/CPLD/MAXII/output_files/RAM2GS.sta.summary index 92e1319..1e43c2a 100644 --- a/CPLD/MAXII/output_files/RAM2GS.sta.summary +++ b/CPLD/MAXII/output_files/RAM2GS.sta.summary @@ -10,36 +10,36 @@ Type : Setup 'DRCLK' Slack : -99.000 TNS : -99.000 -Type : Setup 'RCLK' -Slack : -8.541 -TNS : -253.391 - Type : Setup 'PHI2' -Slack : -8.503 -TNS : -92.361 +Slack : -8.675 +TNS : -99.463 + +Type : Setup 'RCLK' +Slack : -7.924 +TNS : -256.499 Type : Setup 'nCRAS' -Slack : -1.149 -TNS : -5.683 +Slack : -0.977 +TNS : -1.340 Type : Hold 'DRCLK' -Slack : -17.185 -TNS : -17.185 +Slack : -16.324 +TNS : -16.324 Type : Hold 'ARCLK' -Slack : -16.694 -TNS : -16.694 - -Type : Hold 'nCRAS' -Slack : -0.367 -TNS : -1.096 +Slack : -16.276 +TNS : -16.276 Type : Hold 'PHI2' -Slack : -0.107 -TNS : -0.165 +Slack : -1.015 +TNS : -1.898 + +Type : Hold 'nCRAS' +Slack : -0.103 +TNS : -0.198 Type : Hold 'RCLK' -Slack : 1.163 +Slack : 1.151 TNS : 0.000 Type : Minimum Pulse Width 'ARCLK' diff --git a/CPLD/MAXV/RAM2GS.qws b/CPLD/MAXV/RAM2GS.qws deleted file mode 100644 index acccbd5..0000000 Binary files a/CPLD/MAXV/RAM2GS.qws and /dev/null differ diff --git a/CPLD/MAXV/db/RAM2GS.(0).cnf.cdb b/CPLD/MAXV/db/RAM2GS.(0).cnf.cdb index 44fdc4e..98161d8 100644 Binary files a/CPLD/MAXV/db/RAM2GS.(0).cnf.cdb and b/CPLD/MAXV/db/RAM2GS.(0).cnf.cdb differ diff --git a/CPLD/MAXV/db/RAM2GS.(0).cnf.hdb b/CPLD/MAXV/db/RAM2GS.(0).cnf.hdb index 4e17e94..a550f3d 100644 Binary files a/CPLD/MAXV/db/RAM2GS.(0).cnf.hdb and b/CPLD/MAXV/db/RAM2GS.(0).cnf.hdb differ diff --git a/CPLD/MAXV/db/RAM2GS.ace_cmp.cdb b/CPLD/MAXV/db/RAM2GS.ace_cmp.cdb new file mode 100644 index 0000000..ab4f43a Binary files /dev/null and b/CPLD/MAXV/db/RAM2GS.ace_cmp.cdb differ diff --git a/CPLD/MAXV/db/RAM2GS.ace_cmp.hdb b/CPLD/MAXV/db/RAM2GS.ace_cmp.hdb new file mode 100644 index 0000000..7204d15 Binary files /dev/null and b/CPLD/MAXV/db/RAM2GS.ace_cmp.hdb differ diff --git a/CPLD/MAXV/db/RAM2GS.acvq.rdb b/CPLD/MAXV/db/RAM2GS.acvq.rdb new file mode 100644 index 0000000..360d927 Binary files /dev/null and b/CPLD/MAXV/db/RAM2GS.acvq.rdb differ diff --git a/CPLD/MAXV/db/RAM2GS.asm.qmsg b/CPLD/MAXV/db/RAM2GS.asm.qmsg index 2e98dfa..00602f4 100644 --- a/CPLD/MAXV/db/RAM2GS.asm.qmsg +++ b/CPLD/MAXV/db/RAM2GS.asm.qmsg @@ -1,7 +1,7 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691916603004 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691916603004 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:50:02 2023 " "Processing started: Sun Aug 13 04:50:02 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691916603004 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691916603004 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691916603004 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691916603223 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691916603254 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691916603254 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916603363 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:03 2023 " "Processing ended: Sun Aug 13 04:50:03 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916603363 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916603363 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916603363 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691916603363 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691922990269 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922990269 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:36:30 2023 " "Processing started: Sun Aug 13 06:36:30 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922990269 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691922990269 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691922990269 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691922990566 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691922990582 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691922990582 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4663 " "Peak virtual memory: 4663 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922990707 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:36:30 2023 " "Processing ended: Sun Aug 13 06:36:30 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922990707 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922990707 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922990707 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691922990707 ""} diff --git a/CPLD/MAXV/db/RAM2GS.asm.rdb b/CPLD/MAXV/db/RAM2GS.asm.rdb index 2e6801e..d29d87a 100644 Binary files a/CPLD/MAXV/db/RAM2GS.asm.rdb and b/CPLD/MAXV/db/RAM2GS.asm.rdb differ diff --git a/CPLD/MAXV/db/RAM2GS.asm_labs.ddb b/CPLD/MAXV/db/RAM2GS.asm_labs.ddb index a2dd879..8c185b5 100644 Binary files a/CPLD/MAXV/db/RAM2GS.asm_labs.ddb and b/CPLD/MAXV/db/RAM2GS.asm_labs.ddb differ diff --git a/CPLD/MAXV/db/RAM2GS.cmp.cdb b/CPLD/MAXV/db/RAM2GS.cmp.cdb index 4458df8..ab4f43a 100644 Binary files a/CPLD/MAXV/db/RAM2GS.cmp.cdb and b/CPLD/MAXV/db/RAM2GS.cmp.cdb differ diff --git a/CPLD/MAXV/db/RAM2GS.cmp.hdb b/CPLD/MAXV/db/RAM2GS.cmp.hdb index 9e546d2..7204d15 100644 Binary files a/CPLD/MAXV/db/RAM2GS.cmp.hdb and b/CPLD/MAXV/db/RAM2GS.cmp.hdb differ diff --git a/CPLD/MAXV/db/RAM2GS.cmp.idb b/CPLD/MAXV/db/RAM2GS.cmp.idb index 26da0c3..775899a 100644 Binary files a/CPLD/MAXV/db/RAM2GS.cmp.idb and b/CPLD/MAXV/db/RAM2GS.cmp.idb differ diff --git a/CPLD/MAXV/db/RAM2GS.cmp.rdb b/CPLD/MAXV/db/RAM2GS.cmp.rdb index c8d8086..8a6e47c 100644 Binary files a/CPLD/MAXV/db/RAM2GS.cmp.rdb and b/CPLD/MAXV/db/RAM2GS.cmp.rdb differ diff --git a/CPLD/MAXV/db/RAM2GS.cmp0.ddb b/CPLD/MAXV/db/RAM2GS.cmp0.ddb index e3207b8..ac32e2b 100644 Binary files a/CPLD/MAXV/db/RAM2GS.cmp0.ddb and b/CPLD/MAXV/db/RAM2GS.cmp0.ddb differ diff --git a/CPLD/MAXV/db/RAM2GS.db_info b/CPLD/MAXV/db/RAM2GS.db_info index 872ee70..a180ee5 100644 --- a/CPLD/MAXV/db/RAM2GS.db_info +++ b/CPLD/MAXV/db/RAM2GS.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition Version_Index = 503488000 -Creation_Time = Sun Aug 13 04:37:09 2023 +Creation_Time = Sun Aug 13 05:45:43 2023 diff --git a/CPLD/MAXV/db/RAM2GS.fit.qmsg b/CPLD/MAXV/db/RAM2GS.fit.qmsg index cd3d8fc..c530c6c 100644 --- a/CPLD/MAXV/db/RAM2GS.fit.qmsg +++ b/CPLD/MAXV/db/RAM2GS.fit.qmsg @@ -1,45 +1,45 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691916600692 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691916600692 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C4 " "Selected device 5M240ZT100C4 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691916600707 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691916600739 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691916600739 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691916600770 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691916600770 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C4 " "Device 5M80ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916600894 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C4 " "Device 5M160ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916600894 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C4 " "Device 5M570ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691916600894 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691916600894 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691916600941 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691916600941 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691916600941 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691916600941 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916600941 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916600941 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916600941 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916600941 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916600941 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916600941 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916600941 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691916600941 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691916600941 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691916600941 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691916600941 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691916600941 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916600957 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916600957 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916600957 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 336 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691916600957 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916600957 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916600957 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916600957 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691916600957 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916600957 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916600957 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691916600957 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691916600957 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691916600957 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691916600957 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691916600957 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691916600973 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691916600988 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691916600988 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691916601004 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691916601004 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916601019 ""} -{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691916601035 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691916601113 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916601223 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691916601223 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691916601567 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916601567 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691916601582 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691916601707 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691916601707 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691916601832 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691916601832 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916601832 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.22 " "Total time spent on timing analysis during the Fitter is 0.22 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691916601848 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691916601848 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691916601879 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691916601910 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916601941 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:01 2023 " "Processing ended: Sun Aug 13 04:50:01 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916601941 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916601941 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916601941 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691916601941 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691922987941 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691922987941 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C4 " "Selected device 5M240ZT100C4 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691922987941 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691922987988 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691922987988 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691922988019 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691922988019 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C4 " "Device 5M80ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922988145 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C4 " "Device 5M160ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922988145 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C4 " "Device 5M570ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922988145 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691922988145 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691922988191 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691922988191 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691922988191 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691922988191 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922988191 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922988191 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922988191 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922988191 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922988191 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922988191 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922988191 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922988191 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691922988191 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691922988191 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691922988191 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691922988191 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922988207 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922988207 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922988207 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 336 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691922988207 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922988207 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922988207 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922988207 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691922988207 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922988207 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922988207 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922988207 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922988207 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691922988207 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691922988207 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691922988207 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691922988223 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691922988238 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691922988238 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691922988238 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691922988238 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922988269 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691922988269 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691922988363 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922988457 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691922988457 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691922988847 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922988847 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691922988863 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "18 " "Router estimated average interconnect usage is 18% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691922988988 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691922988988 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691922989160 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691922989160 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922989160 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.26 " "Total time spent on timing analysis during the Fitter is 0.26 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691922989176 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922989191 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691922989223 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691922989254 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5346 " "Peak virtual memory: 5346 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922989270 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:36:29 2023 " "Processing ended: Sun Aug 13 06:36:29 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922989270 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922989270 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922989270 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691922989270 ""} diff --git a/CPLD/MAXV/db/RAM2GS.hier_info b/CPLD/MAXV/db/RAM2GS.hier_info index 01107ce..f663955 100644 --- a/CPLD/MAXV/db/RAM2GS.hier_info +++ b/CPLD/MAXV/db/RAM2GS.hier_info @@ -88,25 +88,25 @@ Din[2] => WRD[2].DATAIN Din[2] => Bank[2].DATAIN Din[2] => Equal14.IN6 Din[2] => Equal15.IN3 -Din[2] => Equal17.IN1 +Din[2] => Equal16.IN1 Din[3] => CmdUFMErase.DATAB Din[3] => WRD[3].DATAIN Din[3] => Bank[3].DATAIN Din[3] => Equal14.IN5 Din[3] => Equal15.IN2 -Din[3] => Equal17.IN0 +Din[3] => Equal16.IN0 Din[4] => WRD[4].DATAIN Din[4] => Bank[4].DATAIN Din[4] => Equal14.IN4 Din[4] => Equal15.IN6 -Din[4] => Equal16.IN3 +Din[4] => Equal17.IN3 Din[4] => Equal18.IN0 Din[4] => Equal19.IN3 Din[5] => WRD[5].DATAIN Din[5] => Bank[5].DATAIN Din[5] => Equal14.IN3 Din[5] => Equal15.IN1 -Din[5] => Equal16.IN2 +Din[5] => Equal17.IN2 Din[5] => Equal18.IN3 Din[5] => Equal19.IN0 Din[6] => RA11.IN1 @@ -114,14 +114,14 @@ Din[6] => WRD[6].DATAIN Din[6] => Bank[6].DATAIN Din[6] => Equal14.IN1 Din[6] => Equal15.IN5 -Din[6] => Equal16.IN1 +Din[6] => Equal17.IN1 Din[6] => Equal18.IN2 Din[6] => Equal19.IN2 Din[7] => WRD[7].DATAIN Din[7] => Bank[7].DATAIN Din[7] => Equal14.IN0 Din[7] => Equal15.IN0 -Din[7] => Equal16.IN0 +Din[7] => Equal17.IN0 Din[7] => Equal18.IN1 Din[7] => Equal19.IN1 Dout[0] << Dout[0].DB_MAX_OUTPUT_PORT_TYPE diff --git a/CPLD/MAXV/db/RAM2GS.hif b/CPLD/MAXV/db/RAM2GS.hif index 53614c0..75bab64 100644 Binary files a/CPLD/MAXV/db/RAM2GS.hif and b/CPLD/MAXV/db/RAM2GS.hif differ diff --git a/CPLD/MAXV/db/RAM2GS.map.cdb b/CPLD/MAXV/db/RAM2GS.map.cdb index 6db110c..cd8a6ed 100644 Binary files a/CPLD/MAXV/db/RAM2GS.map.cdb and b/CPLD/MAXV/db/RAM2GS.map.cdb differ diff --git a/CPLD/MAXV/db/RAM2GS.map.hdb b/CPLD/MAXV/db/RAM2GS.map.hdb index c07bd52..2c01cc1 100644 Binary files a/CPLD/MAXV/db/RAM2GS.map.hdb and b/CPLD/MAXV/db/RAM2GS.map.hdb differ diff --git a/CPLD/MAXV/db/RAM2GS.map.qmsg b/CPLD/MAXV/db/RAM2GS.map.qmsg index 26e0d5b..dab2808 100644 --- a/CPLD/MAXV/db/RAM2GS.map.qmsg +++ b/CPLD/MAXV/db/RAM2GS.map.qmsg @@ -1,27 +1,27 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691916590238 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691916590238 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:49:50 2023 " "Processing started: Sun Aug 13 04:49:50 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691916590238 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916590238 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916590238 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691916590566 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691916590566 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691916598863 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691916598863 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916598863 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691916598894 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691916598894 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691916598894 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691916598894 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916598894 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691916598926 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691916598926 "|RAM2GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691916598926 "|RAM2GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691916598926 "|RAM2GS"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691916598941 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" { } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691916598941 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691916599207 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691916599238 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691916599238 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691916599238 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691916599238 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691916599238 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691916599238 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916599285 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4702 " "Peak virtual memory: 4702 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916599301 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:49:59 2023 " "Processing ended: Sun Aug 13 04:49:59 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916599301 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916599301 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916599301 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691916599301 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691922975519 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922975519 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:36:15 2023 " "Processing started: Sun Aug 13 06:36:15 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922975519 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922975519 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922975519 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691922975832 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691922975832 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691922985816 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691922985816 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922985816 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691922985848 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691922985848 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691922985848 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691922985848 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922985848 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691922985863 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691922985879 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691922985879 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691922985879 "|RAM2GS"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691922985879 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" { } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691922985879 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922986176 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922986176 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922986176 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922986176 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922986176 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922986176 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922986176 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922986176 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691922986238 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691922986238 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691922986238 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691922986238 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691922986238 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691922986238 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922986301 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4702 " "Peak virtual memory: 4702 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922986316 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:36:26 2023 " "Processing ended: Sun Aug 13 06:36:26 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922986316 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922986316 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922986316 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922986316 ""} diff --git a/CPLD/MAXV/db/RAM2GS.map.rdb b/CPLD/MAXV/db/RAM2GS.map.rdb index 45e0cf8..5123f7d 100644 Binary files a/CPLD/MAXV/db/RAM2GS.map.rdb and b/CPLD/MAXV/db/RAM2GS.map.rdb differ diff --git a/CPLD/MAXV/db/RAM2GS.pre_map.hdb b/CPLD/MAXV/db/RAM2GS.pre_map.hdb index 92d14d5..ed5f656 100644 Binary files a/CPLD/MAXV/db/RAM2GS.pre_map.hdb and b/CPLD/MAXV/db/RAM2GS.pre_map.hdb differ diff --git a/CPLD/MAXV/db/RAM2GS.routing.rdb b/CPLD/MAXV/db/RAM2GS.routing.rdb index 83c925a..afad910 100644 Binary files a/CPLD/MAXV/db/RAM2GS.routing.rdb and b/CPLD/MAXV/db/RAM2GS.routing.rdb differ diff --git a/CPLD/MAXV/db/RAM2GS.rtlv.hdb b/CPLD/MAXV/db/RAM2GS.rtlv.hdb index 7cb9e29..4c03481 100644 Binary files a/CPLD/MAXV/db/RAM2GS.rtlv.hdb and b/CPLD/MAXV/db/RAM2GS.rtlv.hdb differ diff --git a/CPLD/MAXV/db/RAM2GS.rtlv_sg.cdb b/CPLD/MAXV/db/RAM2GS.rtlv_sg.cdb index c8163b5..e67f164 100644 Binary files a/CPLD/MAXV/db/RAM2GS.rtlv_sg.cdb and b/CPLD/MAXV/db/RAM2GS.rtlv_sg.cdb differ diff --git a/CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb b/CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb index 0252354..72e7392 100644 Binary files a/CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb and b/CPLD/MAXV/db/RAM2GS.rtlv_sg_swap.cdb differ diff --git a/CPLD/MAXV/db/RAM2GS.sta.qmsg b/CPLD/MAXV/db/RAM2GS.sta.qmsg index 54a205f..f00734f 100644 --- a/CPLD/MAXV/db/RAM2GS.sta.qmsg +++ b/CPLD/MAXV/db/RAM2GS.sta.qmsg @@ -1,25 +1,25 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691916604691 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691916604691 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:50:04 2023 " "Processing started: Sun Aug 13 04:50:04 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691916604691 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691916604691 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691916604691 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691916604801 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691916604942 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691916604942 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916604988 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916604988 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691916605035 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691916605223 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691916605254 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916605254 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916605254 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916605254 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916605254 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916605254 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916605254 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691916605254 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691916605254 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691916605254 ""} -{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691916605269 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691916605269 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.164 -118.093 PHI2 " " -10.164 -118.093 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.387 -288.937 RCLK " " -9.387 -288.937 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.870 -7.136 nCRAS " " -2.870 -7.136 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916605269 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.578 " "Worst-case hold slack is -16.578" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.578 -16.578 DRCLK " " -16.578 -16.578 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.552 -16.552 ARCLK " " -16.552 -16.552 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.611 -0.993 PHI2 " " -0.611 -0.993 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.443 0.000 nCRAS " " 0.443 0.000 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.178 0.000 RCLK " " 1.178 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605269 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916605269 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691916605285 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691916605285 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691916605285 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691916605285 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691916605332 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691916605363 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691916605363 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691916605410 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:50:05 2023 " "Processing ended: Sun Aug 13 04:50:05 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691916605410 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691916605410 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691916605410 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691916605410 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691922992019 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922992019 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:36:31 2023 " "Processing started: Sun Aug 13 06:36:31 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922992019 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691922992019 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691922992019 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691922992129 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691922992238 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691922992238 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922992285 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922992285 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691922992316 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691922992504 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691922992535 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922992535 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922992535 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922992535 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922992535 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922992535 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922992535 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922992535 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691922992535 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691922992535 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691922992551 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691922992551 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.765 -121.853 PHI2 " " -10.765 -121.853 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.110 -282.559 RCLK " " -9.110 -282.559 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.305 -17.117 nCRAS " " -2.305 -17.117 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992551 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922992551 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.599 " "Worst-case hold slack is -16.599" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.599 -16.599 DRCLK " " -16.599 -16.599 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.916 -15.916 ARCLK " " -15.916 -15.916 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.387 -0.479 PHI2 " " -0.387 -0.479 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.189 0.000 RCLK " " 1.189 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.744 0.000 nCRAS " " 1.744 0.000 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992551 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922992551 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691922992551 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691922992551 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922992566 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922992566 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691922992660 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691922992676 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691922992676 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922992785 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:36:32 2023 " "Processing ended: Sun Aug 13 06:36:32 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922992785 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922992785 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922992785 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691922992785 ""} diff --git a/CPLD/MAXV/db/RAM2GS.sta.rdb b/CPLD/MAXV/db/RAM2GS.sta.rdb index e72ed65..bc6f224 100644 Binary files a/CPLD/MAXV/db/RAM2GS.sta.rdb and b/CPLD/MAXV/db/RAM2GS.sta.rdb differ diff --git a/CPLD/MAXV/db/RAM2GS.sta_cmp.4_slow.tdb b/CPLD/MAXV/db/RAM2GS.sta_cmp.4_slow.tdb index 0c1d05b..1e167a5 100644 Binary files a/CPLD/MAXV/db/RAM2GS.sta_cmp.4_slow.tdb and b/CPLD/MAXV/db/RAM2GS.sta_cmp.4_slow.tdb differ diff --git a/CPLD/MAXV/db/RAM2GS.tmw_info b/CPLD/MAXV/db/RAM2GS.tmw_info index 5f02de9..305a7eb 100644 --- a/CPLD/MAXV/db/RAM2GS.tmw_info +++ b/CPLD/MAXV/db/RAM2GS.tmw_info @@ -1,6 +1,6 @@ -start_full_compilation:s:00:00:17 -start_analysis_synthesis:s:00:00:10-start_full_compilation +start_full_compilation:s:00:00:18 +start_analysis_synthesis:s:00:00:11-start_full_compilation start_analysis_elaboration:s-start_full_compilation start_fitter:s:00:00:03-start_full_compilation -start_assembler:s:00:00:01-start_full_compilation -start_timing_analyzer:s:00:00:03-start_full_compilation +start_assembler:s:00:00:02-start_full_compilation +start_timing_analyzer:s:00:00:02-start_full_compilation diff --git a/CPLD/MAXV/db/RAM2GS.vpr.ammdb b/CPLD/MAXV/db/RAM2GS.vpr.ammdb index 04358f8..3ca426c 100644 Binary files a/CPLD/MAXV/db/RAM2GS.vpr.ammdb and b/CPLD/MAXV/db/RAM2GS.vpr.ammdb differ diff --git a/CPLD/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg b/CPLD/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg index 94d78d8..9b8d1d4 100644 --- a/CPLD/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg +++ b/CPLD/MAXV/db/prev_cmp_RAM2GS-MAXV.qmsg @@ -1,112 +1,112 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691915089171 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691915089172 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:24:49 2023 " "Processing started: Sun Aug 13 04:24:49 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691915089172 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915089172 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915089172 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691915089467 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691915089467 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691915097582 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691915097582 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915097582 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691915097613 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691915097613 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691915097613 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691915097613 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915097613 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691915097629 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691915097629 "|RAM2GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691915097629 "|RAM2GS"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691915097629 "|RAM2GS"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691915097644 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" { } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691915097644 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915097894 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915097894 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915097894 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915097894 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915097894 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915097894 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915097894 ""} -{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691915097894 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691915097942 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691915097942 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691915097942 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691915097942 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691915097942 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691915097942 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915097988 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4703 " "Peak virtual memory: 4703 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691915098004 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:24:58 2023 " "Processing ended: Sun Aug 13 04:24:58 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691915098004 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691915098004 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691915098004 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691915098004 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1691915099207 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691915099207 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:24:58 2023 " "Processing started: Sun Aug 13 04:24:58 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691915099207 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1691915099207 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1691915099207 ""} -{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1691915099301 ""} -{ "Info" "0" "" "Project = RAM2GS-MAXV" { } { } 0 0 "Project = RAM2GS-MAXV" 0 0 "Fitter" 0 0 1691915099301 ""} -{ "Info" "0" "" "Revision = RAM2GS" { } { } 0 0 "Revision = RAM2GS" 0 0 "Fitter" 0 0 1691915099301 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691915099379 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691915099379 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C4 " "Selected device 5M240ZT100C4 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691915099379 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691915099426 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691915099426 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691915099441 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691915099457 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C4 " "Device 5M80ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691915099551 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C4 " "Device 5M160ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691915099551 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C4 " "Device 5M570ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691915099551 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691915099551 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691915099598 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691915099598 ""} -{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691915099598 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691915099598 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915099598 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915099598 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915099598 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915099598 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915099598 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915099598 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915099598 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691915099598 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691915099598 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691915099598 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691915099598 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691915099598 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691915099613 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915099613 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691915099613 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 336 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691915099613 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915099613 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915099613 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691915099613 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691915099613 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915099613 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915099613 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691915099613 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691915099613 ""} -{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691915099613 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691915099613 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691915099613 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691915099629 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691915099644 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691915099644 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691915099644 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691915099644 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915099676 ""} -{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691915099676 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691915099754 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915099863 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691915099863 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691915100223 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915100223 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691915100238 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691915100348 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691915100348 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691915100488 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691915100488 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915100504 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.23 " "Total time spent on timing analysis during the Fitter is 0.23 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691915100504 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691915100504 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691915100535 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691915100566 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691915100598 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:25:00 2023 " "Processing ended: Sun Aug 13 04:25:00 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691915100598 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691915100598 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691915100598 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691915100598 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1691915101629 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691915101629 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:25:01 2023 " "Processing started: Sun Aug 13 04:25:01 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691915101629 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691915101629 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691915101629 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691915101879 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691915101894 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691915101894 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691915102004 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:25:02 2023 " "Processing ended: Sun Aug 13 04:25:02 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691915102004 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691915102004 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691915102004 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691915102004 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1691915102613 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1691915103146 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691915103146 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 04:25:02 2023 " "Processing started: Sun Aug 13 04:25:02 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691915103146 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691915103146 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691915103146 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691915103254 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691915103379 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691915103379 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915103410 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915103410 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691915103457 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691915103629 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691915103660 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915103660 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915103660 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915103660 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915103660 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915103660 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915103660 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691915103660 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691915103660 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691915103660 ""} -{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691915103676 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691915103676 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.164 -118.093 PHI2 " " -10.164 -118.093 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.387 -288.937 RCLK " " -9.387 -288.937 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.870 -7.136 nCRAS " " -2.870 -7.136 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915103676 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.578 " "Worst-case hold slack is -16.578" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.578 -16.578 DRCLK " " -16.578 -16.578 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.552 -16.552 ARCLK " " -16.552 -16.552 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.611 -0.993 PHI2 " " -0.611 -0.993 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.443 0.000 nCRAS " " 0.443 0.000 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.178 0.000 RCLK " " 1.178 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103676 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915103676 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691915103676 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691915103691 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691915103691 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691915103691 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691915103754 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691915103785 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691915103785 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691915103832 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 04:25:03 2023 " "Processing ended: Sun Aug 13 04:25:03 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691915103832 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691915103832 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691915103832 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691915103832 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 20 s " "Quartus Prime Full Compilation was successful. 0 errors, 20 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691915104519 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1691922464598 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922464598 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:27:44 2023 " "Processing started: Sun Aug 13 06:27:44 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922464598 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922464598 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922464598 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1691922464941 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1691922464941 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2GS-MAX.v(59) " "Verilog HDL warning at RAM2GS-MAX.v(59): extended using \"x\" or \"z\"" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1691922474910 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/onedrive/documents/github/ram2gs/cpld/ram2gs-max.v 1 1 " "Found 1 design units, including 1 entities, in source file /onedrive/documents/github/ram2gs/cpld/ram2gs-max.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2GS " "Found entity 1: RAM2GS" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691922474910 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922474910 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(73) " "Verilog HDL Declaration warning at UFM.v(73): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 73 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691922474941 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(173) " "Verilog HDL Declaration warning at UFM.v(173): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 173 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Analysis & Synthesis" 0 -1 1691922474941 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_38r " "Found entity 1: UFM_altufm_none_38r" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691922474941 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 150 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1691922474941 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922474941 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2GS " "Elaborating entity \"RAM2GS\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1691922474972 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 RAM2GS-MAX.v(162) " "Verilog HDL assignment warning at RAM2GS-MAX.v(162): truncated value with size 32 to match size of target (2)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 162 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691922474972 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 RAM2GS-MAX.v(167) " "Verilog HDL assignment warning at RAM2GS-MAX.v(167): truncated value with size 32 to match size of target (18)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691922474972 "|RAM2GS"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2GS-MAX.v(294) " "Verilog HDL assignment warning at RAM2GS-MAX.v(294): truncated value with size 32 to match size of target (4)" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 294 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1691922474972 "|RAM2GS"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "../RAM2GS-MAX.v" "UFM_inst" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 90 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691922475004 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_38r UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component " "Elaborating entity \"UFM_altufm_none_38r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_38r:UFM_altufm_none_38r_component\"" { } { { "UFM.v" "UFM_altufm_none_38r_component" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v" 201 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1691922475020 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[0\] RD\[0\] " "Output pin \"Dout\[0\]\" driven by bidirectional pin \"RD\[0\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922475316 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[1\] RD\[1\] " "Output pin \"Dout\[1\]\" driven by bidirectional pin \"RD\[1\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922475316 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[2\] RD\[2\] " "Output pin \"Dout\[2\]\" driven by bidirectional pin \"RD\[2\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922475316 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[3\] RD\[3\] " "Output pin \"Dout\[3\]\" driven by bidirectional pin \"RD\[3\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922475316 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[4\] RD\[4\] " "Output pin \"Dout\[4\]\" driven by bidirectional pin \"RD\[4\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922475316 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[5\] RD\[5\] " "Output pin \"Dout\[5\]\" driven by bidirectional pin \"RD\[5\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922475316 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[6\] RD\[6\] " "Output pin \"Dout\[6\]\" driven by bidirectional pin \"RD\[6\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922475316 ""} +{ "Warning" "WATM_BUILD_TRI_TO_BIDIR_AND_OUTPUT_PIN" "Dout\[7\] RD\[7\] " "Output pin \"Dout\[7\]\" driven by bidirectional pin \"RD\[7\]\" cannot be tri-stated" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 26 -1 0 } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 59 -1 0 } } } 0 14632 "Output pin \"%1!s!\" driven by bidirectional pin \"%2!s!\" cannot be tri-stated" 0 0 "Analysis & Synthesis" 0 -1 1691922475316 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "248 " "Implemented 248 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "25 " "Implemented 25 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1691922475363 ""} { "Info" "ICUT_CUT_TM_OPINS" "30 " "Implemented 30 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1691922475363 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1691922475363 ""} { "Info" "ICUT_CUT_TM_LCELLS" "184 " "Implemented 184 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1691922475363 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Design Software" 0 -1 1691922475363 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1691922475363 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922475441 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4701 " "Peak virtual memory: 4701 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922475457 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:27:55 2023 " "Processing ended: Sun Aug 13 06:27:55 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922475457 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922475457 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:26 " "Total CPU time (on all processors): 00:00:26" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922475457 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1691922475457 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1691922476926 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922476926 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:27:56 2023 " "Processing started: Sun Aug 13 06:27:56 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922476926 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1691922476926 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1691922476926 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1691922477097 ""} +{ "Info" "0" "" "Project = RAM2GS-MAXV" { } { } 0 0 "Project = RAM2GS-MAXV" 0 0 "Fitter" 0 0 1691922477097 ""} +{ "Info" "0" "" "Revision = RAM2GS" { } { } 0 0 "Revision = RAM2GS" 0 0 "Fitter" 0 0 1691922477097 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1691922477176 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1691922477176 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2GS 5M240ZT100C4 " "Selected device 5M240ZT100C4 for design \"RAM2GS\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1691922477176 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691922477223 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1691922477223 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1691922477254 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1691922477254 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C4 " "Device 5M80ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922477379 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C4 " "Device 5M160ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922477379 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C4 " "Device 5M570ZT100C4 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1691922477379 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1691922477379 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1691922477441 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1691922477441 ""} +{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" { } { } 0 332127 "Assuming a default timing requirement" 0 0 "Design Software" 0 -1 1691922477441 ""} } { } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1691922477441 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 6 clocks " "Found 6 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922477441 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922477441 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 ARCLK " " 1.000 ARCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922477441 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 DRCLK " " 1.000 DRCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922477441 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCCAS " " 1.000 nCCAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922477441 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 nCRAS " " 1.000 nCRAS" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922477441 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 PHI2 " " 1.000 PHI2" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922477441 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 1.000 RCLK " " 1.000 RCLK" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1691922477441 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1691922477441 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691922477441 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1691922477441 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691922477457 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "RCLK Global clock in PIN 12 " "Automatically promoted signal \"RCLK\" to use Global clock in PIN 12" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 40 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922477457 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "PHI2 Global clock " "Automatically promoted some destinations of signal \"PHI2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "PHI2r " "Destination \"PHI2r\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 13 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922477457 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922477457 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "PHI2 " "Pin \"PHI2\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { PHI2 } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PHI2" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 7 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 337 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691922477457 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCRAS Global clock " "Automatically promoted some destinations of signal \"nCRAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "LED~0 " "Destination \"LED~0\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 21 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922477457 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RASr " "Destination \"RASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 14 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922477457 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922477457 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCRAS " "Pin \"nCRAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCRAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCRAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 339 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691922477457 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "nCCAS Global clock " "Automatically promoted some destinations of signal \"nCCAS\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CBR " "Destination \"CBR\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 17 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922477457 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "comb~0 " "Destination \"comb~0\" may be non-global or may not use global clock" { } { } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922477457 ""} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CASr " "Destination \"CASr\" may be non-global or may not use global clock" { } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 15 -1 0 } } } 0 186217 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "Design Software" 0 -1 1691922477457 ""} } { { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } } 0 186216 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1691922477457 ""} +{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "nCCAS " "Pin \"nCCAS\" drives global clock, but is not placed in a dedicated clock pin position" { } { { "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/19.1/quartus/bin64/pin_planner.ppl" { nCCAS } } } { "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/intelfpga_lite/19.1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "nCCAS" } } } } { "../RAM2GS-MAX.v" "" { Text "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v" 10 -1 0 } } { "temporary_test_loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 0 { 0 ""} 0 338 14177 15141 0 0 "" 0 "" "" } } } } } 0 186228 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0 "Fitter" 0 -1 1691922477457 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1691922477457 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1691922477457 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1691922477473 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1691922477504 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1691922477504 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1691922477504 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1691922477504 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922477519 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1691922477535 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1691922477613 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922477722 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1691922477722 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1691922478141 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922478142 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1691922478161 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "18 " "Router estimated average interconnect usage is 18% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 12 { 0 ""} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1691922478301 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1691922478301 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1691922478473 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1691922478473 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922478473 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1691922478488 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1691922478504 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1691922478535 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg " "Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1691922478566 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5345 " "Peak virtual memory: 5345 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922478582 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:27:58 2023 " "Processing ended: Sun Aug 13 06:27:58 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922478582 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922478582 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922478582 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1691922478582 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1691922479691 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922479691 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:27:59 2023 " "Processing started: Sun Aug 13 06:27:59 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922479691 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1691922479691 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1691922479691 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1691922479957 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1691922479972 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1691922479988 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922480129 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:28:00 2023 " "Processing ended: Sun Aug 13 06:28:00 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922480129 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922480129 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922480129 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1691922480129 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1691922480754 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1691922481426 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition " "Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1691922481426 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 13 06:28:01 2023 " "Processing started: Sun Aug 13 06:28:01 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1691922481426 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1691922481426 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2GS-MAXV -c RAM2GS " "Command: quartus_sta RAM2GS-MAXV -c RAM2GS" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1691922481426 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1691922481551 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1691922481660 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1691922481660 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922481707 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922481707 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1691922481738 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1691922481910 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "RAM2GS.sdc " "Synopsys Design Constraints File file not found: 'RAM2GS.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1691922481988 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922481988 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCCAS nCCAS " "create_clock -period 1.000 -name nCCAS nCCAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922482004 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name nCRAS nCRAS " "create_clock -period 1.000 -name nCRAS nCRAS" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922482004 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name RCLK RCLK " "create_clock -period 1.000 -name RCLK RCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922482004 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name PHI2 PHI2 " "create_clock -period 1.000 -name PHI2 PHI2" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922482004 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name DRCLK DRCLK " "create_clock -period 1.000 -name DRCLK DRCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922482004 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name ARCLK ARCLK " "create_clock -period 1.000 -name ARCLK ARCLK" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1691922482004 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1691922482004 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1691922482004 ""} +{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." { } { } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Timing Analyzer" 0 0 1691922482019 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1691922482019 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -99.000 " "Worst-case setup slack is -99.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482019 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482019 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 ARCLK " " -99.000 -99.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482019 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -99.000 -99.000 DRCLK " " -99.000 -99.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482019 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -10.765 -121.853 PHI2 " " -10.765 -121.853 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482019 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -9.110 -282.559 RCLK " " -9.110 -282.559 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482019 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.305 -17.117 nCRAS " " -2.305 -17.117 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482019 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922482019 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold -16.599 " "Worst-case hold slack is -16.599" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -16.599 -16.599 DRCLK " " -16.599 -16.599 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -15.916 -15.916 ARCLK " " -15.916 -15.916 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.387 -0.479 PHI2 " " -0.387 -0.479 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.189 0.000 RCLK " " 1.189 0.000 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.744 0.000 nCRAS " " 1.744 0.000 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482035 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922482035 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691922482051 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1691922482066 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -29.500 " "Worst-case minimum pulse width slack is -29.500" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 ARCLK " " -29.500 -59.000 ARCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -29.500 -59.000 DRCLK " " -29.500 -59.000 DRCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 PHI2 " " -2.289 -2.289 PHI2 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 RCLK " " -2.289 -2.289 RCLK " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCCAS " " -2.289 -2.289 nCCAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.289 -2.289 nCRAS " " -2.289 -2.289 nCRAS " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1691922482066 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1691922482066 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Timing Analyzer" 0 -1 1691922482144 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691922482191 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1691922482191 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4676 " "Peak virtual memory: 4676 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1691922482254 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 13 06:28:02 2023 " "Processing ended: Sun Aug 13 06:28:02 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1691922482254 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1691922482254 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1691922482254 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691922482254 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 20 s " "Quartus Prime Full Compilation was successful. 0 errors, 20 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1691922482863 ""} diff --git a/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt b/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt index 8d9c648..47359b4 100644 Binary files a/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt and b/CPLD/MAXV/incremental_db/compiled_partitions/RAM2GS.root_partition.map.kpt differ diff --git a/CPLD/MAXV/output_files/RAM2GS.asm.rpt b/CPLD/MAXV/output_files/RAM2GS.asm.rpt index 820df5d..37465bc 100644 --- a/CPLD/MAXV/output_files/RAM2GS.asm.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.asm.rpt @@ -1,5 +1,5 @@ Assembler report for RAM2GS -Sun Aug 13 04:50:03 2023 +Sun Aug 13 06:36:30 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sun Aug 13 04:50:03 2023 ; +; Assembler Status ; Successful - Sun Aug 13 06:36:30 2023 ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; ; Family ; MAX V ; @@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula. +----------------+--------------------------------------------------------------------------------+ ; Option ; Setting ; +----------------+--------------------------------------------------------------------------------+ -; JTAG usercode ; 0x0017116A ; -; Checksum ; 0x001714EA ; +; JTAG usercode ; 0x00174FF3 ; +; Checksum ; 0x001751E3 ; +----------------+--------------------------------------------------------------------------------+ @@ -78,15 +78,15 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sun Aug 13 04:50:02 2023 + Info: Processing started: Sun Aug 13 06:36:30 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 4662 megabytes - Info: Processing ended: Sun Aug 13 04:50:03 2023 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:00 + Info: Peak virtual memory: 4663 megabytes + Info: Processing ended: Sun Aug 13 06:36:30 2023 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXV/output_files/RAM2GS.done b/CPLD/MAXV/output_files/RAM2GS.done index a58a91f..096fda1 100644 --- a/CPLD/MAXV/output_files/RAM2GS.done +++ b/CPLD/MAXV/output_files/RAM2GS.done @@ -1 +1 @@ -Sun Aug 13 04:50:06 2023 +Sun Aug 13 06:36:33 2023 diff --git a/CPLD/MAXV/output_files/RAM2GS.fit.rpt b/CPLD/MAXV/output_files/RAM2GS.fit.rpt index bcc8b06..675e69b 100644 --- a/CPLD/MAXV/output_files/RAM2GS.fit.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.fit.rpt @@ -1,5 +1,5 @@ Fitter report for RAM2GS -Sun Aug 13 04:50:01 2023 +Sun Aug 13 06:36:29 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -59,7 +59,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Fitter Summary ; +-----------------------+---------------------------------------------+ -; Fitter Status ; Successful - Sun Aug 13 04:50:01 2023 ; +; Fitter Status ; Successful - Sun Aug 13 06:36:29 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -135,8 +135,8 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 1.5% ; -; Processors 3-4 ; 1.4% ; +; Processor 2 ; 1.6% ; +; Processors 3-4 ; 1.3% ; +----------------------------+-------------+ @@ -157,9 +157,9 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; -- Combinational with a register ; 77 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 56 ; -; -- 3 input functions ; 48 ; -; -- 2 input functions ; 41 ; +; -- 4 input functions ; 57 ; +; -- 3 input functions ; 46 ; +; -- 2 input functions ; 42 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; @@ -168,11 +168,11 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; -- arithmetic mode ; 16 ; ; -- qfbk mode ; 7 ; ; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 23 ; +; -- synchronous clear/load mode ; 22 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; ; Total registers ; 98 / 240 ( 41 % ) ; -; Total LABs ; 23 / 24 ( 96 % ) ; +; Total LABs ; 24 / 24 ( 100 % ) ; ; Logic elements in carry chains ; 17 ; ; Virtual pins ; 0 ; ; I/O pins ; 63 / 79 ( 80 % ) ; @@ -186,8 +186,8 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; Global signals ; 4 ; ; -- Global clocks ; 4 / 4 ( 100 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 26.0% / 29.1% / 22.8% ; -; Peak interconnect usage (total/H/V) ; 26.0% / 29.1% / 22.8% ; +; Average interconnect usage (total/H/V) ; 23.8% / 26.3% / 21.1% ; +; Peak interconnect usage (total/H/V) ; 23.8% / 26.3% / 21.1% ; ; Maximum fan-out ; 55 ; ; Highest non-global fan-out ; 41 ; ; Total fan-out ; 661 ; @@ -204,20 +204,20 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; CROW[1] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[1] ; 36 ; 1 ; 4 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[6] ; 41 ; 1 ; 5 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[7] ; 40 ; 1 ; 5 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[1] ; 51 ; 1 ; 7 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[1] ; 51 ; 1 ; 7 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[2] ; 50 ; 1 ; 7 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[3] ; 71 ; 2 ; 8 ; 4 ; 3 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[4] ; 70 ; 2 ; 8 ; 4 ; 4 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[5] ; 69 ; 2 ; 8 ; 3 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[6] ; 72 ; 2 ; 8 ; 4 ; 2 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; MAin[7] ; 68 ; 2 ; 8 ; 3 ; 1 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[6] ; 72 ; 2 ; 8 ; 4 ; 2 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; MAin[7] ; 68 ; 2 ; 8 ; 3 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[8] ; 73 ; 2 ; 8 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; MAin[9] ; 74 ; 2 ; 8 ; 4 ; 0 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 22 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; @@ -242,11 +242,11 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; Dout[6] ; 34 ; 1 ; 3 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; Dout[7] ; 43 ; 1 ; 6 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; +; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; -; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; -; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; - ; - ; +; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; +; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; @@ -256,13 +256,13 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; RBA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; RDQMH ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; RDQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nRCS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -272,11 +272,11 @@ The pin-out file can be found in D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/o ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; -; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; +; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ; ; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; ; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; ; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; -; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; +; RD[5] ; 91 ; 2 ; 4 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; yes ; User ; 10 pF ; comb~0 ; - ; ; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; ; RD[7] ; 97 ; 2 ; 3 ; 5 ; 3 ; 1 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; comb~0 ; - ; +-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -494,8 +494,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Din[6] ; Input ; (1) ; ; nFWE ; Input ; (1) ; ; Din[0] ; Input ; (1) ; -; Din[1] ; Input ; (1) ; ; Din[7] ; Input ; (1) ; +; Din[1] ; Input ; (1) ; ; Din[4] ; Input ; (1) ; ; Din[2] ; Input ; (1) ; ; Din[3] ; Input ; (1) ; @@ -508,14 +508,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ -; CmdDRDIn~2 ; LC_X6_Y2_N0 ; 4 ; Clock enable ; no ; -- ; -- ; -; CmdLEDEN~1 ; LC_X6_Y2_N9 ; 3 ; Clock enable ; no ; -- ; -- ; +; CmdDRDIn~1 ; LC_X5_Y4_N7 ; 4 ; Clock enable ; no ; -- ; -- ; +; CmdLEDEN~1 ; LC_X5_Y4_N5 ; 3 ; Clock enable ; no ; -- ; -- ; ; DRDIn~1 ; LC_X5_Y1_N3 ; 2 ; Clock enable ; no ; -- ; -- ; ; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK1 ; ; RCLK ; PIN_12 ; 55 ; Clock ; yes ; Global Clock ; GCLK0 ; -; Ready ; LC_X3_Y3_N8 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ; -; always8~7 ; LC_X5_Y2_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -; comb~0 ; LC_X5_Y4_N1 ; 8 ; Output enable ; no ; -- ; -- ; +; Ready ; LC_X5_Y2_N1 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ; +; always8~6 ; LC_X6_Y4_N7 ; 3 ; Clock enable ; no ; -- ; -- ; +; comb~0 ; LC_X3_Y4_N9 ; 8 ; Output enable ; no ; -- ; -- ; ; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ; ; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK3 ; +------------+-------------+---------+-------------------------+--------+----------------------+------------------+ @@ -538,113 +538,111 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------+--------------------+ ; Routing Resource Type ; Usage ; +-----------------------+--------------------+ -; C4s ; 144 / 784 ( 18 % ) ; -; Direct links ; 51 / 888 ( 6 % ) ; +; C4s ; 145 / 784 ( 18 % ) ; +; Direct links ; 52 / 888 ( 6 % ) ; ; Global clocks ; 4 / 4 ( 100 % ) ; -; LAB clocks ; 17 / 32 ( 53 % ) ; -; LUT chains ; 18 / 216 ( 8 % ) ; -; Local interconnects ; 286 / 888 ( 32 % ) ; -; R4s ; 167 / 704 ( 24 % ) ; +; LAB clocks ; 15 / 32 ( 47 % ) ; +; LUT chains ; 17 / 216 ( 8 % ) ; +; Local interconnects ; 281 / 888 ( 32 % ) ; +; R4s ; 153 / 704 ( 22 % ) ; +-----------------------+--------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 7.61) ; Number of LABs (Total = 23) ; +; Number of Logic Elements (Average = 7.29) ; Number of LABs (Total = 24) ; +--------------------------------------------+------------------------------+ -; 1 ; 2 ; -; 2 ; 1 ; -; 3 ; 1 ; -; 4 ; 2 ; -; 5 ; 0 ; -; 6 ; 2 ; -; 7 ; 0 ; +; 1 ; 1 ; +; 2 ; 2 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 2 ; +; 6 ; 3 ; +; 7 ; 4 ; ; 8 ; 1 ; -; 9 ; 0 ; -; 10 ; 14 ; +; 9 ; 4 ; +; 10 ; 7 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.39) ; Number of LABs (Total = 23) ; +; LAB-wide Signals (Average = 1.50) ; Number of LABs (Total = 24) ; +------------------------------------+------------------------------+ -; 1 Clock ; 13 ; -; 1 Clock enable ; 4 ; -; 1 Sync. clear ; 4 ; -; 1 Sync. load ; 2 ; -; 2 Clocks ; 9 ; +; 1 Clock ; 17 ; +; 1 Clock enable ; 6 ; +; 1 Sync. clear ; 3 ; +; 1 Sync. load ; 3 ; +; 2 Clocks ; 7 ; +------------------------------------+------------------------------+ +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +---------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 7.87) ; Number of LABs (Total = 23) ; +; Number of Signals Sourced (Average = 7.54) ; Number of LABs (Total = 24) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 2 ; -; 2 ; 1 ; -; 3 ; 1 ; -; 4 ; 2 ; -; 5 ; 0 ; -; 6 ; 2 ; -; 7 ; 0 ; +; 1 ; 1 ; +; 2 ; 2 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 2 ; +; 6 ; 3 ; +; 7 ; 3 ; ; 8 ; 1 ; -; 9 ; 0 ; -; 10 ; 10 ; +; 9 ; 3 ; +; 10 ; 7 ; ; 11 ; 2 ; -; 12 ; 2 ; +---------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 5.57) ; Number of LABs (Total = 23) ; +; Number of Signals Sourced Out (Average = 4.96) ; Number of LABs (Total = 24) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 2 ; -; 2 ; 2 ; -; 3 ; 3 ; -; 4 ; 3 ; -; 5 ; 1 ; +; 1 ; 1 ; +; 2 ; 3 ; +; 3 ; 6 ; +; 4 ; 1 ; +; 5 ; 2 ; ; 6 ; 3 ; -; 7 ; 2 ; -; 8 ; 2 ; -; 9 ; 2 ; -; 10 ; 3 ; +; 7 ; 5 ; +; 8 ; 1 ; +; 9 ; 1 ; +; 10 ; 1 ; +-------------------------------------------------+------------------------------+ -+-----------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 10.52) ; Number of LABs (Total = 23) ; -+----------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 2 ; -; 3 ; 1 ; -; 4 ; 0 ; -; 5 ; 3 ; -; 6 ; 0 ; -; 7 ; 1 ; -; 8 ; 1 ; -; 9 ; 2 ; -; 10 ; 0 ; -; 11 ; 1 ; -; 12 ; 1 ; -; 13 ; 4 ; -; 14 ; 3 ; -; 15 ; 0 ; -; 16 ; 1 ; -; 17 ; 1 ; -; 18 ; 1 ; -; 19 ; 1 ; -+----------------------------------------------+------------------------------+ ++----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 9.42) ; Number of LABs (Total = 24) ; ++---------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 1 ; +; 3 ; 2 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 1 ; +; 7 ; 2 ; +; 8 ; 2 ; +; 9 ; 1 ; +; 10 ; 3 ; +; 11 ; 2 ; +; 12 ; 2 ; +; 13 ; 2 ; +; 14 ; 1 ; +; 15 ; 0 ; +; 16 ; 1 ; +; 17 ; 1 ; +; 18 ; 1 ; ++---------------------------------------------+------------------------------+ +-------------------------------------------------------------------------+ @@ -666,7 +664,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------+----------------------+-------------------+ ; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; +-----------------+----------------------+-------------------+ -; I/O ; nCRAS ; 2.2 ; +; I/O ; nCRAS ; 2.6 ; ; I/O ; RCLK ; 1.9 ; +-----------------+----------------------+-------------------+ Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. @@ -678,7 +676,7 @@ This will disable optimization of problematic paths and expose them for further +-----------------+----------------------+-------------------+ ; Source Register ; Destination Register ; Delay Added in ns ; +-----------------+----------------------+-------------------+ -; nCCAS ; CBR ; 2.167 ; +; nCCAS ; CBR ; 2.632 ; ; PHI2 ; PHI2r ; 0.871 ; ; nCRAS ; RASr ; 0.519 ; +-----------------+----------------------+-------------------+ @@ -731,7 +729,7 @@ Info (176234): Starting register packing Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 @@ -739,20 +737,20 @@ Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 20% of the available device resources - Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170195): Router estimated average interconnect usage is 18% of the available device resources + Info (170196): Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.22 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.26 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings - Info: Peak virtual memory: 5345 megabytes - Info: Processing ended: Sun Aug 13 04:50:01 2023 - Info: Elapsed time: 00:00:01 - Info: Total CPU time (on all processors): 00:00:02 + Info: Peak virtual memory: 5346 megabytes + Info: Processing ended: Sun Aug 13 06:36:29 2023 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:03 +----------------------------+ diff --git a/CPLD/MAXV/output_files/RAM2GS.fit.summary b/CPLD/MAXV/output_files/RAM2GS.fit.summary index 256cb2c..f3260e4 100644 --- a/CPLD/MAXV/output_files/RAM2GS.fit.summary +++ b/CPLD/MAXV/output_files/RAM2GS.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Sun Aug 13 04:50:01 2023 +Fitter Status : Successful - Sun Aug 13 06:36:29 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS diff --git a/CPLD/MAXV/output_files/RAM2GS.flow.rpt b/CPLD/MAXV/output_files/RAM2GS.flow.rpt index ecfb508..f7a0da0 100644 --- a/CPLD/MAXV/output_files/RAM2GS.flow.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.flow.rpt @@ -1,5 +1,5 @@ Flow report for RAM2GS -Sun Aug 13 04:50:05 2023 +Sun Aug 13 06:36:32 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+---------------------------------------------+ -; Flow Status ; Successful - Sun Aug 13 04:50:03 2023 ; +; Flow Status ; Successful - Sun Aug 13 06:36:30 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 08/13/2023 04:49:50 ; +; Start date & time ; 08/13/2023 06:36:15 ; ; Main task ; Compilation ; ; Revision Name ; RAM2GS ; +-------------------+---------------------+ @@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------+---------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------+---------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 207120313862967.169191659008924 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 207120313862967.169192297509168 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ; @@ -84,11 +84,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 4702 MB ; 00:00:22 ; -; Fitter ; 00:00:01 ; 1.0 ; 5345 MB ; 00:00:02 ; -; Assembler ; 00:00:01 ; 1.0 ; 4662 MB ; 00:00:00 ; +; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 4702 MB ; 00:00:26 ; +; Fitter ; 00:00:02 ; 1.0 ; 5346 MB ; 00:00:03 ; +; Assembler ; 00:00:00 ; 1.0 ; 4662 MB ; 00:00:00 ; ; Timing Analyzer ; 00:00:01 ; 1.0 ; 4676 MB ; 00:00:01 ; -; Total ; 00:00:12 ; -- ; -- ; 00:00:25 ; +; Total ; 00:00:14 ; -- ; -- ; 00:00:30 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/CPLD/MAXV/output_files/RAM2GS.map.rpt b/CPLD/MAXV/output_files/RAM2GS.map.rpt index 3f94942..1b86fa9 100644 --- a/CPLD/MAXV/output_files/RAM2GS.map.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for RAM2GS -Sun Aug 13 04:49:59 2023 +Sun Aug 13 06:36:26 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sun Aug 13 04:49:59 2023 ; +; Analysis & Synthesis Status ; Successful - Sun Aug 13 06:36:26 2023 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2GS ; ; Top-level Entity Name ; RAM2GS ; @@ -167,9 +167,9 @@ https://fpgasoftware.intel.com/eula. ; -- Combinational with a register ; 68 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 56 ; -; -- 3 input functions ; 48 ; -; -- 2 input functions ; 41 ; +; -- 4 input functions ; 57 ; +; -- 3 input functions ; 46 ; +; -- 2 input functions ; 42 ; ; -- 1 input functions ; 8 ; ; -- 0 input functions ; 1 ; ; ; ; @@ -270,7 +270,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sun Aug 13 04:49:50 2023 + Info: Processing started: Sun Aug 13 06:36:15 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected @@ -302,9 +302,9 @@ Info (21057): Implemented 248 device resources after synthesis - the final resou Info (144001): Generated suppressed messages file D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings Info: Peak virtual memory: 4702 megabytes - Info: Processing ended: Sun Aug 13 04:49:59 2023 - Info: Elapsed time: 00:00:09 - Info: Total CPU time (on all processors): 00:00:22 + Info: Processing ended: Sun Aug 13 06:36:26 2023 + Info: Elapsed time: 00:00:11 + Info: Total CPU time (on all processors): 00:00:27 +------------------------------------------+ diff --git a/CPLD/MAXV/output_files/RAM2GS.map.summary b/CPLD/MAXV/output_files/RAM2GS.map.summary index 27c7401..6ae3a75 100644 --- a/CPLD/MAXV/output_files/RAM2GS.map.summary +++ b/CPLD/MAXV/output_files/RAM2GS.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Sun Aug 13 04:49:59 2023 +Analysis & Synthesis Status : Successful - Sun Aug 13 06:36:26 2023 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2GS Top-level Entity Name : RAM2GS diff --git a/CPLD/MAXV/output_files/RAM2GS.pof b/CPLD/MAXV/output_files/RAM2GS.pof index e4b2cb7..795da91 100644 Binary files a/CPLD/MAXV/output_files/RAM2GS.pof and b/CPLD/MAXV/output_files/RAM2GS.pof differ diff --git a/CPLD/MAXV/output_files/RAM2GS.sta.rpt b/CPLD/MAXV/output_files/RAM2GS.sta.rpt index 3606954..7373b53 100644 --- a/CPLD/MAXV/output_files/RAM2GS.sta.rpt +++ b/CPLD/MAXV/output_files/RAM2GS.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for RAM2GS -Sun Aug 13 04:50:05 2023 +Sun Aug 13 06:36:32 2023 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -24,8 +24,8 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition 16. Hold: 'DRCLK' 17. Hold: 'ARCLK' 18. Hold: 'PHI2' - 19. Hold: 'nCRAS' - 20. Hold: 'RCLK' + 19. Hold: 'RCLK' + 20. Hold: 'nCRAS' 21. Setup Transfers 22. Hold Transfers 23. Report TCCS @@ -87,7 +87,7 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.1% ; +; Processor 2 ; 0.0% ; +----------------------------+-------------+ @@ -112,8 +112,8 @@ https://fpgasoftware.intel.com/eula. +-----------+-----------------+------------+------+ ; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; ; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; -; 46.89 MHz ; 46.89 MHz ; PHI2 ; ; -; 96.27 MHz ; 96.27 MHz ; RCLK ; ; +; 44.39 MHz ; 44.39 MHz ; PHI2 ; ; +; 98.91 MHz ; 98.91 MHz ; RCLK ; ; +-----------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -125,9 +125,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+---------+---------------+ ; ARCLK ; -99.000 ; -99.000 ; ; DRCLK ; -99.000 ; -99.000 ; -; PHI2 ; -10.164 ; -118.093 ; -; RCLK ; -9.387 ; -288.937 ; -; nCRAS ; -2.870 ; -7.136 ; +; PHI2 ; -10.765 ; -121.853 ; +; RCLK ; -9.110 ; -282.559 ; +; nCRAS ; -2.305 ; -17.117 ; +-------+---------+---------------+ @@ -136,11 +136,11 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+---------+---------------+ -; DRCLK ; -16.578 ; -16.578 ; -; ARCLK ; -16.552 ; -16.552 ; -; PHI2 ; -0.611 ; -0.993 ; -; nCRAS ; 0.443 ; 0.000 ; -; RCLK ; 1.178 ; 0.000 ; +; DRCLK ; -16.599 ; -16.599 ; +; ARCLK ; -15.916 ; -15.916 ; +; PHI2 ; -0.387 ; -0.479 ; +; RCLK ; 1.189 ; 0.000 ; +; nCRAS ; 1.744 ; 0.000 ; +-------+---------+---------------+ @@ -176,7 +176,7 @@ No paths to report. ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; -99.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 1.000 ; 0.000 ; 80.000 ; -; -22.448 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -1.761 ; 1.687 ; +; -23.084 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 1.000 ; -2.397 ; 1.687 ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ @@ -186,8 +186,8 @@ No paths to report. ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; -99.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 1.000 ; 0.000 ; 80.000 ; -; -23.156 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.735 ; 2.421 ; -; -22.422 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.735 ; 1.687 ; +; -23.027 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.714 ; 2.313 ; +; -22.401 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 1.000 ; -1.714 ; 1.687 ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ @@ -196,215 +196,215 @@ No paths to report. +---------+-----------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+-----------+--------------+--------------+-------------+--------------+------------+------------+ -; -10.164 ; Bank[6] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.404 ; -; -10.164 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.404 ; -; -10.164 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.404 ; -; -10.084 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.324 ; -; -10.084 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.324 ; -; -9.954 ; Bank[5] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.194 ; -; -9.954 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.194 ; -; -9.954 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.194 ; -; -9.874 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.114 ; -; -9.874 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.114 ; -; -9.731 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.971 ; -; -9.731 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.971 ; -; -9.731 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.971 ; -; -9.696 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.936 ; -; -9.693 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.933 ; -; -9.663 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.903 ; -; -9.663 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.903 ; -; -9.651 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.891 ; -; -9.651 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.891 ; -; -9.531 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.771 ; -; -9.531 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.771 ; -; -9.531 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.771 ; -; -9.486 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.726 ; -; -9.483 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.723 ; -; -9.453 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.693 ; -; -9.453 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.693 ; -; -9.451 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.691 ; -; -9.451 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.691 ; -; -9.263 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.503 ; -; -9.260 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.500 ; -; -9.230 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.470 ; -; -9.230 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.470 ; -; -9.219 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.459 ; -; -9.219 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.459 ; -; -9.219 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.459 ; -; -9.139 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.379 ; -; -9.139 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.379 ; -; -9.063 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.303 ; -; -9.060 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.300 ; -; -9.030 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.270 ; -; -9.030 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.270 ; -; -8.791 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.031 ; -; -8.791 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.031 ; -; -8.791 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.031 ; -; -8.751 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.991 ; -; -8.748 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.988 ; -; -8.718 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.958 ; -; -8.718 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.958 ; -; -8.711 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.951 ; -; -8.711 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.951 ; -; -8.580 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.820 ; -; -8.503 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.743 ; -; -8.503 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.743 ; -; -8.503 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.743 ; -; -8.501 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.741 ; -; -8.501 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.741 ; -; -8.423 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.663 ; -; -8.423 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.663 ; -; -8.370 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.610 ; -; -8.323 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.563 ; -; -8.320 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.560 ; -; -8.291 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.531 ; -; -8.291 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.531 ; -; -8.290 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.530 ; -; -8.290 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.530 ; -; -8.147 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.387 ; -; -8.068 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.308 ; -; -8.068 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.308 ; -; -8.066 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.306 ; -; -8.066 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.306 ; -; -8.066 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.306 ; -; -8.035 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.275 ; -; -8.032 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.272 ; -; -8.002 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.242 ; -; -8.002 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.242 ; -; -7.986 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.226 ; -; -7.986 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.226 ; -; -7.947 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.187 ; -; -7.868 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.108 ; -; -7.868 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.108 ; -; -7.635 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.875 ; -; -7.598 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.838 ; -; -7.595 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.835 ; -; -7.565 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.805 ; -; -7.565 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.805 ; -; -7.556 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.796 ; -; -7.556 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.796 ; -; -7.207 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.447 ; -; -7.128 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.368 ; -; -7.128 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.368 ; -; -6.919 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.159 ; -; -6.840 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.080 ; -; -6.840 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.080 ; -; -6.482 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.722 ; -; -6.403 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.643 ; -; -6.403 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 6.643 ; -; -5.870 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.610 ; -; -5.870 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.610 ; -; -5.870 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.610 ; -; -5.790 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 6.530 ; +; -10.765 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 11.005 ; +; -10.765 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 11.005 ; +; -10.579 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.819 ; +; -10.579 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.819 ; +; -10.404 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.644 ; +; -10.389 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.629 ; +; -10.389 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.629 ; +; -10.218 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.458 ; +; -10.203 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.443 ; +; -10.203 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.443 ; +; -10.182 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.422 ; +; -9.996 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.236 ; +; -9.976 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.216 ; +; -9.976 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.216 ; +; -9.841 ; Bank[1] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.081 ; +; -9.841 ; Bank[1] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.081 ; +; -9.790 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.030 ; +; -9.790 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 10.030 ; +; -9.481 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.721 ; +; -9.481 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.721 ; +; -9.480 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.720 ; +; -9.465 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.705 ; +; -9.465 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.705 ; +; -9.305 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.545 ; +; -9.305 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.545 ; +; -9.295 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.535 ; +; -9.295 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.535 ; +; -9.258 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.498 ; +; -9.125 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.365 ; +; -9.125 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.365 ; +; -9.114 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.354 ; +; -9.114 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.354 ; +; -9.052 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.292 ; +; -9.052 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.292 ; +; -8.944 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.184 ; +; -8.929 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.169 ; +; -8.929 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.169 ; +; -8.901 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.141 ; +; -8.901 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.141 ; +; -8.842 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.082 ; +; -8.842 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.082 ; +; -8.764 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 9.004 ; +; -8.753 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.993 ; +; -8.749 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.989 ; +; -8.749 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.989 ; +; -8.738 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.978 ; +; -8.738 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.978 ; +; -8.722 ; Bank[5] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.962 ; +; -8.715 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.955 ; +; -8.715 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.955 ; +; -8.557 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.797 ; +; -8.557 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.797 ; +; -8.542 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.782 ; +; -8.531 ; Bank[6] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.771 ; +; -8.516 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.756 ; +; -8.516 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.756 ; +; -8.481 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.721 ; +; -8.466 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.706 ; +; -8.466 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.706 ; +; -8.336 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.576 ; +; -8.336 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.576 ; +; -8.325 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.565 ; +; -8.325 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.565 ; +; -8.259 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.499 ; +; -8.053 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.293 ; +; -8.053 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.293 ; +; -8.021 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.261 ; +; -8.021 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.261 ; +; -7.977 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.217 ; +; -7.977 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.217 ; +; -7.841 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.081 ; +; -7.841 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.081 ; +; -7.830 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.070 ; +; -7.830 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 8.070 ; +; -7.806 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 8.546 ; +; -7.806 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 8.546 ; +; -7.662 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.902 ; +; -7.662 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.902 ; +; -7.558 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.798 ; +; -7.558 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.798 ; +; -7.445 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 8.185 ; +; -7.441 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.681 ; +; -7.441 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.681 ; +; -7.301 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.541 ; +; -7.286 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.526 ; +; -7.286 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.526 ; +; -7.261 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.501 ; +; -7.261 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.501 ; +; -7.250 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.490 ; +; -7.250 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.490 ; +; -7.223 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 7.963 ; +; -7.079 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.319 ; +; -7.017 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 7.757 ; +; -7.017 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 7.757 ; +; -6.978 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.218 ; +; -6.978 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.218 ; +; -6.873 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.113 ; +; -6.873 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.500 ; 0.000 ; 7.113 ; +; -6.522 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 7.262 ; +; -6.522 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 1.000 ; 0.000 ; 7.262 ; +---------+-----------+--------------+--------------+-------------+--------------+------------+------------+ -+-----------------------------------------------------------------------------------------------------------+ -; Setup: 'RCLK' ; -+--------+--------------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+--------+--------------+-------------+--------------+-------------+--------------+------------+------------+ -; -9.387 ; FS[17] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 10.127 ; -; -9.117 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.857 ; -; -8.872 ; FS[17] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.612 ; -; -8.682 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.422 ; -; -8.654 ; FS[2] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.394 ; -; -8.600 ; Ready ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.340 ; -; -8.571 ; FS[6] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.311 ; -; -8.559 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.299 ; -; -8.503 ; FS[11] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.243 ; -; -8.442 ; FS[4] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.182 ; -; -8.399 ; FS[3] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.139 ; -; -8.384 ; FS[16] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.124 ; -; -8.351 ; FS[1] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.091 ; -; -8.335 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.075 ; -; -8.301 ; FS[6] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.041 ; -; -8.292 ; FS[0] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.032 ; -; -8.219 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.144 ; 5.315 ; -; -8.172 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.912 ; -; -8.145 ; FS[13] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.885 ; -; -8.117 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.857 ; -; -8.114 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.854 ; -; -8.045 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.197 ; 6.088 ; -; -8.033 ; FS[7] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.773 ; -; -8.003 ; FS[17] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.743 ; -; -7.996 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.736 ; -; -7.992 ; FS[8] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.732 ; -; -7.942 ; S[1] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.682 ; -; -7.869 ; FS[16] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.609 ; -; -7.858 ; S[1] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.598 ; -; -7.780 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.520 ; -; -7.765 ; FS[10] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.505 ; -; -7.763 ; FS[7] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.503 ; -; -7.743 ; FS[6] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.483 ; -; -7.740 ; FS[5] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.480 ; -; -7.727 ; UFMInitDone ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.467 ; -; -7.726 ; InitReady ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.466 ; -; -7.697 ; RCKE~reg0 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.437 ; -; -7.691 ; FS[5] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.431 ; -; -7.642 ; InitReady ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.382 ; -; -7.614 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.354 ; -; -7.611 ; FS[12] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.351 ; -; -7.557 ; FS[5] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.297 ; -; -7.556 ; S[1] ; RA10 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.296 ; -; -7.556 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.296 ; -; -7.526 ; FS[2] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.266 ; -; -7.506 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.144 ; 4.602 ; -; -7.496 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.197 ; 5.539 ; -; -7.472 ; Ready ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.212 ; -; -7.457 ; UFMInitDone ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.197 ; -; -7.433 ; Ready ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.173 ; -; -7.432 ; FS[11] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.172 ; -; -7.395 ; FS[4] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.135 ; -; -7.377 ; FS[7] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.117 ; -; -7.340 ; InitReady ; RA10 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.080 ; -; -7.338 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.197 ; 5.381 ; -; -7.300 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.197 ; 5.343 ; -; -7.287 ; FS[5] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.027 ; -; -7.278 ; FS[15] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.018 ; -; -7.271 ; FS[3] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.011 ; -; -7.265 ; FS[12] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.005 ; -; -7.237 ; FS[6] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.977 ; -; -7.223 ; FS[1] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.963 ; -; -7.212 ; UFMInitDone ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.952 ; -; -7.211 ; FS[16] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.951 ; -; -7.205 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.945 ; -; -7.193 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.933 ; -; -7.164 ; FS[0] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.904 ; -; -7.162 ; FS[6] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.902 ; -; -7.162 ; FS[6] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.902 ; -; -7.157 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.144 ; 4.253 ; -; -7.155 ; CmdSubmitted ; LEDEN ; PHI2 ; RCLK ; 0.500 ; -3.144 ; 4.251 ; -; -7.139 ; FS[17] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.879 ; -; -7.108 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.848 ; -; -7.086 ; FS[11] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.826 ; -; -7.074 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.814 ; -; -7.073 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.813 ; -; -7.019 ; S[0] ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.759 ; -; -7.006 ; FS[14] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.746 ; -; -7.000 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.740 ; -; -6.997 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.737 ; -; -6.993 ; FS[17] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.733 ; -; -6.955 ; FS[5] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.695 ; -; -6.954 ; Ready ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.694 ; -; -6.951 ; PHI2r2 ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.691 ; -; -6.936 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.197 ; 4.979 ; -; -6.935 ; S[0] ; nRRAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.675 ; -; -6.921 ; FS[8] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.661 ; -; -6.917 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.144 ; 4.013 ; -; -6.901 ; InitReady ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.641 ; -; -6.899 ; UFMInitDone ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.639 ; -; -6.875 ; FS[17] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.615 ; -; -6.842 ; RASr2 ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.582 ; -; -6.827 ; FS[5] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.567 ; -; -6.803 ; CBR ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.197 ; 4.846 ; -; -6.783 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.523 ; -; -6.783 ; IS[3] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.523 ; -; -6.770 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.197 ; 4.813 ; -; -6.747 ; FS[6] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.487 ; -; -6.729 ; FS[5] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.469 ; -; -6.728 ; FS[13] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.468 ; -+--------+--------------+-------------+--------------+-------------+--------------+------------+------------+ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'RCLK' ; ++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ +; -9.110 ; FS[16] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.850 ; +; -8.871 ; FS[17] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.611 ; +; -8.747 ; FWEr ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.239 ; 6.748 ; +; -8.640 ; UFMInitDone ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 9.380 ; +; -8.433 ; CBR ; nRowColSel ; nCRAS ; RCLK ; 0.500 ; -2.239 ; 6.434 ; +; -8.311 ; CmdSubmitted ; LEDEN ; PHI2 ; RCLK ; 0.500 ; -3.165 ; 5.386 ; +; -8.242 ; CmdSubmitted ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.165 ; 5.317 ; +; -8.193 ; FS[4] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.933 ; +; -8.156 ; FS[16] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.896 ; +; -8.060 ; FS[5] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.800 ; +; -7.985 ; CBR ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.239 ; 5.986 ; +; -7.964 ; FS[16] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.704 ; +; -7.917 ; FS[17] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.657 ; +; -7.883 ; FS[16] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.623 ; +; -7.802 ; FS[7] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.542 ; +; -7.801 ; FS[2] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.541 ; +; -7.742 ; FS[13] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.482 ; +; -7.725 ; FS[17] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.465 ; +; -7.686 ; UFMInitDone ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.426 ; +; -7.648 ; InitReady ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.388 ; +; -7.644 ; FS[17] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.384 ; +; -7.602 ; FS[10] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.342 ; +; -7.574 ; FS[1] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.314 ; +; -7.570 ; CmdDRCLK ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.165 ; 4.645 ; +; -7.558 ; FS[6] ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.298 ; +; -7.555 ; FS[7] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.295 ; +; -7.548 ; FS[11] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.288 ; +; -7.547 ; FS[4] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.287 ; +; -7.543 ; CmdSubmitted ; DRCLK ; PHI2 ; RCLK ; 0.500 ; -3.165 ; 4.618 ; +; -7.539 ; Ready ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.279 ; +; -7.503 ; S[0] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.243 ; +; -7.494 ; UFMInitDone ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.234 ; +; -7.413 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.153 ; +; -7.396 ; FS[0] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.136 ; +; -7.396 ; FS[15] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.136 ; +; -7.351 ; RASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.091 ; +; -7.341 ; FS[13] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 8.081 ; +; -7.265 ; FWEr ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.239 ; 5.266 ; +; -7.239 ; FS[4] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.979 ; +; -7.238 ; Ready ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.978 ; +; -7.210 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; LEDEN ; DRCLK ; RCLK ; 1.000 ; 1.714 ; 9.664 ; +; -7.201 ; FS[10] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.941 ; +; -7.174 ; FWEr ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.239 ; 5.175 ; +; -7.147 ; FS[11] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.887 ; +; -7.115 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; UFMD ; DRCLK ; RCLK ; 1.000 ; 1.714 ; 9.569 ; +; -7.106 ; FS[5] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.846 ; +; -7.081 ; InitReady ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.821 ; +; -7.078 ; FS[16] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.818 ; +; -7.048 ; CmdDRDIn ; DRDIn ; PHI2 ; RCLK ; 0.500 ; -3.165 ; 4.123 ; +; -7.047 ; FS[4] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.787 ; +; -7.038 ; CmdSubmitted ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.165 ; 4.113 ; +; -6.995 ; FS[15] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.735 ; +; -6.975 ; FS[7] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.715 ; +; -6.966 ; FS[4] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.706 ; +; -6.952 ; RASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.692 ; +; -6.918 ; FS[14] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.658 ; +; -6.914 ; FS[5] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.654 ; +; -6.900 ; Ready ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.640 ; +; -6.872 ; S[0] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.612 ; +; -6.861 ; Cmdn8MEGEN ; n8MEGEN ; PHI2 ; RCLK ; 0.500 ; -3.165 ; 3.936 ; +; -6.860 ; CBR ; nRCS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.239 ; 4.861 ; +; -6.859 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; n8MEGEN ; DRCLK ; RCLK ; 1.000 ; 1.714 ; 9.313 ; +; -6.852 ; FS[2] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.592 ; +; -6.849 ; CBR ; RCKEEN ; nCRAS ; RCLK ; 0.500 ; -2.239 ; 4.850 ; +; -6.848 ; FS[7] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.588 ; +; -6.839 ; FS[17] ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.579 ; +; -6.837 ; FS[13] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.577 ; +; -6.833 ; FS[5] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.573 ; +; -6.811 ; FS[3] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.551 ; +; -6.811 ; FS[12] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.551 ; +; -6.800 ; Ready ; LEDEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.540 ; +; -6.751 ; IS[2] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.491 ; +; -6.746 ; S[1] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.486 ; +; -6.741 ; FS[7] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.481 ; +; -6.737 ; FS[4] ; DRCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.477 ; +; -6.697 ; FS[10] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.437 ; +; -6.656 ; FS[7] ; ARCLK ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.396 ; +; -6.655 ; RCKE~reg0 ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.395 ; +; -6.643 ; FS[11] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.383 ; +; -6.636 ; PHI2r2 ; DRDIn ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.376 ; +; -6.625 ; FS[1] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.365 ; +; -6.617 ; FWEr ; nRWE~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.239 ; 4.618 ; +; -6.608 ; UFMInitDone ; DRShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.348 ; +; -6.606 ; FS[7] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.346 ; +; -6.604 ; FS[6] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.344 ; +; -6.590 ; Ready ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.330 ; +; -6.576 ; IS[0] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.316 ; +; -6.575 ; FS[7] ; UFMInitDone ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.315 ; +; -6.553 ; S[1] ; nRWE~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.293 ; +; -6.547 ; RASr2 ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.287 ; +; -6.522 ; FS[5] ; ARShift ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.262 ; +; -6.517 ; FS[14] ; InitReady ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.257 ; +; -6.503 ; FWEr ; nRCAS~reg0 ; nCRAS ; RCLK ; 0.500 ; -2.239 ; 4.504 ; +; -6.491 ; FS[15] ; UFMReqErase ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.231 ; +; -6.477 ; IS[2] ; nRCS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.217 ; +; -6.470 ; FS[16] ; n8MEGEN ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.210 ; +; -6.451 ; InitReady ; nRCAS~reg0 ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.191 ; +; -6.447 ; FS[0] ; UFMD ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.187 ; +; -6.447 ; IS[1] ; Ready ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.187 ; +; -6.444 ; InitReady ; IS[3] ; RCLK ; RCLK ; 1.000 ; 0.000 ; 7.184 ; ++--------+---------------------------------------------------------------------------------------------+-------------+--------------+-------------+--------------+------------+------------+ +--------------------------------------------------------------------------------------------------------+ @@ -412,20 +412,20 @@ No paths to report. +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; -2.870 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 5.913 ; 9.023 ; -; -2.370 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 5.913 ; 9.023 ; -; -1.177 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 3.614 ; -; -1.046 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 3.483 ; -; -0.854 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 3.291 ; -; -0.301 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.738 ; -; -0.299 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.736 ; -; -0.295 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.732 ; -; -0.294 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.731 ; -; 0.217 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.220 ; -; 0.218 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.219 ; -; 0.222 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.215 ; -; 0.222 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.215 ; -; 0.223 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 2.197 ; 2.214 ; +; -2.305 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.500 ; 5.955 ; 8.500 ; +; -1.805 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 1.000 ; 5.955 ; 8.500 ; +; -1.717 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.239 ; 4.196 ; +; -1.332 ; Ready ; RowA[3] ; RCLK ; nCRAS ; 0.500 ; 2.239 ; 3.811 ; +; -1.330 ; Ready ; RowA[6] ; RCLK ; nCRAS ; 0.500 ; 2.239 ; 3.809 ; +; -1.326 ; Ready ; RowA[7] ; RCLK ; nCRAS ; 0.500 ; 2.239 ; 3.805 ; +; -1.217 ; Ready ; RowA[8] ; RCLK ; nCRAS ; 0.500 ; 2.239 ; 3.696 ; +; -1.214 ; Ready ; RowA[0] ; RCLK ; nCRAS ; 0.500 ; 2.239 ; 3.693 ; +; -1.211 ; Ready ; RowA[1] ; RCLK ; nCRAS ; 0.500 ; 2.239 ; 3.690 ; +; -1.098 ; Ready ; RowA[9] ; RCLK ; nCRAS ; 0.500 ; 2.239 ; 3.577 ; +; -1.097 ; Ready ; RowA[2] ; RCLK ; nCRAS ; 0.500 ; 2.239 ; 3.576 ; +; -1.096 ; Ready ; RowA[4] ; RCLK ; nCRAS ; 0.500 ; 2.239 ; 3.575 ; +; -1.096 ; Ready ; RowA[5] ; RCLK ; nCRAS ; 0.500 ; 2.239 ; 3.575 ; +; -1.078 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; 0.500 ; 2.239 ; 3.557 ; +--------+-----------+-------------+--------------+-------------+--------------+------------+------------+ @@ -434,8 +434,8 @@ No paths to report. +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -16.578 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.735 ; 1.687 ; -; -15.844 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.735 ; 2.421 ; +; -16.599 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.714 ; 1.687 ; +; -15.973 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; RCLK ; DRCLK ; 0.000 ; -1.714 ; 2.313 ; ; 60.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; +---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ @@ -445,7 +445,7 @@ No paths to report. +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ -; -16.552 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -1.761 ; 1.687 ; +; -15.916 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RCLK ; ARCLK ; 0.000 ; -2.397 ; 1.687 ; ; 60.000 ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; +---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ @@ -455,239 +455,239 @@ No paths to report. +--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -; -0.611 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 3.144 ; 2.107 ; -; -0.382 ; LEDEN ; CmdLEDEN ; RCLK ; PHI2 ; -0.500 ; 3.144 ; 2.336 ; -; 1.207 ; LEDEN ; XOR8MEG ; RCLK ; PHI2 ; -0.500 ; 3.144 ; 3.925 ; -; 1.322 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.144 ; 4.540 ; -; 1.473 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.144 ; 4.691 ; -; 1.990 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.064 ; -; 3.231 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.305 ; -; 3.250 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.324 ; -; 3.802 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 3.376 ; -; 4.489 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.063 ; -; 4.855 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.929 ; -; 4.858 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.932 ; -; 4.926 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.500 ; -; 4.952 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.026 ; -; 5.137 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.711 ; -; 5.214 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.788 ; -; 5.574 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.148 ; -; 5.612 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.686 ; -; 5.615 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.689 ; -; 5.642 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.216 ; -; 5.862 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.436 ; -; 5.954 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.528 ; -; 6.035 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.109 ; -; 6.035 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.109 ; -; 6.154 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.728 ; -; 6.254 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.828 ; -; 6.290 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.864 ; -; 6.377 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.951 ; -; 6.456 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.530 ; -; 6.456 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.530 ; -; 6.536 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.610 ; -; 6.536 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.610 ; -; 6.536 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 6.610 ; -; 6.587 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.161 ; -; 6.602 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.176 ; -; 6.691 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.265 ; -; 6.802 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.376 ; -; 6.979 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.553 ; -; 7.025 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.599 ; -; 7.148 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.722 ; -; 7.197 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.771 ; -; 7.235 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.809 ; -; 7.407 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.981 ; -; 7.585 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.159 ; -; 7.634 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.208 ; -; 7.719 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.293 ; -; 7.873 ; Bank[2] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.447 ; -; 7.919 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.493 ; -; 7.922 ; Bank[2] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.496 ; -; 8.142 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.716 ; -; 8.231 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.805 ; -; 8.231 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.805 ; -; 8.301 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.875 ; -; 8.350 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.924 ; -; 8.352 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.926 ; -; 8.613 ; Bank[3] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.187 ; -; 8.652 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.226 ; -; 8.652 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.226 ; -; 8.662 ; Bank[3] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.236 ; -; 8.668 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.242 ; -; 8.668 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.242 ; -; 8.732 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.306 ; -; 8.732 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.306 ; -; 8.732 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.306 ; -; 8.813 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.387 ; -; 8.862 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.436 ; -; 8.956 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.530 ; -; 8.956 ; Bank[2] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.530 ; -; 9.036 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.610 ; -; 9.085 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.659 ; -; 9.089 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.663 ; -; 9.089 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.663 ; -; 9.169 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.743 ; -; 9.169 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.743 ; -; 9.169 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.743 ; -; 9.246 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.820 ; -; 9.295 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.869 ; -; 9.377 ; Bank[2] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.951 ; -; 9.377 ; Bank[2] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.951 ; -; 9.384 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.958 ; -; 9.384 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.958 ; -; 9.457 ; Bank[2] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.031 ; -; 9.457 ; Bank[2] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.031 ; -; 9.457 ; Bank[2] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.031 ; -; 9.696 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.270 ; -; 9.696 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.270 ; -; 9.805 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.379 ; -; 9.805 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.379 ; -; 9.885 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.459 ; -; 9.885 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.459 ; -; 9.885 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.459 ; -; 9.896 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.470 ; -; 9.896 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.470 ; -; 10.117 ; Bank[3] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.691 ; -; 10.117 ; Bank[3] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.691 ; -; 10.119 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.693 ; -; 10.119 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.693 ; -; 10.197 ; Bank[3] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.771 ; -; 10.197 ; Bank[3] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.771 ; -; 10.197 ; Bank[3] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.771 ; +; -0.387 ; n8MEGEN ; Cmdn8MEGEN ; RCLK ; PHI2 ; -0.500 ; 3.165 ; 2.352 ; +; -0.092 ; LEDEN ; XOR8MEG ; RCLK ; PHI2 ; -0.500 ; 3.165 ; 2.647 ; +; 0.020 ; LEDEN ; CmdLEDEN ; RCLK ; PHI2 ; -0.500 ; 3.165 ; 2.759 ; +; 0.398 ; n8MEGEN ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.165 ; 3.637 ; +; 0.399 ; Ready ; RA11 ; RCLK ; PHI2 ; 0.000 ; 3.165 ; 3.638 ; +; 2.804 ; XOR8MEG ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.878 ; +; 2.855 ; UFMOscEN ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 2.929 ; +; 2.909 ; XOR8MEG ; RA11 ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 2.483 ; +; 2.938 ; CmdEnable ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 3.012 ; +; 4.628 ; ADSubmitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.702 ; +; 4.628 ; ADSubmitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 4.702 ; +; 4.860 ; Bank[4] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.434 ; +; 4.861 ; Bank[4] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 4.435 ; +; 5.833 ; C1Submitted ; UFMOscEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.907 ; +; 5.833 ; C1Submitted ; CmdEnable ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 5.907 ; +; 6.040 ; Bank[7] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.614 ; +; 6.041 ; Bank[7] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.615 ; +; 6.312 ; Bank[6] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.886 ; +; 6.313 ; Bank[6] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.887 ; +; 6.323 ; Bank[0] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.897 ; +; 6.324 ; Bank[0] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 5.898 ; +; 6.503 ; Bank[5] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.077 ; +; 6.504 ; Bank[5] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.078 ; +; 6.644 ; Bank[4] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.218 ; +; 7.039 ; Bank[1] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.613 ; +; 7.040 ; Bank[1] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.614 ; +; 7.044 ; Bank[4] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.618 ; +; 7.044 ; Bank[4] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 6.618 ; +; 7.188 ; CmdEnable ; CmdDRDIn ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 7.262 ; +; 7.188 ; CmdEnable ; CmdDRCLK ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 7.262 ; +; 7.539 ; Bank[4] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.113 ; +; 7.539 ; Bank[4] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.113 ; +; 7.566 ; Bank[4] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.140 ; +; 7.683 ; CmdEnable ; CmdSubmitted ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 7.757 ; +; 7.683 ; CmdEnable ; Cmdn8MEGEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 7.757 ; +; 7.745 ; Bank[4] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.319 ; +; 7.777 ; Bank[3] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.351 ; +; 7.778 ; Bank[3] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.352 ; +; 7.824 ; Bank[7] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.398 ; +; 7.889 ; CmdEnable ; CmdLEDEN ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 7.963 ; +; 7.963 ; Bank[2] ; C1Submitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.537 ; +; 7.964 ; Bank[2] ; ADSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.538 ; +; 7.967 ; Bank[4] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.541 ; +; 8.096 ; Bank[6] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.670 ; +; 8.107 ; Bank[0] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.681 ; +; 8.111 ; CmdEnable ; XOR8MEG ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 8.185 ; +; 8.224 ; Bank[7] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.798 ; +; 8.224 ; Bank[7] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.798 ; +; 8.287 ; Bank[5] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.861 ; +; 8.328 ; Bank[4] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.902 ; +; 8.328 ; Bank[4] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 7.902 ; +; 8.472 ; CmdEnable ; CmdUFMErase ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 8.546 ; +; 8.472 ; CmdEnable ; CmdUFMPrgm ; PHI2 ; PHI2 ; 0.000 ; 0.000 ; 8.546 ; +; 8.496 ; Bank[6] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.070 ; +; 8.496 ; Bank[6] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.070 ; +; 8.507 ; Bank[0] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.081 ; +; 8.507 ; Bank[0] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.081 ; +; 8.687 ; Bank[5] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.261 ; +; 8.687 ; Bank[5] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.261 ; +; 8.719 ; Bank[7] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.293 ; +; 8.719 ; Bank[7] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.293 ; +; 8.746 ; Bank[7] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.320 ; +; 8.823 ; Bank[1] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.397 ; +; 8.925 ; Bank[7] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.499 ; +; 8.991 ; Bank[6] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.565 ; +; 8.991 ; Bank[6] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.565 ; +; 9.002 ; Bank[0] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.576 ; +; 9.002 ; Bank[0] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.576 ; +; 9.018 ; Bank[6] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.592 ; +; 9.029 ; Bank[0] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.603 ; +; 9.147 ; Bank[7] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.721 ; +; 9.182 ; Bank[5] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.756 ; +; 9.182 ; Bank[5] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.756 ; +; 9.197 ; Bank[6] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.771 ; +; 9.208 ; Bank[0] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.782 ; +; 9.209 ; Bank[5] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.783 ; +; 9.223 ; Bank[1] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.797 ; +; 9.223 ; Bank[1] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.797 ; +; 9.388 ; Bank[5] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.962 ; +; 9.419 ; Bank[6] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 8.993 ; +; 9.430 ; Bank[0] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.004 ; +; 9.508 ; Bank[7] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.082 ; +; 9.508 ; Bank[7] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.082 ; +; 9.561 ; Bank[3] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.135 ; +; 9.610 ; Bank[5] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.184 ; +; 9.718 ; Bank[1] ; CmdSubmitted ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.292 ; +; 9.718 ; Bank[1] ; Cmdn8MEGEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.292 ; +; 9.745 ; Bank[1] ; UFMOscEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.319 ; +; 9.747 ; Bank[2] ; CmdEnable ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.321 ; +; 9.780 ; Bank[6] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.354 ; +; 9.780 ; Bank[6] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.354 ; +; 9.791 ; Bank[0] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.365 ; +; 9.791 ; Bank[0] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.365 ; +; 9.924 ; Bank[1] ; CmdLEDEN ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.498 ; +; 9.961 ; Bank[3] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.535 ; +; 9.961 ; Bank[3] ; CmdDRCLK ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.535 ; +; 9.971 ; Bank[5] ; CmdUFMErase ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.545 ; +; 9.971 ; Bank[5] ; CmdUFMPrgm ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.545 ; +; 10.146 ; Bank[1] ; XOR8MEG ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.720 ; +; 10.147 ; Bank[2] ; CmdDRDIn ; PHI2 ; PHI2 ; -0.500 ; 0.000 ; 9.721 ; +--------+-------------+--------------+--------------+-------------+--------------+------------+------------+ -+-------------------------------------------------------------------------------------------------------+ -; Hold: 'nCRAS' ; -+-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ -; 0.443 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.214 ; -; 0.444 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.215 ; -; 0.444 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.215 ; -; 0.448 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.219 ; -; 0.449 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.220 ; -; 0.960 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.731 ; -; 0.961 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.732 ; -; 0.965 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.736 ; -; 0.967 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 2.738 ; -; 1.520 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 3.291 ; -; 1.712 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 3.483 ; -; 1.843 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.197 ; 3.614 ; -; 3.036 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 5.913 ; 9.023 ; -; 3.536 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 5.913 ; 9.023 ; -+-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ - - +---------------------------------------------------------------------------------------------------------+ ; Hold: 'RCLK' ; +-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ -; 1.178 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 3.716 ; 4.968 ; ; 1.189 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; 0.000 ; 3.716 ; 4.979 ; -; 1.236 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 3.716 ; 5.026 ; -; 1.678 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 3.716 ; 4.968 ; +; 1.199 ; nCCAS ; CASr ; nCCAS ; RCLK ; 0.000 ; 3.716 ; 4.989 ; +; 1.218 ; nCRAS ; RASr ; nCRAS ; RCLK ; 0.000 ; 3.716 ; 5.008 ; ; 1.689 ; PHI2 ; PHI2r ; PHI2 ; RCLK ; -0.500 ; 3.716 ; 4.979 ; -; 1.736 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 3.716 ; 5.026 ; -; 2.010 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.084 ; -; 2.020 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.094 ; -; 2.038 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.112 ; -; 2.047 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.121 ; -; 2.060 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.134 ; -; 2.307 ; RASr2 ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.381 ; -; 2.318 ; RASr2 ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.392 ; -; 2.380 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.454 ; -; 2.672 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.746 ; -; 2.674 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.748 ; -; 2.736 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.810 ; +; 1.699 ; nCCAS ; CASr ; nCCAS ; RCLK ; -0.500 ; 3.716 ; 4.989 ; +; 1.718 ; nCRAS ; RASr ; nCRAS ; RCLK ; -0.500 ; 3.716 ; 5.008 ; +; 2.011 ; FS[17] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.085 ; +; 2.019 ; FS[0] ; FS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.093 ; +; 2.035 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.109 ; +; 2.071 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.145 ; +; 2.076 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.150 ; +; 2.300 ; IS[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.374 ; +; 2.315 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.389 ; +; 2.380 ; CASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.454 ; +; 2.486 ; UFMD ; UFMD ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.560 ; +; 2.494 ; CASr2 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.568 ; +; 2.726 ; S[0] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.800 ; +; 2.730 ; S[0] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.804 ; ; 2.804 ; FS[6] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.878 ; ; 2.812 ; FS[9] ; FS[9] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.886 ; ; 2.813 ; FS[16] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.887 ; -; 2.813 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.887 ; -; 2.813 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.887 ; -; 2.824 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.898 ; -; 2.843 ; InitReady ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.917 ; -; 2.843 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.917 ; -; 2.845 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.919 ; -; 2.847 ; n8MEGEN ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.921 ; -; 2.852 ; UFMInitDone ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.926 ; -; 2.854 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.928 ; -; 2.932 ; CASr3 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.006 ; -; 2.948 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.022 ; -; 2.949 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.023 ; +; 2.822 ; FS[10] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.896 ; +; 2.824 ; FS[8] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.898 ; +; 2.825 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.899 ; +; 2.833 ; FS[11] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.907 ; +; 2.839 ; FS[0] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.913 ; +; 2.844 ; IS[3] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.918 ; +; 2.850 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.924 ; +; 2.906 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 2.980 ; +; 2.932 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.006 ; +; 2.932 ; CASr3 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.006 ; +; 2.948 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.022 ; +; 2.949 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.023 ; +; 2.949 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.023 ; ; 2.949 ; FS[2] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.023 ; -; 2.958 ; FS[5] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.032 ; -; 2.958 ; FS[3] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.032 ; -; 2.959 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.033 ; +; 2.957 ; FS[14] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.031 ; +; 2.958 ; FS[15] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.032 ; +; 2.959 ; n8MEGEN ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.033 ; ; 2.961 ; FS[7] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.035 ; -; 2.965 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.039 ; -; 2.966 ; UFMErase ; UFMErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.040 ; +; 2.962 ; FS[12] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.036 ; +; 2.963 ; RASr2 ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.037 ; +; 2.966 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.040 ; ; 2.967 ; UFMProgram ; UFMProgram ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.041 ; -; 2.974 ; UFMD ; UFMD ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.048 ; -; 2.975 ; UFMD ; UFMInitDone ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.049 ; -; 2.978 ; IS[1] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.052 ; -; 2.990 ; IS[2] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.064 ; -; 2.995 ; S[1] ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.069 ; -; 3.008 ; S[1] ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.082 ; -; 3.032 ; RASr2 ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.106 ; -; 3.079 ; Ready ; Ready ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.153 ; -; 3.086 ; Ready ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.160 ; -; 3.094 ; InitReady ; RCKEEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.168 ; -; 3.136 ; PHI2r ; PHI2r2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.210 ; -; 3.201 ; FS[13] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.275 ; -; 3.217 ; PHI2r2 ; PHI2r3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.291 ; -; 3.246 ; RASr3 ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.320 ; -; 3.250 ; RASr2 ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.324 ; -; 3.288 ; CASr3 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.362 ; -; 3.318 ; S[0] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.392 ; -; 3.338 ; FS[0] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.412 ; -; 3.405 ; UFMReqErase ; UFMReqErase ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.479 ; -; 3.421 ; PHI2r2 ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.495 ; -; 3.423 ; PHI2r2 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.497 ; -; 3.429 ; CASr2 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.503 ; -; 3.460 ; FS[16] ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.534 ; -; 3.483 ; Ready ; nRRAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.557 ; +; 2.991 ; RASr2 ; S[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.065 ; +; 3.000 ; RASr2 ; S[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.074 ; +; 3.006 ; IS[1] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.080 ; +; 3.046 ; CASr3 ; nRWE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.120 ; +; 3.047 ; CASr2 ; CASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.121 ; +; 3.051 ; CASr2 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.125 ; +; 3.292 ; PHI2r2 ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.366 ; +; 3.331 ; Ready ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.405 ; +; 3.346 ; IS[0] ; IS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.420 ; +; 3.348 ; IS[0] ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.422 ; +; 3.351 ; FS[1] ; FS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.425 ; +; 3.381 ; IS[3] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.455 ; +; 3.404 ; FS[4] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.478 ; +; 3.467 ; RASr ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.541 ; +; 3.468 ; FS[17] ; InitReady ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.542 ; +; 3.517 ; S[0] ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.591 ; ; 3.525 ; FS[6] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.599 ; ; 3.533 ; FS[9] ; FS[10] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.607 ; ; 3.534 ; FS[16] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.608 ; -; 3.534 ; FS[1] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.608 ; -; 3.564 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.638 ; -; 3.566 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.640 ; +; 3.543 ; FS[10] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.617 ; +; 3.554 ; FS[11] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.628 ; +; 3.560 ; FS[0] ; FS[2] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.634 ; +; 3.603 ; CASr3 ; nRCS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.677 ; ; 3.638 ; FS[6] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.712 ; -; 3.643 ; RASr ; RASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.717 ; ; 3.646 ; FS[9] ; FS[11] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.720 ; -; 3.647 ; FS[1] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.721 ; -; 3.647 ; IS[2] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.721 ; -; 3.677 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.751 ; -; 3.679 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.753 ; +; 3.656 ; FS[10] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.730 ; +; 3.667 ; FS[11] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.741 ; +; 3.673 ; FS[0] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.747 ; +; 3.687 ; RASr ; RASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.761 ; ; 3.759 ; FS[9] ; FS[12] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.833 ; -; 3.770 ; PHI2r3 ; DRCLK ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.844 ; -; 3.775 ; CASr2 ; CASr3 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.849 ; -; 3.792 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.866 ; -; 3.813 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.887 ; -; 3.814 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.888 ; +; 3.760 ; S[1] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.834 ; +; 3.769 ; FS[10] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.843 ; +; 3.796 ; PHI2r3 ; DRCLK ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.870 ; +; 3.813 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.887 ; ; 3.814 ; FS[2] ; FS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.888 ; -; 3.816 ; S[0] ; IS[0] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.890 ; -; 3.823 ; FS[5] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.897 ; -; 3.824 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.898 ; +; 3.822 ; FS[14] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.896 ; +; 3.823 ; FS[15] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.897 ; ; 3.826 ; FS[7] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.900 ; -; 3.830 ; FS[4] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.904 ; -; 3.854 ; RASr2 ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.928 ; -; 3.854 ; CASr ; CASr2 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.928 ; +; 3.827 ; FS[12] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.901 ; ; 3.872 ; FS[9] ; FS[13] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 3.946 ; -; 3.926 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.000 ; -; 3.927 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.001 ; -; 3.936 ; FS[5] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.010 ; -; 3.943 ; FS[4] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.017 ; -; 3.972 ; LEDEN ; LEDEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.046 ; -; 3.981 ; CASr3 ; nRCAS~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.055 ; -; 4.034 ; S[0] ; IS[3] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.108 ; -; 4.039 ; FS[14] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.113 ; +; 3.926 ; FS[5] ; FS[7] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.000 ; +; 3.932 ; nRowColSel ; nRowColSel ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.006 ; +; 3.935 ; FS[14] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.009 ; +; 3.936 ; FS[15] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.010 ; +; 3.970 ; RASr2 ; IS[1] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.044 ; +; 4.005 ; IS[0] ; RA10 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.079 ; +; 4.039 ; FS[5] ; FS[8] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.113 ; +; 4.048 ; FS[14] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.122 ; +; 4.079 ; RCKEEN ; RCKE~reg0 ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.153 ; +; 4.142 ; UFMD ; n8MEGEN ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.216 ; +; 4.170 ; FS[11] ; FS[16] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.244 ; +; 4.170 ; FS[11] ; FS[17] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.244 ; +; 4.170 ; FS[11] ; FS[15] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.244 ; +; 4.170 ; FS[11] ; FS[14] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.244 ; +; 4.176 ; FS[0] ; FS[5] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.250 ; +; 4.176 ; FS[0] ; FS[6] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.250 ; +; 4.176 ; FS[0] ; FS[4] ; RCLK ; RCLK ; 0.000 ; 0.000 ; 4.250 ; +-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ ++-------------------------------------------------------------------------------------------------------+ +; Hold: 'nCRAS' ; ++-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ +; 1.744 ; Ready ; RBA[1]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.239 ; 3.557 ; +; 1.762 ; Ready ; RowA[4] ; RCLK ; nCRAS ; -0.500 ; 2.239 ; 3.575 ; +; 1.762 ; Ready ; RowA[5] ; RCLK ; nCRAS ; -0.500 ; 2.239 ; 3.575 ; +; 1.763 ; Ready ; RowA[2] ; RCLK ; nCRAS ; -0.500 ; 2.239 ; 3.576 ; +; 1.764 ; Ready ; RowA[9] ; RCLK ; nCRAS ; -0.500 ; 2.239 ; 3.577 ; +; 1.877 ; Ready ; RowA[1] ; RCLK ; nCRAS ; -0.500 ; 2.239 ; 3.690 ; +; 1.880 ; Ready ; RowA[0] ; RCLK ; nCRAS ; -0.500 ; 2.239 ; 3.693 ; +; 1.883 ; Ready ; RowA[8] ; RCLK ; nCRAS ; -0.500 ; 2.239 ; 3.696 ; +; 1.992 ; Ready ; RowA[7] ; RCLK ; nCRAS ; -0.500 ; 2.239 ; 3.805 ; +; 1.996 ; Ready ; RowA[6] ; RCLK ; nCRAS ; -0.500 ; 2.239 ; 3.809 ; +; 1.998 ; Ready ; RowA[3] ; RCLK ; nCRAS ; -0.500 ; 2.239 ; 3.811 ; +; 2.383 ; Ready ; RBA[0]~reg0 ; RCLK ; nCRAS ; -0.500 ; 2.239 ; 4.196 ; +; 2.471 ; nCCAS ; CBR ; nCCAS ; nCRAS ; 0.000 ; 5.955 ; 8.500 ; +; 2.971 ; nCCAS ; CBR ; nCCAS ; nCRAS ; -0.500 ; 5.955 ; 8.500 ; ++-------+-----------+-------------+--------------+-------------+--------------+------------+------------+ + + +-------------------------------------------------------------------+ ; Setup Transfers ; +------------+----------+----------+----------+----------+----------+ @@ -752,7 +752,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 31 ; 31 ; -; Unconstrained Input Port Paths ; 255 ; 255 ; +; Unconstrained Input Port Paths ; 249 ; 249 ; ; Unconstrained Output Ports ; 38 ; 38 ; ; Unconstrained Output Port Paths ; 78 ; 78 ; +---------------------------------+-------+------+ @@ -948,7 +948,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Sun Aug 13 04:50:04 2023 + Info: Processing started: Sun Aug 13 06:36:31 2023 Info: Command: quartus_sta RAM2GS-MAXV -c RAM2GS Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -974,17 +974,17 @@ Info (332146): Worst-case setup slack is -99.000 Info (332119): ========= =================== ===================== Info (332119): -99.000 -99.000 ARCLK Info (332119): -99.000 -99.000 DRCLK - Info (332119): -10.164 -118.093 PHI2 - Info (332119): -9.387 -288.937 RCLK - Info (332119): -2.870 -7.136 nCRAS -Info (332146): Worst-case hold slack is -16.578 + Info (332119): -10.765 -121.853 PHI2 + Info (332119): -9.110 -282.559 RCLK + Info (332119): -2.305 -17.117 nCRAS +Info (332146): Worst-case hold slack is -16.599 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -16.578 -16.578 DRCLK - Info (332119): -16.552 -16.552 ARCLK - Info (332119): -0.611 -0.993 PHI2 - Info (332119): 0.443 0.000 nCRAS - Info (332119): 1.178 0.000 RCLK + Info (332119): -16.599 -16.599 DRCLK + Info (332119): -15.916 -15.916 ARCLK + Info (332119): -0.387 -0.479 PHI2 + Info (332119): 1.189 0.000 RCLK + Info (332119): 1.744 0.000 nCRAS Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -29.500 @@ -1001,7 +1001,7 @@ Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 3 warnings Info: Peak virtual memory: 4676 megabytes - Info: Processing ended: Sun Aug 13 04:50:05 2023 + Info: Processing ended: Sun Aug 13 06:36:32 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXV/output_files/RAM2GS.sta.summary b/CPLD/MAXV/output_files/RAM2GS.sta.summary index b6bef3b..c609e42 100644 --- a/CPLD/MAXV/output_files/RAM2GS.sta.summary +++ b/CPLD/MAXV/output_files/RAM2GS.sta.summary @@ -11,35 +11,35 @@ Slack : -99.000 TNS : -99.000 Type : Setup 'PHI2' -Slack : -10.164 -TNS : -118.093 +Slack : -10.765 +TNS : -121.853 Type : Setup 'RCLK' -Slack : -9.387 -TNS : -288.937 +Slack : -9.110 +TNS : -282.559 Type : Setup 'nCRAS' -Slack : -2.870 -TNS : -7.136 +Slack : -2.305 +TNS : -17.117 Type : Hold 'DRCLK' -Slack : -16.578 -TNS : -16.578 +Slack : -16.599 +TNS : -16.599 Type : Hold 'ARCLK' -Slack : -16.552 -TNS : -16.552 +Slack : -15.916 +TNS : -15.916 Type : Hold 'PHI2' -Slack : -0.611 -TNS : -0.993 - -Type : Hold 'nCRAS' -Slack : 0.443 -TNS : 0.000 +Slack : -0.387 +TNS : -0.479 Type : Hold 'RCLK' -Slack : 1.178 +Slack : 1.189 +TNS : 0.000 + +Type : Hold 'nCRAS' +Slack : 1.744 TNS : 0.000 Type : Minimum Pulse Width 'ARCLK' diff --git a/CPLD/RAM2GS-MAX.v b/CPLD/RAM2GS-MAX.v index 30d48e1..9c21a77 100644 --- a/CPLD/RAM2GS-MAX.v +++ b/CPLD/RAM2GS-MAX.v @@ -344,7 +344,9 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout, // if (Din[7:4]==4'h0) begin // MAX w/o LED // if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM // if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2 - XOR8MEG <= Din[0] || (LEDEN && Din[1]); + XOR8MEG <= Din[0] && !(LEDEN && Din[1]); + end else if (Din[7:4]==4'h0) begin // Unsupported type + XOR8MEG <= 0; end else if (Din[7:4]==4'h1) begin CmdLEDEN <= Din[1]; Cmdn8MEGEN <= ~Din[0]; diff --git a/CPLD/RAM2GS-SPI.v b/CPLD/RAM2GS-SPI.v new file mode 100644 index 0000000..4736e25 --- /dev/null +++ b/CPLD/RAM2GS-SPI.v @@ -0,0 +1,411 @@ +module RAM2GS(PHI2, MAin, CROW, Din, Dout, + nCCAS, nCRAS, nFWE, LED, + RBA, RA, RD, nRCS, RCLK, RCKE, + nRWE, nRRAS, nRCAS, RDQMH, RDQML, + nUFMCS, UFMCLK, UFMSDI, UFMSDO); + + /* 65816 Phase 2 Clock */ + input PHI2; + + /* Async. DRAM Control Inputs */ + input nCCAS, nCRAS; + + /* Synchronized PHI2 and DRAM signals */ + reg PHI2r, PHI2r2, PHI2r3; + reg RASr, RASr2, RASr3; + reg CASr, CASr2, CASr3; + reg FWEr; + reg CBR; + + /* Activity LED */ + reg LEDEN = 0; + output LED; + assign LED = !(!nCRAS && !CBR && LEDEN); + + /* 65816 Data */ + input [7:0] Din; + output [7:0] Dout; + assign Dout[7:0] = RD[7:0]; + + /* Latched 65816 Bank Address */ + reg [7:0] Bank; + + /* Async. DRAM Address Bus */ + input [1:0] CROW; + input [9:0] MAin; + input nFWE; + reg n8MEGEN = 0; + reg XOR8MEG = 0; + + /* SDRAM Clock */ + input RCLK; + + /* SDRAM */ + reg RCKEEN; + output reg RCKE = 0; + output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1; + output reg [1:0] RBA; + reg nRowColSel; + reg RA11; + reg RA10; + reg [9:0] RowA; + output [11:0] RA; + assign RA[11] = RA11; + assign RA[10] = RA10; + assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0]; + output RDQML, RDQMH; + assign RDQML = ~nRowColSel ? 1'b1 : ~MAin[9]; + assign RDQMH = ~nRowColSel ? 1'b1 : MAin[9]; + reg [7:0] WRD; + inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ; + + /* UFM Interface */ + output reg nUFMCS = 1; + output reg UFMCLK = 0; + output reg UFMSDI = 0; + input UFMSDO; + + /* UFM Command Interface */ + reg C1Submitted = 0; + reg ADSubmitted = 0; + reg CmdEnable = 0; + reg CmdSubmitted = 0; + reg Cmdn8MEGEN = 0; + reg CmdLEDEN = 0; + reg CmdUFMCLK = 0; + reg CmdUFMSDI = 0; + reg CmdUFMCS = 0; + wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE; + wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE; + wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE; + + /* State Counters */ + reg InitReady = 0; // 1 if ready for init sequence + reg Ready = 0; // 1 if done with init sequence + reg [1:0] S = 0; // post-RAS State counter + reg [17:0] FS = 0; // Fast init state counter + reg [3:0] IS = 0; // Init state counter + reg WriteDone; + + /* Synchronize PHI2, RAS, CAS */ + always @(posedge RCLK) begin + PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2; + RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2; + CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2; + end + + /* Latch 65816 bank when PHI2 rises */ + always @(posedge PHI2) begin + if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11 + else RA11 <= 1'b0; // Reserved in mode register + Bank[7:0] <= Din[7:0]; // Latch bank + end + + /* Latch bank address, row address, WE, and CAS when RAS falls */ + always @(negedge nCRAS) begin + if (Ready) begin + RBA[1:0] <= CROW[1:0]; + RowA[9:0] <= MAin[9:0]; + end else begin + RBA[1:0] <= 2'b00; // Reserved in mode register + RowA[9] <= 1'b1; // "1" for single write mode + RowA[8] <= 1'b0; // Reserved + RowA[7] <= 1'b0; // "0" for not test mode + RowA[6:4] <= 3'b010; // "2" for CAS latency 2 + RowA[3] <= 1'b0; // "0" for sequential burst (not used) + RowA[2:0] <= 3'b000; // "0" for burst length 1 (no burst) + end + FWEr <= ~nFWE; + CBR <= ~nCCAS; + end + + /* Latch write data when CAS falls */ + always @(negedge nCCAS) begin + WRD[7:0] <= Din[7:0]; + end + + /* State counter from RAS */ + always @(posedge RCLK) begin + if (~RASr2) S <= 0; + else if (S==2'h3) S <= 2'h3; + else S <= S+1; + end + /* Init state counter */ + always @(posedge RCLK) begin + // Wait ~4.178ms (at 62.5 MHz) before starting init sequence + FS <= FS+1; + if (FS[17:10] == 8'hFF) InitReady <= 1'b1; + end + + /* SDRAM CKE */ + always @(posedge RCLK) begin + // Only 1 LUT4 allowed for this function! + RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3); + end + + /* SDRAM command */ + always @(posedge RCLK) begin + if (Ready) begin + if (S==0) begin + if (RASr2) begin + if (CBR) begin + // AREF + nRCS <= 1'b0; + nRRAS <= 1'b0; + nRCAS <= 1'b0; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + end else begin + // ACT + nRCS <= 1'b0; + nRRAS <= 1'b0; + nRCAS <= 1'b1; + nRWE <= 1'b1; + RA10 <= 1'b1; // Bank RA10 consistently "1" + end + // Enable clock only for reads + RCKEEN <= ~CBR & ~FWEr; + end else if (RCKE) begin + // PCall + nRCS <= 1'b0; + nRRAS <= 1'b0; + nRCAS <= 1'b1; + nRWE <= 1'b0; + RA10 <= 1'b1; // "all" + RCKEEN <= 1'b1; + end else begin + // NOP + nRCS <= 1'b1; + nRRAS <= 1'b1; + nRCAS <= 1'b1; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + RCKEEN <= 1'b1; + end + nRowColSel <= 1'b0; // Select registered row addres + end else if (S==1) begin + // NOP + nRCS <= 1'b1; + nRRAS <= 1'b1; + nRCAS <= 1'b1; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + nRowColSel <= 1'b1; // Select asynchronous column address + RCKEEN <= ~CBR; // Disable clock if refresh cycle + end else if (S==2) begin + if (~FWEr & ~CBR) begin + // RD + nRCS <= 1'b0; + nRRAS <= 1'b1; + nRCAS <= 1'b0; + nRWE <= 1'b1; + RA10 <= 1'b1; // Auto-precharge + end else begin + // NOP + nRCS <= 1'b1; + nRRAS <= 1'b1; + nRCAS <= 1'b1; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + end + nRowColSel <= 1'b1; // Select asynchronous column address + RCKEEN <= ~CBR & FWEr; // Enable clock only for writes + end else if (S==3) begin + if (CASr2 & ~CASr3 & ~CBR & FWEr) begin + // WR + nRCS <= 1'b0; + nRRAS <= 1'b1; + nRCAS <= 1'b0; + nRWE <= 1'b0; + RA10 <= 1'b1; // Auto-precharge + end else begin + // NOP + nRCS <= 1'b1; + nRRAS <= 1'b1; + nRCAS <= 1'b1; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + end + nRowColSel <= ~(~FWEr | CASr3 | CBR); + RCKEEN <= ~(~FWEr | CASr2 | CBR); + end + end else if (InitReady) begin + if (S==0 & RASr2) begin + if (IS==0) begin + // NOP + nRCS <= 1'b1; + nRRAS <= 1'b1; + nRCAS <= 1'b1; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + end else if (IS==1) begin + // PC all + nRCS <= 1'b0; + nRRAS <= 1'b0; + nRCAS <= 1'b1; + nRWE <= 1'b0; + RA10 <= 1'b1; // "all" + end else if (IS==9) begin + // Load mode register + nRCS <= 1'b0; + nRRAS <= 1'b0; + nRCAS <= 1'b0; + nRWE <= 1'b0; + RA10 <= 1'b0; // Reserved in mode register + end else begin + // AREF + nRCS <= 1'b0; + nRRAS <= 1'b0; + nRCAS <= 1'b0; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + end + IS <= IS+1; + end else begin + // NOP + nRCS <= 1'b1; + nRRAS <= 1'b1; + nRCAS <= 1'b1; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + end + if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1; + nRowColSel <= 1'b0; // Select registered row address + RCKEEN <= 1'b1; + end else begin + // NOP + nRCS <= 1'b1; + nRRAS <= 1'b1; + nRCAS <= 1'b1; + nRWE <= 1'b1; + RA10 <= 1'b1; // RA10 is don't care + nRowColSel <= 1'b0; // Select registered row address + RCKEEN <= 1'b0; + end + end + + /* Submit command when PHI2 falls */ + always @(negedge PHI2) begin + // Magic number check + if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number + if (ADSubmitted) begin + CmdEnable <= 1'b1; + end + C1Submitted <= 1'b1; + ADSubmitted <= 1'b0; + end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number + if (C1Submitted) begin + CmdEnable <= 1'b1; + end + ADSubmitted <= 1'b1; + C1Submitted <= 1'b0; + end else if (C1WR | ADWR) begin // wrong magic number submitted + CmdEnable <= 1'b0; + C1Submitted <= 1'b0; + ADSubmitted <= 1'b0; + end else if (CMDWR) CmdEnable <= 1'b0; + + // Submit command + if (CMDWR & CmdEnable) begin + // if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED + // if (Din[7:4]==4'h0) begin // MAX w/o LED + if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM + // if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2 + XOR8MEG <= Din[0] && !(LEDEN && Din[1]); + end else if (Din[7:4]==4'h0) begin // Unsupported type + XOR8MEG <= 0; + end else if (Din[7:4]==4'h1) begin + CmdLEDEN <= Din[1]; + Cmdn8MEGEN <= ~Din[0]; + CmdSubmitted <= 1'b1; + end else if (Din[7:4]==4'h2) begin + // Reserved for MAX commands + end else if (Din[7:4]==4'h3 && ~Din[3]) begin + // Reserved for LCMXO2 commands + // Din[1] - Shift when high, execute when low + // Din[0] - Shift data + end else if (Din[7:4]==4'h3 && Din[3]) begin + // SPI (LCMXO, iCE40, AGM) commands + CmdLEDEN <= LEDEN; + Cmdn8MEGEN <= n8MEGEN; + CmdUFMCS <= Din[2]; + CmdUFMCLK <= Din[1]; + CmdUFMSDI <= Din[0]; + CmdSubmitted <= 1'b1; + end + end + end + + /* UFM Control */ + always @(posedge RCLK) begin + if (~InitReady && FS[17:10]==8'h00) begin + nUFMCS <= 1'b1; + UFMCLK <= 1'b0; + UFMSDI <= 1'b0; + end else if (~InitReady && FS[17:10]==8'h01) begin + nUFMCS <= 1'b0; + UFMCLK <= 1'b0; + UFMSDI <= 1'b0; + end else if (~InitReady && FS[17:10]==8'h02) begin + nUFMCS <= 1'b0; + UFMCLK <= FS[4]; + case (FS[9:5]) // Shift out read data command (0x03) + 5'h00: UFMSDI <= 1'b0; // command bit 7 (0) + 5'h01: UFMSDI <= 1'b0; // command bit 6 (0) + 5'h02: UFMSDI <= 1'b0; // command bit 5 (0) + 5'h03: UFMSDI <= 1'b0; // command bit 4 (0) + 5'h04: UFMSDI <= 1'b0; // command bit 3 (0) + 5'h05: UFMSDI <= 1'b0; // command bit 2 (0) + 5'h06: UFMSDI <= 1'b1; // command bit 1 (1) + 5'h07: UFMSDI <= 1'b1; // command bit 0 (1) + 5'h08: UFMSDI <= 1'b0; // address bit 23 (0) + 5'h09: UFMSDI <= 1'b0; // address bit 22 (0) + 5'h0A: UFMSDI <= 1'b0; // address bit 21 (0) + 5'h0B: UFMSDI <= 1'b0; // address bit 20 (0) + 5'h0C: UFMSDI <= 1'b0; // address bit 19 (0) + 5'h0D: UFMSDI <= 1'b0; // address bit 18 (0) + 5'h0E: UFMSDI <= 1'b0; // address bit 17 (0) + 5'h0F: UFMSDI <= 1'b0; // address bit 16 (0) + 5'h10: UFMSDI <= 1'b0; // address bit 15 (0) + 5'h11: UFMSDI <= 1'b0; // address bit 14 (0) + 5'h12: UFMSDI <= 1'b0; // address bit 13 (0) + 5'h13: UFMSDI <= 1'b1; // address bit 12 (0) + 5'h14: UFMSDI <= 1'b0; // address bit 11 (0) + 5'h15: UFMSDI <= 1'b0; // address bit 10 (0) + 5'h16: UFMSDI <= 1'b0; // address bit 09 (0) + 5'h17: UFMSDI <= 1'b0; // address bit 08 (0) + 5'h18: UFMSDI <= 1'b0; // address bit 07 (0) + 5'h19: UFMSDI <= 1'b0; // address bit 06 (0) + 5'h1A: UFMSDI <= 1'b0; // address bit 05 (0) + 5'h1B: UFMSDI <= 1'b0; // address bit 04 (0) + 5'h1C: UFMSDI <= 1'b0; // address bit 03 (0) + 5'h1D: UFMSDI <= 1'b0; // address bit 02 (0) + 5'h1E: UFMSDI <= 1'b0; // address bit 01 (0) + 5'h1F: UFMSDI <= 1'b0; // address bit 00 (0) + endcase + end else if (~InitReady && FS[17:10]==8'h03) begin + nUFMCS <= 1'b0; + UFMCLK <= FS[4]; + UFMSDI <= 1'b0; + // Latch n8MEGEN and LEDEN + if (FS[9:5]==5'h00 && FS[4:0]==5'h10) n8MEGEN <= ~UFMSDO; + //if (FS[9:5]==5'h01 && FS[4:0]==5'h10) LEDEN <= 1;//~UFMSDO; + LEDEN <= 1; + end else if (~InitReady && FS[17:10]!=8'hFE && FS[17:10]!=8'hFF) begin + nUFMCS <= 1'b0; + UFMCLK <= FS[1]; + UFMSDI <= 1'b0; + end else if (~InitReady) begin + nUFMCS <= 1'b1; + UFMCLK <= 1'b0; + UFMSDI <= 1'b0; + end else if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin + // Set user command signals after PHI2 falls + // Cmdn8MEGEN, CmdUFMCS, CmdUFMCLK, CmdUFMSDI + n8MEGEN <= Cmdn8MEGEN; + nUFMCS <= ~CmdUFMCS; + UFMCLK <= CmdUFMCLK; + UFMSDI <= CmdUFMSDI; + end + end +endmodule